RU2369008C2 - Device and method for coding/decoding block code for low density parity check with variable block length - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: invention relates to a mobile communication system and is meant for coding/decoding block codes for low density parity check (LDPC) with variable block length. The device and procedure involve reception of data words and coding the data words in the LDPC block code in accordance with the first or second parity check matrix depending on the length used for generating data words in the LDPC block code.

EFFECT: prevention of information data loss.

12 cl, 28 dwg

Description

FIELD OF THE INVENTION

The present invention, in General, relates to a mobile communication system, and in particular to an apparatus and method for encoding / decoding block low-density parity check codes (LDPC).

State of the art

As a result of the rapid development of mobile communication systems, it became necessary to develop a technology that allows the transfer of large amounts of data, approaching the bandwidth of the cable network in a wireless communication environment. To meet the ever-increasing demand for a high-speed, high-bandwidth communication system that can process and transmit various data, such as image and radio data, in addition to the service focused on voice transmission, it is necessary to increase the transmission efficiency of the system using an appropriate channel coding scheme so as to improve overall system performance. However, the mobile communication system, taking into account its characteristics, inevitably generates errors during data transmission due to noise, interference and attenuation, in accordance with the conditions of the channel. The generation of errors leads to the loss of a large amount of information data.

To prevent the loss of information data as a result of error generation, various error management schemes are currently used, which are partially based on channel characteristics, in order to thereby increase the reliability of the mobile communication system. In the most typical error management scheme, error correction codes are used.

Below, with reference to FIG. 1, a description is given of the structure of a transmitter / receiver in a common mobile communication system.

In FIG. 1 is a diagram illustrating a structure of a transmitter / receiver in a common mobile communication system. As shown in FIG. 1, transmitter 100 includes an encoder 111, a modulator 113, and a radio frequency (RF) processor 115, and a receiver 150 includes an RF processor 151, a demodulator 153, and a decoder 155.

In the transmitter 100, if information information “u” intended for transmission is generated, it is transmitted to the encoder 111. The encoder 111 generates an encoded symbol “c” by encoding the information data “u” using a predetermined coding scheme, and outputs the encoded symbol “c” to modulator 113. Modulator 113 generates a modulation symbol "s" by modulating the encoded symbol "c" using a predetermined modulation scheme and outputs the modulation symbol "s" to the RF processor 115. The RF processor 115 performs RF processing of the modulation symbol "s" coming from out a modulator 113, and transmits the signal after RF processing on the wireless link through an antenna ANT (ANT).

The signal transmitted over the wireless channel by the transmitter 100 is thus received at the receiver 150 through its ANT antenna, and the signal received through the antenna is supplied to the RF processor 151. The RF processor 151 performs RF processing of the received signal and outputs the “r” signal after RF processing to the demodulator 153. Demodulator 153 demodulates the “r” signal after RF processing from the output of the RF processor 151 using the demodulation circuit corresponding to the modulation scheme used in the modulator 113 and outputs the demodulated signal “x” to the decoder 155. Decoder 155 decodes the demodulated signal "x" coming from the output of the demodulator 153 using the decoding scheme corresponding to the encoding scheme used in the encoder 111, and outputs the decoded signal "u" as the finally decoded information data.

In order to enable error-free decoding at the receiver 150 of the “u” information data transmitted by the transmitter 100, it is necessary to use a highly efficient encoder and decoder. In particular, since it is necessary to take into account the radio channel environment and the characteristics of the mobile communication system, one should more seriously take into account errors that can be generated under the influence of the radio channel environment.

The most common error correction codes include turbo codes and low density parity check (LDPC) codes.

It is known that a turbo code provides a better performance improvement compared to a convolutional code, which is usually used to correct errors during data transmission at high speed. The advantage of the turbo code is that it allows you to effectively correct the error caused by the noise generated in the data channel, thereby increasing the reliability of data transmission. The LDPC code can be decoded using an iterative decoding algorithm based on a sum-multiplication algorithm in a factor graph. Since the decoder for the LDPC code uses an iterative decoding algorithm based on the summation-multiplication algorithm, it is less complex than the decoder for the turbo code. In addition, the decoder for the LDPC code is easy to put into practice using the parallel processing decoder compared to the decoder for the turbo code.

The Shannon theorem of channel coding shows that reliable communication is possible only at a data transfer rate not exceeding the channel capacity. However, the Shannon channel coding theorem does not offer a detailed channel coding / decoding method to maintain the data rate up to the maximum channel bandwidth. Usually, although a random code having a very large block size exhibits performance characteristics approaching the limit value of the channel throughput in accordance with the Shannon theorem of channel coding, in practice, using the MAP decoding method (maximum a posteriori, MAV (maximum a posteriori probability) ) or ML (MP, maximum likelihood), it is impossible to perform this decoding method due to the extremely large computational load.

The turbo code was proposed by Berrou, Glavieux, and Thitimajshima in 1993, and it exhibits exceptional performance characteristics that approach the limit value of channel capacity in accordance with the Shannon theorem of channel coding. The advent of the turbo code initiated an active study in the field of iterative decoding and graphic expression of codes; as a result, the LDPC codes proposed by the author of Gallager in 1962 came to the fore in these studies. Loops exist in the factor graph of the turbo code and LDPC code, and iterative decoding in the factor graph of the LDPC code in which loops exist is known to be suboptimal. In addition, it was experimentally confirmed that the LDPC code has exceptional performance using iterative decoding. The LDPC code, as you know, shows the best characteristics, differing only by approximately 0.04 [dB] from the limit value of the channel throughput, in accordance with the Shannon theorem of channel coding, with a transmission frequency of error bits (BER, BWO) of 10 ^-5 , at using block size 10 ⁷ . In addition, although the complexity of the decoding process of the LDPC code defined in the Galois field (GF, PG) for q> 2, that is, GF (q), increases, its characteristics far exceed the binary code. However, there is no satisfactory theoretical description of successful decoding using an iterative decoding algorithm for the LDPC code defined in GF (q).

The LDPC code proposed by the author of Gallager is determined by the parity matrix, in which most of the elements have a value of 0 and a smaller number of elements, with the exception of elements having a value of 0, have a nonzero value, for example, a value of 1. In the following description, it is assumed that a non-zero value is a value of 1.

For example, the LDPC code (N, j, k) is a linear block code having a block length of N and is defined as a sparse parity check matrix in which each column has j elements having a value of 1, each row has k elements having value 1, and all elements, with the exception of elements having a value of 1, have a value of 0.

An LDPC code in which the weight of each column in the parity matrix is fixed by the value “j” and the weight of each row in the parity matrix is fixed by the value “k”, as described above, is called the “regular LDPC code”. Here, “weight” refers to the number of elements having a nonzero value among the elements making up the parity check matrix. Unlike a regular LDPC code, an LDPC code in which the weight of each column and the weight of each row in the parity matrix are not fixed is called an “irregular LDPC code”. It is well known that an irregular LDPC code has better performance than a regular LDPC code. However, in the case of an irregular LDPC code, since the weight of each column and the weight of each row in the parity matrix is not fixed, that is, it is irregular, the weight of each column in the parity matrix and the weight of each row in the parity matrix must be adjusted accordingly for guaranteeing the best performance.

Below, with reference to FIG. 2, a description is given of a parity check matrix of an LDPC code (8, 2, 4) as an example of an LDPC code (N, j, k).

In FIG. 2 is a diagram illustrating a parity check matrix for a common LDPC code (8, 2, 4). As shown in FIG. 2, the parity check matrix H of the LDPC code (8, 2, 4) consists of 8 columns and 4 rows, in which the weight of each column is fixed and equal to 2 and the weight of each row is fixed and equal to 4. Since the weight of each column and the weight of each row in the parity check matrix is regular, as indicated above, the LDPC code (8, 2, 4) shown in FIG. 2, becomes a regular LDPC code.

The LDPC code parity check matrix (8, 2, 4) has been described above with reference to FIG. 2. Next, with reference to FIG. 3, the factor graph of the LDPC code (8, 2, 4) described with reference to FIG. 2.

In FIG. 3 is a diagram illustrating a factor graph of the LDPC code (8, 2, 4) of FIG. 2. As shown in FIG. 3, the factor graph of the LDPC code (8, 2, 4) consists of 8 variable nodes x ₁ 300, x ₂ 302, x ₃ 304, x ₄ 306, x ₅ 308, x ₆ 310, x ₇ 312 and x ₈ 314 and 4 check nodes 316, 318, 320 and 322. When an element having a value of 1, that is, having a non-zero value, exists at the point at which the i-th row and j-th column of the LDPC (8, 2, 4) code parity matrix intersect each other, between by the variable node x _i and the jth node of the check, a branch is formed.

Since the LDPC code parity check matrix has a very small weight, as described above, it is possible to perform decoding using iterative decoding even in a relatively long block code that exhibits a performance approaching the channel bandwidth limit for the Shannon coding theorem channel, such as turbo code, while constantly increasing the length of the block code block. The authors of MacKay and Neal proved that the iterative decoding of the LDPC code using the flow transfer scheme approximates in its performance characteristics to the iterative decoding of the turbo code.

To generate high performance LDPC code, the following conditions must be met.

(1) The factor graph cycles of the LDPC code should be considered.

The term "cycle" refers to a loop formed by edges connecting variable nodes to test nodes in the factor graph of the LDPC code, and the cycle length is determined by the number of edges making up the loop. A long cycle means that the number of edges connecting the variable nodes to the verification nodes that make up the loop in the factor graph of the LDPC code is large. In contrast, a short cycle means that the number of edges connecting the variable nodes to the verification nodes that make up the loop in the factor graph of the LDPC code is small.

As the cycles in the factor graph of the LDPC code become longer, the performance of the LDPC code improves for the following reasons. When long cycles are generated in the factor graph of the LDPC code, it becomes possible to prevent a decrease in a characteristic such as the minimum error level that occurs when there are too many short cycles in the factor graph of the LDPC code.

(2) Effective coding of the LDPC code should be considered.

For LDPC code, it is difficult to perform real-time coding compared to a convolutional code or turbo code due to the high coding complexity. To reduce the complexity of encoding the LDPC code, a re-accumulation code (RA, PN) has been proposed. However, the RA code also has limitations with respect to reducing the complexity of the LDPC code. Therefore, effective coding of the LDPC code should be considered.

(3) The degree of distribution of the factor graph of the LDPC code should be considered.

Typically, an irregular LDPC code has better performance than a regular LDPC code, since the factor graph of an irregular LDPC code has varying degrees. The term “degree” refers to the number of edges connected to the variable nodes and the verification nodes in the factor graph of the LDPC code. In addition, the phrase “degree distribution” of the factor graph of the LDPC code refers to the ratio of the number of nodes having a certain degree to the total number of nodes. Richardson has proven that LDPC code with a certain degree of distribution has better performance.

Next, with reference to FIG. 4, a description will be given of a parity check matrix of a block LDPC code.

In FIG. 4 is a diagram illustrating a parity check matrix of a common block LDPC code. Before describing FIG. 4, it should be noted that the block LDPC code is a new LDPC code for which not only effective coding is taken into account, but also the effective storage and performance improvement of the parity check matrix, and the block LDPC code is an LDPC code, continued by generalizing regular LDPC code structures. As shown in FIG. 4, the parity check matrix of the block LDPC code is divided into a plurality of partial blocks, and a permutation matrix is displayed on each of the partial blocks. In FIG. 4 “P” is a permutation matrix of size N _s × N _s , and the superscript (or exponent) a _{pq of} the permutation matrix P is either 0 <a _pq <N _s -1 or a _pq = ∞.

представляет матрицу перестановок, расположенную в частичном блоке, где р-ая строка и q-ый столбец матрицы проверки на четность, состоящей из множества частичных блоков, пересекаются друг с другом. Таким образом, "p" и "q" представляют количество строк и количество столбцов частичных блоков, соответствующих информационной части матрицы проверки на четность соответственно.In addition, “p” indicates that the corresponding permutation matrix is located in the pth row of partial blocks of the parity check matrix, and “q” indicates that the corresponding permutation matrix is located in the qth column of partial blocks of the parity check matrix. In this way,

represents a permutation matrix located in a partial block, where the p-th row and q-th column of the parity check matrix, consisting of many partial blocks, intersect each other. Thus, “p” and “q” represent the number of rows and the number of columns of partial blocks corresponding to the information part of the parity check matrix, respectively.

A permutation matrix will be described below with reference to FIG. 5.

In FIG. 5 is a diagram illustrating the permutation matrix P of FIG. 4. As shown in FIG. 5, the permutation matrix P is a square matrix having a size of N _s × N _s , and each of the N _s columns constituting the permutation matrix P has a weight of 1, and each of the N _s rows constituting the permutation matrix P also has a weight of 1 Here, although the size of the permutation matrix P is expressed as N _s × N _s , it can also be expressed as N _s since the permutation matrix P is a square matrix.

, и матрица P перестановок с верхним индексом a_pq=∞, то есть матрица P∞ перестановок представляет собой нулевую матрицу. Здесь

представляет собой единичную матрицу с размером N_s×N_s.In FIG. 4, the permutation matrix P with superscript a _pq = 0, i.e., the permutation matrix P ° is the identity

, and the permutation matrix P with superscript a _pq = ∞, that is, the permutation matrix P∞ is a zero matrix. Here

represents an identity matrix with a size of N _s × N _s .

Throughout the entire parity check matrix of the block LDPC code shown in FIG. 4, since the total number of rows is N _s × p and the total number of columns is N _s × q (for p ≤ q), when the entire LDPC code parity matrix is full rank, the coding rate can be expressed as equation (1) independently on the size of partial blocks.

(1)

(one)

If a _pq ≠ ∞ for all p and q, the permutation matrices corresponding to the partial blocks are non-zero matrices, and the partial blocks form a regular LDPC code in which the weight value of each column and the weight value of each row in each of the permutation matrices corresponding to partial blocks equal p and q respectively. Here, each of the permutation matrices corresponding to the partial blocks will be called the "partial matrix".

Since (p-1) dependent rows exist in the entire parity check matrix, a higher coding rate is obtained than the coding rate calculated by equation (1). In the case of the block LDPC code, if the position of the weight of the first row of each of the partial matrices constituting the entire parity check matrix is determined, it will also be possible to determine the position of the weights for the remaining rows (N _s - 1). Therefore, the required memory size is reduced to 1 / N _s compared to the case when the weights are selected irregularly to store information throughout the parity check matrix.

As described above, the term “cycle” refers to a loop formed by edges connecting different nodes to test nodes in the factor graph of the LDPC code, and the cycle length is defined as the number of edges making up the loop. A long cycle means that the number of edges connecting the variable nodes to the verification nodes that make up the loop in the factor graph of the LDPC code is large. As the cycles in the factor graph of the LDPC code become longer, the performance of the LDPC code improves.

In contrast, as the cycles in the factor graph of the LDPC code become shorter, the possibilities for error correction of the LDPC code are reduced due to degradation of performance due to a minimum error level. That is, in the case when there are many cycles with a short length in the factor graph of the LDPC code, information about a particular node belonging to a cycle with a shorter length starting from it is returned after a small number of iterations. As the number of iterations increases, the information returns to the corresponding node more often, as a result of which the information cannot be correctly updated, which leads to a deterioration in the ability of error correction of the LDPC code.

Below, with reference to FIG. 6, a description is given of the loop structure of the block LDPC code.

In FIG. 6 is a diagram illustrating a loop structure of a block LDPC code in which the parity check matrix consists of 4 partial matrices. Before describing FIG. 6, it should be noted that the block LDPC code is a new LDPC code for which not only effective coding is taken into account, but also efficient storage and improvement of the performance of the parity check matrix. The block LDPC code is also an LDPC code, extended by generalizing the structure of the regular LDPC code. The parity check matrix of the block LDPC code shown in FIG. 6, consists of 4 partial blocks, the diagonal line represents the position where the elements having a value of 1 are located, and other parts, except for the sections located on the diagonal line, represent the positions where the elements having a value equal to 0. In addition, “P” represents the same permutation matrix as the permutation matrix described with reference to FIG. 5.

To analyze the loop structure of the block LDPC code shown in FIG. 6, an element having a value of 1 located in an i-th row of the partial matrix P ^a, is defined as a reference element, and an element having a value of 1 located in an i-th row will be referred to as "point 0". Here, a “partial matrix” refers to a matrix corresponding to a partial block. The 0-point is located in an (i + a) th column of the partial matrix P ^a.

An element having a value of 1 in the partial matrix P ^b located in the same row as point 0 is called “point 1”. For the same reason as point 0, point 1 is located in the (i + b) th column of the partial matrix P ^b .

Further, an element having a value of 1 in the partial matrix P ^c located in the same column as point 1 will be called “point 2”. Since the partial matrix P ^c is a matrix obtained by shifting the corresponding columns of the identity matrix I to the right relative to the module N _s by c, point 2 is located in the (i + bc) -th row of the partial matrix P ^c .

In addition, an element having a value of 1 in the partial matrix P ^d located in the same row as point 2 will be called “point 3”. Point 3 is located in the (i + b-c + d) -th column of the partial matrix P ^d .

Finally, an element having a value of 1 in a partial matrix P ^a located in the same column as point 3 will be called “point 4”. Point 4 is located in the (i + b-c + da ) th row of the partial matrix P ^a.

In the loop structure of the LDPC code shown in FIG. 6, if there is a cycle with a length of 4, point 0 and point 4 are located in the same position. That is, the relationship between point 0 and point 4 is defined by equation (2)

i + b-c + d-a (modNs) i

i + bc + da (modNs) or (2) i + a

i + bc + d (modNs)

Equation (2) can be rewritten as equation (3)

b + d (modN_s)a + c

b + d (modN _s ) (3)

i + p(b - c + d - e) As a result, when the interdependence according to equation (3) is satisfied, a cycle with a length of 4 is generated. Usually, when point 0 and point 4p are the first points identical to each other, the relation i

i + p (b - c + d - e)

(modN _s ), and the following relation is satisfied, shown in equation (4)

0 (modN_s)p (a - b + c - d)

0 (modN _s ) (four)

In other words, if a positive integer with a minimum value among positive integers satisfying equation (4) for given a, b, c and d is defined as “p”, a cycle with a length of 4p becomes a cycle having a minimum length in the structure of a block cycle the LDPC code shown in FIG. 6.

In conclusion, as described above, for (a-b + cd) ≠ 0, if the condition gcd (N _s , a-b + cd) = 1 is satisfied, then p = N _s . Here, gcd (N _s , a-b + cd) is a function for calculating the “greatest common factor” for the integers N _s and a-b + cd. Therefore, a cycle with a length of 4N _S becomes a cycle with a minimum length.

The Richardson-Urbanke technique will be used as the coding technique for the LDPC block code. Since the Richardson-Urbanke technique is used as a coding technique, the degree of coding can be minimized as the shape of the parity check matrix becomes similar to that of the full lower triangular matrix.

Below, with reference to FIG. 7, a description is made of a parity check matrix having a form similar to that of a complete lower triangular matrix.

и

также представляют собой матрицы перестановок, а верхние индексы ai - a_p последовательно индексированы для частичных матриц, расположенных в диагональной части, для части проверки на четность. Кроме того, P^x и P^y также представляют собой матрицы перестановок, и для удобства пояснения они индексированы по-другому для различения части проверки на четность от информационной части. Если длина блочного кода LDPC, имеющего матрицу проверки на четность, представленную на фиг. 7, как предполагается, равна N, степень кодирования блочного кода LDPC линейно увеличивается относительно длины N (0(N)) блока.In FIG. 7 is a diagram illustrating a parity check matrix having a shape similar to that of a full lower triangular matrix. The parity check matrix shown in FIG. 7 differs from the parity check matrix in the form of a complete lower triangular matrix in the form of the parity check part. In FIG. 7, the superscript (or exponent) a _{pq of the} matrix P of permutations of the information part is either 0 ≤ a _pq ≤ N _s - 1 or a _pq = ∞, as described above. The permutation matrix P with superscript a _pq = 0, that is, the permutation matrix P ⁰ in the information part is the identity matrix N _s × N _s , and the permutation matrix P with superscript a _pq = ∞, that is, the permutation matrix P ^∞ represents is a zero matrix. In FIG. 7, “p” represents the number of rows of partial blocks mapped to the information part, and “q” represents the number of columns of partial blocks mapped to the parity part. In addition, the superscripts a _p , x, and y of the permutation matrices P mapped to the parity part are exponentials of the permutation matrix P. However, for convenience of explanation, various superscripts a _p , x, and y are used to distinguish the parity part from the information part. That is, in FIG. 7,

and

also represent permutation matrices, and the superscripts ai - a _{p are} sequentially indexed for partial matrices located in the diagonal part, for the parity part. In addition, P ^x and P ^{y are} also permutation matrices, and for convenience of explanation, they are indexed differently to distinguish the parity part from the information part. If the length of the block LDPC code having the parity check matrix shown in FIG. 7 is assumed to be N, the degree of coding of the block LDPC code linearly increases with respect to the length N (0 (N)) of the block.

The biggest problem of the LDPC code having the parity check matrix of FIG. 7, is that if the length of the partial block is determined to be N _s , N _s verification nodes will be generated, the degrees of which are always 1 in the factor graph of the block LDPC code. Verification nodes of degree 1 cannot affect performance improvements based on iterative decoding. Therefore, the standard irregular LDPC code based on the methodology of the authors of Richardson-Urbanke does not include a check node with degree 1. Therefore, it is assumed that the parity check matrix of FIG. 7 is a basic parity check matrix for designing a parity check matrix so that it enables efficient coding when it does not include a check node with degree 1. If the parity check matrix of FIG. 7 contains partial matrices, the selection of the partial matrix is a very important factor for improving the performance of the block LDPC code, so finding the appropriate selection criteria for the partial matrix also becomes a very important factor.

Next, a description will be given of a method for developing a parity check matrix of a block LDPC code based on the above block LDPC code.

In order to simplify the method for developing the parity check matrix of the block LDPC code and the coding method for the block LDPC code, it is assumed that the parity check matrix shown in FIG. 7 will be formed with 6 partial matrices as shown in FIG. 8.

In FIG. 8 is a diagram illustrating a parity check matrix of FIG. 7, which is divided into 6 partial blocks. As shown in FIG. 8, the parity check matrix of the block LDPC code shown in FIG. 7 is divided into the information part “s”, the first parity part p ₁ and the second parity part p ₂ . The information part “s” is the part of the parity check matrix mapped to the actual information word in the encoding process of the block LDPC code, the same as the information part described with reference to FIG. 7, but for convenience of explanation, the information part "s" is represented by other letters indicating the reference position. The first part p ₁ of the parity check and the second part p ₂ of the parity check are part of the parity check matrix mapped to the actual parity during the coding process of the block LDPC code, as well as the part of the parity check described with reference to FIG. . 7, and the parity check part is divided into two parts.

Partial matrices A and C correspond to partial blocks A (802) and C (804) of the information part “s”, partial matrices B and D correspond to partial blocks B (806) and D (808) of the first parity part p ₁ , and partial matrices T and E correspond to partial blocks T (810) and E (812) of the second part p ₂ of the parity check. Although the parity check matrix in FIG. 8 is divided into 7 partial blocks, it should be noted that “0” is not a separate partial block, and since the partial matrix T corresponding to the partial block T (810) has a complete lower triangular shape, the region where the zero matrices are located at the base of the diagonal , represented by "0". The process of simplifying the encoding method using partial matrices of the information part "s" of the first parity part p ₁ and the second parity part p ₂ will be described below with reference to FIG. 10.

The partial matrices of FIG. 8 will be described below with reference to FIG. 9.

In FIG. 9 is a diagram illustrating a transposed matrix of the partial matrix B shown in FIG. 8, a partial matrix E, a partial matrix T, and an inverse matrix of a partial matrix T, in the parity check matrix of FIG. 7.

представляет

. Матрицы перестановок, представленные на фиг. 9, например

, могут представлять собой единичную матрицу. Как описано выше, если верхний индекс матрицы перестановок, то есть a₁ равен 0,

будет представлять собой единичную матрицу. Кроме того, если верхний индекс матрицы перестановок, то есть a₁ увеличивается на заданное значение, для матрицы перестановок будет выполнен циклический сдвиг на заданное значение, в результате чего матрица

перестановок станет единичной матрицей.As shown in FIG. 9, the partial matrix B ^T is the transposed matrix of the partial matrix B, and the partial matrix T ^-1 is the inverse matrix of the partial matrix T.

represents

. The permutation matrices shown in FIG. 9 for example

, can be a unit matrix. As described above, if the superscript of the permutation matrix, that is, a ₁ is 0,

will be a unit matrix. In addition, if the superscript of the permutation matrix, that is, a ₁ increases by a given value, a cyclic shift by a given value will be performed for the permutation matrix, as a result of which the matrix

permutations will become the identity matrix.

Below, with reference to FIG. 10, a description is given of a process for developing a parity check matrix of a block LDPC code.

In FIG. 10 is a flowchart illustrating a procedure for generating a parity check matrix of a common block LDPC code. Before describing FIG. 10 it should be noted that in order to generate a block LDPC code, it is necessary to determine the size of the keyword and the coding rate of the block LDPC code to be generated, as well as the size of the parity check matrix must be determined in accordance with the determined size of the keyword and the value of the coding rate. If the keyword size of the LDPC block code is represented as N and the coding rate is represented as R, the size of the parity check matrix becomes N (1-R) × N. In fact, the procedure for generating the parity check matrix of the block LDPC code shown in FIG. 10 is performed only once, since the parity check matrix is initially generated so that it matches the situation in the data transmission system, and then the generated parity check matrix is used.

In FIG. 10, in step 1011, the controller divides the parity check matrix with a size of N (1-R) x N in total into pxq blocks including p blocks on the horizontal axis and q blocks on the vertical axis, and then proceeds to step 1013. Since each block is N _s × N _{s in} size; the parity matrix consists of N _s × p columns and N _s × q rows. At step 1013, the controller classifies the p × q blocks extracted from the parity check matrix into the information part “s”, the first parity check part p ₁ and the second parity check part p ₂ , and then proceeds to steps 1015 and 1021.

перестановок так, чтобы минимальная длина цикла для цикла блока была максимальной, как описано выше на участках ненулевых матриц в блоках, имеющих низкую степень, среди блоков, определенных в соответствии со степенью распределения, для гарантирования хороших рабочих характеристик блочного кода LDPC, и затем переходит на этап 1019. Матрицы

перестановок должны быть определены с учетом циклов блоков не только по информационной части "s", но также и по первой части p₁ проверки на четность и второй части p₂ проверки на четность.In step 1015, the controller divides the information part “s” into non-zero blocks, or non-zero matrices, and zero blocks, or zero matrices according to the degree of distribution so as to guarantee good performance of the block LDPC code, and then proceeds to step 1017. Since the degree of distribution for the guaranteed good performance of the LDPC block code has been described above, a detailed description thereof is not given here. At 1017, the controller determines the matrices

permutations so that the minimum cycle length for a block cycle is maximum, as described above in sections of nonzero matrices in blocks with a low degree, among blocks determined according to the degree of distribution, to guarantee good performance of the block LDPC code, and then switches to step 1019. Matrices

permutations should be determined taking into account the cycles of the blocks not only by the information part "s", but also by the first part p ₁ of the parity check and the second part p ₂ of the parity check.

перестановок на участках ненулевой матрицы в блоках, имеющих высокую степень по сравнению с другими блоками, определенную в соответствии с распределением степени для гарантирования хороших рабочих характеристик блочного кода LDPC, и затем заканчивает процедуру. Даже когда определены матрицы Pa^pq перестановок, которые должны быть применены к участкам ненулевой матрицы в блоках, имеющих высокую степень, матрицы

перестановок должны быть определены таким образом, чтобы минимальная длина цикла для цикла блока была максимизирована, и матрицу

определяют с учетом циклов блоков, не только информационной части "s", но также и первой части p₁ проверки на четность и второй части p₂ проверки на четность. Пример матриц

перестановок, расположенных в информационной части "s" матрицы проверки на четность, представлен на фиг. 7.At 1019, the controller randomly determines matrices

permutations on sections of a nonzero matrix in blocks having a high degree compared to other blocks, determined in accordance with the degree distribution to guarantee good performance of the block LDPC code, and then ends the procedure. Even when the matrices Pa ^{pq of} permutations are determined, which should be applied to sections of a nonzero matrix in blocks with a high degree, matrices

permutations should be defined so that the minimum cycle length for the block cycle is maximized, and the matrix

determine, taking into account the cycles of the blocks, not only the information part "s", but also the first part p ₁ of the parity check and the second part p ₂ of the parity check. Matrix Example

permutations located in the information part "s" of the parity check matrix are shown in FIG. 7.

и

перестановок в 2 частичных блоках среди частичных блоков, составляющих частичную матрицу B, и затем переходит на этап 1025. Структура для ввода ненулевых матриц

и

перестановок в 2 частичных блоках среди частичных блоков, составляющих частичную матрицу B, была описана со ссылкой на фиг. 9.At step 1021, the controller divides the first part p ₁ and the second part p ₂ of the parity check into 4 partial matrices B, T, D and E and then proceeds to step 1023. At step 1023, the controller enters non-zero matrices

and

permutations in 2 partial blocks among the partial blocks making up the partial matrix B, and then proceeds to step 1025. Structure for inputting non-zero matrices

and

permutations in 2 partial blocks among the partial blocks constituting the partial matrix B has been described with reference to FIG. 9.

,

, …,

в (i, i+1)-ые частичные блоки под диагональными компонентами частичной матрицы T, и затем переходит на этап 1027. Структура для ввода единичных матриц I в диагональные частичные блоки частичной матрицы T и ввода частичных матриц перестановок

,

, …,

в (i, i+1)-ые частичные блоки под диагональными компонентами частичной матрицы T была описана со ссылкой на фиг. 9.At 1025, the controller enters the identity matrices I into the diagonal partial blocks of the partial matrix T, enters specific permutation matrices

,

, ...,

to the (i, i + 1) th partial blocks under the diagonal components of the partial matrix T, and then proceeds to step 1027. Structure for inputting the unit matrices I into the diagonal partial blocks of the partial matrix T and entering the partial permutation matrices

,

, ...,

in the (i, i + 1) th partial blocks under the diagonal components of the partial matrix T was described with reference to FIG. 9.

перестановок только в последний частичный блок в частичной матрице E и затем заканчивает процедуру. Структура для ввода 2 матриц

перестановок только в последний частичный блок среди частичных блоков, составляющих частичную матрицу E, была описана со ссылкой на фиг. 9.At step 1027, the controller enters the partial matrix P ^x into the partial matrix D and then proceeds to step 1029. At step 1029, the controller enters the matrices

permutations only to the last partial block in the partial matrix E and then ends the procedure. Structure for entering 2 matrices

permutations of only the last partial block among the partial blocks making up the partial matrix E has been described with reference to FIG. 9.

SUMMARY OF THE INVENTION

As described above, it is known that the LDPC code, like the turbo code, has a high increase in performance during high-speed data transmission and effectively corrects the error caused by noise generated in the transmission channel, thereby increasing the reliability of data transmission. However, the LDPC code has a disadvantage associated with the coding rate, since the LDPC code has a relatively high coding rate, and has limitations in terms of coding rate. Among the currently available LDPC codes, the main LDPC codes have a 1/2 coding rate, and only a small number of LDPC codes have a 1/3 coding rate. Limiting the coding rate has a fatal effect on data transmission with high speed and high bandwidth. Of course, although the degree of distribution representing the best performance can be calculated using the density evolution scheme to perform the relatively low coding rate of the LDPC code, it is difficult to implement the LDPC code having the degree of distribution representing the best performance, due to various limitations, such as cycle structure in a factor graph, and when implemented in hardware.

Thus, an object of the present invention is to provide an apparatus and method for encoding / decoding an LDPC code having a variable block length in a mobile communication system.

Another objective of the present invention is to provide an apparatus and method for encoding / decoding an LDPC code having a variable block length, the encoding of which would be minimized in a mobile communication system.

In accordance with one aspect of the present invention, there is provided a method for encoding a block variable density parity check (LDPC) code. The method includes the steps of taking an information word; and encode this information word into a block LDPC code based on one matrix from the first parity check matrix and the second parity check matrix depending on the length to be used when generating the information word in the LDPC block code.

In accordance with another aspect of the present invention, there is provided an apparatus for encoding a variable low density block parity check (LDPC) code. This device includes an encoder for encoding an information word into a block LDPC code based on one of the first parity check matrix and the second parity check matrix depending on the length to be used when generating the information word in the LDPC block code; and a modulator for modulating the block LDPC code into a modulation symbol using a predetermined modulation scheme.

In accordance with another further aspect of the present invention, there is provided a method for decoding a low density block parity check (LDPC) code having a variable length. The method includes receiving a signal and selecting one matrix from the first parity check matrix and the second parity check matrix in accordance with the length of the block LDPC code for decoding, and decode the received signal in accordance with the selected parity check matrix thus detecting the block LDPC code.

In accordance with yet another aspect of the present invention, there is provided an apparatus for decoding a low density block parity check (LDPC) code having a variable length. The device includes a receiver for receiving a signal; and a decoder for selecting one matrix from the first parity check matrix and the second parity check matrix in accordance with the length of the block LDPC code for decoding, and decoding the received signal in accordance with the selected parity check matrix with detection, thus, the block code LDPC.

Brief Description of the Drawings

The above and other objectives, features and advantages of the present invention will be better understood from the following detailed description, which should be considered in conjunction with the accompanying drawings, in which:

in FIG. 1 is a diagram illustrating a structure of a transmitter / receiver in a conventional mobile communication system;

in FIG. 2 is a diagram illustrating a parity check matrix of a common LDPC code (8, 2, 4);

in FIG. 3 is a diagram illustrating a factor graph of the LDPC code (8, 2, 4) of FIG. 2;

in FIG. 4 is a diagram illustrating a parity check matrix of a conventional block LDPC code;

in FIG. 5 is a diagram illustrating the permutation matrix P of FIG. four;

in FIG. 6 is a diagram illustrating a loop structure of a block LDPC code in which a parity check matrix consists of 4 partial matrices;

in FIG. 7 is a diagram illustrating a parity check matrix having a shape similar to that of a full lower triangular matrix;

in FIG. 8 is a diagram illustrating a parity check matrix of FIG. 7, which is divided into 6 partial blocks;

in FIG. 9 is a diagram illustrating a transposed matrix of the partial matrix B shown in FIG. 8, a partial matrix E, a partial matrix T, and an inverse matrix of a partial matrix T;

in FIG. 10 is a flowchart illustrating a procedure for generating a parity check matrix of a conventional block LDPC code;

in FIG. 11 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a first embodiment of the present invention;

in FIG. 12 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a second embodiment of the present invention;

in FIG. 13 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a third embodiment of the present invention;

in FIG. 14 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fourth embodiment of the present invention;

in FIG. 15 is a flowchart illustrating a process for encoding a block LDPC code with a variable block length in accordance with first to fourth embodiments of the present invention;

in FIG. 16 is a block diagram illustrating an internal structure of an apparatus for encoding a block LDPC code with a variable block length in accordance with embodiments of the present invention;

in FIG. 17 is a block diagram illustrating an internal structure of an apparatus for decoding a block LDPC code in accordance with embodiments of the present invention;

in FIG. 18 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fifth embodiment of the present invention;

in FIG. 19 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a sixth embodiment of the present invention;

in FIG. 20 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a seventh embodiment of the present invention;

in FIG. 21 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to an eighth embodiment of the present invention;

in FIG. 22 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a ninth embodiment of the present invention;

in FIG. 23 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a tenth embodiment of the present invention;

in FIG. 24 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to an eleventh embodiment of the present invention;

in FIG. 25 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a twelfth embodiment of the present invention;

in FIG. 26 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a thirteenth embodiment of the present invention;

in FIG. 27 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fourteenth embodiment of the present invention; and

in FIG. 28 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fifteenth embodiment of the present invention.

Detailed Description of a Preferred Embodiment

Several preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following description, a detailed explanation of the known functions and configurations given here is not presented for brevity.

The present invention provides an apparatus and method for encoding and decoding a block low density parity check (LDPC) code having a variable block length (hereinafter referred to as a "block variable LDPC code with a variable block length"). Thus, the present invention provides an apparatus and method for encoding and decoding a block LDPC code with a variable block length in which the minimum cycle length in the factor graph of the LDPC block code is maximized, the degree of coding of the LDPC block code is minimized, the degree of distribution of the factor graph The block LDPC code has an optimal value of 1, and variable block lengths are supported. Although not separately described, the variable block length LDPC coding and decoding apparatus in accordance with the present invention can be applied to the transmitter / receiver described with reference to FIG. one.

The next generation mobile communication system has been developed as a packet service data transmission system, and the packet service data transmission system, which is a system for transmitting packet data to a plurality of mobile stations, has been designed to match high-bandwidth data transmission capabilities. . To increase data throughput, a hybrid automatic request for data retransmission (HARQ, HAZP) scheme and an adaptive modulation and coding scheme (AMC, AMC) were proposed. Because the HARQ scheme and the AMC scheme support variable coding rates, there is a need for block LDPC codes having different block lengths.

The construction of a block LDPC code with a variable block length, as well as the construction of a conventional LDPC code, is performed using a matrix design with parity. However, in a mobile communication system, to provide a block LDPC code with a variable block length, with one codec, that is, to provide a block LDPC code having different block lengths, the parity check matrix must include parity check matrices to represent block LDPC codes having different block lengths. The following is a description of the parity check matrix of a block LDPC code providing a variable block length.

Initially, a block LDPC code having the minimum block length required in the system is designed for the desired coding rate. In the parity check matrix, if you increase N _s denoting the size of its partial matrix, a block LDPC code having a large block length is obtained. A “partial matrix”, as described above, refers to a permutation matrix corresponding to each of the partial blocks obtained by dividing the parity check matrix into a plurality of partial blocks. If we assume that the block LDPC code is expanded in such a way that first a block LDPC code with a short block length is developed, and then a block LDPC code with a large block length is developed, due to an increase in the size N _{s, the} partial matrix leads to a modification of the loop structure, when In this case, the exponents of the permutation matrices for the parity check matrices are chosen so that the cycle length is maximized. Here, the size of the partial matrix constituting N _s means that the partial matrix is a square matrix having a size of N _s × N _s , and for convenience of description, the size of the partial matrix is represented as N _s .

For example, assuming that the partial block size of the main block LDPC code is N _s = 2, when you want to expand the basic block LDPC code with N _s = 2 to the block LDPC code with N _s = 4 2 times longer than the main block code LDPC, a partial matrix whose exponent is 0 in the permutation matrix, can choose the value 0 or 2 if its length increases from N _s = 2 to N _s = 4. Among these two values, choose a value that maximizes the cycle. Similarly, in a block LDPC code with N _s = 2, a partial matrix with exponent 1 can choose the value 1 or 3 if its length increases from N _s = 2 to N _s = 4.

As described above, it is possible to develop a block LDPC code having maximum performance for each block length by developing a block LDPC code using a basic block LDPC code, while increasing the value of N _s . In addition, one random block LDPC code among block LDPC codes having different block lengths can be defined as a basic block LDPC code, which contributes to an increase in storage efficiency. Next, a description will be given of a method for generating a parity check matrix of a block LDPC code with a variable block length. The present invention provides 4 types of parity check matrices for a variable block length LDPC code according to the coding rate, and the coding rate values discussed in the present invention include 1/2, 2/3, 3/4, and 5/6.

Before describing the parity check matrices of the block LDPC code with a variable block length for coding rates 1/2, 2/3, 3/4, and 5/6, with reference to FIG. 15, a process for encoding a block LDPC code with a variable block length will be described using the parity check matrix developed in the present invention. fifteen.

In FIG. 15 is a flowchart illustrating a process for encoding a block LDPC code with a variable block length in accordance with the first to fourth embodiments of the present invention. Before describing FIG. 15, it is assumed that the parity check matrix for the variable block length LDPC block code consists of 6 partial matrices, as described with reference to FIG. 8.

As shown in FIG. 15, in step 1511, a controller (not shown) receives an information word vector “ s ” intended to be encoded into a variable block length LDPC code, and then proceeds to steps 1513 and 1515. Here, it is assumed that the length of the information vector “ s ” words taken for encoding into the block LDPC code is k. At step 1513, the controller performs matrix multiplication of the received vector “ s ” of the information word by the partial matrix A of the parity matrix (As), and then proceeds to step 1517. Here, since the number of elements having a value of 1 located in the partial matrix A is much less than the number of elements having a value of 0, matrix multiplication (As) of the vector s of the information word and the partial matrix A of the parity check matrix can be obtained with a relatively small number of summation-multiplication operations. In addition, in the partial matrix A, since the positions where the elements having the value 1 are located can be expressed as the exponential multiplication of the positions of the nonzero block and the matrix of permutations of the block, the matrix multiplication can be performed using a very simple operation compared to a random parity check matrix. At step 1515, the controller performs matrix multiplication (C s ) for the partial matrix C in the parity check matrix and the information word vector s , and then proceeds to step 1519.

At step 1517, the controller multiplies the matrices (ET ⁻¹ A s ) by the result of multiplying the matrices (A s ) of the information word vector s and the partial matrix A from the parity check matrix and the matrix ET ^-1 , and then proceeds to step 1519 Here, since the number of elements having a value of 1 in the matrix ET ^-1 is very small, as described above, if the exponent of the matrix of permutations of the block is specified, matrix multiplication can be performed simply. At step 1519, the controller calculates the first parity check vector P ₁ by summing ET ^-1 A s and C s ( P ₁ = ET ^-1 A s + C s ), and then proceeds to step 1521. Here, the summing operation is an exclusive operation OR (XOR), and its result becomes equal to 0 for operations between bits having the same value, and 1 for operations between bits having different values. That is, the process, up to step 1519, is the process of calculating the first parity check vector P ₁ .

At step 1521, the controller multiplies the partial matrix B for the parity check matrix by the first parity check vector P ₁ (B P ₁ ), sums the multiplication result (B P ₁ ) with A s (A s + B P ₁ ), and then goes to step 1523. If the vector s of the information word and the first parity check vector P _{1 are} specified, they should be multiplied by the inverse matrix T ^{−1 of the} partial matrix T of the parity check matrix to calculate the second parity check vector P ₂ . Therefore, in step 1523, the controller multiplies the calculation result (A s + B P ₁ ) in step 1521 by the inverse matrix T ^{−1 of the} partial matrix T to calculate the second parity check vector P ₂ ( P ₂ = T ⁻¹ (A s + B P _1), and then proceeds to step 1525. As described above, if there is a specified vector "s" information word block code LDPC, intended for encoding, can be calculated first vector P ₁ and the parity vector P ₂ of the second parity check and, as a result, all codeword vectors can be obtained. At block 1525, the controller generates a vector p "c" codeword vector using the "s" information word, the first vector P ₁ and the parity vector P ₂ of the second parity check, and transmits the generated vector "c" of the codeword.

Next, with reference to FIG. 16, the internal structure of an apparatus for encoding a block LDPC code with a variable block length is described in accordance with embodiments of the present invention.

In FIG. 16 is a block diagram illustrating an internal structure of an apparatus for encoding a block LDPC code with a variable block length in accordance with embodiments of the present invention. As shown in FIG. 16, an apparatus for encoding a variable block length LDPC block code includes a matrix A multiplier 1611, a matrix C multiplier 1613, an ET ^-1 matrix multiplier 1615, an adder 1617, a matrix B multiplier 1619, an adder 1621, a T matrix multiplier 1623 ^-1 and switches 1625, 1627 and 1629.

If an input signal is received, that is, an information word vector “ s ” of length k, which is to be encoded into a variable block length LDPC code, the received information word vector “ s ” of length k is supplied to switch 1625, matrix-A multiplier 1611, and matrix C multiplier 1613, matrix-A multiplier 1611 multiplies the information word vector " s " by the partial matrix A of the full parity check matrix, and outputs the multiplication result to matrix multiplier 1615 of ET ^-1 and to adder 1621. Matrix-C multiplier 1613 multiplies vector "s" information of words to complete a partial matrix C of the parity check matrix, and outputs the multiplication result to the adder 1617. The multiplier 1615 multiplies a matrix ET ^-1 signal output from the matrix multiplier 1611-A by a partial matrix ET ^-1 full parity check matrix, and outputs the multiplication result to the adder 1617.

y₁, x₂

y₂, x₃

y₃) после обработки с применением операции "исключающее ИЛИ" вектора x = (x₁, x₂, x₃) длиной 3, и вектора y = (y₁, y₂, y₃) длиной 3. Здесь операция

представляет собой операцию "исключающее ИЛИ", результат которой становится равным 0 для операций между битами, имеющими одинаковое значение, и 1 для операций между битами, имеющими разные значения. Сигнал, поступающий с выхода сумматора 1617, становится первым вектором P ₁ проверки на четность.The adder 1617 sums the signal from the output of the calculator 1615 of the matrix ET ^-1 with the signal from the output of the multiplier 1613 of the matrix-C, and outputs the result of the summation to the multiplier 1619 of the matrix-B and the switch 1627. Here, the adder 1617 performs an exclusive OR operation "on a bit by bit basis. For example, if a vector of length 3, which is x = (x ₁ , x ₂ , x ₃ ), and a vector of length 3, which is y = (y _1, y ₂ , y ₃ ), is fed to adder 1617, adder 1617 outputs a vector length 3, which is z = (x ₁

y ₁ , x ₂

y ₂ , x ₃

y ₃ ) after processing using the exclusive OR operation of the vector x = (x ₁ , x ₂ , x ₃ ) of length 3, and the vector y = (y ₁ , y ₂ , y ₃ ) of length 3. Here, the operation

represents an exclusive-OR operation, the result of which becomes 0 for operations between bits having the same value, and 1 for operations between bits having different values. The signal from the output of the adder 1617 becomes the first parity check vector P ₁ .

Matrix-B multiplier 1619 multiplies the signal from the output of adder 1617, that is, the first parity check vector P ₁ , by the partial matrix B of the full parity check matrix, and outputs the multiplication result to adder 1621. Adder 1621 adds the signal coming from the output matrix-B multiplier 1619, to a signal coming from the output of matrix-A multiplier 1611, and outputs the summation result to matrix T ^-1 multiplier 1623. The adder 1621, as well as the adder 1617, performs an exclusive OR operation for the signal coming from the output of the matrix-B multiplier 1619, and the signal coming from the output of the matrix-A multiplier 1611, and outputs the result of the exclusive-OR operation to a multiplier 1623 of the matrix T ^-1 .

The multiplier 1623 of the matrix T ^-1 multiplies the signal from the output of the adder 1621 by the inverse matrix T ^{-1 of the} partial matrix T of the full matrix of the parity check, and outputs the multiplication result to the switch 1629. The output of the multiplier 1623 of the matrix T ^-1 becomes the second vector P ₂ parity checks. Each of the switches 1625, 1627, and 1629 is turned on only during transmission, to transmit an associated signal. A switch 1625 is turned on during the transmission of the information word vector s , a switch 1627 is turned on during the transmission of the first parity vector P ₁ , and a switch 1629 is turned on during the transmission of the second parity vector P ₂ .

Since embodiments of the present invention should be capable of generating a block LDPC code with a variable block length, each of the matrices used in the encoding device of FIG. 16 for a variable block length LDPC block code, change each time a parity check matrix of a variable block length LDPC code is changed, as will be described with reference to FIG. 17. Therefore, although not separately shown in FIG. 16, the controller modifies the matrices used in the encoding device for the variable block length LDPC block code as the parity check matrix of the variable block length LDPC code is changed.

The above is a description of a method for generating a block LDPC code with a variable block length taking into account effective coding. As described above, a block LDPC code with a variable block length due to its structural characteristics is preferred for ensuring memory efficiency, for storing information related to a parity check matrix, and allows for efficient coding by appropriately selecting partial matrices from the check matrix for parity. However, as the parity check matrix is generated block by block, its randomness decreases, and a decrease in randomness can lead to a deterioration in the performance of the block LDPC code. Thus, since an irregular block LDPC code has better performance than a regular block LDPC code, as described above, it is very important to select partial matrices from the full parity check matrix when developing block LDPC code.

Below, with reference to FIG. 11, a detailed method is described for generating a block LDPC code with a variable block length for a 1/2 coding rate.

, и верхний индекс a_pq матрицы P перестановок равен либо In FIG. 11 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a first embodiment of the present invention. Before describing FIG. 11, it should be noted that, in a first embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 1/2. As shown in FIG. 11, assuming that the possible size N _{s of the} partial matrices is 4, 8, 12, 16, 20, 24, 28, 32, 36, and 40, it becomes possible to generate a block LDPC code having a length of 96, 192, 288, 384, 480, 576, 672, 768, 864, and 960 using the parity check matrix shown in FIG. 11. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 11 represents the exponential value of the corresponding permutation matrix. Here, the parity check matrix of a block LDPC code with a variable block length consists of a plurality of partial blocks, and partial matrices, individually corresponding to partial blocks, constitute a permutation matrix. For example, if the matrix parity check matrix of a block LDPC code with a variable block length consists of pxq partial blocks, that is, if the number of rows of partial blocks in a parity check matrix for a block LDPC code with a variable block length is “p” and the number of columns of partial blocks in the parity check matrix for a variable-length block LDPC code is “q”, the permutation matrices constituting the parity check matrix of a variable-length LDPC block code can be expressed as

, and the superscript a _{pq of} the permutation matrix P is either

перестановок представляет собой матрицу перестановок, расположенную в частичном блоке, где p-ая строка и q-ый столбец матрицы проверки на четность блочного кода LDPC с переменной длиной блока, состоящего из множества частичных блоков, пересекают друг друга. Поэтому экспонентное значение матрицы перестановок, представленное на фиг. 11, приведено как a_pq, и путем выполнения операции модуль-N_s (где N_s соответствует размеру частичной матрицы) для экспоненциального значения матрицы перестановок, становится возможным рассчитать экспонентное значение матрицы перестановок для матрицы проверки на четность для блочного кода LDPC с переменной длиной блока, имеющей значение N_s. Если значение, полученное в результате выполнения операции модуль- N_s для экспоненты матрицы перестановок равно 0, соответствующая матрица перестановок становится единичной матрицей.0 ≤ a _pq ≤ N _s -1 or a _pq = ∞. So the matrix

permutation is a permutation matrix located in a partial block, where the pth row and qth column of the parity check matrix of a block LDPC code with a variable block length consisting of many partial blocks intersect each other. Therefore, the exponential value of the permutation matrix shown in FIG. 11 is shown as a _pq , and by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponential value of the permutation matrix, it becomes possible to calculate the exponential value of the permutation matrix for the parity matrix for the block LDPC code with a variable block length having a value of N _s . If the value obtained as a result of the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

For a detailed description of the present invention, the following parameters will be defined.

The parity check matrix of the variable block length LDPC code shown in FIG. 11 is called the “mother matrix,” the number of nonzero permutation matrices among the partial matrices, that is, the permutation matrices that make up the mother matrix, is defined as L, the exponents L of non-zero permutation matrices, among the permutation matrices that make up the mother matrix, are presented as a ₁ , a ₂ , ..., al, and the size of the permutation matrices constituting the parent matrix is assumed to be N _s . Since the number of nonzero permutation matrices among the permutation matrices that make up the parent matrix is L, the exponent of the first permutation matrix becomes a ₁ , the exponent of the second permutation matrix becomes a ₂ , and thus, the exponent of the last permutation matrix becomes aL.

Unlike the parent matrix, the parity matrix that needs to be regenerated is called the “daughter matrix,” the number of nonzero permutation matrices among the partial matrices, that is, the permutation matrices that make up the daughter matrix, is defined as L, the size of the permutation matrices that make up a daughter matrix is defined as N _s ′, and the exponents of the permutation matrices that make up the daughter matrix are represented as a ₁ ', a ₂ ', ..., al '. Since the number of nonzero permutation matrices among the permutation matrices constituting the daughter matrix is L, the exponent of the first permutation matrix becomes a ₁ ', the exponent of the second permutation matrix becomes a ₂ ' and, therefore, the exponent of the last permutation matrix becomes aL '.

Using equation (5) below, it is possible to generate a daughter matrix having a variable block length by selecting the size N _s ′ of the permutation matrices constituting the daughter matrix to be generated from one parent matrix.

a _i '= a _i modN _s ' (for 1 ≤ i ≤ L) (5)

Next, with reference to FIG. 12, a detailed description is given of a method for generating a block LDPC code with a variable block length for a coding rate of 2/3.

In FIG. 12 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a second embodiment of the present invention. Before describing FIG. 12, it should be noted that in a second embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 2/3. As shown in FIG. 12, assuming that the possible size N _{s of the} partial matrices is 8 and 16, it is possible to generate a block LDPC code having a length of 288 and 576 using the parity check matrix shown in FIG. 12. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 12 is the exponential value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value Ns can be calculated. If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 13, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 3/4 coding rate.

In FIG. 13 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a third embodiment of the present invention. Before describing FIG. 13, it should be noted that in a third embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a 3/4 coding rate. As shown in FIG. 13, assuming that the possible size N _{s of the} partial matrices is 3, 6, 9, 12, 15, and 18, it is possible to generate a block LDPC code having a variable length of 96, 192, 288, 384, 480, and 576 using a check matrix on the parity shown in FIG. 13. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 13 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 14, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 5/6 coding rate.

In FIG. 14 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fourth embodiment of the present invention. Before describing FIG. 14, it should be noted that in a fourth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a 5/6 coding rate. As shown in FIG. 14, assuming that the possible size N _{s of the} partial matrices is 8 and 16, it is possible to generate a block LDPC code having a length of 288 and 576 using the parity check matrix shown in FIG. 14. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 14 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 18, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 1/2 coding rate.

In FIG. 18 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fifth embodiment of the present invention. Before describing FIG. 18, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 1/2. As shown in FIG. 18, it is possible to generate a block LDPC code of length 48N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 18. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 18 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 19, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a coding rate of 2/3.

In FIG. 19 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a sixth embodiment of the present invention. Before describing FIG. 19, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 2/3. As shown in FIG. 19, it is possible to generate a block LDPC code of length 48N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 19. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 19 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 20, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 3/4 coding rate.

In FIG. 20 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a seventh embodiment of the present invention. Before describing FIG. 20, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a 3/4 coding rate. As shown in FIG. 20, it is possible to generate a block LDPC code of length 48N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 20. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 20 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 21, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 3/4 coding rate.

In FIG. 21 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to an eighth embodiment of the present invention. Before describing FIG. 21, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a 3/4 coding rate. As shown in FIG. 21, it is possible to generate a block LDPC code of length 48N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 21. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 21 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 22, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 1/2 coding rate.

In FIG. 22 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a ninth embodiment of the present invention. Before describing FIG. 22, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 1/2. As shown in FIG. 22, it is possible to generate a block LDPC code of 24N _S length in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 22. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 22 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 23, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 1/2 coding rate.

In FIG. 23 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a tenth embodiment of the present invention. Before describing FIG. 23, it should be noted that, in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 1/2. As shown in FIG. 23, it is possible to generate a block LDPC code with a length of 24 N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 23. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 23 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 24, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a coding rate of 2/3.

In FIG. 24 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to an eleventh embodiment of the present invention. Before describing FIG. 24, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 2/3. As shown in FIG. 24, it is possible to generate a block LDPC code of length 24N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 24. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 24 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 25, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a coding rate of 2/3.

FIG. 25 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a twelfth embodiment of the present invention. Before describing FIG. 25, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 2/3. As shown in FIG. 25, it is possible to generate a block LDPC code of length 24N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 25. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 25 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 26, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 1/2 coding rate.

In FIG. 26 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a thirteenth embodiment of the present invention. Before describing FIG. 26, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 1/2. As shown in FIG. 26, it is possible to generate a block LDPC code of length 24N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 26. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 26 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 27, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a 1/2 coding rate.

In FIG. 27 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fourteenth embodiment of the present invention. Before describing FIG. 27, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 1/2. As shown in FIG. 27, it is possible to generate a block LDPC code of 24N _S length in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 27. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 27 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

Next, with reference to FIG. 28, a detailed description will be given of a method for generating a block LDPC code with a variable block length for a coding rate of 2/3.

In FIG. 28 is a diagram illustrating a parity check matrix of a variable block length LDPC code block according to a fifteenth embodiment of the present invention. Before describing FIG. 28, it should be noted that in a fifth embodiment of the present invention, there is provided a parity check matrix of a block LDPC code with a variable block length for a coding rate of 2/3. As shown in FIG. 28, it is possible to generate a block LDPC code with a length of 24N _S in accordance with the size N _{s of the} partial matrix using the parity check matrix shown in FIG. 28. The value recorded in each of the partial blocks, that is, in the partial matrices shown in FIG. 28 is the exponent value of the corresponding permutation matrix. Therefore, by performing the module-N _s operation (where N _s corresponds to the size of the partial matrix) for the exponent of the permutation matrix, we can calculate the exponent of the permutation matrix for the parity check matrix for the block LDPC code having the value N _s . If the value obtained from the module-N _s operation for the exponent of the permutation matrix is 0, the corresponding permutation matrix becomes the identity matrix.

All codes of the LDPC family can be decoded in a factor graph using the intermediate result algorithm. The LDPC code decoding scheme can be roughly divided into a bidirectional transmission scheme and a stream transmission scheme. When the decoding operation is performed using the bidirectional transmission scheme, each verification node has a node processor that increases the decoding complexity in proportion to the number of verification nodes. However, since all verification nodes are updated at the same time, the decoding speed is significantly increased.

In contrast, the flow transmission scheme has one node processor, and the node processor updates information passing through all nodes in the factor graph. Therefore, the flow transmission scheme has less decoding complexity, but with an increase in the size of the parity check matrix, that is, with an increase in the number of nodes, the decoding speed decreases. However, if the parity check matrix is generated block by block, as in the LDPC block code with a variable block length having different block lengths in accordance with the coding rate proposed in the present invention, then the number of node processors equal to the number of blocks making up the parity check matrix is used. In this case, it is possible to execute a decoder that has less decoding complexity than the bidirectional transmission scheme and a higher decoding speed than the stream transmission scheme.

Next, with reference to FIG. 17, a description is made of the internal structure of a decoding apparatus for decoding a block LDPC code with a variable block length using a parity check matrix in accordance with an embodiment of the present invention.

In FIG. 17 is a block diagram illustrating an internal structure of an apparatus for decoding a block LDPC code in accordance with embodiments of the present invention. As shown in FIG. 17, a decoding apparatus for decoding a block LDPC code with a variable block length includes a block controller 1710, a variable node part 1700, an adder 1715, an interleaver 1717, an interleaver 1719, a controller 1721, a memory device 1723, an adder 1725, part 1750 the verification node and the hard decision block 1729. The variable node portion 1700 includes a variable node decoder 1711 and switches 1713 and 1714, and the verification node portion 1750 includes a verification node decoder 1727.

The signal received over the air is supplied to a block controller 1710. The block controller 1710 determines the block size of the received signal. If there is a part of the information word punctured in the encoding device corresponding to the decoding device, the block controller 1710 inserts “0” into the punctured part of the information word to adjust the block to full size and outputs the resulting signal to the variable node decoder 1711.

The variable node decoder 1711 calculates the probability values of the signal from the block controller 1710, updates the calculated probability values and outputs the updated probability values to the switches 1713 and 1714. The variable node decoder 1711 connects the variable nodes in accordance with the parity check matrix previously set in the decoding device for an irregular block LDPC code, and does the update job for as many input values and output values as the number of units connected to AC nodes. The number of units connected to variable nodes is equal to the weight of each column making up the parity check matrix. The internal operation of the variable node decoder 1711 is different in accordance with the weight of each column constituting the parity check matrix. Unless the switch 1713 is turned on, the switch 1714 is turned on to output the output signal of the variable node decoder 1711 to the adder 1715.

The adder 1715 receives the signal from the output of the decoder 1711 of the variable node, and the output signal of the interleaver 1719 in the previous iterative decoding process, subtracts the output signal of the interleaver 1719 in the previous iterative decoding process from the output signal of the decoder 1711 of the variable node, and outputs the subtraction result to the inverse interleaver 1717 If the decoding process is the original decoding process, it should be considered that the output signal of the interleaver 1719 is 0.

Reverse interleaver 1717 interleaves the signal from the adder 1715 in accordance with a predetermined interleaving scheme and outputs the signal after interleaving to the adder 1725 and the decoder 1727 of the verification node. The inverse interleaver 1717 has an internal structure corresponding to the parity check matrix, since the output value for the input value of the interleaver 1719 corresponding to the inverse interleaver 1717 differs according to the position of elements having a value of 1 in the parity check matrix.

The adder 1725 receives the output signal of the decoder 1727 of the verification node in the previous iterative decoding process and the output signal of the deinterleaver 1717, subtracts the output signal of the deinterleaver 1717 from the output of the decoder 1727 of the verification node in the previous iterative decoding process and outputs the subtraction result to the interleaver 1719. Node decoder 1727 checks connects the nodes of the check in accordance with the matrix parity set previously in the decoding device for the block LDPC code, and performs the operation This update is for the number of input values and output values equal to the number of units connected to the test nodes. The number of units connected to the check nodes is equal to the weight of each of the lines that make up the parity check matrix. Therefore, the internal operation of the decoder 1727 of the check node is different in accordance with the weight of each of the lines constituting the parity check matrix.

The interleaver 1719, under the control of the controller 1721, interleaves the signal from the output of the adder 1725, in accordance with the specified interleaving circuit, and outputs the signal after interleaving to the adder 1715 and the decoder 1711 of the variable node. The controller 1721 reads information related to the interleaving scheme previously stored in the storage device 1723, and performs control of the interleaving circuit of the interleaver 1719 and the reverse interleaving circuit of the interleaver 1717, in accordance with the read interleaving circuit information. Since only the mother matrix is recorded in the storage device 1723, with which a block variable-length LDPC code can be generated, the controller 1721 reads the mother matrix stored in the storage device 1723 and generates the exponents of the permutation matrices constituting the corresponding daughter matrix using size N _s ′ of the permutation matrix corresponding to the given block size. In addition, the controller 1721 controls the interleaver interleaver 1719 and the reverse interleaver deinterleaver 1717 using the generated daughter matrix. Similarly, if the decoding process is an initial decoding process, it should be considered that the output signal of the deinterleaver 1717 is 0.

As a result of the iterative execution of the above processes, the decoding device performs reliable decoding without errors. After performing iterative decoding a predetermined number of times, the switch 1714 turns off the connection between the variable node decoder 1711 and the adder 1715, and the switches 1713 turn on the connection between the variable node decoder 1711 and the hard decision block 1729 for transmitting the output signal from the variable node decoder 1711 to the hard decision block 1729 solutions. The hard decision block 1729 makes a hard decision on the signal from the output of the variable node decoder 1711 and outputs the result of the hard decision, and the output of the hard decision block 1729 becomes the finally decoded value.

As can be seen from the previous description, the present invention provides a block LDPC code with a variable block length in which the minimum cycle length is maximized in a mobile communication system, thereby providing maximum error correction capabilities and thereby improving system performance. In addition, an effective parity check matrix is generated in the present invention, thereby minimizing the complexity of decoding a block LDPC code with a variable block length. In addition, the present invention proposes such a design of a block LDPC code with a variable block length such that the complexity of its decoding should be proportional to its block length, thus providing the possibility of efficient coding. In particular, in the present invention, a block LDPC code is generated that can be applied to different coding rates and different block lengths, thereby helping to minimize hardware complexity.

Although the invention has been shown and described with reference to a certain preferred embodiment, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (15)

1. The method of generating a block code parity check with low density (LDPC), namely, that
take the information word and
generating a block LDPC code by encoding an information word using one of the first parity check matrix and the second parity check matrix depending on the length to be used when generating the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a predetermined number of partial blocks, and each of the partial blocks has a predetermined size, and
when the coding rate is 1/2, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 2. A method of generating a block code parity check with low density (LDPC), namely, that
take the information word and
generating a block LDPC code by encoding an information word using one of the first parity check matrix and the second parity check matrix depending on the length to be used when generating the block LDPC code, the second parity check matrix being a parity check matrix, determined by changing the size of the first parity check matrix, wherein the first parity check matrix is a parity check matrix generated so that the block the LDPC code has a predetermined length and is satisfied at a given coding rate, the first parity check matrix includes a given number of partial blocks, and each of the partial blocks has a given size, and when the coding rate is 2/3, the first parity check matrix expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 3. A method of generating a block code parity check with low density (LDPC), namely, that
receive the information word and generate the block LDPC code by encoding the information word using one of the first parity check matrix and the second parity check matrix depending on the length to be used when generating the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a predetermined number of partial blocks, and each of the partial blocks has a predetermined size, and
when the coding rate is 3/4, the first parity check matrix is expressed as one of the following 3 tables

where in each of these 3 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 4. An apparatus for generating a low density block parity check (LDPC) code comprising
an encoder for receiving an information word, generating a block LDPC code by encoding an information word using one of the first parity check matrix and the second parity check matrix depending on the length to be used when generating the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a given number of partial blocks, and each of the partial blocks has a given size, and when the speed encoding is 1/2, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponents of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 5. An apparatus for generating a low density block parity check (LDPC) code comprising
an encoder for receiving an information word, generating a block LDPC code by encoding an information word using one of the first parity check matrix and the second parity check matrix depending on the length to be used in generating the block LDPC code, the second parity check matrix representing a parity check matrix determined by changing the size of the first parity check matrix, wherein the first parity check matrix is a check matrix parity generated so that the block LDPC code has a given length and is satisfied at a given coding rate, the first parity check matrix includes a given number of partial blocks, and each of the partial blocks has a given size, and when the coding rate is 2 / 3, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponents of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 6. A device for generating a block low-density parity check code (LDPC), comprising an encoder for receiving an information word, generating a block LDPC code by encoding an information word using one of the first parity check matrix and the second parity check matrix, depending on the length to be used when generating the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a predetermined number of partial blocks, and each of the partial blocks has a predetermined size, and
when the coding rate is 3/4, the first parity matrix is expressed as one of the following 3 tables

where in each of these 3 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 7. The method of decoding a block code parity check with low density (LDPC), which consists in the fact that the receive signal
one of the first parity check matrix and the second parity check matrix are selected in accordance with the length of the block LDPC code for decoding, and the received signal is decoded in accordance with the selected parity check matrix, thereby detecting the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a given number of partial blocks, and each of the partial blocks has a given size, and when the speed encoding is 1/2, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 8. A method for decoding a block low-density parity check (LDPC) code, wherein
receive the signal and
one of the first parity check matrix and the second parity check matrix are selected in accordance with the length of the block LDPC code for decoding, and the received signal is decoded in accordance with the selected parity check matrix, thereby detecting the block LDPC code, wherein the second the parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, wherein the first parity check matrix is a pro The parity check generated so that the block LDPC code has a given length and is satisfied at a given coding rate, the first parity check matrix includes a given number of partial blocks, and each of the partial blocks has a given size, and when the coding rate is 2 / 3, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 9. A method for decoding a block low-density parity check (LDPC) code, wherein
receive the signal and select one of the first parity check matrix and the second parity check matrix in accordance with the length of the block LDPC code for decoding, and decode the received signal in accordance with the selected parity check matrix, thereby detecting the block LDPC code ,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a predetermined number of partial blocks, and each of the partial blocks has a predetermined size, and
when the coding rate is 3/4, the first parity check matrix is expressed as one of the following 3 tables

where in each of these 3 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 10. A device for decoding a block code parity check with low density (LDPC) containing
a receiver for receiving a signal and
a decoder for selecting one of the first parity check matrix and the second parity check matrix in accordance with the length of the block LDPC code for decoding and decoding the received signal in accordance with the selected parity check matrix, thereby detecting the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a given number of partial blocks, and each of the partial blocks has a given size, and when the speed encoding is 1/2, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponents of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 11. A device for decoding a block low-density parity check code (LDPC), comprising
a receiver for receiving a signal and
a decoder for selecting one of the first parity check matrix and the second parity check matrix in accordance with the length of the block LDPC code for decoding and decoding the received signal in accordance with the selected parity check matrix, thereby detecting the block LDPC code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a predetermined number of partial blocks, and each of the partial blocks has a predetermined size, and
when the coding rate is 2/3, the first parity check matrix is expressed as one of the following 5 tables

where in each of these 5 tables, the blocks represent partial blocks, the numbers represent the exponents of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped. 12. A device for decoding a block low-density parity check (LDPC) code, comprising
a receiver for receiving a signal and a decoder for selecting one of the first parity check matrix and the second parity check matrix in accordance with the length of the block LDPC code for decoding and decoding the received signal in accordance with the selected parity check matrix, thereby detecting , LDPC block code,
moreover, the second parity check matrix is a parity check matrix determined by changing the size of the first parity check matrix, while the first parity check matrix is a parity check matrix generated so that the block LDPC code has a given length and is satisfied when a given coding rate, and the first parity check matrix includes a predetermined number of partial blocks, and each of the partial blocks has a predetermined size, and
when the coding rate is 3/4, the first parity matrix is expressed as one of the following 3 tables

where in each of these 3 tables, the blocks represent partial blocks, the numbers represent the exponentials of the corresponding permutation matrices, and the blocks without numbers represent the partial blocks onto which the zero matrices are mapped.
Priorities: December 13, 2004 according to claims 1, 4, 7, 10; 01/14/2005 according to claims 2, 5, 8, 11; 08/16/2004 according to claims 3, 6, 9, 12.

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