RU2348103C2 - Device and method for coding and decoding of block code of low density parity check - Google Patents

Abstract

FIELD: physics, radio.

SUBSTANCE: invention is related to device and method for coding of block code of low density parity check (LDPC). Substance of invention consists in the fact that during reception of information word vector coder codes vector of information word into block code of LDPC in compliance with preset generating matrix. Modulator modulates block code LDPC into modulation symbol using preset modulation pattern. Transmitter sends modulation symbol.

EFFECT: provision of decoding reliability with minimization of LDPC block code coding complexity.

11 cl, 17 dwg

Description

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The present invention relates to an apparatus and method for encoding and decoding block LDPC (Sparse Parity Check) codes.

Description of the Related Art

In connection, the most significant problem is the efficient and reliable transmission of data over the channel. The next generation mobile multimedia communication system, which is being investigated, requires a high-speed communication system capable of processing and transmitting various information, such as images or broadcast data, in addition to the previous voice-oriented service. Therefore, it is necessary to increase the efficiency of the system by using a channel coding scheme suitable for the system.

Data transmission inevitably suffers from errors due to noise, interference and fading in accordance with the conditions of the channel, thereby causing the loss of a large amount of information. In order to reduce the loss of information, various error control schemes are currently being used, which are based in part on channel characteristics, thereby improving the reliability of the mobile communication system. The most basic error correction scheme uses error correction codes.

1 is a diagram illustrating a transceiver in a conventional mobile communication system. Referring to FIG. 1, in a transmitter, a transmission message 'u' is encoded by an encoder 101 using a predetermined coding scheme before being transmitted over a channel. The encoded symbol 'c' encoded by encoder 101 is modulated by a modulator 103 using a predetermined modulation scheme, and the modulated signal 's' is transmitted to the receiver on channel 105.

At the receiver, the received signal 'r' is a distorted signal in which the signal 's' transmitted by the transmitter is mixed with several noises according to channel conditions. The received signal 'r' is demodulated by the demodulator 107 using a demodulation scheme corresponding to the modulation scheme used in the transmitter modulator 103, and the demodulated signal 'x' is decoded by the decoder 109 using the decoding scheme corresponding to the encoding scheme used in the encoder 101 of the transmitter. A signal decoded by decoder 109 is denoted by û .

Accordingly, there is a need for a high-performance channel encoder and decoder for the receiver to be able to recover the 'u' signal transmitted by the transmitter without error. In particular, when channel 105 is a wireless channel, errors caused by the channel should be considered more seriously. Receiver decoder 109 may evaluate the transmission message based on data received on channel 105.

In connection with the rapid development of the mobile communication system, there is a need for a technology capable of transmitting data in a wireless network having a large capacity approaching that of a wireless network. Since there is a need for a high-speed, high-performance communication system capable of processing and transmitting multimedia data, for example, image and broadcast data, in addition to the voice-oriented service, it is necessary to increase transmission efficiency in the system by using a suitable channel coding scheme to improve system performance. However, the mobile communication system inevitably suffers from errors that usually occur due to noise, interference and fading according to channel conditions during data transmission. As described above, the occurrence of errors causes the loss of information data.

In order to reduce the loss of information data due to errors, it is possible to improve the reliability of a mobile communication system by using error control techniques. A technique that uses error correction codes is the most common error control technique used. A description will now be made of turbo codes and LDPC (Sparse Parity Check) codes, which are common error correction codes.

It is well known that turbo code is superior in performance enhancement to the convolutional code traditionally used to correct errors during high-speed data transfer. The turbo code is advantageous in that it can efficiently correct an error caused by noise generated in the transmission channel, thereby increasing the reliability of data transmission.

The LDPC code can be decoded using an iterative decoding algorithm based on the sum-product algorithm in the factor graph. Since the decoder uses an iterative decoding algorithm for the LDPC code based on the sum-product algorithm, it is less complex with respect to the decoder for the turbo code. In addition, the decoder for the LDPC code is easy to implement using a parallel processing decoder, compared to a decoder for a turbo code.

Shannon’s channel coding theorem shows that reliable communication is only possible with a data rate that does not exceed the bandwidth of the communication channel. However, Shannon’s channel coding theorem did not propose a detailed coding and decoding method for the channel to maintain the data rate to the maximum bandwidth of the communication channel. Although a random code having a very large block size shows performance approaching the bandwidth limit of the communication channel according to the Shannon theorem on channel coding, it is practically impossible to implement a decoding method with a maximum a posteriori probability (MAP) or the most plausible (ML) due to its complex computational load.

The turbo code was proposed by Burrow, Glavo and Titimajshima in 1993 and has higher performance, approaching the limit of the bandwidth of the communication channel according to the Shannon theorem on channel coding. The turbo code proposal initiated an active study on iterative decoding and graphical representation of codes, and the LDPC codes proposed by Gallagher in 1962 are once again the focus of research. Loops exist in the multiplier graph of the turbo code and LDPC code, and it is well known that iterative decoding in the multiplier graph of the LDPC code, where loops exist, is conditionally optimal. It has also been experimentally proven that LDPC code has excellent iterative decoding performance. It is known that the LDPC code has the highest performance that performance has ever shown, having a difference of only about 0.04 [dB] at the limit of the throughput of the communication channel according to the Shannon theorem on channel coding at the occurrence frequency of error bits (BER) 10 ^-5 using a block size of 10 ⁷ . In addition, although the LDPC code defined in the Galois field (GF) with q> 2, i.e. GF (q), increases the complexity in its decoding, it is superior in its performance to binary code. However, a satisfactory theoretical description of successful decoding by means of an iterative decoding algorithm for the LDPC code defined in GF (q) is not provided.

The LDPC code proposed by the Gallagher is determined by means of a parity check matrix in which the main elements have a value of 0 and secondary elements, i.e. elements that do not have a value of 0 have a value of 1. For example, the LDPC code (N, j, k) is a linear block code having a block length of N, and is determined by a sparse parity check matrix in which each column has j elements with a value of 1 , each row has k elements having a value of 1, and all elements except elements having a value of 1 have a value of 0.

An LDPC code in which the weight of each column in the parity matrix is fixed to 'j' and the weight of each row in the parity matrix is fixed to 'k', as described above, is called the “regular LDPC code”. In this document, "weight" refers to the number of elements having a non-zero value among the elements included in the generator matrix and the parity matrix. Unlike a regular LDPC code, an LDPC code in which the weight of each column in the parity matrix and the weight of each row in the parity matrix are not fixed is called an “irregular LDPC code”. It is well known that irregular LDPC code is higher in performance with respect to the regular LDPC code. However, in the case of an irregular LDPC code, since the weight of each column and the weight of each row in the parity matrix are not fixed, i.e. irregular, the weight of each column in the parity matrix and the weight of each row in the parity matrix must be properly set in order to guarantee excellent performance.

2 is a diagram illustrating a parity check matrix of a common LDPC code (8, 2, 4). Referring to FIG. 2, the LDPC code parity check matrix H (8, 2, 4) has 8 columns and 4 rows, in which the weight of each column is fixed at 2 and the weight of each row is fixed at 4. Since the weight of each column and the weight of each the rows in the parity matrix are regular, the LDPC code (8, 2, 4) illustrated in FIG. 2 becomes the regular LDPC code.

FIG. 3 is a diagram illustrating a graph of multipliers of the LDPC code (8, 2, 4) in FIG. 2. Referring to FIG. 3, the multiplier graph of the LDPC code (8, 2, 4) includes 8 variable nodes x ₁ 300, x ₂ 302, x ₃ 304, x ₄ 306, x ₅ 308, x ₆ 310, x ₇ 312 and x ₈ 314 and 4 of the control nodes 316, 318, 320 and 322. When the element having a value of 1, i.e. a nonzero value exists at the point where the i-th row and j-th column of the LDPC code parity matrix (8, 2, 4) intersect each other, a branch is created between the variable node x _i and the control j-th node.

Since the LDPC code parity matrix is very lightweight, it is possible to perform decoding by iterative decoding, even in a block code having a relatively large size, which shows performance approaching the bandwidth limit of the communication channel according to Shannon’s channel coding theorem, for example, turbo code, while the block code block size is constantly increasing. Mack Kay and Neil have proven that the iterative process of decoding an LDPC code using a flowchart diagram approaches the iterative process of decoding a turbo code in terms of performance.

In order to generate a high-performance LDPC code, the following conditions must be met.

(1) The cycles in the multiplier graph of the LDPC code should be taken into account.

The term “loop” refers to a loop formed by faces connecting variable nodes to control nodes in the multiplier graph of the LDPC code, and the length of the loop is defined as the number of faces making up the loop. The loop cycle means that the number of faces connecting the variable nodes to the control nodes that make up the loop in the multiplier graph of the LDPC code is large. In contrast, a short loop means that the number of faces connecting the variable nodes to the control nodes that make up the loop in the factor graph of the LDPC code is small.

As the cycles in the LDPC code factor graph become longer, the relative performance level of the LDPC code increases. Those. when long loops are formed in the LDPC code factor graph, it becomes possible to prevent performance degradation, for example, the minimum level of error that occurs when too many short-cycle cycles exist in the LDPC code factor graph.

(2) Effective coding of the LDPC code should be taken into account

LDPC code is difficult to encode in real time, compared to a convolutional code or turbo code due to the high complexity of its coding. In order to reduce the encoding complexity of the LDPC code, an RA (re-accumulation) code is proposed. However, the RA code also has a limit in reducing the encoding complexity of the LDPC code. Therefore, efficient coding of the LDPC code must be taken into account.

(3) The degree distribution in the factor graph of the LDPC code should be taken into account.

In general, an irregular LDPC code is superior in performance to a regular LDPC code, since the factor graph of an irregular LDPC code has varying degrees. The term “degree” refers to the number of faces connected to variable nodes and control nodes in the multiplier graph of the LDPC code. Additionally, the phrase “degree distribution” in the factor graph of the LDPC code refers to the ratio of the number of nodes having a specific degree to the total number of nodes. In addition, Richardson proved that LDPC code with a specific degree distribution is superior in performance.

4 is a diagram illustrating a parity matrix for a common block LDPC code. However, before the description of FIG. 4 is given, it should be noted that the block LDPC code is a new LDPC code, that efficient coding and efficient storage and improved performance of the parity matrix are taken into account, and the block LDPC code is an LPDC code extended by generalizing the structure of the regular LDPC code.

представляет матрицу перестановок, расположенную в частном блоке, где p-тая строка и q-тый столбец матрицы контроля четности, содержащей множество частных блоков, пересекают друг друга. Более конкретно, 'p' и 'q' представляют собой число строк и число столбцов частных блоков, сопоставленных, соответственно, информационной части в матрице контроля четности.Referring to FIG. 4, a parity check matrix of a block LDPC code is divided into a plurality of private blocks, and a permutation matrix is mapped to each of the private blocks. 4, 'P' represents a permutation matrix having a size N _s xN _s and a superscript (or exponent) a _{pq of} the permutation matrix P is either 0 _pqs -l or a _pq =. In addition, 'p' indicates that the corresponding permutation matrix is located in the pth row of partial blocks of the parity matrix, and 'q' indicates that the corresponding permutation matrix is located in the qth column of partial blocks of the parity matrix. I.e

represents a permutation matrix located in a private block, where the pth row and the qth column of the parity matrix containing many private blocks intersect each other. More specifically, 'p' and 'q' represent the number of rows and the number of columns of the private blocks associated, respectively, of the information part in the parity matrix.

5 is a diagram illustrating a permutation matrix P of FIG. 4. As illustrated in Figure 5, the permutation matrix P is a square matrix having a size of N _s xN _s and each of the columns N _s, is included in the permutation matrix P has a weight of 1 and each of the rows N _s, included in the permutation matrix P also It has a weight of 1. In this document, although the size and the permutation matrix P is expressed as N _s xN _s, it will also be expressed also as N _s, because the permutation matrix P is a square matrix.

In Fig. 4, the permutation matrix P with superscript a _pq = 0, i.e. the permutation matrix P ° is the identity matrix I _NsxNs and the permutation matrix P with the superscript a _pq =, i.e. permutation matrix P is a zero matrix. In this document, I _NsxNs is a unit matrix of size N _s xN _s .

In the full parity check matrix of the block LDPC code illustrated in FIG. 4, since the total number of rows is N _s xp and the total number of columns is N _s xq (for p), when the full LDPC code parity matrix has a full rank, the code rate can be expressed by equation (1) regardless of the size of the private blocks.

If a _pq for all p and q, then the permutation matrices corresponding to the private blocks are not null matrices and the private blocks compose a regular LDPC code in which the weight value of each column and the weight value of each row in each of the permutation matrices corresponding to the private blocks are p and q respectively. In this document, each of the permutation matrices corresponding to the private blocks will be referred to as a “private matrix”.

Since dependent rows (p-1) exist in the parity check matrix, the coding rate is higher than the coding rate calculated by equation (1). In the block LDPC code, if the position of the weight of the first row of each of the partial matrices included in the full matrix of the parity is determined, then the position of the weights of the remaining rows (N _s -1) can be determined. Therefore, the required memory size is reduced to 1 / N _S , compared with when the weights are irregularly selected for storing information in the entire parity matrix.

As described above, the term “loop” refers to a loop formed by faces connecting the variable nodes to the control nodes in the factor graph of the LDPC code, and the cycle length is defined as the number of faces making up the loop. A long cycle means that the number of faces connecting the variable nodes to the control nodes that make up the loop in the multiplier graph of the LDPC code is large. As the cycles in the multiplier graph of the LDPC code become longer, the relative performance level of the LDPC code increases. In contrast, when the cycles in the multiplier graph of the LDPC code become shorter, the possibility of correcting errors in the LDPC code increases, since performance degradation, for example, the minimum error level, occurs. That is, when there are many small cycles of small length in the factor graph of the LDPC code, information on a particular node belonging to a small cycle, starting from it, is returned after a small number of iterations. When the number of iterations increases, the information returns to the corresponding node more often, so that the information cannot be updated correctly, thereby impairing the ability to correct LDPC code errors.

6 is a diagram illustrating a loop structure of a block LDPC code whose parity matrix includes 4 partial matrices. However, before the description of FIG. 6, it should be noted that the block LDPC code is a new LDPC code, that efficient coding and efficient storage and improved performance of the parity matrix were taken into account. The block LDPC code is also an LDPC code extended by generalizing the structure of a regular LDPC code.

The parity check matrix of the block LDPC code illustrated in FIG. 6 includes 4 private blocks. The diagonal line represents the position where the elements having a value of 1 and the parts other than the parts on the diagonal are located, represent the positions in which the elements having a value of 0 are located. In addition, 'P' represents the same permutation matrix that and a permutation matrix described in connection with FIG.

In order to analyze a cycle structure of a block code, LDPC, illustrated in Figure 6, an element having a value of 1 located in an i-th row of the partial matrix P ^a, is defined as a reference element and an element having a value of 1 located in an i-one line, will be indicated as "mark-0". As used herein, a “private matrix” will refer to a matrix corresponding to a private block. The 0 located in the (i + a) th column of the partial matrix P ^a.

An element having a value of 1 in the partial matrix P ^b located in the same row as the zero mark will be indicated as “mark-1”. For the same reason as mark-0, mark-1 is located in the (i + b) -th column of the partial matrix P ^b .

An element having a value of 1 in the partial matrix P ^c located in the same column as mark-1 will be indicated as “mark-2”. Since the partial matrix P ^c is the matrix obtained by shifting the corresponding columns of the identity matrix I to the right relative to the module N _s by c, the mark-2 is located in the (i + bc) -th row of the private matrix P ^c .

In addition, an element having a value of 1 in the partial matrix P ^b located on the same line as mark-2 will be referred to as “mark-3”. Mark-3 is located in the (i + b-c + d) -th column of the partial matrix P ^d .

An element having a value of 1 in the partial matrix P ^a located in the same column as mark-3 will be indicated as “mark-4”. 4-point is located in an (i + b-c + da ) th row of the partial matrix P ^a.

In the loop structure of the LDPC code illustrated in FIG. 6, if there is a loop of length 4, then mark-0 and mark-4 are in the same position. That is, the relationship between the mark-0 and the mark-4 is determined by equation (2)

или

or

(2)

Equation (2) can be rewritten as shown in equation (3).

(3)

и зависимость, показанная в уравнении (4), выполняется.When the dependence of equation (3) is fulfilled, a cycle with a length of 4 is formed. In general, when the mark-0 and the mark-4p are first identical to each other, then the dependence

and the dependence shown in equation (4) is satisfied.

(four)

That is, if a positive integer having a minimum value among positive integers satisfying equation (4) for given a, b, c and d is defined as 'p', then a cycle with a length of 4p becomes a cycle having a minimum length in the structure the block LDPC code cycle illustrated in FIG.

Accordingly, as described above, for (a-b + cd) 0, if gcd (N _s , a-b + cd) = l holds, then p = N _s . Therefore, a cycle of length 4N _S becomes a cycle with a minimum length.

Later in this document, the Richardson-Urbank technique will be used as the coding technique for the block LDPC code. Since the Richardson-Urbanke technique is used as a coding technique, the coding complexity can be minimized, since the form of the parity check matrix becomes similar to that of the complete lower triangular matrix.

7 is a diagram illustrating a parity check matrix having a shape similar to that of a full lower triangular matrix. However, the parity check matrix illustrated in FIG. 7 has an excellent even part than the parity check matrix having the form of a complete lower triangular matrix.

по

являются также матрицами перестановок и верхние индексы с a₁ по a_p последовательно индексируются по отношению к частным матрицам, расположенным в диагональной части четной части.Referring to FIG. 7, the superscript (or exponent) a _{pq of the} matrix P of the permutation of the piece of information is either 0 _pqs -1 or a _pq =. The permutation matrix P with superscript a _pq = 0, i.e. the permutation matrix P ° of the information part is the identity matrix I _NsxNs and the permutation matrix P with the superscript a _pq =, i.e. permutation matrix P is a zero matrix. In addition, 'p' represents the number of rows of private blocks mapped to the information part in the parity matrix, and 'q' represents the number of columns of private blocks mapped to the information part. In addition, the superscripts a _p , x, and y of the matrices P of permutations associated with the even part represent the powers of the matrix P of permutations. However, for convenience, various superscripts a _p , x, and y are used to distinguish the even part from the information part. That is, in FIG. 7 c

by

are also permutation matrices, and the superscripts a ₁ through a _{p are} sequentially indexed with respect to the partial matrices located in the diagonal part of the even part.

In addition, P ^x and P ^y are also permutation matrices and, for convenience, they are indexed differently to distinguish the even part from the information part. If the block size of the block LDPC code having the parity matrix shown in FIG. 7 is assumed to be N, then the coding complexity of the block LDPC code linearly increases with respect to the block size N (O (N)).

The biggest problem with the LDPC code having the parity matrix of Fig. 7 is that if the size of the private block is defined as N _s , then N _s control nodes are formed, the degree of which is always 1 in the factor graph of the block LDPC code. The control nodes with degree 1 cannot influence the performance increase based on iterative decoding. Consequently, the standard irregular LDPC code based on the Richardson-Urbank technique does not include a control node with degree 1.

Accordingly, the parity check matrix of FIG. 7 will be assumed as the main parity check matrix in order to calculate the parity check matrix so that it enables efficient coding, while not including a control node with degree 1.

In the parity matrix of FIG. 7, including partial matrices, the selection of a particular matrix is a very important factor for improving the performance of the block LDPC code, so that finding the appropriate selection criteria for the partial matrix also becomes a very important factor.

In order to facilitate a method for calculating a parity check matrix of a block LDPC code and a method for encoding a block LDPC code, it is assumed that the parity check matrix illustrated in FIG. 7 is composed using 6 partial matrices, as illustrated in FIG.

FIG. 8 is a diagram illustrating the parity matrix of FIG. 7, which is divided into 6 private blocks. Referring to FIG. 8, the parity check matrix of the block LDPC code illustrated in FIG. 7 is divided into the information part 's', the first even part p ₁ and the second even part p ₂ . The information part 's' represents the part of the parity check matrix associated with the actual information word during the encoding process of the block LDPC code, similar to the information part described in connection with Fig. 7, and for convenience, the information part 's' is represented by various reference characters. The first even part p ₁ and the second even part p ₂ represent the part of the parity check matrix compared with the actual parity during the LDPC block code coding process, like the even part described in connection with FIG. 7, and the even part is divided into two parts.

The partial matrices A and C correspond to the private blocks A (802) and C (804) of the information part 's', the partial matrices B and D correspond to the private blocks B (806) and D (808) of the first even part p ₁ , and the partial matrices T and E correspond to the private blocks T (810) and E (812) of the second even part p ₂ . Although the parity check matrix is divided into 7 private blocks in Fig. 8, it should be noted that since '0' is not a separate private block and the partial matrix T corresponding to the private side T (810) has a full lower triangular shape, the region where zero matrices based on diagonal division, represented by '0'. The process of simplifying the encoding method using the partial matrices of the information part 's', the first even part p ₁ and the second even part p ₂ will be described later with reference to FIG. 10.

.FIG. 9 is a diagram illustrating a transposed matrix of a partial matrix B illustrated in FIG. 8, a private matrix E, a private matrix T, and an inverse matrix of a private matrix T in the parity matrix illustrated in FIG. 7. Referring to FIG. 9, the partial matrix B ^T is the transposed matrix of the partial matrix B and the partial matrix T ^-1 represents the inverse matrix of the private matrix T. P ^{(k1 ~ k2)} represents

.

могут являться единичными матрицами. Как описано выше, если показатель степени матрицы перестановок, т.е. a₁ является 0, то матрица

перестановок будет являться единичной матрицей. К тому же, если показатель степени матрицы перестановок, т.е. a₁ увеличивается на заранее определенную величину, то матрица перестановок циклически сдвигается на заранее определенную величину, из условия, что матрица

будет являться единичной матрицей.The permutation matrices illustrated in FIG. 9, for example,

can be unit matrices. As described above, if the exponent of the permutation matrix, i.e. a ₁ is 0, then the matrix

permutations will be the identity matrix. In addition, if the exponent of the permutation matrix, i.e. a ₁ increases by a predetermined amount, then the permutation matrix is cyclically shifted by a predetermined amount, from the condition that the matrix

will be the identity matrix.

10 is a flowchart illustrating an algorithm for generating a parity check matrix of a common block LDPC code. However, before the description of FIG. 10 is given, it should be noted that in order to generate the block LDPC code, the codeword size and the coding rate of the block LDPC code to be generated must be determined and the size of the parity check matrix must be determined according to the determined size code word and coding rate. If the codeword size of the block LDPC code is represented by N and the coding rate is represented by R, then the size of the parity matrix is converted to N (1-R) xN.

In fact, the algorithm for generating the parity check matrix of the block LDPC code illustrated in FIG. 10 is performed only once, since the parity check matrix is initially formed suitable for the situation in the communication system, and then the generated parity check matrix is used.

Referring to FIG. 10 in step 1011, the controller divides the parity check matrix with a size of N (1-R) xN by the sum of pxq blocks including p blocks along the horizontal axis and q blocks along the vertical axis. Since each of the blocks has a size of N _s xN _s, the parity check matrix includes N _s xp rows and N _s xq columns. At 1013, the controller classifies the pxq blocks separated by the parity matrix into the information part 's', the first even part p ₁ and the second even part p ₂ .

At 1015, the controller divides the information part 's' into non-zero blocks or non-zero matrices and zero blocks or zero matrices according to a power distribution to ensure sufficient performance of the block LDPC code. Since the degree distribution to ensure sufficient performance of the block LDPC code is described above, a detailed description of this will be omitted here.

перестановок из условия, что минимальная длина блочного цикла должна быть максимизирована, как описано выше в частях ненулевой матрицы в блоках, имеющих низкую степень среди блоков, определенных согласно распределению степеней для гарантирования достаточной производительности блочного кода LDPC. Матрицы

перестановок должны определяться, принимая во внимание блочные циклы информационной части 's', первую четную часть p₁ и вторую четную часть p₂.At 1017, the controller determines the matrices

permutations from the condition that the minimum length of the block cycle should be maximized, as described above in parts of a nonzero matrix in blocks having a low degree among blocks determined according to the degree distribution to ensure sufficient performance of the block LDPC code. Matrices

permutations should be determined, taking into account the block cycles of the information part 's', the first even part p ₁ and the second even part p ₂ .

перестановок в частях ненулевой матрицы в блоках, имеющих высокую степень среди блоков, определенных согласно распределению степеней, для гарантирования хорошей производительности блочного кода LDPC и затем заканчивает алгоритм. Даже когда матрицы

перестановок определяются для использования в частях ненулевой матрицы в блоках, имеющих высокую степень, матрицы

перестановок должны определяться из условия, что минимальная длина блочного цикла максимизируется. Матрицы

перестановок определяются, принимая во внимание блочные циклы информационной части 's', первую четную часть p₁ и вторую четную часть p₂. Пример матриц

перестановок, расположенных в информационной части 's' матрицы контроля четности, проиллюстрирован на фиг.9.At 1019, the controller randomly determines matrices

permutations in parts of a nonzero matrix in blocks having a high degree among blocks determined according to the degree distribution to guarantee good performance of the block LDPC code and then terminates the algorithm. Even when the matrices

permutations are determined for use in parts of a nonzero matrix in blocks with a high degree of matrix

permutations should be determined from the condition that the minimum length of the block cycle is maximized. Matrices

permutations are determined taking into account the block cycles of the information part 's', the first even part p ₁ and the second even part p ₂ . Matrix Example

permutations located in the information part 's' of the parity check matrix are illustrated in FIG.

перестановок в 2 частных блока среди частных блоков, включенных в частную матрицу B. Структура для ввода ненулевых матриц P^y и

перестановок в 2 частных блока среди частных блоков, составляющих частную матрицу B, описана выше со ссылкой на фиг.9.At step 1021, the controller divides the first part p ₁ and the second even part p ₂ into 4 partial matrices B, T, D and E. At step 1023, the controller inputs non-zero matrices P ^y and

permutations of 2 private blocks among the private blocks included in the private matrix B. Structure for entering nonzero matrices P ^y and

permutations of 2 private blocks among the private blocks making up the private matrix B are described above with reference to Fig.9.

,

,...,

в частные блоки (i, i+1)^th под диагональные элементы частной матрицы T. Структура для ввода единичных матриц I в диагональные частные блоки частной матрицы T и ввода конкретных матриц перестановок

,

,...,

в частные (i, i+1)-тые блоки под диагональные элементы частной матрицы T описана выше со ссылкой на фиг.9.At 1025, the controller enters the identity matrices I into the diagonal quotient blocks of the quotient matrix T and enters specific permutation matrices

,

, ...,

into the private blocks (i, i + 1) ^th under the diagonal elements of the private matrix T. The structure for introducing the identity matrices I into the diagonal private blocks of the private matrix T and entering the specific permutation matrices

,

, ...,

into partial (i, i + 1) -th blocks for the diagonal elements of a particular matrix T is described above with reference to Fig.9.

перестановок только в последний частный блок в частной матрице E и затем заканчивает алгоритм. Структура для ввода 2 матриц

перестановок только в последний частный блок среди частных блоков, составляющих частную матрицу E, описана выше со ссылкой на фиг.9.At 1027, the controller enters the permutation matrix P ^x into the private matrix D. At 1029, the controller enters the matrix

permutations only to the last private block in the private matrix E and then ends the algorithm. Structure for entering 2 matrices

permutations only to the last private block among the private blocks making up the private matrix E is described above with reference to Fig.9.

As described above, it is known that the LDPC code together with the turbo code has a significant increase in performance during data transmission at high speed and effectively corrects errors caused by noise generated in the transmission channel, thereby increasing the reliability of data transmission. However, the LDPC code is disadvantageous in terms of coding rate. That is, since the LDPC code has a relatively high coding rate, it has a limitation in terms of coding rate. Among the currently available LDPC codes, the main LDPC codes have a 1/2 coding rate and only minor LDPC codes have a 1/3 coding rate. A limitation in coding rate has an inevitable effect on high-speed, high-performance data transmission.

Although the distribution of degrees representing optimal characteristics can be calculated using a density evolution scheme to implement a relatively low coding rate for an LDPC code, it is difficult to implement an LDPC code having a distribution of degrees showing optimal characteristics due to various constraints, such as structure cycle in the graph of factors and hardware implementation.

SUMMARY OF THE INVENTION

An object of the present invention, therefore, is to provide an apparatus and method for encoding and decoding block LDPC (Sparse Parity Check) codes.

Another aspect of the present invention is the provision of a device and method for encoding and decoding block LDPC codes with minimized coding complexity in a mobile communication system.

In accordance with one aspect of the present invention, there is provided a method for encoding a block LDPC code. The method comprises the steps of receiving an information word vector and encoding the information word vector into a block LDPC code in accordance with a predetermined generating matrix.

In accordance with another aspect of the present invention, there is provided an apparatus for encoding a block LDPC code. The device comprises an encoder for encoding an information word vector in a block LDPC code in accordance with a predetermined generator matrix; a modulator for modulating the block LDPC code in the modulation symbol using a predetermined modulation scheme; and a transmitter for transmitting a modulation symbol.

In accordance with another further aspect of the present invention, there is provided a method for decoding a block LDPC code. The method comprises the steps of: receiving a signal; decoding the received signal using a parity matrix predetermined in accordance with the length of the block LDPC code to be decoded; and detecting the block LDPC code from the decoded received signal.

In accordance with another aspect of the present invention, there is provided an apparatus for decoding a block LDPC code. The device comprises a receiver for receiving a signal; and a decoder for decoding the received signal using the parity matrix predetermined in accordance with the length of the block LDPC code to be decoded; and detecting the block LDPC code from the decoded received signal.

Brief Description of the Drawings

The above and other objectives, features and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, of which:

Figure 1 is a diagram illustrating a transceiver in a conventional mobile communication system;

Figure 2 is a diagram illustrating a parity check matrix for a standard LDPC code (8, 2, 4);

FIG. 3 is a diagram illustrating a factor graph of the LDPC code (8, 2, 4) illustrated in FIG. 2;

4 is a diagram illustrating a parity check matrix of a standard block LDPC code;

FIG. 5 is a diagram illustrating a permutation matrix P illustrated in FIG. 4;

6 is a diagram illustrating a loop structure of a block LDPC code whose parity matrix includes 4 partial matrices;

7 is a diagram illustrating a parity check matrix having a shape similar to that of a full lower triangular matrix;

Fig. 8 is a diagram illustrating a parity check matrix in Fig. 7, which is divided into 6 private blocks;

FIG. 9 is a diagram illustrating a transposed matrix of a partial matrix B illustrated in FIG. 8, a private matrix E, a private matrix T, and an inverse matrix of a private matrix T;

10 is a flowchart illustrating an algorithm for generating a parity check matrix of a standard block LDPC code;

11 is a diagram illustrating a transposed matrix B ^{T of a} private matrix B, a private matrix D and a private matrix T among 6 private matrices separated from a parity matrix of an irregular block LDPC code in accordance with an embodiment of the present invention;

12 is a diagram illustrating a matrix F used to form a matrix H ′ in accordance with an embodiment of the present invention;

13 is a diagram illustrating a parity check matrix of an irregular block LDPC code in accordance with an embodiment of the present invention;

Fig. 14 is a diagram illustrating a generator matrix of an irregular block LDPC code in accordance with an embodiment of the present invention;

15 is a diagram illustrating a coding process of an irregular block LDPC code in accordance with an embodiment of the present invention;

16 is a diagram illustrating an internal structure of an irregular block LDPC code encoding apparatus according to an embodiment of the present invention; and

17 is a diagram illustrating an internal structure of an irregular block LDPC code decoding apparatus according to an embodiment of the present invention.

Detailed Description of a Preferred Embodiment

Preferred embodiments of the present invention are further described in detail herein below with reference to the accompanying drawings. In the following description, a detailed description of known functions and configurations included in the materials of this application is omitted for brevity.

The present invention provides an apparatus and method for encoding and decoding block LDPC codes providing high performance. That is, the present invention provides an apparatus and method for encoding and decoding block LDPC codes in which the minimum cycle length in the multiplier graph is maximized, the coding complexity is minimized, and the degree distribution in the multiplier graph has the best degree distribution per unit. Although not specifically illustrated herein, an apparatus for encoding and decoding block LDPC codes in accordance with the present invention can be applied to the transceiver described with reference to FIG. 1.

11 is a diagram illustrating a transposed matrix B ^{T of a} private matrix B, a private matrix D and a private matrix T of among 6 private matrices separated from the parity check matrix of a block LDPC code in accordance with an embodiment of the present invention.

Before the description of FIG. 11 is given, it should be noted that the parity check matrix has a private block structure described in the section of the prior art with reference to FIG. That is, the parity check matrix of the block LDPC code is divided into private blocks for the information part 's', the first even part p _l and the second even part p ₂ . The information part 's' represents the part of the parity matrix mapped to the actual information word during the coding process of the block LDPC code. The first even part p ₁ and the second even part p ₂ represent portions of the parity matrix mapped to the actual parity during the coding process of the block LDPC code.

As illustrated in FIG. 8, the information part 's' is divided into the private block A and the private block C, the first even part p _{1 is} divided into the private block B and the private block D, the second even part p ₂ is divided into the private block T and the private block E. The partial matrices A and C correspond to the private blocks A and C, the partial matrices B and D correspond to the private blocks B and D, the partial matrices T and E correspond to the private blocks T and E.

перестановок и нулевые матрицы. Матрица P перестановок является квадратной матрицей с размером NsxNs, в которой вес каждой строки N_s равен 1 и вес каждого столбца равен также 1. Хотя размер матрицы P перестановок выражается как N_sxN_s, размер матрицы P перестановок, которая является квадратной матрицей, будет выражаться как N_s для удобства.Referring to FIG. 11, the partial matrix B includes two identity matrices

permutations and zero matrices. The permutation matrix P is a square matrix with size NsxNs, in which the weight of each row N _s is 1 and the weight of each column is also 1. Although the size of the permutation matrix P is expressed as N _s xN _s , the size of the permutation matrix P, which is a square matrix, will be expressed as N _s for convenience.

и P^x перестановок и нулевые матрицы. В случае стандартного блочного кода LDPC, чтобы удовлетворять равенству ET^-1B + D = I, матрицы

и P^x перестановок, отличные от нулевых матриц частной матрицы B, должны быть зафиксированы в положении, как проиллюстрировано на фиг.9, и матрицы

и P^x перестановок являются отличными друг от друга. Тем не менее, в настоящем изобретении две матрицы

перестановок, отличные от нулевых матриц частной матрицы B, не должны быть зафиксированы в положении, и две матрицы перестановок

обладают переменным положением и равны друг другу. Частная матрица T имеет единичные матрицы I в двухдиагональной структуре и нулевые матрицы. Частная матрица D включает в себя частную матрицу P^x.In the above description given with reference to FIG. 9, the partial matrix B includes matrices

and P ^x permutations and zero matrices. In the case of the standard block LDPC code, in order to satisfy the equality ET ^-1 B + D = I, the matrices

and P ^x permutations other than the zero matrices of the partial matrix B, must be fixed in position, as illustrated in FIG. 9, and the matrices

and P ^x permutations are distinct from each other. However, in the present invention, two matrices

permutations other than the zero matrices of the partial matrix B should not be fixed in position, and two permutation matrices

have a variable position and are equal to each other. The partial matrix T has unit matrices I in a bi-diagonal structure and zero matrices. The partial matrix D includes the partial matrix P ^x .

11, the superscripts a _i and x of the permutation matrix P represent the degrees of the permutation matrix P.

перестановок сопоставляются с транспонированной матрицей B^T частной матрицы B и матрица P^x перестановок сопоставляется с частной матрицей D на фиг.11 в качестве примера, тот же самый результат может быть достигнут, если матрицы

перестановок сопоставляются только с двумя матрицами перестановок среди всего трех матриц перестановок, будучи сопоставленными с транспонированной матрицей B^T частной матрицы B и частной матрицей D. То есть, хотя матрица

перестановок сопоставляется с любой из двух матриц перестановок, существующих в транспонированной матрице B^T частной матрицы B, и матрица

перестановок сопоставляется с матрицей перестановок, существующей в частной матрице D, то может быть достигнут тот же самый результат.Although two matrices

permutations are compared with the transposed matrix B ^{T of the} partial matrix B and the permutation matrix P ^{x is} compared with the partial matrix D in FIG. 11 as an example, the same result can be achieved if the matrices

permutations are mapped to only two permutation matrices among only three permutation matrices, being mapped to the transposed matrix B ^{T of the} partial matrix B and the partial matrix D. That is, although the matrix

permutations is mapped to either of the two permutation matrices existing in the transposed matrix B ^{T of the} private matrix B, and the matrix

permutations matched with the permutation matrix existing in the partial matrix D, then the same result can be achieved.

перестановок сопоставляются с двумя из двух матриц перестановок, существующих в транспонированной матрице B^T частной матрицы B и матрице перестановок, существующей в частной матрице D.Alternatively, the same effect can be achieved even if the matrices

permutations are mapped to two of the two permutation matrices existing in the transposed matrix B ^{T of the} private matrix B and the permutation matrix existing in the private matrix D.

перестановок может быть единичной матрицей, так как если степень матрицы перестановок равна a₁=0, то матрица

перестановок становится единичной матрицей, как описано выше. К тому же, показатель a₁ матрицы перестановок увеличивается на предопределенную величину, матрица перестановок циклически сдвигается на предопределенную величину, так, что матрица

перестановок будет являться единичной матрицей.In addition, in FIG. 11, the matrix

permutations can be the identity matrix, since if the degree of the permutation matrix is a ₁ = 0, then the matrix

permutations becomes the identity matrix, as described above. In addition, the exponent a _{1 of} the permutation matrix is increased by a predetermined value, the permutation matrix is cyclically shifted by a predetermined value, so that the matrix

permutations will be the identity matrix.

In the case of the standard block LDPC code, the pristine parity matrix used in the decoder is used as a generator matrix for the encoder. However, in the case of the block LDPC code proposed in the present invention, the parity matrix used in the decoder is modified to be used as a generator matrix for the encoder, thereby minimizing the coding complexity of the block LDPC code.

The parity matrix represented by H may be expressed as shown in equation (5).

(5)

In equation (5), H ₁ denotes a matrix mapped to an information word, i.e. a matrix mapped to the information part 's' in the parity check matrix H, and H ₂ denotes a matrix mapped to parity, i.e. a matrix mapped to the first even part p ₁ and the second even part p ₂ in the parity check matrix H. That is, H ₁ represents a matrix including a private matrix A and a private matrix C, and H ₂ represents a matrix including a private matrix B, a private matrix T, a private matrix D and a private matrix E. However, since the encoding scheme, Since the present invention is not based on the Richardson-Urbank technique, the proposed coding scheme does not require dividing the parity check matrix of the LDPC block code into six partial matrices, as in the Richardson-Urbank technique. Instead, the proposed scheme divides the parity check matrix into a matrix H ₁ mapped to the information part and matrices H ₂₁ and H ₂₂ mapped to the first even part and the second even part.

The generator matrix provided for by the modification of the parity check matrix H used in the encoder is represented by H ′, and the generator matrix H ′ can be expressed by equation (6) using the new matrix F.

(6)

In equation (6), F denotes a matrix with a size of (NK) x (NK), N denotes a block size or a codeword length of a code, and K denotes an information word length. Matrix F is illustrated in FIG. 12 and will be described later. Similarly to the parity check matrix H described with reference to equation (5), the generating matrix H ′ is divided by H ₁ ′ mapped to the information word, and H ₂ ′ mapped with parity and H ₂ ′ is divided by H ₂₁ ′ mapped with the first parity, and H ₂₂ ', compared with the second parity.

In the generator matrix H 'shown in equation (6), the degrees of all nonzero permutation matrices corresponding to the last block increase by a _m by the modulo action N _s , H ₂₂ ', compared with the second parity, have unit matrices in a bi-diagonal structure for each block, and all remaining matrices, with the exception of unit matrices, include zero matrices.

A description will now be made of the coding process of the block LDPC code using the generator matrix H ′.

четности и второй вектор

четности. Как описано выше, первый вектор

четности сопоставляется с частными блоками B и D и второй вектор

четности сопоставляется с частными блоками T и E.The LDPC block code codeword vector c may be divided into the information word vector s , the first vector

parity and second vector

parity. As described above, the first vector

parity is mapped to private blocks B and D and the second vector

parity is mapped to private blocks T and E.

четности достигается применением уравнения (7) и уравнения (8), приведенными ниже. Так как Hc ^T = H'c ^T = 0, то зависимость уравнения (7) выполняетсяThe coding of the first vector

parity is achieved by applying equation (7) and equation (8) below. Since H c ^T = H ' c ^T = 0 , the dependence of equation (7) is satisfied

(7)

обозначает матрицу N_sxK, предусмотренную суммированием строк блоков по всем строкам в каждом блоке в H'. Когда вычисление матрицы, основанное на суммировании по каждому блоку, применяется к матрице контроля четности, описанной со ссылкой на фиг.4, результирующая матрица становится матрицей N_sxqN, и каждая матрица N_sxN_s становится матрицей, заданной суммированием всех матриц перестановок, соответствующих каждому столбцу блока. Например, первая матрица N_sxN_s имеет значение

на фиг.4.In equation (7)

denotes the matrix N _s xK provided by summing the rows of blocks over all rows in each block in H '. When the matrix calculation based on summation over each block is applied to the parity matrix described with reference to FIG. 4, the resulting matrix becomes the matrix N _s xqN, and each matrix N _s xN _s becomes the matrix given by the summation of all permutation matrices corresponding to each column of the block. For example, the first matrix N _s xN _s has the value

figure 4.

,

обозначает матрицу N_sxN_s, обеспеченную суммированием всех строк каждого блока в H₂₁'. Подобным образом

обозначает матрицу N_sx(N-K-N_s), обеспеченную суммированием всех строк каждого блока в H₂₂'.Similarly

,

denotes the matrix N _s xN _s provided by summing all the rows of each block in H ₂₁ '. In a similar way

denotes the matrix N _s x (NKN _s ) provided by summing all the rows of each block in H ₂₂ ′.

в уравнении (7), так как H₂₂' имеет двухдиагональную структуру аналогично частной матрице T, проиллюстрированной на фиг.11, матрица, полученная суммированием строк каждого блока, становится нулевой матрицей N_sx(N-K-N_s), в которой все элементы равны 0. Так как

становится нулевой матрицей N_sx(N-K-N_s), то элемент

удаляется из уравнения (7), следовательно, матрица H₂₁' может выражаться в уравнении (8) в соответствии со свойством частной матрицы B, описанной со ссылкой на фиг.11The expression "summation of rows in a matrix in each block" refers to the summation of rows in private blocks included in the corresponding matrix in such a way that the first rows in private blocks are added exclusively to each other. Regarding the calculation

in equation (7), since H ₂₂ 'has a two-diagonal structure similar to the partial matrix T illustrated in FIG. 11, the matrix obtained by summing the rows of each block becomes the zero matrix N _s x (NKN _s ), in which all elements are 0 . As

becomes the zero matrix N _s x (NKN _s ), then the element

is removed from equation (7), therefore, the matrix H ₂₁ ′ can be expressed in equation (8) in accordance with the property of the partial matrix B described with reference to FIG. 11

(8)

является вектором, полученным циклическим сдвигом

на x, и

представляет транспонированный вектор первого вектора

четности.In equation (8)

is a cyclic shift vector

on x and

represents the transposed vector of the first vector

parity.

четности.The second parity vector p ₂ can be easily calculated by reverse substitution, since H ₂₂ 'has a bi-diagonal structure. Since the block LDPC code, different from the RA code, has a block structure, it can perform backward substitution in each block, increasing the speed of computing the second vector

parity.

More specifically, if it is assumed that the RA code has a parity vector p = (p ₁ , p ₂ , ..., p _NK ), then P ₂ can be calculated after p _{1 is} determined. Similarly, p ₃ can be calculated after p _{2 is} determined. Therefore, parity bits (NK) can be computed sequentially.

However, in the encoding process of the block LDPC code, as proposed in the present invention, since the private block mapped to the parity of the generator matrix H ′ has a two-diagonal structure, p ₁ by p _Ns can be calculated simultaneously, and the next N _s bits can be computed simultaneously using N _s bits from P ₁ to p _Ns calculated in the previous step. Therefore, the LDPC block code encoding process proposed in the present invention is N _s times faster than the RA code encoding process.

13 is a diagram illustrating a parity check matrix of a block LDPC code in accordance with an embodiment of the present invention. The parity check matrix illustrated in FIG. 13 represents a parity check matrix of a block LDPC code with a 1/2 coding rate and includes 12 x 24 blocks.

13, the numbers recorded in the blocks represent the degrees of the permutation matrices located in the respective blocks, and 'I' represents the identity matrices located in the corresponding blocks. The degree of degree of the permutation matrix for the parity check matrix of the block LDPC code with the block size N _s can be calculated by performing the modulo N _s action on each exponent of the degree of permutation matrices located in the corresponding blocks. If the indicator of the corresponding block is higher than the size N _{s of the} corresponding block, then this means that you need to perform the action modulo N _s .

In general, the indicator should be less than N _s . However, when the same parity matrix is generally used for both large and small block sizes, an indicator value greater than N _s is included in the matrix randomly. In this case, many parity matrices are necessary in accordance with the coding rate and block sizes, increasing the required memory capacity. If the value achieved by performing the action modulo N _s on the exponent of the permutation matrix is 0, then the permutation matrix located in the corresponding block becomes the identity matrix.

14 is a diagram illustrating a block matrix LDPC matrix generator in accordance with an embodiment of the present invention. However, before the description of FIG. 14 is given, it should be noted that the generator matrix H ′ is a matrix formed by multiplying the parity check matrix H by the matrix F, as described above. Matrix F will be described with reference to FIG.

перестановок располагается в последнем элементе линии диагонали. Матрица

перестановок является матрицей перестановок, имеющей отрицательный показатель степени для матрицы

перестановок, расположенной в последней части матрицы E перестановок матрицы контроля четности. На фиг.12 предполагается, что a_m=1.12 is a diagram illustrating a matrix F used to form a matrix H ′ in accordance with an embodiment of the present invention. Referring to FIG. 12, in the matrix F, the identity matrices I are located along the diagonal line and the matrix

permutations are located in the last element of the diagonal line. Matrix

permutation is a permutation matrix having a negative exponent for the matrix

permutations located in the last part of the matrix E permutations of the parity matrix. 12, it is assumed that a _m = 1.

перестановок, расположенная в последней части матрицы F, является P^-1, как описано выше, то порождающая матрица H' сравнивается с матрицей H контроля четности, и только матрицы, расположенные в последней строке блока порождающей матрицы H', имеют значения степеней меньше на 1 по сравнению со степенями матрицы H перестановок.Referring to FIG. 14, a generator matrix H ′ is formed by multiplying the parity check matrix H by a matrix F, as described above. However, since the matrix

permutations located in the last part of the matrix F is P ^-1 , as described above, then the generator matrix H 'is compared with the parity control matrix H, and only the matrices located in the last row of the block of the generator matrix H' have degrees less than 1 compared with powers of the permutation matrix H.

FIG. 15 is a flowchart illustrating a process for encoding a block LDPC code in accordance with an embodiment of the present invention. Referring to FIG. 15, in step 1511, the controller receives the information word vector s for encoding into the block LDPC code. In this document, it is assumed that the information word vector s has a size corresponding to the coding rate for encoding into the block LDPC code, and the size of the information word vector s is k.

четности, используя матрицу, сформированную суммированием всех строк в H₁' порождающей матрицы H' в каждом блоке, и транспонированный вектор принятого вектора s информационного слова. Матрица, сформированная суммированием всех строк в H₁' порождающей матрицы H' имеет размер N_sxK, и первый вектор

четности вычисляется, используя уравнение (8).At step 1513, the controller calculates the first vector

parity using a matrix formed by summing all the rows in H ₁ 'of the generating matrix H' in each block, and the transposed vector of the received information word vector s . The matrix formed by summing all the rows in H ₁ 'of the generating matrix H' has size N _s xK, and the first vector

parity is calculated using equation (8).

четности обратной подстановкой, используя вектор s информационного слова и первый вектор

четности. На этапе 1517 контроллер формирует вектор c кодового слова, используя вектор s информационного слова, первый вектор

четности и второй вектор

четности, и передает сформированный вектор c кодового слова.At step 1515, the controller calculates a second vector

parity by reverse substitution using the vector s of the information word and the first vector

parity. At step 1517, the controller generates a codeword vector c using the information word vector s , the first vector

parity and second vector

parity, and transmits the generated codeword vector c .

16 is a block diagram illustrating an internal structure of an LDPC block code encoding apparatus according to an embodiment of the present invention. Referring to FIG. 16, an apparatus for encoding a block LDPC code includes a matrix multiplier 1611, a memory 1613, a cyclic shifter 1615, a backward substitution processor 1617, and switches 1619, 1621 and 1623.

, полученным циклическим сдвигом транспонированного вектора

первого вектора

четности на x.Input signal i.e. an information word vector s of length k, which must be encoded into a block LDPC code, is used by switch 1619, matrix multiplier 1611, and backward substitution processor 1617. The matrix multiplier 1611 multiplies the information word vector s by the matrix N _s xK formed by summing all the rows in H ₁ ′ of the generating matrix H ′ stored in the memory 1613 by each block and outputs the result to the cyclic shifting device 1615. The signal output from the matrix multiplier 1611 is a vector

obtained by cyclic shift of the transposed vector

first vector

parity at x.

первого вектора

четности обратным циклическим сдвигом сигнала, выводимого от матричного умножителя 1611 на x, вычисляет первый вектор

четности, используя транспонированный вектор

первого вектора

четности, и выводит результат на процессор 1617 обратной подстановки и переключатель 1621. Процессор 1617 обратной подстановки вычисляет второй вектор

четности обратной заменой, используя вектор s информационного слова и первый вектор

четности, выведенный из циклического сдвигающего устройства 1615, и выводит результат на переключатель 1623.The cyclic shifter 1615 computes the transposed vector

first vector

the parity by the reverse cyclic shift of the signal output from the matrix multiplier 1611 by x, calculates the first vector

parity using a transposed vector

first vector

parity, and outputs the result to the backward substitution processor 1617 and the switch 1621. The backward substitution processor 1617 calculates a second vector

parity by reverse substitution using the vector s of the information word and the first vector

parity output from the cyclic shifting device 1615, and outputs the result to the switch 1623.

Each of the switches 1619, 1621 and 1623 is included only in its own transmission time interval in order to transmit its associated signal. That is, the switch 1619 is turned on during the transmission of the information word vector s , the switch 1621 is turned on during the transmission of the first even part vector P ₁ and the switch 1623 is turned on during the transmission of the second even part vector P ₂ .

All codes of the LDPC series can be decoded in the multiplier graph using the sub-product algorithm. The LDPC code decoding scheme can be roughly divided into a bidirectional transmission scheme and a stream transmission scheme. When the decoding operation is performed using the bidirectional transmission scheme, each control node has a node processor, thereby increasing the decoding complexity in proportion to the number of control nodes. However, since all control nodes are updated simultaneously, the decoding speed increases dramatically.

Different from this, the flow transmission scheme has a single nodal processor and the nodal processor updates information passing through all nodes in the multiplier graph. Therefore, the stream transmission scheme is lower in decoding complexity, but an increase in the size of the parity check matrix, i.e. an increase in the number of nodes causes a decrease in decoding speed. However, a parity check matrix is generated per block like the block LDPC code proposed in the present invention, then the number of node processors equal to the number of blocks making up the parity check matrix is used during decoding. In this case, it is possible to implement a decoder that is less complicated to decode than the bidirectional transmission scheme, and with a higher decoding speed than the stream transmission scheme.

17 is a block diagram illustrating an internal structure of a decoding apparatus for a block LDPC code in accordance with an embodiment of the present invention. Referring to FIG. 17, a decoding apparatus for a block LDPC code includes a block controller 1710, a variable node portion 1700, an adder 1715, a deinterleaver 1717, an interleaver 1719, a controller 1721, a memory 1723, an adder 1725, a control node 1750, and a block 1729 hard decision choices. The variable nodal part 1700 includes a variable nodal decoder 1711 and switches 1713 and 1714, and the control nodal part includes a control nodal decoder 1727.

The signal received over the air is the input to the controller 1710 blocks. Block controller 1710 determines the block size of the received signal. If there is a part of the information word punctured in the encoding device corresponding to the decoding device, then the block controller 1710 inserts '0' into the punctured part of the information word to adjust the size of the full block, and outputs the resulting signal to a variable node decoder 1711. The variable node decoder 1711 calculates the probability values of the output signal of the controller 1710 blocks, updates the calculated probability values and displays the updated probability values on the switches 1713 and 1714. The variable y lovoy decoder 1711 connects the variable nodes according to a parity check matrix previously set in the decoding apparatus for the block code, LDPC, and performs an update operation on as many input values and output values as the number of units connected to the variable nodes. The number of units connected to variable nodes is equal to the weight of each of the columns that make up the parity matrix. The internal operation of the variable node decoder 1711 differs in accordance with the weight of each of the columns constituting the parity matrix. Unless the switch 1713 is turned on, the switch 1714 is turned on to output the output signal of the variable node decoder 1711 to the adder 1715.

The adder 1715 receives the signal output from the variable node decoder 1711 and outputs the signal of the interleaver 1719 in the previous iterative decoding process, subtracts the output signal of the interleaver 1719 in the previous iterative decoding process from the output signal of the variable node decoder 1711, and outputs the subtraction result to the inverted interleaver 1717. If the decoding process is the initial decoding process, it should be assumed that the output signal of the interleaver 1719 is 0.

Reversed interleaver 1717 eliminates the interleaving of the output signal from the adder 1715 according to a predetermined interleaving scheme and outputs a signal with the eliminated interleaving to the adder 1725 and the control node decoder 1727. The inverted interleaver 1717 has an internal device corresponding to the parity matrix, since the output value for the input interleaver 17 corresponding to the deinterleaver 1717 is different in accordance with the position of the elements having a value of 1 in the parity check matrix.

The adder 1725 receives the output signal of the control node decoder 1711 in the previous iterative decoding process and the output signal of the deinterleaver 1717, subtracts the output signal of the deinterleaver 1717 from the output signal of the control node decoder 1727 in the previous iterative decoding process and outputs the subtraction to the interleaver 1719. The control node decoder 1727 connects the control nodes in accordance with a parity check matrix predefined in a block decoding device of the LDPC code, and performs an update operation on as many input values and output values as the number of units connected to the check nodes. The number of units connected to the control nodes is equal to the weight of each row included in the parity matrix. Therefore, the internal operation of the control node decoder 1727 is different in accordance with the weight of each line constituting the parity check matrix.

An interleaver 1719 under the control of the controller 1721 interleaves the output signal from the adder 1725 in accordance with a predetermined interleaving circuit and outputs the interleaved signal to the adder 1715 and the variable node decoder 1711. The controller 1721 reads the information related to the interleaving stored in the memory 1723 and controls the interleaving circuit interleaver 1719 according to the read information. Similarly, if the decoding process is the original decoding process, it should be taken into account that the output signal of the deinterleaver 1717 is 0.

By iteratively performing the above processes, the decoding apparatus performs reliable error-free decoding.

After iterative decoding is performed a predetermined number of times, the switch 1714 turns off the connection between the variable node decoder 1711 and the adder 1715, and the switches 1713 turn on the connection between the variable node decoder 1711 and the hard decision block 1729 to provide a signal output from the variable node decoder 1711 to block 1729 hard decision. The hard decision block 1729 applies the hard decision over the output signal from the variable node decoder 1711 and outputs the result of the hard decision, and the output of the hard decision block 1729 becomes the finally decoded value.

As can be taken into account from the above description, the present invention provides a block LDPC code whose minimum cycle length is maximized in a mobile communication system, thereby maximizing error correction capability. Therefore, the decoding apparatus can correctly decode the received data using the block LDPC code, providing reliable decoding.

In addition, the present invention generates an efficient generator matrix using a parity matrix, thereby minimizing the coding complexity of the block LDPC code.

That is, the present invention proposes to provide thus high performance LDPC block code by using iterative decoding in the factor graph.

In addition, the present invention provides a block-by-block LDPC parity check matrix, thus making it possible to implement a decoder with minimal decoding complexity, improved in terms of decoding speed. In particular, the present invention minimizes coding complexity using simple matrix multiplication and blockwise inverse substitution.

Although the present invention has been shown and described with reference to its specific embodiments, it will be understood by those skilled in the art that various changes in form and content may be made without departing from the spirit and scope of the present invention as defined by the appended claims. .

Claims (11)

1. A method for encoding / decoding a block code of a low-density parity check (LDPC), comprising the steps of: receiving a vector of the information word and encoding the vector of the information word in the block LDPC code in accordance with the generating matrix; moreover, the generating matrix is formed by modifying the parity check matrix corresponding to the length that must be used when forming the vector of the information word in the LDPC block code;
moreover, the LDPC block code includes an information word vector, a first parity vector and a second parity vector, and the generating matrix includes a first matrix mapped to the information word vector, a second matrix mapped to the first parity vector, and a third matrix mapped to the second parity vector; the first matrix is formed by multiplying the fourth matrix associated with the vector of the information word of the parity check matrix corresponding to the length to be used when forming the vector of the information word in the LDPC block code by the predetermined fifth matrix, the second matrix is formed by multiplying the sixth matrix compared with the first parity vector the parity check matrix by the fifth matrix, and the third matrix is formed by multiplying the seventh matrix associated with the second matrix parity vector parity, on the fifth matrix; wherein the step of encoding the information word vector in the LDPC block code in accordance with a predetermined generating matrix comprises the steps of forming a first parity vector from the condition that the vector formed by multiplying the matrix formed by summing all rows of the fourth matrix in each block by the transposed vector of the information vector words, becomes a vector formed by a cyclic shift of the transposed vector of the first parity vector by a predetermined value; forming a second parity vector using backward substitution; and form a block LDPC code by combining the first parity vector and the second parity vector into an information word vector. 2. The method according to claim 1, in which the matrix formed by summing all the rows of the fourth matrix in each block is formed by summing the same rows of private blocks included in the fourth matrix. 3. The method according to claim 1, in which the first parity vector is formed using the formula

where s denotes the vector of the information word,

denotes the first parity vector, s ^T denotes the transposed vector of the information word vector,

denotes the transposed vector of the first parity vector, P ^x denotes a matrix formed by cyclic shift of a permutation matrix with size N _s x N _s by x, p ₁ ^{T '} denotes a vector formed by cyclic shift

on x and

denotes the action of summing all the rows of the corresponding matrix in each block, H ₁ ′ denotes the matrix associated with the vector of the information word, in which the generating matrix is included, x denotes the exponent of the permutation matrix. 4. The method according to claim 3, in which the action of summing all the rows of the corresponding matrix in each block adds up the same rows of private blocks included in the corresponding matrix. 5. The method according to claim 1, additionally containing steps
decoding the received signal using a parity matrix; and
extracting the block LDPC code from the decoded received signal,
moreover, the steps of decoding the received signal using the parity matrix and extracting the block LDPC code from the decoded received signal comprise the steps of determining an interleaving elimination circuit and an interleaving scheme in accordance with the parity matrix; detect the probability values of the received signal; generating an output signal of a variable nodal decoder by calculating a probability value of a signal output from a received signal and a signal of previous decoding processing; generating the first signal by subtracting the signal generated in the previous decoding process from the probability values of the output signal of the variable node decoder; eliminating interleaving of the first signal using said interleaving elimination circuit; detecting probability values from a signal with eliminated interleaving; form the output signal of the control node decoder from the signal with the eliminated interleaving; generating a second signal by subtracting the signal with the eliminated interleaving from the probability values of the output signal of the control node decoder; interleaving a second signal using an interleaving scheme; and determining the block LDPC code by iteratively decoding the interleaved signal. 6. An apparatus for encoding / decoding a block LDPC code, comprising: an encoder for encoding an information word vector into a block LDPC code in accordance with a predetermined generator matrix and a modulator for modulating the block LDPC code into a modulation symbol using a predetermined modulation scheme; moreover, the generating matrix is formed by modifying the parity check matrix corresponding to the length that must be used when forming the vector of the information word in the LDPC block code; moreover, the LDPC block code includes an information word vector, a first parity vector and a second parity vector, and the generating matrix includes a first matrix mapped to the information word vector, a second matrix mapped to the first parity vector, and a third matrix mapped to the second parity vector; the first matrix is formed by multiplying the fourth matrix associated with the vector of the information word of the parity check matrix corresponding to the length to be used when forming the vector of the information word in the LDPC block code by the predetermined fifth matrix, the second matrix is formed by multiplying the sixth matrix compared with the first parity vector the parity check matrix by the fifth matrix, and the third matrix is formed by multiplying the seventh matrix associated with the second matrix parity vector parity, on the fifth matrix; and wherein the encoder comprises a matrix multiplier for multiplying the information word vector by a matrix formed by summing all rows of the fourth matrix in each block; a cyclic shifting device for generating a first parity vector by cyclic shifting the output signal from the matrix multiplier by a predetermined value; a backward substitution processor for generating a second parity vector by performing backward substitution for the information word vector and the output signal from the cyclic shifting device; and switches for generating the LDPC block code by switching the information word vector, the first parity vector and the second parity vector. 7. The device according to claim 6, in which the encoder generates a first parity vector from the condition that the vector formed by multiplying the matrix formed by summing all the rows of the fourth matrix in each block by the transposed vector of the information word vector becomes a vector formed by cyclic shift of the transposed vector the first parity vector by a predetermined value, forms a second parity vector by reverse substitution and forms a block LDPC code by adding the first parity vector and the second vect Dr. parity vector to the information word. 8. The device according to claim 7, in which the matrix formed by summing all the rows of the fourth matrix in each block is formed by summing the same rows of private blocks included in the fourth matrix. 9. The device according to claim 7, in which the encoder generates a first parity vector using

where s denotes the vector of the information word,

denotes the first parity vector, s ^T denotes the transposed vector of the information word vector,

denotes the transposed vector of the first parity vector, P ^x denotes a matrix formed by cyclic shift of a permutation matrix with a size of N _s x N _s by x, p ₁ ^T denotes a vector formed by a cyclic shift

on x and

denotes the action of summing all the rows of the corresponding matrix in each block. 10. The device according to claim 9, in which the action of summing all the rows of the corresponding matrix in each block adds up the same rows of private blocks included in the corresponding matrix. 11. The device according to claim 6, further comprising a decoder for decoding the received signal using the parity matrix and determining a block LDPC code from the decoded received signal, the decoder comprising a variable nodal decoder for detecting probability values of the received signal by connecting variable nodes in accordance with the weight of each column included in the parity matrix; a first adder for subtracting the signal generated in the previous decoding process from the output signal from the variable node decoder; inverted interleaver to eliminate the interleaving of the output signal from the first adder using the interleave elimination circuitry set in accordance with the parity check matrix; a control node decoder for detecting probability values of an output signal from a deinterleaver by connecting control nodes in accordance with the weight of each row included in the parity matrix; a second adder for subtracting the output signal from the deinterleaver from the output signal from the control node decoder; an interleaver for interleaving the output signal from the second adder using the interleaving circuit defined in accordance with the parity check matrix and outputting the interleaved signal to an alternating nodal decoder and a first adder; and a controller for controlling the interleaving circuit and the interleaving circuit in accordance with the parity check matrix.

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