CN114866186B

CN114866186B - LDPC decoding delay optimization method based on 5G

Info

Publication number: CN114866186B
Application number: CN202210358110.XA
Authority: CN
Inventors: 刘多强; 卜智勇; 薛顺瑞; 韩晓萌
Original assignee: Chengdu Zhongke Micro Information Technology Research Institute Co Ltd
Current assignee: Chengdu Zhongke Micro Information Technology Research Institute Co Ltd
Priority date: 2022-04-07
Filing date: 2022-04-07
Publication date: 2024-06-11
Anticipated expiration: 2042-04-07
Also published as: CN114866186A

Abstract

The invention provides a 5G-based LDPC decoding delay optimization method, which comprises the following steps: s1, ARM finishes calculation of parameters required by a PUSCH link processing module of each slot in advance through MAC scheduling information, and sends the calculation to an uplink baseband processing unit; s2, the uplink baseband processing unit receives the IQ frequency domain data, processes the IQ frequency domain data and outputs a plurality of CB code blocks; s3, determining whether LDPC decoding delay optimization is carried out on the CB code block; s4, cutting and punching the code word check bit of the CB code block; s5, filling 0x00 into 2Z _c LLR soft values at the beginning of a CB code block; s6, performing parallel LDPC decoding on the CB code block; s7, reading CB code blocks after parallel LDPC decoding and combining; s8, CRC check is carried out on the combined CB code block, a TB transmission block is synthesized after the CRC check is passed, and then the TB transmission block is sent to a 5G NR protocol MAC layer. The invention can improve LDPC decoding performance, reduce LDPC decoding time delay and improve system peak data rate.

Description

LDPC decoding delay optimization method based on 5G

Technical Field

The invention relates to the technical field of wireless communication, in particular to a 5G-based LDPC decoding delay optimization method.

Background

With the rapid development of mobile communication technology, explosive mobile data traffic increases, mass devices are linked, new service requirements and application scenes are continuously emerging, and a 5G system is coming into the vigorous development period.

The design of the 5G NR physical layer is the most central part of the overall 5G system design, and compared with LTE, ITU and 3GPP put forward higher and more comprehensive key performance index requirements on 5G. The most challenging key technical indexes such as peak rate, user experience rate, time delay and the like need to be achieved through the design of a physical layer.

The OFDM+MIMO technology is used as the basis of physical layer design, flexible frame structure and duplex mechanism are adopted, and compared with LTE, in the field of channel coding, the 5G NR adopts a new combination technology of data channel LDPC coding and control channel Polar coding. The LDPC code has lower coding complexity and lower decoding delay compared with the Turbo code, so that the signal transmission with large data volume can be better supported.

In order to support eMBB and other application scenes, the key technology of the 5G NR physical layer adopts a novel channel coding technology, and the key technology provides powerful support for realizing key technical indexes of the 5G system, wherein the key technology adopts a larger carrier bandwidth and a richer modulation mode.

In a 5G NR system, a data channel adopts a Quasi-cyclic LDPC (quick-CYCLIC LDPC, QC-LDPC) code for channel encoding and decoding. For the base station, the LDPC decoding performance of the uplink PUSCH directly determines the throughput rate and the error rate of the system.

In 5G NR, the LDPC codec needs to support flexible code rates and flexible code lengths, and thus flexible variation of information block sizes through a base matrix and a shift factor. Since 5G NR needs to support multiple code rates and has high requirements on flexibility of code length, LDPC codes are superior to other coding schemes in implementation complexity.

Although LDPC codes have the advantage of being highly parallelizable in decoding relative to Turbo codes, hardware resource overhead and low latency processing problems are encountered. Meanwhile, as NR supports different application scenarios, the flexibility of the NR enables the implementation complexity of LDPC codes to be increased.

The performance of the 5G physical layer baseband processing unit is directly related to the performance of the whole 5G system as a core component. The base station design scheme taking X86, ARM, FPGA and ASIC as main realization architecture has advantages and disadvantages in research and development cost, industry ecology and performance. The base station product of the multi-core stacking technical architecture with the CPU or ARM as the main component can be rapidly driven into the market, and the research and development cost is low. The base station product with the technical architecture of the FPGA/ASIC chip has long research and development period, higher cost, good performance and long life cycle.

In order to adapt to the novel LDPC channel coding and decoding technology and support flexible uplink and downlink time slot matching of a base station, LDPC decoding processing needs to be further optimized, LDPC decoding performance is improved, physical layer processing time delay is reduced, and system peak data rate is improved.

When the 5G base station physical layer receiver based on the OFDM technology is realized, multi-antenna MIMO and multi-user access can lead to the design and realization complexity of the receiver to be increased sharply. Meanwhile, in order to support flexible uplink and downlink time slot matching, in the occasion with higher requirement on the peak rate of uplink traffic, the channel coding and decoding are core components of the baseband, consume a large amount of hardware resources and bring challenges to the realization of the programmable logic circuit. The hardware implementation represented by FPGA/ASIC is a necessary choice for industry design of 5G base stations. In order to support a multi-user multi-cell service scenario, high throughput rate and low delay of PUSCH link LDPC decoding become a technical solution bottleneck.

The performance and the time delay of the LDPC decoding processing are determined by the performance and the time delay of the whole baseband unit. The LDPC decoding time delay is reduced, the uplink data rate of the system is improved to a plurality of Gbit/s, and meanwhile, the LDPC decoder has low bit error rate BER, and great challenges are brought to the design and implementation of the LDPC decoder and the whole receiver link.

Therefore, while meeting the performance index of the 5G system, the application requirement is met with lower design complexity as much as possible, and the layout and optimization are required from the baseband processing architecture and the signal processing algorithm.

Disclosure of Invention

The invention aims to provide a 5G-based LDPC decoding delay optimization method, which is used for improving LDPC decoding performance, reducing LDPC decoding delay and improving system peak data rate.

The invention provides a 5G-based LDPC decoding delay optimization method, which comprises the following steps:

S1, ARM finishes calculation of parameters required by a PUSCH link processing module of each slot through MAC scheduling information in advance, and transmits the parameters required by the obtained PUSCH link processing module to an uplink baseband processing unit;

S2, the uplink baseband processing unit receives the IQ frequency domain data, performs symbol level and bit level signal processing of a PUSCH link on the IQ frequency domain data by utilizing parameters required by a PUSCH link processing module, and then outputs a plurality of CB code blocks with equal codeword lengths;

S3, determining whether LDPC decoding delay optimization is carried out on the CB code block, and if so, entering a step S4; otherwise, entering step S5;

s4, cutting and punching the code word check bit of the CB code block;

S5, filling 0x00 into 2Z _c LLR soft values at the beginning of a CB code block;

S6, performing parallel LDPC decoding on the CB code block processed in the step S5;

S7, reading out CB code blocks after parallel LDPC decoding, and carrying out information bit combining;

S8, CRC check is carried out on the combined CB code block, a TB transmission block is synthesized after the CRC check is passed, and then the TB transmission block is sent to a 5G NR protocol MAC layer.

Further, in step S2, the symbol level and bit level signal processing of the PUSCH link includes sequentially completing OFDM demodulation, channel estimation, MIMO equalization, demapping and soft demodulation at the symbol level, and descrambling and rate matching at the bit level.

Further, when bit-level rate-decoding matching is performed, according to parameters required by a PUSCH link processing module, dividing the TB transmission block obtained after descrambling into a plurality of CB code blocks with equal codeword lengths according to a rate-decoding matching processing mode, wherein the codeword length of each CB code block is N; and when the bit-level solution rate matching is performed, the MAC layer schedule confirms whether to perform HARQ retransmission according to the indexes such as the block error rate (Block ErrorRate):

When the HARQ retransmission is not started by the MAC layer scheduling, the de-rate matching module of the physical layer baseband is processed according to the redundancy version RV=0, and a certain CB code block is not reprocessed due to decoding errors;

When the MAC layer starts HARQ retransmission, the de-rate matching module performs data combination by retransmitting a certain CB code block or adding check bits according to the specific value of the redundancy version RV, so as to improve the signal-to-noise ratio gain and further be beneficial to improving the success rate of LDPC decoding.

Further, in step S3, whether to perform LDPC decoding delay optimization on the CB code block is determined according to the modulation and coding scheduling MCS, the code rate R, the redundancy version RV, the signal-to-noise ratio SNR, and the data traffic demand.

Further, step S4 includes the following sub-steps:

S41, calculating the total length N _cb of the code words of each CB code block before LDPC decoding:

N_cb＝N+2Z_c(1)

Wherein N is the codeword length before CB code block phase shift;

S42, calculating a codeword check bit length _paritybits of the CB code block:

length_paritybits＝N+2Z_c-K(2)

Wherein Z _c is a shifting factor, and K is the codeword information bit length of the CB code block;

S43, calculating the number of columns mb of the parity check matrix check bits:

s44, obtaining a relation between mb and N according to formulas (1) - (3):

N＝K+Z_c(mb-2)(4)

S45, calculating an actual coding rate R:

S46, obtaining the relation between mb and R, K and Z _c from formulas (3) and (5):

When calculating mb, rounding is needed, and the value is not smaller than 4;

S47, under the modulation coding scheme MCS, aiming at redundancy version RV=0, cutting and punching check bits of a CB code block output by rate-demodulation matching processing, calculating mb by a formula (6) after removing LLR soft values filled with 0x00 at the tail, and substituting the calculated mb into the formula (4), wherein the obtained codeword length N is the codeword length N' before shifting the CB code block and after cutting and punching.

Further, in step S5, after filling "0x00" into the soft values of 2Z _c LLRs at the beginning of the CB code block, the information is the sum check bit; the total length of codewords fed into the LDPC decoding is therefore:

(1) If the step S4 is not performed, the check bits of the code words of the CB code block are cut and punched, and the total length of the code words sent into the LDPC decoding is N _cb＝N+2Z_c;

(2) If the codeword check bits of the CB code block are cut and punctured in step S4, the total length of the codeword sent to the LDPC decoding is N _cb＝N′+2Z_c.

Further, in step S5, a state machine FSM is designed to implement the operation of filling "0x00" into soft values of 2Z _c LLRs at the beginning of the CB code block.

Further, the state machine FSM includes four states:

ilde state: waiting for a front-stage module to input a CB code block, and skipping the state when a rear-stage module can receive data;

read state: reading a CB code block with a code word length of N or N', and filling 0x00 into 2Z _c LLR soft values at the beginning of the CB code block;

wait state: waiting for a CB code block to finish filling operation, and then entering a gap state;

gap state: and isolating and protecting between the filling operation of two adjacent CB code blocks through a delay processing time limit.

Further, after filling "0x00" into 2Z _c LLR soft values at the beginning of CB code block, data splicing is required:

Firstly, calculating the relative position of data splicing according to the codeword length N or N' of the CB code block and the shift factor Z _c: for LLR soft values of floating point numbers, fixed-point processing is needed during hardware processing; the integer and remainder of 2Z _c/32, and the remainder of (N _cb-2Z_c)/32, need to be calculated; then determining the end position of the last beat of effective data in 32 bytes in the transmission process of the data stream of each CB code block according to the remainder of (N _cb-2Z_c)/32; then determining specific positions of the front and back 2 effective clock cycles of data splicing according to the remainder of (N _cb-2Z_c)/32;

Then, data splicing is carried out according to the relative positions of the data splicing: when 2Z _c/32 can not be divided, the rest number of 0 LLR values are placed at the lower bit of 256 bits, and the data of the CB code block of the current clock are placed at the upper bit of 256 bits; and subsequent data splicing, namely placing the data of the CB code block of the previous clock in the high position of 256 bits according to the data of the CB code block of the current clock, and placing the data of the CB code block of the previous clock in the low position of 256 bits.

Further, step S6 includes the following sub-steps:

S61, initializing: according to the selected channel model, solving LLR soft values after symbol soft demodulation after channel equalization, and initializing LLR soft values L _i after soft demodulation for all variable nodes i; then, M _j,i＝L_i is set for all i, j satisfying the parity check equation h _i,j =1, and the iteration number iter _num =0; definition B _j represents the bit set in the j-th parity-check equation of parity-check matrix H, and a _i represents the parity-check equation of the i-th LLR value;

S62, updating a check node CN: for each check node CN, the CN output of message E _j,i is calculated using the following:

M_j,i＝α_j,iβ_j,i

α_j,i＝sign(M_j,i)

β_j,i＝|M_j,i|

S63, for i=0, 1, …, N-1, apply the following equation to calculate the sum of LLRs

S64, judging an ending criterion: for i=0, 1, …, N-1, let:

According to the above, a decision is obtained If/>Or stopping decoding calculation if the decoding iteration number reaches the set maximum iteration number iter _max; otherwise, enter S65;

S65, variable node VN update: for each variable node VN, the VN output of message M _j,i is calculated using the following:

iter_num＝iter_num+1

returning to S62, iterative decoding computation is continued.

In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:

1. The invention adopts the ARM+FPGA realization architecture, fully utilizes the flexibility of ARM soft solution design, and realizes the functions of command control, parameter calculation and the like; and the real-time processing of the streaming data signals is realized by utilizing the architecture advantages of FPGA parallel and streaming processing. Compared with the BBU architecture of X86 and ARM, the method has great advantages in processing delay, peak rate, energy consumption and the like.

2. The method for accelerating the implementation of the multi-channel parallel LDPC decoding of the 5G NR receiver is convenient for hardware implementation, on one hand, the low bit error rate performance requirement of LDPC decoding is met, and on the other hand, the requirement that the data rate reaches 1G bit/s in an uplink two-stream or four-stream multi-cell multi-user application scene is met. Under the conditions of high-order modulation and high signal-to-noise ratio, LDPC decoding can be realized with fewer iteration times. Multiple LDPC decoders are processed in parallel to increase the throughput of decoded data by several times.

3. The invention is based on the normalized minimum and LDPC decoding algorithm adopting hierarchical scheduling, under the conditions of high code rate and RV=0, the code word check bit clipping and punching method of the CB code block is adopted, compared with the method for directly decoding the original code word length, the decoding time of a single LDPC decoder for the CB code block is greatly shortened, and the data rate can be improved by 3-4 times. And proper normalization factors and LDPC decoding iteration times are selected, LDPC decoding processing can be completed in a time slot (slot) scheduling period, and the time delay requirement of less than 1ms of 5G NR is met.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly describe the drawings in the embodiments, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered as limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of an LDPC decoding delay optimization method based on 5G in an embodiment of the present invention.

Fig. 2 is a flowchart of uplink PUSCH processing of an NR base station in an embodiment of the present invention.

Fig. 3 is a block diagram of the base map BG1 in the embodiment of the present invention.

Fig. 4 is a block diagram of the base map BG2 in the embodiment of the present invention.

Fig. 5 is a state transition diagram of a state machine FSM according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a stuffing operation and data stitching in an embodiment of the present invention.

Fig. 7 is a block diagram of a multi-path parallel LDPC decoder according to an embodiment of the present invention.

Fig. 8 is a block diagram of a parameter manager in an embodiment of the present invention.

FIG. 9 is a schematic diagram of iterative decoding (first layer calculation) using hierarchical scheduling normalized min-sum LDPC decoding algorithm in accordance with an embodiment of the present invention

Fig. 10 is a schematic diagram (second-layer calculation) of iterative decoding by using hierarchical normalized minimum sum LDPC decoding algorithm in the embodiment of the present invention.

Fig. 11 is a block diagram of a parity check matrix H in an embodiment of the present invention.

FIG. 12 is a block diagram of LDPC decoding in an embodiment of the present invention

Fig. 13 is a block diagram of an output control unit of LDPC decoding in an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Examples

As shown in fig. 1, this embodiment proposes a 5G-based LDPC decoding delay optimization method, including the following steps:

S1, ARM finishes calculation of parameters required by a PUSCH (Physical Uplink SHARED CHANNEL ) link processing module of each slot in advance through MAC scheduling information, and sends the parameters required by the obtained PUSCH link processing module to an Uplink baseband processing unit BBU (Baseband Unit);

The parameters required by the PUSCH link processing module comprise a DMRS symbol position, a modulation mode qm, a transmission block size TB size, a rate matching codeword length E, a code rate R, a redundancy version RV, an LDPC codeword length N and a shift factor Zc; these parameters will be used for specific digital signal processing by the PUSCH link functional units.

S2, an uplink baseband processing unit receives IQ frequency domain data (through a forward CPRI (Common Pubic Radio Interface) interface), performs symbol level and bit level signal processing of a PUSCH link on the IQ frequency domain data by utilizing parameters required by a PUSCH link processing module, and then outputs a plurality of CB code blocks with equal codeword lengths;

as shown in fig. 2, the symbol-level and bit-level signal processing of the PUSCH link includes sequentially performing OFDM demodulation, channel estimation, MIMO equalization, demapping and soft demodulation at the symbol level, and descrambling and rate matching at the bit level.

When performing bit-level rate-decoding matching, according to parameters (such as modulation and coding scheme MCS, transmission block size TB size, code block number C, shift factor Z _c, redundancy version RV, etc.) required by the PUSCH link processing module, dividing the TB transmission block obtained after descrambling into a plurality of CB code blocks with equal codeword lengths according to a rate-decoding matching processing manner, where the codeword length of each CB code block is N. And when the bit-level solution Rate matching is performed, the MAC layer schedule confirms whether to perform HARQ retransmission according to indexes such as Block Error Rate (Block Error Rate):

When the HARQ retransmission is not started by the MAC layer scheduling, the de-rate matching module of the physical layer baseband is processed according to the redundancy version RV=0, and a certain CB code block is not reprocessed due to decoding errors; when the MAC layer starts HARQ retransmission, the de-rate matching module performs data combination by retransmitting a certain CB code block or adding check bits according to the specific value of the redundancy version RV, so as to improve the signal-to-noise ratio gain and further be beneficial to improving the success rate of LDPC decoding.

It should be noted that, while the performance of the HARQ retransmission is improved, the delay of the baseband digital signal processing is increased, which may cause the traffic to drop, so that whether to start the HARQ retransmission can be selected as required.

And determining whether LDPC decoding delay optimization is carried out on the CB code block according to the modulation and coding scheduling MCS, the code rate R, the redundancy version RV, the signal-to-noise ratio SNR, the data flow requirement and the like.

For example, when performing LDPC decoding based on a CB code block, if conditions such as redundancy version rv=0, modulation mode of 256QAM (for example, MCS > 16), signal-to-noise ratio SNR being 20dB or more, and data traffic flow requiring uplink traffic to reach up Gbit/S are satisfied, LDPC decoding delay optimization can be performed on the CB code block, step S4 is performed, so that LDPC decoding processing time is greatly shortened, and meanwhile, good decoding performance and high throughput requirements of the system can be maintained.

S4, cutting and punching the code word check bit of the CB code block; specifically:

N_cb＝N+2Z_c(1)

Wherein N is the codeword length before CB code block phase shift;

S42, calculating a codeword check bit length _paritybits of the CB code block:

length_paritybits＝N+2Z_c-K(2)

s44, obtaining a relation between mb and N according to formulas (1) - (3):

N＝K+Z_c(mb-2)(4)

S45, calculating an actual coding rate R:

Wherein, when calculating mb, rounding is needed, and the value is not less than 4. In the current 5G NR technical specification, for the base map BG1, k=22z _c, the maximum value of mb is 46; for the base map BG2, k=10z _c, the maximum value of mb is 42. As shown in fig. 3 and 4, the structures of the base map BG1 and the base map BG2 are shown, wherein kb represents the number of columns of system bits, and the value of kb is 22 for the base map BG 1; for the base map BG2, kb may take values of 6,8,9, 10.mb represents the number of columns of check bits, and the value range of mb is 4-46 for the base map BG 1; for the base map BG2, the mb value ranges from 4 to 44.nb is the total number of columns of the parity check matrix H. The core matrix has the characteristic of high row weight, and can ensure LDPC decoding performance. The line orthogonality is beneficial to designing a hardware implementation structure of line parallelism or block parallelism, so that the decoding speed can be improved. For the base map BG2, the non-row orthogonal design has better performance for the matrix with medium and low code rate, and can support the application scene with high reliability through matrix expansion.

S47, under the modulation coding scheme MCS, aiming at redundancy version RV=0, cutting and punching check bits of a CB code block output by rate-demodulation matching processing, calculating mb by a formula (6) after removing LLR soft values filled with 0x00 at the tail, and substituting the calculated mb into the formula (4), wherein the obtained codeword length N is the codeword length N' before shifting the CB code block and after cutting and punching. For example: the transmission block TB at a certain slot can be calculated by formula (6) using the base map BG1, k=8448, z _c =384, r= 0.8148. At this time, according to the formula (4), the codeword length N' =8448+384× (5-2) =9600 after the CN block is shifted and the clipping and puncturing are completed is calculated. Therefore, the LLR soft value of the check bit is cut, namely the length of the code word check bit of the CB code block is reduced, the effective code word information bit and the necessary code word check bit are reserved, the LDPC decoding performance is almost not affected, but the length of the code word is greatly shortened, so that the code rate is indirectly improved, the size of the parity check matrix H is reduced, the operation amount of iterative decoding is reduced, and the LDPC decoding time can be greatly shortened.

Filling '0 x 00' into 2Z _c LLR soft values at the beginning of a CB code block, and then, information is a sum check bit; the total length of codewords fed into the LDPC decoding is therefore:

The present embodiment implements the operation of filling "0x00" for the soft values of the 2Z _c LLRs at the beginning of the CB code block by designing a state machine FSM. As shown in fig. 5, the state machine FSM includes four states:

gap state: between the filling operations of two adjacent CB code blocks, logic time sequence tension is prevented by a time delay processing time limit isolation protection.

Firstly, calculating the relative position of data splicing according to the codeword length N or N' of the CB code block and the shift factor Z _c: for LLR soft values of floating point numbers, fixed-point processing is required during hardware processing. For example, the bit width of the LLR soft value for each CB code block may be defined as 8 bits, the fixed point format 8Q2, expressed as a total bit width of 8 bits, the lowest bits being the decimal bits of 2 bits, and the highest bits being the sign bits. To improve the throughput of LDPC decoding, the data bit width of the LDPC decoder interface is designed according to 256 bits. To facilitate data stitching, an integer number and remainder of 2Z _c/32, and a remainder of (N _cb-2Z_c)/32 need to be calculated; then determining the end position of the last beat of effective data in 32 bytes in the transmission process of the data stream of each CB code block according to the remainder of (N _cb-2Z_c)/32; and then determining specific positions of the front and back 2 effective clock cycles of the data splicing according to the remainder of (N _cb-2Z_c)/32.

Then, data splicing is carried out according to the relative positions of the data splicing: as shown in fig. 6, when 2Z _c/32 is not divisible, the remaining number of "0" llr values are placed at the low bits of 256 bits, and the data of the CB code block of the current clock is placed at the high bits of 256 bits; and subsequent data splicing, namely placing the data of the CB code block of the previous clock in the high position of 256 bits according to the data of the CB code block of the current clock, and placing the data of the CB code block of the previous clock in the low position of 256 bits.

As shown in fig. 7, in this embodiment, the LDPC decoder performs iterative decoding by using a hierarchical scheduled normalized minimum sum LDPC decoding algorithm, and the CB code block poll processed in step S5 is sent to a plurality of parallel LDPC decoders for LDPC decoding in a time-sharing manner, and when the decoding parity passes, the decoding process is allowed to end in advance. The parameter manager in the figure converts the parameters of the TB level into parameters of the CB level and distributes the parameters to the padding 2Zc processing unit and the multiplexer. The padding 2Zc processing unit completes the padding of the initial 2Zc LLR soft values of each CB code block with 0x00 and concatenates the valid LLR codeword information. And the multiplexer module sequentially polls and sends the CB code blocks to 4 LDPC decoders for LDPC decoding according to the CB code blocks currently processed. The LDPC decoder performs LDPC decoding according to the CB code blocks and outputs LDPC decoding results of each CB code block. And the output control unit polls and outputs LDPC decoding results of the 4 LDPC decoders according to the CB code block sequence and transmits the result to a CRC check module at a later stage.

In order to facilitate the hardware logic processing, parameters such as a check bit control factor mb, a shift factor Zc, a base map type BG1 or BG2 and the like issued by a higher layer (such as a protocol stack in 5G communication, L2/L3) are cached (FIFO memory) and managed by a parameter manager, and as shown in fig. 8, the parameter manager performs LDPC decoding parameter configuration based on CB code blocks.

To facilitate multi-user access and management, each of the TB transport blocks scheduled by the slot and the CB code blocks in the TB transport blocks are assigned, and corresponding ID numbers (e.g., ID number slot_id of the slot, ID number tb_id of the TB transport block, and ID number cb_id of the CB code block) are assigned, so that the hardware circuit performs LDPC decoding processing according to the CB code blocks.

The principle diagrams of the normalized minimum sum LDPC decoding algorithm adopting hierarchical scheduling are shown in fig. 9 and 10, in the iterative decoding process, check nodes are divided into a plurality of groups, one group of check node information in the check matrix is updated firstly during each round of iterative computation, then all variable nodes adjacent to the group of check nodes are updated, next group of check node information and variable node information adjacent to the group of check nodes are updated again, and the like until the last group of updating is completed. After the iteration of the round is finished, judging whether to perform the next iteration according to the checking equation and the iteration number setting. Meanwhile, the variable node information updated in the iteration of the round can be used for updating check node information of the next iteration, so that the convergence speed is increased, the iteration times can be saved, and the throughput can be improved. And when the check passes or the maximum iteration number is reached, ending the LDPC decoding process. The number of parity check equation units at the same time determines the consumption of hardware resources, and all check nodes participate in operation at the same time to improve the throughput of full parallel LDPC decoding. Therefore, the adoption of the normalized minimum sum LDPC decoding algorithm of hierarchical scheduling can lead to the relative compromise between the decoding throughput rate and the hardware resource consumption, and has practical applicability in practice.

The main calculation formula of the normalized minimum sum LDPC decoding algorithm is as follows:

the metrics of the binary variables are represented by the following Log Likelihood Ratios (LLRs):

Where L (x) provides a hard decision of x, and modulo L (x) determines the reliability of the hard decision.

Converting the log-likelihood ratio LLR into probabilities:

The extrinsic information from check node j to variable node i is represented as log-likelihood ratio LLR:

Defining an LDPC decoded parity check matrix H, using a B _j symbol to represent a bit set (a position set of 1 in each row) in a parity check equation of the parity check matrix H, and using A _i to represent a parity check equation of an ith bit (a position set of 1 in each column). The structure of the parity check matrix H is shown in fig. 11, and the LDPC parity check matrix H is composed of A, B, C, D, E sub-matrices. The sub-matrix A corresponds to information bits to be coded by the system; the sub-matrix B is a square matrix having a double diagonal structure corresponding to the parity check bits. The first or last column of the sub-matrix B has a weight equal to 1, the last row of the sub-matrix B has a non-zero value and a weight equal to 1, and if there is a column with a weight of 1, the remaining columns contain a square matrix such that the weight of the first column is 3. Columns following columns with a weight of 3 have diagonal structures (i.e., main diagonal and off-diagonal elements). If there is no column with a weight of 1, the sub-matrix B consists of only one square matrix, so that the weight of the first column is 3. The submatrix C is an all-zero matrix, the submatrix D corresponds to a single parity check row, and the submatrix E is a unit matrix of a base map (BG) corresponding to check bits of a low extended code rate.

Thus, the following formulas (8) to (10) can be obtained:

Wherein,

Consider the sign bit and size of M _j,i:

M_j,i＝α_j,iβ_j,i(12-a)

α_j,i＝sign(M_j,i)(12-b)

β_j,i＝|M_j,i|(12-c)

from formulas (11) and (12), we get:

Wherein, The definition is as follows:

for external information E _j,i, from In terms of (a), consider equation (13), the maximum in the summation corresponds to the minimum β _j,i. Thus, the following relationship can be obtained:

since an approximation of equation (15) is larger, the convergence rate of LDPC decoding is affected, and this equation is corrected:

Wherein lambda is a normalized scaling factor, and the value range is more than 0 and less than or equal to 1. In this embodiment, the normalized scaling factor λ is dynamically configured based on CB code blocks, that is, one normalized scaling factor λ is configured when LDPC decoding is performed for each CB code block. In particular, where the LDPC decoding duration permits, a suitable single normalized scaling factor λ may be selected to approximately scale the LLR values for all CB code blocks. In a hardware implementation, it is not practical to update the normalized scaling factor λ in real time, especially for channel decoding processing of the 5G base station uplink PUSCH. The value range of the configured normalized scaling factor lambda is 0 < lambda less than or equal to 1, and in order to improve LDPC decoding performance, the value of the normalized scaling factor lambda is preferably limited to be between 0.6 and 0.9, and the default value is generally set as lambda=0.75. In practical engineering implementation, the most suitable normalized scaling factor lambda needs to be selected according to the system simulation situation.

Thus, equation (13) can be written as:

Since each variable node can be connected with the LLR of the input channel and the LLR of each check node. The total LLR of the ith bit is the sum of the two LLRs

Where L _i represents the soft LLR values after soft demodulation.

For a gaussian white noise (AWGN) model in a communication system, the i-th sample y _i＝x_ih_i+n_i is received, where N _i conforms to an independent normal distribution N (0, σ ²),N ₀ is the noise density.

Therefore, the channel transition probability is easily obtained:

Where x ε {0,1}, then we can:

the final hard decision of LDPC decoding is composed of The sign gives the basis for the decision to check if the parity check equation/>And whether the set maximum number of decoding iterations is reached. If not, update M _j,i:

therefore, the process of parallel LDPC decoding on the CB code block processed in step S5 in step S6 includes the steps of:

M_j,i＝α_j,iβ_j,i

α_j,i＝sign(M_j,i)

β_j,i＝|M_j,i|

S64, judging an ending criterion: for i=0, 1, …, N-1, let:

According to the above, a decision is obtained If/>Or stopping decoding calculation if the decoding iteration number reaches the set maximum iteration number iter _max; otherwise, the process advances to S65.

iter_num＝iter_num+1

returning to S62, iterative decoding computation is continued.

In the LDPC decoding process, the check nodes are divided into a plurality of groups, and in each round of iterative decoding, a group of check nodes CN in the parity check matrix H are updated first, and then all variable nodes VN adjacent to the group of check nodes are updated. The CN information of the next group and the VN information adjacent to the group are then updated until the CN information and the VN information of the last group are updated. Because the updated VN information is applied to the updating process of the CN information after the iteration of the round, the iteration convergence speed is increased, the iteration times can be saved, the decoding delay is reduced, and the decoding throughput rate is improved.

The throughput rate of the LDPC decoder is calculated as follows:

N _cb is the total length of the code word before each CB code block performs LDPC decoding; cycle is a single decoding iteration time period; num _iter is the actual iteration number; Δ _t is the parameter control processing time; f _clk is the LDPC decoder clock frequency; r is the code rate.

During LDPC decoding, main parameters are as follows: the total length N _cb of the code word before LDPC decoding of each CB code block, the base graph BG1 or BG2, the parameters a and j for the index shift factor Z _c, the number mb of the parity check matrix check bit, the maximum iteration number iter _max and the like.

Wherein Z _c＝a×2^j, a= {2,3,5,7,9,11,13,15}, j= {0,1,2,3,4,5,6,7}.

The structure of each of the parallel LDPC decoders is shown in FIG. 12, and the LDPC decoder includes an input control unit, a check node unit, an LLR memory slice, a routing network module, a shift network module, and an output control unit. The input control unit realizes the configuration of LDPC decoding parameters and the flow control of data, and transmits data frames by taking the codeword length of one CB code block as a processing unit. The LLR memory slices are used for storing the input channel LLR values and the LLR values after iterative updating, and the number of the memory slices is equal to the column number of the core matrix of the parity check matrix H plus 1. The number of input pins of the check node unit is equal to the maximum row weight of the parity check matrix. And the routing network module inputs the LLR data subjected to cyclic shift in the LLR storage fragments to the pin ports of the check node unit, and the check node unit realizes the function of hierarchical scheduling decoding by reading the data on the pin ports of different groups and realizes final decoding output through iterative calculation. In order to facilitate the iterative check of LDPC decoding, the shift network module may calculate all parity check matrices H only including 0 and 1 in advance through a PCM list and a shift factor Z _c value index table provided by the 5G NR technical specification, and index the parity check matrices H through the base map BG1 or BG2 and the shift factor Z _c, thereby completing the parity check. The shift network module adopts a Banyan network structure so as to support different shift factors Z _c and hardware parallel processing. The check node memory is used for caching the check node value after each iteration and updating the variable node information when the next iteration is performed. The output control unit completes data bit width matching and cross-clock domain processing, and simultaneously sends out relevant decoding states, so that the internal execution condition of the decoder is conveniently monitored.

S7, reading out CB code blocks after parallel LDPC decoding, carrying out information bit combination, and realizing by an output control unit, wherein the structure of the output control unit is shown in FIG. 13, and the module mainly completes the polling output data stream of 4 LDPC decoders according to the CB code block requirement, and carries out cascade output on information bits decoded and output by the CB code blocks, thus essentially being a design idea of parallel-serial conversion and time division multiplexing. When the output control unit outputs, a FIFO memory is used for buffering and is used for isolating the functional modules. In fig. 13, the input control unit inputs the original frame header information, updates the frame information such as the length of the output data packet, buffers the frame information, waits for the output of the LDPC decoding result of the CB code block, and finally performs the output of the level joint. The read controller is used for controlling the data and state output read process of the 4 LDPC decoders, realizing the alignment of the data output by the TB blocks, and preventing the data among different TB transmission blocks from being cross-scrambled so as to influence the transmission of the data packet. The CB code block data counter and the state counter are all modulo-4 counters, so that the polling reading operation of 4 LDPC decoders is conveniently realized. The output selector is used for realizing the information bit combination of the LDPC decoding results of the CB code blocks through framing, namely, firstly outputting a frame header and then outputting an information bit set of the LDPC decoding results of all the CB code blocks of one TB transmission block. And finally, the data frame is put into a buffer unit, and a later CRC check module reads the combined information bit set and performs CRC check. In order to prevent the buffer unit from overflowing, the full state of the buffer unit is fed back to the read controller, so that the flow control is performed. In addition, in order to facilitate system debugging and diagnosis, a monitor is designed for monitoring the state of the output control unit in real time and grabbing key information for on-line analysis and diagnosis.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The LDPC decoding delay optimization method based on 5G is characterized by comprising the following steps:

s4, cutting and punching the code word check bit of the CB code block; step S4 comprises the following sub-steps:

N_cb＝N+2Z_c (1)

Wherein N is the codeword length before CB code block phase shift;

S42, calculating a codeword check bit length _paritybits of the CB code block:

length_paritybits＝N+2Z_c-K (2)

s44, obtaining a relation between mb and N according to formulas (1) - (3):

N＝K+Z_c(mb-2) (4)

S45, calculating an actual coding rate R:

When calculating mb, rounding is needed, and the value is not smaller than 4;

S47, under the modulation coding scheme MCS, aiming at redundancy version RV=0, clipping and punching check bits of CB code blocks output by rate-demodulation matching processing, calculating mb by a formula (6) after removing LLR soft values filled with 0x00 at the tail, and substituting the calculated mb into the formula (4), wherein the obtained codeword length N is the codeword length N 'before shifting CB code blocks and after clipping and punching'

2. The 5G-based LDPC decoding delay optimization method of claim 1, wherein in step S2, symbol-level and bit-level signal processing of the PUSCH link includes sequentially performing OFDM demodulation, channel estimation, MIMO equalization, demapping and soft demodulation at a symbol level, and descrambling and rate-matching at a bit level.

3. The method for optimizing delay time of LDPC decoding based on 5G according to claim 2 wherein, when performing bit-level decoding rate matching, dividing the TB transmission block obtained after descrambling into a plurality of CB code blocks with equal codeword lengths according to the processing mode of decoding rate matching according to the parameters required by the PUSCH link processing module, wherein the codeword length of each CB code block is N; and when the bit-level solution Rate matching is performed, the MAC layer schedule confirms whether to perform HARQ retransmission according to indexes such as Block Error Rate (Block Error Rate):

4. The 5G-based LDPC decoding delay optimization method of claim 1, wherein in step S3, whether to perform LDPC decoding delay optimization on CB code blocks is determined according to a modulation coding schedule MCS, a code rate R, a redundancy version RV, a signal-to-noise ratio SNR, and a data traffic demand.

5. The 5G-based LDPC decoding delay optimization method of claim 1, wherein in step S5, after filling "0x00" into 2Z _c LLR soft values at the start of CB code block, information is next the sum check bits; the total length of codewords fed into the LDPC decoding is therefore:

6. The 5G-based LDPC decoding delay optimization method of claim 5, wherein the operation of filling "0x00" into 2Z _c LLR soft values at the start of CB code blocks is implemented by designing a state machine FSM in step S5.

7. The 5G-based LDPC decoding delay optimization method of claim 6, wherein the state machine FSM comprises four states:

8. The 5G-based LDPC decoding delay optimization method of claim 7, wherein data concatenation is required after filling "0x00" into 2Z _c LLR soft values at the beginning of CB code block:

9. The 5G-based LDPC decoding delay optimization method of claim 1, wherein step S6 comprises the sub-steps of:

M_j,i＝α_j,iβ_j,i

α_j,i＝sign(M_j,i)

β_j,i＝|M_j,i|

S64, judging an ending criterion: for i=0, 1, …, N-1, let:

iter_num＝iter_num+1

returning to S62, iterative decoding computation is continued.