CN114866047A - Bi-Hemt technology-based broadband dual-channel transceiving amplification chip - Google Patents

Bi-Hemt technology-based broadband dual-channel transceiving amplification chip Download PDF

Info

Publication number
CN114866047A
CN114866047A CN202210792416.6A CN202210792416A CN114866047A CN 114866047 A CN114866047 A CN 114866047A CN 202210792416 A CN202210792416 A CN 202210792416A CN 114866047 A CN114866047 A CN 114866047A
Authority
CN
China
Prior art keywords
resistor
inductor
triode
capacitor
network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210792416.6A
Other languages
Chinese (zh)
Other versions
CN114866047B (en
Inventor
叶珍
童伟
邬海峰
胡柳林
王测天
滑育楠
廖学介
刘莹
吴曦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Ganide Technology Co ltd
Original Assignee
Chengdu Ganide Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Ganide Technology Co ltd filed Critical Chengdu Ganide Technology Co ltd
Priority to CN202210792416.6A priority Critical patent/CN114866047B/en
Publication of CN114866047A publication Critical patent/CN114866047A/en
Application granted granted Critical
Publication of CN114866047B publication Critical patent/CN114866047B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

The invention discloses a broadband dual-channel transceiving amplification chip based on a Bi-Hemt process, which belongs to the technical field of integrated circuits and comprises a first switch switching network, a novel traveling wave amplification network, a novel current multiplexing amplification network, a first active bias network, a second active bias network and a second switch switching network. The invention adopts the Bi-HEMT technology, and the technology integrates the HBT device and the pHEMT device, thereby enabling the circuit design to be more flexible; the novel traveling wave network is adopted in the emission channel of the chip circuit, so that the performance of the traditional traveling wave structure such as broadband and good matching characteristic is kept, and the chip circuit has the characteristics of high gain, high power and high linearity; a receiving channel of the circuit adopts a novel current multiplexing amplification network, so that the receiving channel has the characteristics of wide band, low noise, high gain and high linearity; meanwhile, the whole circuit has good isolation and temperature self-adaptive characteristics.

Description

Bi-Hemt technology-based broadband dual-channel transceiving amplification chip
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a broadband dual-channel transceiving amplification chip based on a Bi-Hemt process.
Background
With the trend of miniaturization of microwave systems, it is often necessary to integrate a low noise amplifier LNA and a power amplifier PA on one chip to perform amplification switching of received and transmitted signals. The existing transmitting-receiving amplification multifunctional chip usually adopts the same type of transistor during design, so that the low-noise characteristic of a receiving channel is difficult to meet while the high-power and high-linearity output of a transmitting channel is met. In a broadband circuit, due to the limitation of gain-bandwidth product and the difficulty of broadband matching, it is very challenging to achieve high gain and high linearity output.
Disclosure of Invention
In order to solve the problems, the invention provides a broadband dual-channel transceiving amplification chip based on a Bi-Hemt process.
The technical scheme of the invention is as follows: a broadband dual-channel transceiving amplification chip based on a Bi-Hemt process is characterized by comprising a first switch switching network, a novel traveling wave amplification network, a novel current multiplexing amplification network, a first active bias network, a second active bias network and a second switch switching network;
the first input end of the first switch switching network is used as the transmitting input end/receiving output end of the broadband dual-channel transceiving amplification chip, the second input end of the first switch switching network is connected with the output end of the novel current multiplexing amplification network, and the output end of the first switch switching network is connected with the first input end of the novel traveling wave amplification network;
the first output end of the second switch switching network is used as the transmitting output end/receiving input end of the broadband dual-channel transceiving amplification chip, the second output end of the second switch switching network is connected with the input end of the novel current multiplexing amplification network, and the input end of the second switch switching network is connected with the output end of the novel traveling wave amplification network;
the output end of the first active bias network is connected with the second input end of the novel traveling wave amplification network; the first output end of the second active bias network is connected with the third input end of the novel traveling wave amplification network; and the second output end of the second active bias network is connected with the fourth input end of the novel traveling wave amplification network.
The invention has the beneficial effects that:
(1) the invention adopts a Bi-HEMT process, which integrates an HBT device and a pHEMT device, wherein the pHEMT device has the characteristics of high input impedance, low noise, good thermal stability and the like, and the HBT device has the advantages of high linearity, high transconductance, strong current driving capability and the like, so that the design is more flexible, and particularly, the optimal performance of transmitting and receiving is realized in a transceiving integrated circuit.
(2) The broadband dual-channel transceiving amplification chip has a dual-channel transceiving amplification function, transceiving switching is completed by adopting a balanced single-pole double-throw switch and an unbalanced single-pole double-throw switch, and a circuit has high isolation; the single-pole double-throw switch with the unbalanced structure can bear larger voltage swing and higher power capacity of a transmitting channel, lower differential loss of a receiving channel is considered, and lower noise of the receiving channel is guaranteed.
(3) The transmitting channel of the invention adopts a novel traveling wave amplification network. The structure adopts five sub-networks, and each sub-network is composed of two stages of amplifying circuits. This novel traveling wave amplification network has kept under the wide advantage of traditional traveling wave structure operating frequency band, can also realize following function: firstly, the circuit achieves very high gain; secondly, the pHEMT tube has high input impedance, is beneficial to input matching when placed at the front stage, has good thermal stability and can improve the reliability of the circuit; thirdly, the HBT tube is positioned at the final stage and is innovatively synthesized by the main transistor and the auxiliary transistor, so that the circuit not only can realize higher output power, but also has good linearity.
(4) The receiving channel of the invention adopts a novel current multiplexing amplifying network. The structure combines a current multiplexing structure, a Darlington structure and a negative feedback structure, and adopts a pHEMT tube at the first stage to ensure the low noise characteristic of the circuit, and adopts an HBT tube at the last stage to ensure the high linear output characteristic of the circuit, so that the novel current multiplexing amplification network has the characteristics of broadband, low noise, high gain and high linearity. Meanwhile, the feed network and the radio frequency network are partially shared, so that the chip area is reduced.
(5) The transmitting channel and the receiving channel of the invention both adopt the self-adaptive active bias network, so that when the external environment changes or the self heat effect generates temperature change, the circuit keeps more stable performance through self-adaptive adjustment, and simultaneously, the reliability of the circuit is improved.
Further, the first switch switching network comprises a resistor Rs1, a resistor Rs2, a resistor Rs3, a resistor Rs4, a capacitor Cs1, a microstrip line TLs1, a microstrip line TLs2, a microstrip line TLs3, a switch tube Ms1, a switch tube Ms2, a switch tube Ms3 and a switch tube Ms 4;
one end of the capacitor Cs1 is used as a first input end of the first switch switching network, and the other end of the capacitor Cs1 is connected to one end of the microstrip line TLs 1; the other end of the microstrip line TLs1 is connected with the drain of the switch tube Ms1 and the drain of the switch tube Ms3 respectively; the gate of the switch tube Ms1 is connected with one end of the resistor Rs 1; the other end of the resistor Rs1 is connected with a control voltage Vcon 1; the source electrode of the switch tube Ms1 is connected with the drain electrode of the switch tube Ms 2; the gate of the switch tube Ms2 is connected with one end of the resistor Rs 2; the other end of the resistor Rs2 is connected with a control voltage Vcon 1; the source of the switch tube Ms2 is connected with one end of the microstrip line TLs 2; the other end of the microstrip line TLs2 is used as the output end of the first switch switching network; the gate of the switch tube Ms3 is connected with one end of the resistor Rs 3; the other end of the resistor Rs3 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms3 is connected with the drain electrode of the switch tube Ms 4; the gate of the switch tube Ms4 is connected with one end of the resistor Rs 4; the other end of the resistor Rs4 is connected with a control voltage Vcon 2; the source of the switch tube Ms4 is connected with one end of the microstrip line TLs 3; the other end of the microstrip line TLs3 serves as a second input terminal of the first switching network.
The beneficial effects of the further scheme are as follows: the first switch switching network adopts a balanced structure, and each side adopts two switch tubes connected in series, so that the bandwidth can be expanded, and the first switch switching network has smaller difference loss.
Further, the novel traveling wave amplification network includes a resistor Rg, a ground resistor Rg, a resistor Rt, a capacitor Ct, a ground capacitor Ct, a capacitor Ct, an inductor Lt, an inductor microstrip line Lt, an inductor Lt, a microstrip line Lt, an inductor TLt, an inductor, a microstrip line, an inductor Lt, a microstrip line Lt, an inductor Lt, a microstrip line, an inductor Lt, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, an inductor, a microstrip line, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, an inductor, a microstrip line, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, an inductor Lt, a microstrip line, a microstrip line TLt4, a transistor Ht1, a transistor Ht2, a transistor Ht3, a transistor Ht4, a transistor Ht5, a transistor Ht6, a transistor Ht7, a transistor Ht8, a transistor Ht9, a transistor Ht10, a field effect transistor Mt1, a field effect transistor Mt2, a field effect transistor Mt3, a field effect transistor Mt4, and a field effect transistor Mt 5;
one end of the capacitor Ct1 is used as a first input end of the novel traveling wave amplification network; one end of the resistor Rt1 is used as a second input end of the novel traveling wave amplification network and is respectively connected with one end of the resistor Rt2, one end of the resistor Rt3, one end of the resistor Rt4 and one end of the resistor Rt 5; the other end of the resistor Rt1 is respectively connected with the base of the triode Ht1 and one end of the capacitor Ct 2; the collector of the triode Ht1 is connected with one end of the inductor Lt 9; the emitter of the triode Ht1 is grounded; the base electrode of the triode Ht2 is respectively connected with one end of a resistor Rt6 and one end of a capacitor Ct 7; the collector of the triode Ht2 is connected with one end of the inductor Lt 10; the emitter of the triode Ht2 is grounded; the other end of the inductor Lt9 is respectively connected with one end of a resistor Rt12, one end of an inductor Lt23, one end of an inductor Lt19 and the other end of an inductor Lt 10; the other end of the resistor Rt12 is connected with a grounding capacitor Ct 13; the base electrode of the triode Ht3 is respectively connected with the other end of the resistor Rt2 and one end of the capacitor Ct 3; the collector of the triode Ht3 is connected with one end of the inductor Lt 11; the emitter of the triode Ht3 is grounded; the base electrode of the triode Ht4 is respectively connected with one end of a resistor Rt7 and one end of a capacitor Ct 8; the collector of the triode Ht4 is connected with one end of the inductor Lt 12; the emitter of the triode Ht4 is grounded; the other end of the inductor Lt11 is connected with the other end of the inductor Lt19, one end of the inductor Lt20 and the other end of the inductor Lt12 respectively; the base electrode of the triode Ht5 is respectively connected with the other end of the resistor Rt3 and one end of the capacitor Ct 4; the collector of the triode Ht5 is connected with one end of the inductor Lt 13; the emitter of the triode Ht5 is grounded; the base electrode of the triode Ht6 is respectively connected with one end of a resistor Rt8 and one end of a capacitor Ct 9; the collector of the triode Ht6 is connected with one end of the inductor Lt 14; the emitter of the triode Ht6 is grounded; the other end of the inductor Lt13 is connected with the other end of the inductor Lt20, one end of the inductor Lt21 and the other end of the inductor Lt14 respectively; the base electrode of the triode Ht7 is respectively connected with the other end of the resistor Rt4 and one end of the capacitor Ct 5; the collector of the triode Ht7 is connected with one end of the inductor Lt 15; the emitter of the triode Ht7 is grounded; the base electrode of the triode Ht8 is respectively connected with one end of a resistor Rt9 and one end of a capacitor Ct 10; the collector of the triode Ht8 is connected with one end of the inductor Lt 16; the emitter of the triode Ht8 is grounded; the other end of the inductor Lt15 is connected with the other end of the inductor Lt21, one end of the inductor Lt22 and the other end of the inductor Lt16 respectively; the base electrode of the triode Ht9 is respectively connected with the other end of the resistor Rt5 and one end of the capacitor Ct 6; the collector of the triode Ht9 is connected with one end of the inductor Lt 17; the emitter of the triode Ht9 is grounded; the base electrode of the triode Ht10 is respectively connected with one end of a resistor Rt10 and one end of a capacitor Ct 11; the collector of the triode Ht10 is connected with one end of the inductor Lt 18; the emitter of the triode Ht10 is grounded; the other end of the inductor Lt17 is connected with the other end of the inductor Lt22, one end of the capacitor Ct15 and the other end of the inductor Lt18 respectively; the other end of the inductor Lt23 is respectively connected with one end of an inductor Lt24, one end of a resistor Rt13 and the power supply voltage VDT of the novel traveling wave amplification network; the other end of the resistor Rt13 is connected with a grounding capacitor Ct 14; the grid electrode of the field effect transistor Mt1 is respectively connected with the other end of the capacitor Ct1, one end of the resistor Rg6 and one end of the inductor Lt 1; the drain electrode of the field effect transistor Mt1 is respectively connected with the other end of the inductor Lt24, the other end of the capacitor Ct2, the other end of the capacitor Ct7 and one end of the inductor Lt 5; the source electrode of the field effect transistor Mt1 is grounded; the grid electrode of the field effect transistor Mt2 is respectively connected with the other end of the inductor Lt1 and one end of the inductor Lt 2; the drain electrode of the field effect transistor Mt2 is respectively connected with the other end of the inductor Lt5, the other end of the capacitor Ct3, the other end of the capacitor Ct8 and one end of the inductor Lt 6; the source electrode of the field effect transistor Mt2 is grounded; the grid electrode of the field effect transistor Mt3 is respectively connected with the other end of the inductor Lt2 and one end of the inductor Lt 3; the drain electrode of the field effect transistor Mt3 is respectively connected with the other end of the inductor Lt6, the other end of the capacitor Ct4, the other end of the capacitor Ct9 and one end of the inductor Lt 7; the source electrode of the field effect transistor Mt3 is grounded; the grid electrode of the field effect transistor Mt4 is respectively connected with the other end of the inductor Lt3 and one end of the inductor Lt 4; the drain electrode of the field effect transistor Mt4 is respectively connected with the other end of the inductor Lt7, the other end of the capacitor Ct5, the other end of the capacitor Ct10 and one end of the inductor Lt 8; the source electrode of the field effect transistor Mt4 is grounded; the grid electrode of the field effect transistor Mt5 is respectively connected with the other end of the inductor Lt4 and one end of the resistor Rt 11; the drain electrode of the field effect transistor Mt5 is respectively connected with the other end of the inductor Lt8, the other end of the capacitor Ct6 and the other end of the capacitor Ct 11; the source electrode of the field effect transistor Mt5 is grounded; the other end of the resistor Rt11 is connected with a grounding capacitor Ct 12; the other end of the resistor Rg6 is connected with one end of a grounding resistor Rg7 and one end of a resistor Rg5 respectively; the other end of the resistor Rg5 is used as a third input end of the novel traveling wave amplification network; one end of the microstrip line TLt1 is used as a fourth input end of the novel traveling wave amplification network and is connected with the other end of the resistor Rt 6; the other end of the microstrip line TLt1 is connected with the other end of the resistor Rt7 and one end of the microstrip line TLt2 respectively; the other end of the microstrip line TLt2 is connected with the other end of the resistor Rt8 and one end of the microstrip line TLt3 respectively; the other end of the microstrip line TLt3 is connected with the other end of the resistor Rt9 and one end of the microstrip line TLt4 respectively; the other end of the microstrip line TLt4 is connected with the other end of the resistor Rt 10; the other end of the capacitor Ct15 is used as the output end of the novel traveling wave amplification network.
The beneficial effects of the further scheme are as follows: in the invention, a novel traveling wave amplification network is adopted in the emission channel. The novel traveling wave amplification network adopts five sub-networks, and each sub-network consists of two stages of amplification circuits in order to improve the gain. The pHEMT transistor has a low noise figure and a high input impedance, and is used in the former stage, and the HBT transistor has a high linearity and a good current driving capability, and is used in the final stage. Therefore, pHEMT tubes (Mt 1-Mt 5) are adopted in the first stage, each tube has the same size and the same offset, and the pHEMT tubes are used for improving the gain of the circuit and providing enough driving capability for the second stage; the second stage employs HBT transistors (Ht 1-Ht 10) with transistors Hti and Ht (i +1) in each sub-network for maximum output efficiency, where i =1,3,5,7, 9; the transistor Hti is a main transistor, the bias of the transistor is in class AB, the bias of the transistor Ht (i +1) is an auxiliary transistor, and the bias of the transistor is in class C, so that the inband intermodulation signal can be restrained, and the linear output power of the circuit can be improved. In addition, the HBT transistor has the characteristics of high linearity and low harmonic wave, and the novel traveling wave amplification network has good linearity and ideal output efficiency. The radio frequency input end of each traveling wave sub-network is connected through an inductor Lt1-Lt4, the output ends of two main HBT transistors and two auxiliary HBT transistors of the second stage of each sub-network are connected with an inductor (Lt 9-Lt 18) for adjusting phase delay, so that in-band harmonic components can be inhibited, good linearity is achieved, the main transistors and the auxiliary transistors of each stage are connected through inductors Lt19-Lt22 after being synthesized, the propagation phase speeds among each stage can be consistent as much as possible, and the working bandwidth can be effectively widened. In conclusion, the novel traveling wave amplification network not only keeps the performance of the traditional traveling wave structure broadband and good matching characteristics, but also has the characteristics of high gain, high power and high linearity.
Further, the novel current multiplexing amplification network comprises a ground resistor Rr1, a resistor Rr2, a resistor Rr3, a ground resistor Rr4, a resistor Rr5, a ground resistor Rr6, a resistor Rr7, a resistor Rr8, a resistor Rr9, a resistor Rr10, a resistor Rr11, a resistor Rr12, a capacitor Cr1, a capacitor Cr2, a ground capacitor Cr3, a capacitor Cr4, a capacitor Cr5, a ground capacitor Cr6, a ground capacitor Cr7, a ground capacitor Cr8, a ground capacitor Cr9, a capacitor Cr10, an inductor Lr1, an inductor Lr2, an inductor Lr3, an inductor Lr4, an inductor Lr5, a microstrip line TLr1, a triode Hr1, a triode Hr2, a triode Hr3, a field effect transistor Mr1 and a field effect transistor Mr 2;
one end of the capacitor Cr10 is used as the output end of the novel current multiplexing amplification network, and the other end of the capacitor Cr10 is respectively connected with one end of the grounding capacitor Cr9 and one end of the inductor Lr 5; the base electrode of the triode Hr1 is respectively connected with the collector electrode of the triode Hr3, one end of the capacitor Cr4 and one end of the resistor Rr 7; the collector of the triode Hr1 is respectively connected with the collector of the triode Hr2, one end of the inductor Lr4, the other end of the inductor Lr5, one end of the capacitor Cr5 and one end of the resistor Rr 8; the other end of the resistor Rr7 is connected with the other end of the capacitor Cr5 and the other end of the resistor Rr8 respectively; an emitter electrode of the triode Hr1 is respectively connected with a base electrode of the triode Hr2, one end of the resistor Rr11 and one end of the resistor Rr 10; the other end of the inductor Lr4 is respectively connected with one end of a resistor Rr12 and a power supply voltage VDR of the novel current multiplexing network; the other end of the resistor Rr12 is connected with a grounding capacitor Cr 8; an emitter of the triode Hr2 is respectively connected with the grounding capacitor Cr7, one end of the inductor Lr3 and the other end of the resistor Rr 11; the base electrode of the triode Hr3 is connected with one end of the resistor Rr 9; the other end of the resistor Rr9 is connected with the other end of the resistor Rr10 and the grounding capacitor Cr6 respectively; the emitter of the triode Hr3 is connected with the grounding resistor Rr 6; the other end of the capacitor Cr4 is respectively connected with one end of a resistor Rr5 and one end of an inductor Lr 2; the other end of the resistor Rr5 is connected with a grounding capacitor Cr 3; the other end of the inductor Lr2 is connected with the other end of the inductor Lr3 and one end of the microstrip line TLr1 respectively; the grid of the field effect transistor Mr1 is respectively connected with one end of a grounding resistor Rr1, one end of an inductor Lr1 and one end of a resistor Rr 2; the drain of the field effect transistor Mr1 is respectively connected with the other end of the microstrip line TLr1, the drain of the field effect transistor Mr2, one end of the capacitor Cr2 and one end of the resistor Rr 3; the source electrode of the field effect tube Mr1 is respectively connected with the grid electrode of the field effect tube Mr2 and the grounding resistor Rr 4; the source electrode of the field effect transistor Mr2 is grounded; the other end of the resistor Rr2 is connected with the other end of the capacitor Cr2 and the other end of the resistor Rr3 respectively; the other end of the inductor Lr1 is connected with one end of the capacitor Cr 1; the other end of the capacitor Cr1 is used as the input end of the novel current multiplexing amplification network.
The beneficial effects of the further scheme are as follows: in the invention, a novel current multiplexing amplification network is adopted in a receiving channel. The novel current multiplexing amplification network combines a Darlington structure and a current multiplexing structure, a Darlington tube composed of two pHEMT transistors Mr1 and Mr2 is positioned at the front stage and used for realizing low-noise characteristics, and a Darlington tube composed of two HBT tubes Hr1 and Hr2 is positioned at the last stage and used for realizing high-linearity characteristics. The characteristic of the darlington tube is that the amplification factor is very high, the amplification factor is the product of two transistors that make up the darlington tube. In the circuit, two Darlington tubes are cascaded, and the current flowing through the first-stage pHEMT Darlington tube simultaneously flows through the second-stage HBT Darlington tube, so that the gain is further improved while the current is multiplexed, and the bandwidth can be well expanded by the Darlington structure and the current multiplexing structure. Therefore, the novel current multiplexing amplification network has the characteristics of wide band, low noise, high gain and high linearity.
Further, the first active bias network comprises a resistor Rg1, a resistor Rg2 at ground, a capacitor Cg1 at ground, a transistor Hg1, a transistor Hg2 and a transistor Hg 3;
the base electrode of the triode Hg1 is respectively connected with the base electrode of the triode Hg2, the collector electrode of the triode Hg2, one end of the resistor Rg1 and the grounding capacitor Cg 1; the collector of the triode Hg1 is respectively connected with the other end of the resistor Rg1 and a first active bias network bias voltage VG 1; an emitter of the transistor Hg1 is used as an output end of the first active bias network; the emitter of the triode Hg2 is respectively connected with the base of the triode Hg3 and the collector of the triode Hg 3; the emitter of the triode Hg3 is connected with a grounding resistor Rg 2.
Further, the second active bias network comprises a capacitor Cg2, a resistor Rg3, a resistor Rg4, a transistor Hg4, a transistor Hg5 and a transistor Hg 6;
the base electrode of the triode Hg4 is respectively connected with the grounding capacitor Cg2, the base electrode of the triode Hg5, the collector electrode of the triode Hg5 and one end of the resistor Rg 3; a collector of the triode Hg4 is used as a first output end of the second active bias network and is respectively connected with the other end of the resistor Rg3 and a bias voltage VG2 of the second active bias network; an emitter of the transistor Hg4 is used as a second output end of the second active bias network; the emitter of the triode Hg5 is respectively connected with the base of the triode Hg6 and the collector of the triode Hg 6; the emitter of the triode Hg6 is connected with a grounding resistor Rg 4.
The beneficial effects of the further scheme are as follows: in the invention, the transmitting channel and the receiving channel of the invention both adopt the self-adaptive active bias network, so that when the external environment changes or the self thermal effect generates temperature change, the circuit keeps more stable performance through self-adaptive adjustment, and simultaneously, the reliability of the circuit is improved.
Further, the second switch switching network comprises a resistor Rs5, a resistor Rs6, a resistor Rs7, a resistor Rs8, a resistor Rs9, a capacitor Cs2, a microstrip line TLs4, a microstrip line TLs5, a microstrip line TLs6, a switch tube Ms5, a switch tube Ms6, a switch tube Ms7, a switch tube Ms8 and a switch tube Ms 9;
one end of the microstrip line TLs4 is used as the input end of the second switch switching network, and the other end is connected with the drain of the switch tube Ms6 and the source of the switch tube Ms5 respectively; the base electrode of the switch tube Ms6 is connected with one end of the resistor Rs 6; the other end of the resistor Rs6 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms6 is connected with the drain electrode of the switch tube Ms 7; the base electrode of the switch tube Ms7 is connected with one end of a resistor Rs 7; the source of the switch tube Ms7 is grounded; the other end of the resistor Rs7 is connected with a control voltage Vcon 2; the base electrode of the switch tube Ms5 is connected with one end of the resistor Rs 5; the other end of the resistor Rs5 is connected with a control voltage Vcon 1; the drain electrode of the switch tube Ms5 is respectively connected with the drain electrode of the switch tube Ms8 and one end of the microstrip line Tls 6; the other end of the microstrip line TLs6 is connected with one end of a capacitor Cs 2; the other end of the capacitor Cs2 is used as a first output end of the second switching network; the base electrode of the switch tube Ms8 is connected with one end of the resistor Rs 8; the other end of the resistor Rs8 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms8 is connected with the drain electrode of the switch tube Ms 9; the base electrode of the switch tube Ms9 is connected with one end of the resistor Rs 9; the other end of the resistor Rs9 is connected with a control voltage Vcon 2; the source of the switch tube Ms9 is connected with one end of the microstrip line TLs 5; the other end of the microstrip line TLs5 serves as a second output terminal of the second switching network.
The beneficial effects of the further scheme are as follows: in the invention, the second switch switching network adopts an unbalanced structure, and the switch network is positioned at the tail end of the transmitting channel, so that the switch network needs to bear larger voltage swing and higher power capacity, and a serial pipe and two stacked parallel pipes are adopted for connecting the transmitting channel; connecting the receiving channels requires both noise and isolation, so two series pipes are used. The switch structure can well expand the bandwidth, has higher isolation degree and can ensure higher output power.
Drawings
Fig. 1 is a schematic block diagram of a Bi-Hemt process-based broadband dual-channel transceiver amplifier chip according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a broadband dual-channel transceiver amplifier chip based on a Bi-Hemt process according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a Bi-Hemt process-based wideband dual-channel transceiving amplification chip, which comprises a first switch switching network, a novel traveling wave amplification network, a novel current multiplexing amplification network, a first active bias network, a second active bias network and a second switch switching network;
the first input end of the first switch switching network is used as the transmitting input end/receiving output end of the broadband dual-channel transceiving amplification chip, the second input end of the first switch switching network is connected with the output end of the novel current multiplexing amplification network, and the output end of the first switch switching network is connected with the first input end of the novel traveling wave amplification network;
the first output end of the second switch switching network is used as the transmitting output end/receiving input end of the broadband dual-channel transceiving amplification chip, the second output end of the second switch switching network is connected with the input end of the novel current multiplexing amplification network, and the input end of the second switch switching network is connected with the output end of the novel traveling wave amplification network;
the output end of the first active bias network is connected with the second input end of the novel traveling wave amplification network; the first output end of the second active bias network is connected with the third input end of the novel traveling wave amplification network; and the second output end of the second active bias network is connected with the fourth input end of the novel traveling wave amplification network.
In the embodiment of the present invention, as shown in fig. 2, the first switch switching network includes a resistor Rs1, a resistor Rs2, a resistor Rs3, a resistor Rs4, a capacitor Cs1, a microstrip line TLs1, a microstrip line TLs2, a microstrip line TLs3, a switch tube Ms1, a switch tube Ms2, a switch tube Ms3, and a switch tube Ms 4;
one end of the capacitor Cs1 is used as a first input end of the first switch switching network, and the other end of the capacitor Cs1 is connected to one end of the microstrip line TLs 1; the other end of the microstrip line TLs1 is connected with the drain of the switch tube Ms1 and the drain of the switch tube Ms3 respectively; the gate of the switch tube Ms1 is connected with one end of the resistor Rs 1; the other end of the resistor Rs1 is connected with a control voltage Vcon 1; the source electrode of the switch tube Ms1 is connected with the drain electrode of the switch tube Ms 2; the gate of the switch tube Ms2 is connected with one end of the resistor Rs 2; the other end of the resistor Rs2 is connected with a control voltage Vcon 1; the source of the switch tube Ms2 is connected with one end of the microstrip line TLs 2; the other end of the microstrip line TLs2 is used as the output end of the first switch switching network; the gate of the switch tube Ms3 is connected with one end of the resistor Rs 3; the other end of the resistor Rs3 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms3 is connected with the drain electrode of the switch tube Ms 4; the gate of the switch tube Ms4 is connected with one end of the resistor Rs 4; the other end of the resistor Rs4 is connected with a control voltage Vcon 2; the source of the switch tube Ms4 is connected with one end of the microstrip line TLs 3; the other end of the microstrip line TLs3 serves as a second input terminal of the first switching network.
In the embodiment of the present invention, as shown in fig. 2, the novel traveling wave amplifying network includes a resistor Rg, a resistor Rt, a ground resistor Rt, a capacitor Ct, a ground capacitor Ct, a capacitor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, an inductor Lt, a resistor, an inductor Lt, a resistor, an inductor Lt, a microstrip line TLt2, a microstrip line TLt3, a microstrip line TLt4, a transistor Ht1, a transistor Ht2, a transistor Ht3, a transistor Ht4, a transistor Ht5, a transistor Ht6, a transistor Ht7, a transistor Ht8, a transistor Ht9, a transistor Ht10, a field effect transistor Mt1, a field effect transistor Mt2, a field effect transistor Mt3, a field effect transistor Mt4, and a field effect transistor Mt 5;
one end of the capacitor Ct1 is used as a first input end of the novel traveling wave amplification network; one end of the resistor Rt1 is used as a second input end of the novel traveling wave amplification network and is respectively connected with one end of the resistor Rt2, one end of the resistor Rt3, one end of the resistor Rt4 and one end of the resistor Rt 5; the other end of the resistor Rt1 is respectively connected with the base of the triode Ht1 and one end of the capacitor Ct 2; the collector of the triode Ht1 is connected with one end of the inductor Lt 9; the emitter of the triode Ht1 is grounded; the base electrode of the triode Ht2 is respectively connected with one end of a resistor Rt6 and one end of a capacitor Ct 7; the collector of the triode Ht2 is connected with one end of the inductor Lt 10; the emitter of the triode Ht2 is grounded; the other end of the inductor Lt9 is respectively connected with one end of a resistor Rt12, one end of an inductor Lt23, one end of an inductor Lt19 and the other end of an inductor Lt 10; the other end of the resistor Rt12 is connected with a grounding capacitor Ct 13; the base electrode of the triode Ht3 is respectively connected with the other end of the resistor Rt2 and one end of the capacitor Ct 3; the collector of the triode Ht3 is connected with one end of the inductor Lt 11; the emitter of the triode Ht3 is grounded; the base electrode of the triode Ht4 is respectively connected with one end of a resistor Rt7 and one end of a capacitor Ct 8; the collector of the triode Ht4 is connected with one end of the inductor Lt 12; the emitter of the triode Ht4 is grounded; the other end of the inductor Lt11 is connected with the other end of the inductor Lt19, one end of the inductor Lt20 and the other end of the inductor Lt12 respectively; the base electrode of the triode Ht5 is respectively connected with the other end of the resistor Rt3 and one end of the capacitor Ct 4; the collector of the triode Ht5 is connected with one end of the inductor Lt 13; the emitter of the triode Ht5 is grounded; the base electrode of the triode Ht6 is respectively connected with one end of a resistor Rt8 and one end of a capacitor Ct 9; the collector of the triode Ht6 is connected with one end of the inductor Lt 14; the emitter of the triode Ht6 is grounded; the other end of the inductor Lt13 is connected with the other end of the inductor Lt20, one end of the inductor Lt21 and the other end of the inductor Lt14 respectively; the base electrode of the triode Ht7 is respectively connected with the other end of the resistor Rt4 and one end of the capacitor Ct 5; the collector of the triode Ht7 is connected with one end of the inductor Lt 15; the emitter of the triode Ht7 is grounded; the base electrode of the triode Ht8 is respectively connected with one end of a resistor Rt9 and one end of a capacitor Ct 10; the collector of the triode Ht8 is connected with one end of the inductor Lt 16; the emitter of the triode Ht8 is grounded; the other end of the inductor Lt15 is connected with the other end of the inductor Lt21, one end of the inductor Lt22 and the other end of the inductor Lt16 respectively; the base electrode of the triode Ht9 is respectively connected with the other end of the resistor Rt5 and one end of the capacitor Ct 6; the collector of the triode Ht9 is connected with one end of the inductor Lt 17; the emitter of the triode Ht9 is grounded; the base electrode of the triode Ht10 is respectively connected with one end of a resistor Rt10 and one end of a capacitor Ct 11; the collector of the triode Ht10 is connected with one end of the inductor Lt 18; the emitter of the triode Ht10 is grounded; the other end of the inductor Lt17 is connected with the other end of the inductor Lt22, one end of the capacitor Ct15 and the other end of the inductor Lt18 respectively; the other end of the inductor Lt23 is respectively connected with one end of an inductor Lt24, one end of a resistor Rt13 and the power supply voltage VDT of the novel traveling wave amplification network; the other end of the resistor Rt13 is connected with a grounding capacitor Ct 14; the grid electrode of the field effect transistor Mt1 is respectively connected with the other end of the capacitor Ct1, one end of the resistor Rg6 and one end of the inductor Lt 1; the drain electrode of the field effect transistor Mt1 is respectively connected with the other end of the inductor Lt24, the other end of the capacitor Ct2, the other end of the capacitor Ct7 and one end of the inductor Lt 5; the source electrode of the field effect transistor Mt1 is grounded; the grid electrode of the field effect transistor Mt2 is respectively connected with the other end of the inductor Lt1 and one end of the inductor Lt 2; the drain electrode of the field effect transistor Mt2 is respectively connected with the other end of the inductor Lt5, the other end of the capacitor Ct3, the other end of the capacitor Ct8 and one end of the inductor Lt 6; the source electrode of the field effect transistor Mt2 is grounded; the grid electrode of the field effect transistor Mt3 is respectively connected with the other end of the inductor Lt2 and one end of the inductor Lt 3; the drain electrode of the field effect transistor Mt3 is respectively connected with the other end of the inductor Lt6, the other end of the capacitor Ct4, the other end of the capacitor Ct9 and one end of the inductor Lt 7; the source electrode of the field effect transistor Mt3 is grounded; the grid electrode of the field effect transistor Mt4 is respectively connected with the other end of the inductor Lt3 and one end of the inductor Lt 4; the drain electrode of the field effect transistor Mt4 is respectively connected with the other end of the inductor Lt7, the other end of the capacitor Ct5, the other end of the capacitor Ct10 and one end of the inductor Lt 8; the source electrode of the field effect transistor Mt4 is grounded; the grid electrode of the field effect transistor Mt5 is respectively connected with the other end of the inductor Lt4 and one end of the resistor Rt 11; the drain electrode of the field effect transistor Mt5 is respectively connected with the other end of the inductor Lt8, the other end of the capacitor Ct6 and the other end of the capacitor Ct 11; the source electrode of the field effect transistor Mt5 is grounded; the other end of the resistor Rt11 is connected with a grounding capacitor Ct 12; the other end of the resistor Rg6 is connected with one end of a grounding resistor Rg7 and one end of a resistor Rg5 respectively; the other end of the resistor Rg5 is used as a third input end of the novel traveling wave amplification network; one end of the microstrip line TLt1 is used as a fourth input end of the novel traveling wave amplification network and is connected with the other end of the resistor Rt 6; the other end of the microstrip line TLt1 is connected with the other end of the resistor Rt7 and one end of the microstrip line TLt2 respectively; the other end of the microstrip line TLt2 is connected with the other end of the resistor Rt8 and one end of the microstrip line TLt3 respectively; the other end of the microstrip line TLt3 is connected with the other end of the resistor Rt9 and one end of the microstrip line TLt4 respectively; the other end of the microstrip line TLt4 is connected with the other end of the resistor Rt 10; the other end of the capacitor Ct15 is used as the output end of the novel traveling wave amplification network.
In the embodiment of the present invention, as shown in fig. 2, the novel current multiplexing amplification network includes a ground resistor Rr1, a resistor Rr2, a resistor Rr3, a ground resistor Rr4, a resistor Rr5, a ground resistor Rr6, a resistor Rr7, a resistor Rr8, a resistor Rr9, a resistor Rr10, a resistor Rr11, a resistor Rr12, a capacitor Cr1, a capacitor Cr2, a ground capacitor Cr3, a capacitor Cr4, a capacitor Cr5, a ground capacitor Cr6, a ground capacitor Cr7, a ground capacitor Cr8, a ground capacitor Cr9, a capacitor Cr10, an inductor Lr1, an inductor Lr2, an inductor Lr3, an inductor Lr4, an inductor Lr5, a microstrip line TLr1, a triode Hr1, a triode Hr2, a triode Hr3, a field effect transistor Mr1, and a field effect transistor Mr 2;
one end of the capacitor Cr10 is used as the output end of the novel current multiplexing amplification network, and the other end of the capacitor Cr10 is respectively connected with one end of the grounding capacitor Cr9 and one end of the inductor Lr 5; the base electrode of the triode Hr1 is respectively connected with the collector electrode of the triode Hr3, one end of the capacitor Cr4 and one end of the resistor Rr 7; the collector of the triode Hr1 is respectively connected with the collector of the triode Hr2, one end of the inductor Lr4, the other end of the inductor Lr5, one end of the capacitor Cr5 and one end of the resistor Rr 8; the other end of the resistor Rr7 is connected with the other end of the capacitor Cr5 and the other end of the resistor Rr8 respectively; an emitter electrode of the triode Hr1 is respectively connected with a base electrode of the triode Hr2, one end of the resistor Rr11 and one end of the resistor Rr 10; the other end of the inductor Lr4 is respectively connected with one end of a resistor Rr12 and a power supply voltage VDR of the novel current multiplexing network; the other end of the resistor Rr12 is connected with a grounding capacitor Cr 8; an emitter of the triode Hr2 is respectively connected with one end of a grounding capacitor Cr7 and an inductor Lr3 and the other end of the resistor Rr 11; the base electrode of the triode Hr3 is connected with one end of the resistor Rr 9; the other end of the resistor Rr9 is connected with the other end of the resistor Rr10 and the grounding capacitor Cr6 respectively; the emitter of the triode Hr3 is connected with the grounding resistor Rr 6; the other end of the capacitor Cr4 is respectively connected with one end of a resistor Rr5 and one end of an inductor Lr 2; the other end of the resistor Rr5 is connected with a grounding capacitor Cr 3; the other end of the inductor Lr2 is connected with the other end of the inductor Lr3 and one end of the microstrip line TLr1 respectively; the grid of the field effect transistor Mr1 is respectively connected with one end of a grounding resistor Rr1, one end of an inductor Lr1 and one end of a resistor Rr 2; the drain of the field effect transistor Mr1 is respectively connected with the other end of the microstrip line TLr1, the drain of the field effect transistor Mr2, one end of the capacitor Cr2 and one end of the resistor Rr 3; the source electrode of the field effect tube Mr1 is respectively connected with the grid electrode of the field effect tube Mr2 and the grounding resistor Rr 4; the source electrode of the field effect transistor Mr2 is grounded; the other end of the resistor Rr2 is connected with the other end of the capacitor Cr2 and the other end of the resistor Rr3 respectively; the other end of the inductor Lr1 is connected with one end of the capacitor Cr 1; the other end of the capacitor Cr1 is used as the input end of the novel current multiplexing amplification network.
In the embodiment of the present invention, as shown in fig. 2, the first active bias network includes a resistor Rg1, a resistor Rg2 at ground, a capacitor Cg1 at ground, a transistor Hg1, a transistor Hg2, and a transistor Hg 3;
the base electrode of the triode Hg1 is respectively connected with the base electrode of the triode Hg2, the collector electrode of the triode Hg2, one end of the resistor Rg1 and the grounding capacitor Cg 1; the collector of the triode Hg1 is respectively connected with the other end of the resistor Rg1 and a first active bias network bias voltage VG 1; an emitter of the transistor Hg1 is used as an output end of the first active bias network; the emitter of the triode Hg2 is respectively connected with the base of the triode Hg3 and the collector of the triode Hg 3; the emitter of the triode Hg3 is connected with a grounding resistor Rg 2.
In the embodiment of the present invention, as shown in fig. 2, the second active bias network includes a capacitor Cg2, a resistor Rg3, a resistor Rg4, a transistor Hg4, a transistor Hg5, and a transistor Hg 6;
the base electrode of the triode Hg4 is respectively connected with the grounding capacitor Cg2, the base electrode of the triode Hg5, the collector electrode of the triode Hg5 and one end of the resistor Rg 3; a collector of the triode Hg4 is used as a first output end of the second active bias network and is respectively connected with the other end of the resistor Rg3 and a bias voltage VG2 of the second active bias network; an emitter of the transistor Hg4 is used as a second output end of the second active bias network; the emitter of the triode Hg5 is respectively connected with the base of the triode Hg6 and the collector of the triode Hg 6; the emitter of the triode Hg6 is connected with a grounding resistor Rg 4.
In the embodiment of the present invention, as shown in fig. 2, the second switch switching network includes a resistor Rs5, a resistor Rs6, a resistor Rs7, a resistor Rs8, a resistor Rs9, a capacitor Cs2, a microstrip line TLs4, a microstrip line TLs5, a microstrip line TLs6, a switch tube Ms5, a switch tube Ms6, a switch tube Ms7, a switch tube Ms8, and a switch tube Ms 9;
one end of the microstrip line TLs4 is used as the input end of the second switch switching network, and the other end of the microstrip line TLs4 is respectively connected with the drain electrode of the switch tube Ms6 and the source electrode of the switch tube Ms 5; the base electrode of the switch tube Ms6 is connected with one end of the resistor Rs 6; the other end of the resistor Rs6 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms6 is connected with the drain electrode of the switch tube Ms 7; the base electrode of the switch tube Ms7 is connected with one end of the resistor Rs 7; the source of the switch tube Ms7 is grounded; the other end of the resistor Rs7 is connected with a control voltage Vcon 2; the base electrode of the switch tube Ms5 is connected with one end of the resistor Rs 5; the other end of the resistor Rs5 is connected with a control voltage Vcon 1; the drain electrode of the switch tube Ms5 is respectively connected with the drain electrode of the switch tube Ms8 and one end of the microstrip line Tls 6; the other end of the microstrip line TLs6 is connected with one end of a capacitor Cs 2; the other end of the capacitor Cs2 is used as a first output end of the second switching network; the base electrode of the switch tube Ms8 is connected with one end of the resistor Rs 8; the other end of the resistor Rs8 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms8 is connected with the drain electrode of the switch tube Ms 9; the base electrode of the switch tube Ms9 is connected with one end of the resistor Rs 9; the other end of the resistor Rs9 is connected with a control voltage Vcon 2; the source of the switch tube Ms9 is connected with one end of the microstrip line TLs 5; the other end of the microstrip line TLs5 serves as a second output terminal of the second switching network.
The specific working principle and process of the present invention are described below with reference to fig. 2:
when a transmitting channel works, a signal enters a first switch switching network from a transmitting input end, at the moment, through the control of a control voltage Vcon1 and a control voltage Vcon2, a series switch tube Ms1 and an Ms2 are connected, the other side of the first switch switching network is connected with a series switch tube Ms3 and an Ms4 in series, the signal enters a novel traveling wave amplification network to be amplified and then reaches a second switch switching network, and through the control of the control voltage Vcon1 and the control voltage Vcon2, the series switch tube Ms5 is connected, the parallel switch tube Ms6 and the Ms7 are connected, meanwhile, the series switch tube Ms8 and the Ms9 on the other side of the second switch switching network are connected, and then the signal is output from a transmitting output end; when the receiving channel works, a signal enters the second switch switching network from the receiving input end, at the moment, Ms5 in the second switch switching network is turned off, Ms6 and Ms7 are turned on, meanwhile, Ms8 and Ms9 on the other side are turned on, the signal enters the novel current multiplexing amplification network to be amplified and then reaches the first switch switching network, wherein Ms1 and Ms2 are turned off, Ms3 and Ms4 are turned on, and then the signal is output from the receiving output end.
In the novel traveling wave amplification network, the grid voltage of a first-stage amplification pHEMT transistor (Mt 1-Mt 5) is obtained through a second bias voltage VG2 of the novel traveling wave amplification network, the voltage is divided by resistors Rg5 and Rg7 and then is obtained through a large resistor Rg6, and the leakage voltage is obtained through a power supply voltage VDT of the novel traveling wave amplification network respectively through an inductor Lt24 and an inductor Lt5-Lt 8; the second-stage HBT tube (Ht 1-Ht 10) is biased by adopting an active bias network structure, wherein the base voltage of a main transistor Hti (i =1,3,5,7, 9) is obtained through a first active bias network respectively through a large resistor Rt1-Rt5, and the base voltage of an auxiliary transistor Ht (i +1) (i =1,3,5,7, 9) is obtained through a second active bias network respectively through a large resistor Rt6-Rt 10.
The active bias network is an adaptive linearization bias circuit. Taking the first active bias network as an example, the bias circuit comprises two diodes connected transistors Hg2 and Hg3, a linear capacitor Cg1 and a driving transistor Hg 1. The transistors Hg1 and Hg2 form a mirror current source that provides a bias current to the main transistor Hti (i =1,3,5,7, 9). As the radio frequency power increases, and due to the self-heating effect and diode rectification effect of the HBT transistors, the base potential of transistor Hti (i =1,3,5,7, 9) will decrease; a small part of radio frequency power leaks to a bias circuit and is bypassed to the ground by a capacitor Cg1 after passing through a transistor Hg1, so that the base level potential of a transistor Hg1 is kept unchanged, the leaked power enables direct current of a transistor Hg1 to be increased, and direct current rectification of a transistor Hg1 enables direct current component V of B-E junction voltage to be rectified be Reduced due to the transistor Hg1 base V b The component is constant, so its emitter potential V e Is raised so the base potential of transistor Hti (i =1,3,5,7, 9) is compensated. The technology for compensating the base potential is the self-adaptive linearization biasing technology. A second active bias network that provides bias to the auxiliary transistor Ht (i +1) (i =1,3,5,7, 9) works the same way.
In the novel current multiplexing amplification network, a negative feedback structure is adopted, and the negative feedback structure is innovatively combined with a biasing circuit, so that the chip area is reduced. Taking the first-stage negative feedback as an example, a radio frequency signal passes through a capacitor Cr2 and a resistor Rr2, the bandwidth and the gain flatness can be adjusted through the two components, and a direct current signal passes through a resistor R1, a resistor R2 and a resistor R3 and provides a gate voltage for a field effect transistor Mr1 through resistor voltage division. The gate voltage of the field effect transistor Mr2 is the same as the source potential of the field effect transistor Mr 1. The drain voltages of the fet Mr1 and the fet Mr2 are provided by the emitter potential of the transistor Hr2 via the inductor Lr 3. The collector voltages of the triode Hr1 and the triode Hr2 are provided by a novel current multiplexing network power supply voltage VDR, the base level of the triode Hr1 and the base level of the triode Hr2 obtains a bias current through a resistor Rr6, a resistor Rr7, a resistor Rr8 and a triode Hr3, and the bias also has a self-adaptive characteristic due to the existence of the triode Hr 3. The LC structure composed of the inductor Lr5, the parallel capacitor Cr9 and the series capacitor Cr10 at the output end of the novel current multiplexing amplification network expands the bandwidth of the circuit and optimizes output matching.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (7)

1. A broadband dual-channel transceiving amplification chip based on a Bi-Hemt process is characterized by comprising a first switch switching network, a novel traveling wave amplification network, a novel current multiplexing amplification network, a first active bias network, a second active bias network and a second switch switching network;
the first input end of the first switch switching network is used as the transmitting input end/receiving output end of the broadband dual-channel transceiving amplification chip, the second input end of the first switch switching network is connected with the output end of the novel current multiplexing amplification network, and the output end of the first switch switching network is connected with the first input end of the novel traveling wave amplification network;
the first output end of the second switch switching network is used as the transmitting output end/receiving input end of the broadband dual-channel transceiving amplification chip, the second output end of the second switch switching network is connected with the input end of the novel current multiplexing amplification network, and the input end of the second switch switching network is connected with the output end of the novel traveling wave amplification network;
the output end of the first active bias network is connected with the second input end of the novel traveling wave amplification network; the first output end of the second active bias network is connected with the third input end of the novel traveling wave amplification network; and the second output end of the second active bias network is connected with the fourth input end of the novel traveling wave amplification network.
2. The Bi-Hemt process-based broadband dual-channel transceiving amplification chip of claim 1, wherein the first switching network comprises a resistor Rs1, a resistor Rs2, a resistor Rs3, a resistor Rs4, a capacitor Cs1, a microstrip line TLs1, a microstrip line TLs2, a microstrip line TLs3, a switch tube Ms1, a switch tube Ms2, a switch tube Ms3 and a switch tube Ms 4;
one end of the capacitor Cs1 is used as a first input end of the first switch switching network, and the other end of the capacitor Cs1 is connected to one end of the microstrip line TLs 1; the other end of the microstrip line TLs1 is connected with the drain of the switch tube Ms1 and the drain of the switch tube Ms3 respectively; the grid of the switch tube Ms1 is connected with one end of a resistor Rs 1; the other end of the resistor Rs1 is connected with a control voltage Vcon 1; the source electrode of the switch tube Ms1 is connected with the drain electrode of the switch tube Ms 2; the grid electrode of the switch tube Ms2 is connected with one end of a resistor Rs 2; the other end of the resistor Rs2 is connected with a control voltage Vcon 1; the source electrode of the switch tube Ms2 is connected with one end of the microstrip line TLs 2; the other end of the microstrip line TLs2 is used as the output end of the first switch switching network; the grid of the switch tube Ms3 is connected with one end of a resistor Rs 3; the other end of the resistor Rs3 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms3 is connected with the drain electrode of the switch tube Ms 4; the grid of the switch tube Ms4 is connected with one end of a resistor Rs 4; the other end of the resistor Rs4 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms4 is connected with one end of the microstrip line TLs 3; the other end of the microstrip line TLs3 is used as a second input end of the first switch switching network.
3. The Bi-Hemt process-based broadband dual-channel transceiving amplification chip according to claim 1, wherein the novel traveling wave amplification network comprises a resistor Rg, a ground resistor Rg, a resistor Rt, a capacitor Ct, a ground capacitor Ct, a capacitor Ct, an inductor Lt, an, An inductor Lt20, an inductor Lt21, an inductor Lt22, an inductor Lt23, an inductor Lt24, a microstrip line TLt1, a microstrip line TLt2, a microstrip line TLt3, a microstrip line TLt4, a triode Ht1, a triode Ht2, a triode Ht3, a triode Ht4, a triode Ht5, a triode Ht6, a triode Ht7, a triode Ht8, a triode Ht9, a triode Ht10, a field effect tube Mt1, a field effect tube Mt2, a field effect tube Mt3, a field effect tube Mt4 and a field effect tube Mt 5;
one end of the capacitor Ct1 is used as a first input end of the novel traveling wave amplification network; one end of the resistor Rt1 is used as a second input end of the novel traveling wave amplification network and is respectively connected with one end of the resistor Rt2, one end of the resistor Rt3, one end of the resistor Rt4 and one end of the resistor Rt 5; the other end of the resistor Rt1 is respectively connected with the base electrode of the triode Ht1 and one end of the capacitor Ct 2; the collector of the triode Ht1 is connected with one end of an inductor Lt 9; the emitter of the triode Ht1 is grounded; the base electrode of the triode Ht2 is respectively connected with one end of a resistor Rt6 and one end of a capacitor Ct 7; the collector of the triode Ht2 is connected with one end of an inductor Lt 10; the emitter of the triode Ht2 is grounded; the other end of the inductor Lt9 is respectively connected with one end of a resistor Rt12, one end of an inductor Lt23, one end of an inductor Lt19 and the other end of an inductor Lt 10; the other end of the resistor Rt12 is connected with a grounding capacitor Ct 13; the base electrode of the triode Ht3 is respectively connected with the other end of the resistor Rt2 and one end of the capacitor Ct 3; the collector of the triode Ht3 is connected with one end of an inductor Lt 11; the emitter of the triode Ht3 is grounded; the base electrode of the triode Ht4 is respectively connected with one end of a resistor Rt7 and one end of a capacitor Ct 8; the collector of the triode Ht4 is connected with one end of an inductor Lt 12; the emitter of the triode Ht4 is grounded; the other end of the inductor Lt11 is respectively connected with the other end of the inductor Lt19, one end of the inductor Lt20 and the other end of the inductor Lt 12; the base electrode of the triode Ht5 is respectively connected with the other end of the resistor Rt3 and one end of the capacitor Ct 4; the collector of the triode Ht5 is connected with one end of an inductor Lt 13; the emitter of the triode Ht5 is grounded; the base electrode of the triode Ht6 is respectively connected with one end of a resistor Rt8 and one end of a capacitor Ct 9; the collector of the triode Ht6 is connected with one end of an inductor Lt 14; the emitter of the triode Ht6 is grounded; the other end of the inductor Lt13 is respectively connected with the other end of the inductor Lt20, one end of the inductor Lt21 and the other end of the inductor Lt 14; the base electrode of the triode Ht7 is respectively connected with the other end of the resistor Rt4 and one end of the capacitor Ct 5; the collector of the triode Ht7 is connected with one end of an inductor Lt 15; the emitter of the triode Ht7 is grounded; the base electrode of the triode Ht8 is respectively connected with one end of a resistor Rt9 and one end of a capacitor Ct 10; the collector of the triode Ht8 is connected with one end of an inductor Lt 16; the emitter of the triode Ht8 is grounded; the other end of the inductor Lt15 is respectively connected with the other end of the inductor Lt21, one end of the inductor Lt22 and the other end of the inductor Lt 16; the base electrode of the triode Ht9 is respectively connected with the other end of the resistor Rt5 and one end of the capacitor Ct 6; the collector of the triode Ht9 is connected with one end of an inductor Lt 17; the emitter of the triode Ht9 is grounded; the base electrode of the triode Ht10 is respectively connected with one end of a resistor Rt10 and one end of a capacitor Ct 11; the collector of the triode Ht10 is connected with one end of an inductor Lt 18; the emitter of the triode Ht10 is grounded; the other end of the inductor Lt17 is respectively connected with the other end of the inductor Lt22, one end of the capacitor Ct15 and the other end of the inductor Lt 18; the other end of the inductor Lt23 is respectively connected with one end of an inductor Lt24, one end of a resistor Rt13 and the power supply voltage VDT of the novel traveling wave amplification network; the other end of the resistor Rt13 is connected with a grounding capacitor Ct 14; the grid electrode of the field effect transistor Mt1 is respectively connected with the other end of the capacitor Ct1, one end of the resistor Rg6 and one end of the inductor Lt 1; the drain electrode of the field effect transistor Mt1 is respectively connected with the other end of the inductor Lt24, the other end of the capacitor Ct2, the other end of the capacitor Ct7 and one end of the inductor Lt 5; the source electrode of the field effect transistor Mt1 is grounded; the grid electrode of the field effect transistor Mt2 is respectively connected with the other end of the inductor Lt1 and one end of the inductor Lt 2; the drain electrode of the field effect transistor Mt2 is respectively connected with the other end of the inductor Lt5, the other end of the capacitor Ct3, the other end of the capacitor Ct8 and one end of the inductor Lt 6; the source electrode of the field effect transistor Mt2 is grounded; the grid electrode of the field effect transistor Mt3 is respectively connected with the other end of the inductor Lt2 and one end of the inductor Lt 3; the drain electrode of the field effect transistor Mt3 is respectively connected with the other end of the inductor Lt6, the other end of the capacitor Ct4, the other end of the capacitor Ct9 and one end of the inductor Lt 7; the source electrode of the field effect transistor Mt3 is grounded; the grid electrode of the field effect transistor Mt4 is respectively connected with the other end of the inductor Lt3 and one end of the inductor Lt 4; the drain electrode of the field effect transistor Mt4 is respectively connected with the other end of the inductor Lt7, the other end of the capacitor Ct5, the other end of the capacitor Ct10 and one end of the inductor Lt 8; the source electrode of the field effect transistor Mt4 is grounded; the grid electrode of the field effect transistor Mt5 is respectively connected with the other end of the inductor Lt4 and one end of the resistor Rt 11; the drain electrode of the field effect transistor Mt5 is respectively connected with the other end of the inductor Lt8, the other end of the capacitor Ct6 and the other end of the capacitor Ct 11; the source electrode of the field effect transistor Mt5 is grounded; the other end of the resistor Rt11 is connected with a grounding capacitor Ct 12; the other end of the resistor Rg6 is connected with one end of a grounding resistor Rg7 and one end of a resistor Rg5 respectively; the other end of the resistor Rg5 is used as a third input end of the novel traveling wave amplification network; one end of the microstrip line TLt1 is used as a fourth input end of the novel traveling wave amplification network and is connected with the other end of the resistor Rt 6; the other end of the microstrip line TLt1 is connected with the other end of the resistor Rt7 and one end of the microstrip line TLt2 respectively; the other end of the microstrip line TLt2 is connected with the other end of the resistor Rt8 and one end of the microstrip line TLt3 respectively; the other end of the microstrip line TLt3 is connected with the other end of the resistor Rt9 and one end of the microstrip line TLt4 respectively; the other end of the microstrip line TLt4 is connected with the other end of the resistor Rt 10; and the other end of the capacitor Ct15 is used as the output end of the novel traveling wave amplification network.
4. The Bi-Hemt process-based broadband dual-channel transceiving amplification chip according to claim 1, wherein the novel current multiplexing amplification network comprises a ground resistor Rr1, a ground resistor Rr1, a capacitor Cr1, a ground capacitor Cr1, a ground capacitor Cr1, a capacitor Cr1, an inductor Lr1, a microstrip line Lr 685r 1, a triode Hr1, a field effect transistor Hr1, a Mr1, a microstrip line Mr1 and a field effect transistor mk 1;
one end of the capacitor Cr10 is used as the output end of the novel current multiplexing amplification network, and the other end of the capacitor Cr10 is respectively connected with one end of the grounding capacitor Cr9 and one end of the inductor Lr 5; the base electrode of the triode Hr1 is respectively connected with the collector electrode of the triode Hr3, one end of the capacitor Cr4 and one end of the resistor Rr 7; the collector of the triode Hr1 is respectively connected with the collector of the triode Hr2, one end of an inductor Lr4, the other end of an inductor Lr5, one end of a capacitor Cr5 and one end of a resistor Rr 8; the other end of the resistor Rr7 is connected with the other end of the capacitor Cr5 and the other end of the resistor Rr8 respectively; the emitter electrode of the triode Hr1 is respectively connected with the base electrode of the triode Hr2, one end of the resistor Rr11 and one end of the resistor Rr 10; the other end of the inductor Lr4 is respectively connected with one end of a resistor Rr12 and a power supply voltage VDR of the novel current multiplexing network; the other end of the resistor Rr12 is connected with a grounding capacitor Cr 8; an emitter of the triode Hr2 is respectively connected with the grounding capacitor Cr7, one end of the inductor Lr3 and the other end of the resistor Rr 11; the base electrode of the triode Hr3 is connected with one end of the resistor Rr 9; the other end of the resistor Rr9 is respectively connected with the other end of the resistor Rr10 and the grounding capacitor Cr 6; the emitting electrode of the triode Hr3 is connected with a grounding resistor Rr 6; the other end of the capacitor Cr4 is respectively connected with one end of a resistor Rr5 and one end of an inductor Lr 2; the other end of the resistor Rr5 is connected with a grounding capacitor Cr 3; the other end of the inductor Lr2 is connected with the other end of the inductor Lr3 and one end of the microstrip line TLr1 respectively; the grid of the field effect transistor Mr1 is respectively connected with one end of a grounding resistor Rr1, one end of an inductor Lr1 and one end of a resistor Rr 2; the drain of the field effect transistor Mr1 is respectively connected with the other end of the microstrip line TLr1, the drain of the field effect transistor Mr2, one end of the capacitor Cr2 and one end of the resistor Rr 3; the source electrode of the field effect transistor Mr1 is respectively connected with the grid electrode of the field effect transistor Mr2 and the grounding resistor Rr 4; the source electrode of the field effect transistor Mr2 is grounded; the other end of the resistor Rr2 is connected with the other end of the capacitor Cr2 and the other end of the resistor Rr3 respectively; the other end of the inductor Lr1 is connected with one end of a capacitor Cr 1; the other end of the capacitor Cr1 is used as the input end of the novel current multiplexing amplification network.
5. The Bi-Hemt process-based broadband dual-channel transceiver amplification chip of claim 1, wherein the first active bias network comprises a resistor Rg1, a ground resistor Rg2, a ground capacitor Cg1, a transistor Hg1, a transistor Hg2, and a transistor Hg 3;
the base electrode of the triode Hg1 is respectively connected with the base electrode of the triode Hg2, the collector electrode of the triode Hg2, one end of the resistor Rg1 and the grounding capacitor Cg 1; the collector of the triode Hg1 is respectively connected with the other end of the resistor Rg1 and a first active bias network bias voltage VG 1; an emitter of the triode Hg1 is used as an output end of the first active bias network; the emitter of the triode Hg2 is respectively connected with the base of the triode Hg3 and the collector of the triode Hg 3; the emitter of the triode Hg3 is connected with a grounding resistor Rg 2.
6. The Bi-Hemt process-based broadband dual-channel transceiver amplification chip of claim 1, wherein the second active bias network comprises a grounded capacitor Cg2, a resistor Rg3, a grounded resistor Rg4, a transistor Hg4, a transistor Hg5, and a transistor Hg 6;
the base electrode of the triode Hg4 is respectively connected with a grounding capacitor Cg2, the base electrode of the triode Hg5, the collector electrode of the triode Hg5 and one end of a resistor Rg 3; a collector of the triode Hg4 is used as a first output end of the second active bias network and is respectively connected with the other end of the resistor Rg3 and a bias voltage VG2 of the second active bias network; an emitter of the triode Hg4 is used as a second output end of the second active bias network; the emitter of the triode Hg5 is respectively connected with the base of the triode Hg6 and the collector of the triode Hg 6; the emitter of the triode Hg6 is connected with a grounding resistor Rg 4.
7. The Bi-Hemt process-based broadband dual-channel transceiving amplification chip of claim 1, wherein the second switch switching network comprises a resistor Rs5, a resistor Rs6, a resistor Rs7, a resistor Rs8, a resistor Rs9, a capacitor Cs2, a microstrip line TLs4, a microstrip line TLs5, a microstrip line TLs6, a switch tube Ms5, a switch tube Ms6, a switch tube Ms7, a switch tube Ms8 and a switch tube Ms 9;
one end of the microstrip line TLs4 is used as the input end of the second switch switching network, and the other end of the microstrip line TLs4 is respectively connected with the drain electrode of the switch tube Ms6 and the source electrode of the switch tube Ms 5; the base electrode of the switch tube Ms6 is connected with one end of the resistor Rs 6; the other end of the resistor Rs6 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms6 is connected with the drain electrode of the switch tube Ms 7; the base electrode of the switch tube Ms7 is connected with one end of the resistor Rs 7; the source electrode of the switch tube Ms7 is grounded; the other end of the resistor Rs7 is connected with a control voltage Vcon 2; the base electrode of the switch tube Ms5 is connected with one end of the resistor Rs 5; the other end of the resistor Rs5 is connected with a control voltage Vcon 1; the drain electrode of the switch tube Ms5 is respectively connected with the drain electrode of the switch tube Ms8 and one end of the microstrip line Tls 6; the other end of the microstrip line TLs6 is connected with one end of a capacitor Cs 2; the other end of the capacitor Cs2 is used as a first output end of the second switching network; the base electrode of the switch tube Ms8 is connected with one end of the resistor Rs 8; the other end of the resistor Rs8 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms8 is connected with the drain electrode of the switch tube Ms 9; the base electrode of the switch tube Ms9 is connected with one end of the resistor Rs 9; the other end of the resistor Rs9 is connected with a control voltage Vcon 2; the source electrode of the switch tube Ms9 is connected with one end of the microstrip line TLs 5; the other end of the microstrip line TLs5 is used as a second output end of the second switch switching network.
CN202210792416.6A 2022-07-07 2022-07-07 Bi-Hemt technology-based broadband dual-channel transceiving amplification chip Active CN114866047B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210792416.6A CN114866047B (en) 2022-07-07 2022-07-07 Bi-Hemt technology-based broadband dual-channel transceiving amplification chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210792416.6A CN114866047B (en) 2022-07-07 2022-07-07 Bi-Hemt technology-based broadband dual-channel transceiving amplification chip

Publications (2)

Publication Number Publication Date
CN114866047A true CN114866047A (en) 2022-08-05
CN114866047B CN114866047B (en) 2022-11-11

Family

ID=82625765

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210792416.6A Active CN114866047B (en) 2022-07-07 2022-07-07 Bi-Hemt technology-based broadband dual-channel transceiving amplification chip

Country Status (1)

Country Link
CN (1) CN114866047B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117318635A (en) * 2023-11-28 2023-12-29 成都嘉纳海威科技有限责任公司 Reconfigurable high-linearity low-power amplifier

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070176677A1 (en) * 2006-01-18 2007-08-02 Triquint Semiconductor, Inc. Switched distributed power amplifier
CN101282110A (en) * 2008-04-25 2008-10-08 北京大学 Low-power consumption single-ended input difference output low-noise amplifier
US20090021309A1 (en) * 2004-12-30 2009-01-22 Yuan Jin Zheng Fully Integrated Ultra Wideband Transmitter Circuits and Systems
US20140235184A1 (en) * 2013-02-20 2014-08-21 Micro Mobio Corporation World Band Radio Frequency Front End Module, System And Method Thereof
US20140247092A1 (en) * 2013-03-04 2014-09-04 Harris Corporation Wideband distributed amplifier with integral bypass
US20200119694A1 (en) * 2017-03-28 2020-04-16 Mitsubishi Electric Corporation Current reuse type field effect transistor amplifier
CN114024511A (en) * 2021-10-11 2022-02-08 电子科技大学 Digitally controlled broadband high-linearity variable gain amplifier
US20220103134A1 (en) * 2020-09-28 2022-03-31 QuantalRF AG Differential amplifier including dual magnetically coupled feedback loops
CN114567264A (en) * 2022-04-29 2022-05-31 成都嘉纳海威科技有限责任公司 Three-channel amplification attenuation filtering multifunctional chip
CN114710126A (en) * 2022-06-08 2022-07-05 成都嘉纳海威科技有限责任公司 Reconfigurable broadband amplifier based on GaAs Bi-HEMT technology

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090021309A1 (en) * 2004-12-30 2009-01-22 Yuan Jin Zheng Fully Integrated Ultra Wideband Transmitter Circuits and Systems
US20070176677A1 (en) * 2006-01-18 2007-08-02 Triquint Semiconductor, Inc. Switched distributed power amplifier
CN101282110A (en) * 2008-04-25 2008-10-08 北京大学 Low-power consumption single-ended input difference output low-noise amplifier
US20140235184A1 (en) * 2013-02-20 2014-08-21 Micro Mobio Corporation World Band Radio Frequency Front End Module, System And Method Thereof
US20140247092A1 (en) * 2013-03-04 2014-09-04 Harris Corporation Wideband distributed amplifier with integral bypass
US20200119694A1 (en) * 2017-03-28 2020-04-16 Mitsubishi Electric Corporation Current reuse type field effect transistor amplifier
US20220103134A1 (en) * 2020-09-28 2022-03-31 QuantalRF AG Differential amplifier including dual magnetically coupled feedback loops
CN114024511A (en) * 2021-10-11 2022-02-08 电子科技大学 Digitally controlled broadband high-linearity variable gain amplifier
CN114567264A (en) * 2022-04-29 2022-05-31 成都嘉纳海威科技有限责任公司 Three-channel amplification attenuation filtering multifunctional chip
CN114710126A (en) * 2022-06-08 2022-07-05 成都嘉纳海威科技有限责任公司 Reconfigurable broadband amplifier based on GaAs Bi-HEMT technology

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
刘超等: "基于SiGe BiCMOS工艺的X和Ka波段T/R多功能芯片设计", 《微波学报》 *
许春良等: "4～20GHz超宽带低噪声放大器单片电路", 《半导体技术》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117318635A (en) * 2023-11-28 2023-12-29 成都嘉纳海威科技有限责任公司 Reconfigurable high-linearity low-power amplifier
CN117318635B (en) * 2023-11-28 2024-04-09 成都嘉纳海威科技有限责任公司 Reconfigurable high-linearity low-power amplifier

Also Published As

Publication number Publication date
CN114866047B (en) 2022-11-11

Similar Documents

Publication Publication Date Title
WO2012098863A1 (en) High-frequency power amplifier
US7928799B2 (en) Power amplifying apparatus and mobile communication terminal
CN114978074B (en) Three-channel transceiving amplification chip
US12088268B2 (en) Variable-gain amplifier and phased array system
JP2005516524A (en) Power amplifier for portable terminal
US10224892B2 (en) Power amplification module
JP2007184955A (en) Amplifier circuit with high efficiency mode of operation and high linearity mode of operation
JP2010021719A (en) Doherty amplifier
JP2020184665A (en) Transmitter-receiver circuit
JP5158425B2 (en) RF power amplifier
CN114866047B (en) Bi-Hemt technology-based broadband dual-channel transceiving amplification chip
WO2023273417A1 (en) Radio frequency power amplification circuit, chip and communication device
JP2008277882A (en) Amplifying circuit and radio communication device
CN116961690B (en) Dual-mode radio frequency front end module
CN1972118A (en) High-linear high-gain broadband radio frequency low-noise amplifier
JP2020043518A (en) Power amplifier circuit
CN113228521B (en) Transmit-receive separation circuit, transceiver and wireless communication equipment
US9660587B2 (en) Power amplifier
US10879847B2 (en) Transmission unit
KR20150078386A (en) Power amplifying apparatus
KR20170073459A (en) Power amplifier and wireless communication apparatus
KR101500570B1 (en) Asymmetric Doherty Amplifier
CN217159562U (en) Circuit with double topological structures
US20210336592A1 (en) Power amplifier circuit
US20210126601A1 (en) Power amplifier and electronic device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant