CN217159562U

CN217159562U - Circuit with double topological structures

Info

Publication number: CN217159562U
Application number: CN202123027576.1U
Authority: CN
Inventors: 朱贤能; 侯兴江; 邢利敏
Original assignee: Shenzhen Times Suxin Technology Co Ltd
Current assignee: Shenzhen Times Suxin Technology Co Ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-08-09
Anticipated expiration: 2031-12-02

Abstract

The utility model discloses a two topological structure's circuit, including first topological circuit, second topological circuit, switch module and radio frequency shunt module. The on-off control of the switch MOS tube is realized through the switch module, the switching of two topological circuit structures is realized in one circuit, and the problem that a single topological circuit cannot realize the compatibility of gain, standing wave and stability at the same time is solved. Simultaneously, the same radio frequency of two kinds of topologies sharing is along separate routes the module, compares and provides two sets of single topologies, the utility model discloses a circuit can be to a certain extent abbreviate the circuit area.

Description

Circuit with double topological structures

Technical Field

The utility model relates to a radio frequency, electron technical field especially relate to a two topological structure's circuit.

Background

Currently, as the concept of multiband and multistandard is receiving more and more attention in modern wireless communications, broadband transceivers are essential in order to support a wide range of communication standards and accommodate different applications in a single device. For an amplification circuit for a high frequency signal of a mobile communication device, excellent amplification characteristics and gain capability are required across a wide dynamic range.

In the design of an amplifying circuit, in order to make the whole system relatively stable, a negative feedback structure is generally introduced to carry out negative feedback on an amplifying device, but the gain of an amplifier module is sacrificed; the gain of the amplifier module is made smaller than the gain of the amplifying device itself, e.g. due to the introduction of negative feedback. In turn, although positive feedback structures can increase the gain of the amplifier module, the introduction of positive feedback is avoided in current designs because it causes many negative problems to the system, typically leading to system instability.

The method generally adopted in the prior art is a stacked CSCG (Common source Common gate) circuit or a CSCS (Co-source Common source) circuit, and a negative feedback mode is generally supplemented for the requirement of wideband ultra-wideband. However, the CSCG wideband circuit has a weak performance in a high frequency band, a poor gain capability as compared with the CSCS circuit, and is prone to high frequency instability. The low frequency band of the CSCS broadband circuit has weaker performance, the bandwidth is not as good as that of the CSCG circuit, and the low frequency is easy to be unstable. The single circuit mode cannot be compatible with the requirements of gain, performance and stability under different frequency bands.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is: the defects that a single circuit cannot be compatible with performance, gain and stability are overcome, and application scenes are widened.

In order to solve the above problem, the utility model provides a circuit of two topological structure, include: the device comprises a first topological circuit, a second topological circuit, a switch module and a radio frequency shunt module; the first topological circuit and the second topological circuit share the same radio frequency shunt module; the radio frequency shunt module comprises an input matching network module, an output matching network module, a first amplification MOS tube, a second amplification MOS tube, a first inductor, a third inductor and a fourth inductor; the input matching network module is connected with the grid electrode of the first amplification MOS tube; the source electrode of the first amplification MOS tube is connected with the fourth inductor; the third inductor is connected with the first inductor and the drain electrode of the second amplification MOS tube;

the switch module is connected with the first topology circuit and the second topology circuit.

Further, the switch module comprises a first switch MOS tube unit and a second switch MOS tube unit;

the first switching MOS tube unit is connected with the first topology circuit;

the second switching MOS tube unit is connected with the second topological circuit;

the first switch MOS tube unit comprises a third switch MOS tube, a fourth switch MOS tube and a seventh switch MOS tube;

the second switch MOS tube unit comprises a fifth switch MOS tube and a sixth switch MOS tube.

Further, the first topology circuit comprises a first capacitor and a first resistor;

the drain electrode of the third switch MOS tube is connected with the grid electrode of the second amplification MOS tube; the drain electrode of the fourth switch MOS tube is connected with the drain electrode of the first amplification MOS tube; the source electrode of the fourth switch MOS tube is connected with the source electrode of the second amplification MOS tube; the source electrode of the seventh switch MOS tube is connected with the grid electrode of the first amplification MOS tube; the first capacitor is respectively connected with the source electrode of the third switch MOS tube and the first resistor; the other end of the first resistor is grounded.

Further, the first topology circuit further comprises a feedback network module;

the feedback network module comprises a second resistor and a fourth capacitor;

the fourth capacitor is respectively connected with the drain electrode of the seventh switch MOS tube and the second resistor, and the second resistor is connected with the output matching network module.

Further, the second topology circuit includes a second inductor;

the source electrode of the fifth switch MOS tube is connected with the grid electrode of the second amplification MOS tube; the second inductor is respectively connected with the drain electrode of the first amplification MOS tube and the source electrode of the second amplification MOS tube; and the source electrode of the sixth switching MOS tube is connected with the source electrode of the second amplifying MOS tube.

Further, the second topology circuit further comprises an inter-stage matching network module;

the interstage matching network module comprises a second capacitor and a third capacitor;

the second capacitor is connected with the drain electrode of the fifth switch MOS tube and the drain electrode of the first amplification MOS tube respectively, the third capacitor is connected with the drain electrode of the sixth switch MOS tube, and the other end of the third capacitor is grounded.

Further, the first inductor is a choke inductor, the third inductor is an impedance matching inductor, and the fourth inductor is a feedback inductor.

Further, the input matching network module is an input impedance matching section; the output matching network module is an output impedance matching section.

Further, the second inductor is a choke inductor.

Further, the third capacitor is a common ground capacitor.

The embodiment of the utility model provides a two topological structure's circuit compares with prior art, and its beneficial effect lies in:

the utility model discloses a two topological structure's circuit, include: the device comprises a first topological circuit, a second topological circuit, a switch module and a radio frequency shunt module; on-off control of the switch MOS tube is realized through the switch module, switching of two topological circuit structures is realized in one circuit, the problems that a single topological circuit cannot be compatible with gain, standing wave and stability are solved, and application scenes are widened. Meanwhile, the first topological circuit and the second topological circuit share the same radio frequency shunt module, and compared with the two single topological circuits, the area of the circuit can be reduced to a certain extent.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic diagram of a module structure of a circuit with a dual topology structure provided by the present invention;

fig. 2 is a schematic structural diagram of a circuit with a dual topology structure provided by the present invention;

fig. 3 is a schematic circuit diagram of an embodiment of a dual topology circuit in the CSCG operating mode according to the present invention;

FIG. 4 is a schematic diagram of an amplifying circuit stacked in CSCG series;

FIG. 5 is a schematic circuit diagram of an embodiment of a dual topology circuit operating in a CSCG series stacked circuit configuration;

fig. 6 is a schematic circuit diagram of an embodiment of a dual topology circuit in a CSCS operating mode according to the present invention;

FIG. 7 is a schematic diagram of an amplifying circuit structure stacked in CSCS series;

fig. 8 is a schematic circuit diagram of an embodiment of a dual topology circuit operating in a circuit structure stacked in CSCS stages according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the following description will be made in detail with reference to the accompanying drawings of the present invention. It should be understood that the embodiments described herein are only some embodiments, not all embodiments, and are not intended to limit the present invention. Based on the embodiments in the present invention, other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

Example 1

Referring to fig. 1 and fig. 2, fig. 1 is a schematic diagram of a module structure of a circuit with a dual topology structure provided by the present invention, and fig. 2 is a schematic diagram of a structure of a circuit with a dual topology structure provided by the present invention. As shown in fig. 1, the module composition of the circuit includes, specifically, as follows: the radio frequency shunt module comprises a first topology circuit 101, a second topology circuit 102, a radio frequency shunt module 103 and a switch module 104, wherein the switch module 104 comprises a first switch MOS unit 1041 and a second switch MOS unit 1042.

The radio frequency shunt module 103 comprises an input matching network module IMN, an output matching network module OMN, a first amplification MOS transistor T1, a second amplification MOS transistor T2, a first inductor L1, a third inductor L3, and a fourth inductor L4; the input matching network module IMN is connected with the grid electrode of the first amplification MOS tube T1; the source electrode of the first amplification MOS transistor T1 is connected with the fourth inductor L4; the third inductor L3 is connected with the first inductor L1 and the drain of the second amplifying MOS transistor T2. The input matching module IMN and the output matching module OMN are an input impedance matching section and an output impedance matching section, respectively, and may be lumped parameter matching elements or distributed parameter elements, specifically selected according to actual circuit conditions.

In this embodiment, the first switching MOS unit 1041 of the switching module 104 is connected to the first topology circuit 101, and the second switching MOS unit 1042 is connected to the second topology circuit 102. The digital circuit unit gives TTL level to the switch module, when TTL levels V11, V12 and V13 are high level and TTL levels V21 and V22 are low level, the first switch MOS tube unit 1041 is in on state, the second switch MOS tube unit 1042 is in off state, and the circuit works in CSCG mode at this time. The circuit comprises a first topology circuit 101, a radio frequency shunt module 103 and a first switching MOS tube unit 1041. When the TTL levels V21 and V22 are high and the TTL levels V11, V12 and V13 are low, the second switching MOS unit 1042 is in a conducting state, the first switching MOS unit 1041 is in a disconnecting state, and at this time, the circuit operates in the CSCS mode. The circuit comprises a second topology circuit 102, a radio frequency shunt module 103 and a second switching MOS transistor unit 1042.

In this embodiment 1, the switching of the circuit operating modes is realized by switching the high and low levels of the first switching MOS transistor unit 1041 and the second switching MOS transistor unit 1042 of the switch module 104, and the switching of the CSCG operating mode and the CSCS operating mode is realized in one circuit, which is simple to operate and can solve the problem that a single topology circuit cannot realize compatibility of gain, standing wave and stability at the same time. Simultaneously, the same radio frequency of two kinds of topological circuit sharing is along separate routes module 103, compares and provides two sets of single topologies, the utility model discloses a circuit area can be contracted to a certain extent to the circuit.

Example 2

Referring to fig. 3, fig. 3 is a schematic circuit diagram of an embodiment of a dual topology circuit in a CSCG operating mode according to the present invention. As shown in fig. 2, the circuit structure includes, specifically, as follows: the first topology circuit 101, the radio frequency shunt module 103 and the first switching MOS transistor unit 1041.

The first topology circuit 101 includes, specifically, the following: the feedback network module, the first capacitor C1 and the first resistor R1. The feedback network module comprises a second resistor R2 and a fourth capacitor C4. The fourth capacitor C4 is respectively connected to the drain of the seventh switch MOS transistor T7 and the second resistor R2, and the second resistor R2 is connected to the output matching network module OMN. The drain electrode of the third switching MOS transistor T3 is connected with the gate electrode of the second amplifying MOS transistor T2; the source electrode of the fourth switching MOS transistor T4 is connected with the source electrode of the second amplifying MOS transistor T2, and the drain electrode of the fourth switching MOS transistor T4 is connected with the drain electrode of the first amplifying MOS transistor T1; the source electrode of the seventh switching MOS transistor T7 is connected with the gate electrode of the first amplifying MOS transistor T1; the first capacitor C1 is respectively connected with the source of the third switching MOS transistor T3 and the first resistor R1; the other end of the first resistor R1 is grounded.

In this embodiment, a radio frequency signal AC is input from an In end, enters a gate of the first amplification MOS transistor T1 after passing through the input matching network module IMN, flows out from a drain of the first amplification MOS transistor T1 after radio frequency amplification, enters a source of the second amplification MOS transistor T2 after passing through the fourth switch MOS transistor T4, flows out from a drain of the second amplification MOS transistor T2 after radio frequency amplification, and enters the third inductor L3, where the third inductor L3 is an output end impedance matching inductor of the second amplification MOS transistor T2, and is used to improve high frequency band feedback gain In a CSCG topology circuit working state. The AC flows out of the third inductor L3 and is output through the output matching network OMN. The second resistor R2 is connected in series with the fourth capacitor C4 and is connected in parallel with the gate of the first amplifying MOS transistor T1 and the output node of the third inductor L3, so that a negative feedback circuit is added in the CSCG working mode, and the gain flatness and standing wave are improved.

As a preferred solution of the circuit with dual topology provided by the embodiment of the present invention, a CSCG-level structure is stacked on the basis of fig. 2, see fig. 4. Fig. 4 is a schematic diagram of an amplifying circuit structure stacked in a CSCG stage, where the CSCG stage structure includes a third amplifying MOS transistor T8, a fifth capacitor C5 and a third resistor R3, and the fifth capacitor C5 and the third resistor R3 are connected in series to a gate of the third amplifying MOS transistor T8.

The function of the fifth capacitor C5 and the third resistor R3 is equal to that of the second resistor R2 connected in series with the fourth capacitor C4 and connected in parallel to the gate of the first amplification MOS transistor T1 and the output node of the third inductor L3, so that a negative feedback circuit is added in the CSCG working mode, and the gain flatness and the standing wave are improved.

When the TTL levels V11, V12, and V13 are high and the TTL levels V21 and V22 are low, the first switching MOS unit 1041 is in a conducting state and the second switching MOS unit 1042 is in a disconnecting state. Referring to fig. 5, fig. 5 is a schematic circuit diagram of an embodiment when a circuit with a dual topology structure operates in a circuit structure stacked in a CSCG series. The flow direction of the radio frequency signal AC is substantially the same as that of the circuit configuration diagram of an embodiment in the CSCG operation mode in fig. 3. The radio frequency signal AC is input from the In end, enters the gate of the first amplification MOS transistor T1 after passing through the input matching network module IMN, flows out from the drain thereof after radio frequency amplification by the first amplification MOS transistor T1, enters the source of the second amplification MOS transistor T2 after passing through the fourth switch MOS transistor T4, flows out from the drain thereof after radio frequency amplification by the second amplification MOS transistor T2, and differently, enters the source of the third amplification MOS transistor T8 again, and enters the third inductor L3 after flowing out from the drain thereof. The AC flows out of the third inductor L3 and is output through the output matching network OMN.

In this embodiment, a digital circuit unit provides a TTL high level to the first switching MOS transistor unit 1041, and at this time, the third switching MOS transistor T3, the fourth switching MOS transistor T4, and the seventh switching MOS transistor T7 connected to the first switching MOS transistor unit are in a conducting state; the second switching MOS unit 1042 is set to TTL low, and at this time, the fifth switching MOS T5 and the sixth switching MOS T6 connected to it are in the off state. The VDD power supply provides a direct current signal DC for the circuit, and the DC flows out of the first inductor L1, enters the third inductor L3, flows out of the third inductor L3, and enters the drain of the second amplification MOS transistor T2. The first inductor L1 is a drain supply terminal choke inductor of the second amplifying MOS transistor T2. After the DC flows out from the source of the second amplification MOS transistor T2, one way goes downward and enters the drain of the first amplification MOS transistor T1. The first capacitor C1 and the first resistor R1 are connected in series at the gate of the second amplifying MOS transistor, so that the high-frequency stability of the CSCG operating mode can be improved. The first capacitor C1 is a gate rf capacitor of the second amplifying MOS transistor, and the first resistor R1 is a small ground resistor. The DC enters the first amplifying MOS transistor and then flows out from the source thereof, and passes through the fourth inductor L4 to the ground terminal. The fourth inductor L4 is a source degeneration inductor of the first amplifying MOS transistor T1, which facilitates adjustment of input standing waves, gain, and noise.

Example 3

Referring to fig. 6, fig. 6 is a schematic circuit diagram of an embodiment of a dual topology circuit in a CSCS operating mode according to the present invention. As shown in fig. 6, the circuit structure includes, specifically, as follows: a second topology circuit 102, a radio frequency shunt module 103 and a second switching MOS transistor unit 1042.

The second topology circuit 102 includes, specifically, the following: an inter-stage matching network module and a second inductor L2. The interstage matching network module comprises a second capacitor C2 and a third capacitor C3; the second capacitor C2 is respectively connected to the drain of the fifth switch MOS transistor T5 and the drain of the first amplification MOS transistor T1, and the third capacitor is connected to the drain of the sixth switch MOS transistor T6, and the other end of the third capacitor is grounded. The source electrode of the fifth switching MOS transistor T5 is connected with the gate electrode of the second amplifying MOS transistor T2; the second inductor L2 is respectively connected to the drain of the first amplification MOS transistor T1 and the source of the second amplification MOS transistor T2; the source of the sixth switching MOS transistor T6 is connected to the source of the second amplifying MOS transistor T2.

In this embodiment, a radio frequency signal AC is input from the In terminal, enters the gate of the first amplification MOS transistor T1 after passing through the input matching network module IMN, flows out from the drain of the first amplification MOS transistor T1 after being radio frequency amplified, and then flows into the drain of the fifth switching MOS transistor T5 through the second capacitor C2. The radio-frequency signal AC flows out from the source of the fifth switching MOS transistor and enters the gate of the second amplifying MOS transistor T2. The second capacitor C2 is an amplification capacitor for performing common-source mode amplification on the gate of the second amplification MOS transistor T2 in the CSCS operating mode. The radio frequency signal AC is radio frequency amplified by the second amplification MOS transistor T2 and then flows out from the drain thereof, and is output through the output matching network module OMN after passing through the third inductor L3 and the first inductor L1.

As a preferred solution of the circuit with dual topology structure provided by the embodiment of the present invention, a CSCS-level structure is stacked on the basis of fig. 6, see fig. 7. Fig. 7 is a schematic diagram of an amplifying circuit structure stacked in a CSCS series. The CSCS stage structure comprises a fifth inductor L5, a fifth capacitor C5, a sixth capacitor C6 and a third amplifying MOS tube T8. The fifth inductor L5 is respectively connected to the drain of the second amplification MOS transistor T2 and the source of the third amplification MOS transistor T8, the fifth capacitor C5 is connected to the gate of the third amplification MOS transistor T8, the sixth capacitor C6 is connected to the source of the third amplification MOS transistor T8, the other end of the sixth capacitor C6 is grounded, and the drain of the third amplification MOS transistor T8 is connected to the third inductor L3. The sixth capacitor C6 is the rf common ground capacitor at the source terminal of the third amplifying MOS transistor T8.

When the TTL levels V21 and V22 are high and the TTL levels V11, V12 and V13 are low, the second switching MOS unit 1042 is in the on state and the first switching MOS unit 1041 is in the off state. Referring to fig. 8, fig. 8 is a schematic circuit diagram of an embodiment of a dual topology circuit operating in a circuit structure stacked in CSCS stages according to an embodiment of the present invention. The flow direction of the radio frequency signal AC is substantially the same as the flow direction of the schematic circuit structure of fig. 6 in the CSCS operation mode. The radio frequency signal AC is input from the In terminal, enters the gate of the first amplification MOS transistor T1 after passing through the input matching network module IMN, flows out from the drain thereof after radio frequency amplification by the first amplification MOS transistor T1, and then flows into the drain of the fifth switching MOS transistor T5 through the second capacitor C2. The radio-frequency signal AC flows out from the source of the fifth switching MOS transistor and enters the gate of the second amplifying MOS transistor T2. The radio frequency signal AC flows out from the drain of the second amplification MOS transistor T2, and enters the gate of the third amplification MOS transistor T8 through the fifth capacitor C5. The fifth capacitor is an amplification capacitor for performing common-source mode amplification on the gate of the third amplification MOS transistor T8 in the CSCS operating mode. The radio frequency signal AC is radio frequency amplified by the third amplification MOS transistor T8 and then flows out from the drain thereof, passes through the third inductor L3 and the first inductor L1, and is output through the output matching network module OMN.

The difference is that the radio-frequency amplified signal flows out from the drain of the second amplifying MOS tube T2, and then enters the source of the third amplifying MOS tube T8, and flows out from the drain of the third amplifying MOS tube T3556 before entering the third inductor L3. The AC flows out of the third inductor L3 and is output through the output matching network OMN.

In this embodiment, a TTL high level is given to the second switch 1012 through the digital circuit unit, and at this time, the fifth switch MOS transistor T5 and the sixth switch MOS transistor T6 connected to the second switch are in a conducting state; the TTL low level is given to the first switch 1011, and the third, fourth and seventh switching MOS transistors T3, T4 and T7 connected to the first switch are in the off state. The VDD power supply provides a direct current signal DC for the circuit, and the DC flows out of the first inductor L1, enters the third inductor L3, flows out of the third inductor L3, and enters the drain of the second amplification MOS transistor T2. The third capacitor C3 and the sixth switching MOS transistor are connected in series to the source of the second amplification MOS transistor, and the third capacitor C3 is a source radio frequency common ground capacitor (T6 transistor on) DC of the second amplification MOS transistor T2 in the CSCS mode, and after flowing out from the source of the second amplification MOS transistor T2, the DC goes downward all the way, passes through the second inductor L2, and enters the drain of the first amplification MOS transistor T1. The second inductor L2 is a drain rf choke inductor for the first amplifying MOS transistor T1 in the CSCS mode.

In summary, the circuit with a dual topology structure of the present invention is introduced in detail, and the specific examples applied herein illustrate the embodiments of the present invention, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and replacements can be made without departing from the technical principle of the present invention, and these modifications and replacements should also be regarded as the protection scope of the present invention.

Claims

1. A circuit having a dual topology, comprising: the device comprises a first topological circuit, a second topological circuit, a switch module and a radio frequency shunt module;

the first topological circuit and the second topological circuit share the same radio frequency shunt module; the radio frequency shunt module comprises an input matching network module, an output matching network module, a first amplification MOS tube, a second amplification MOS tube, a first inductor, a third inductor and a fourth inductor; the input matching network module is connected with the grid electrode of the first amplification MOS tube; the source electrode of the first amplification MOS tube is connected with the fourth inductor; the third inductor is connected with the first inductor and the drain electrode of the second amplification MOS tube;

2. The circuit of claim 1, wherein,

the switch module comprises a first switch MOS tube unit and a second switch MOS tube unit;

the first switching MOS tube unit is connected with the first topology circuit;

3. The circuit of claim 2, wherein,

the first topological circuit comprises a first capacitor and a first resistor;

4. The circuit of claim 2, wherein,

the first topology circuit further comprises a feedback network module;

the feedback network module comprises a second resistor and a fourth capacitor;

5. The circuit of claim 2, wherein the first and second nodes are configured to operate in a single operation,

the second topology circuit comprises a second inductor;

the source electrode of the fifth switching MOS tube is connected with the grid electrode of the second amplifying MOS tube; the second inductor is respectively connected with the drain electrode of the first amplification MOS tube and the source electrode of the second amplification MOS tube; and the source electrode of the sixth switching MOS tube is connected with the source electrode of the second amplifying MOS tube.

6. The circuit of claim 2, wherein,

the second topology circuit further comprises an inter-stage matching network module;

7. The circuit of claim 1, wherein,

the first inductor is a choke inductor, the third inductor is an impedance matching inductor, and the fourth inductor is a feedback inductor.

8. The circuit of claim 1, wherein,

the input matching network module is an input impedance matching section;

the output matching network module is an output impedance matching section.

9. A circuit of dual topology according to claim 5,

the second inductor is a choke inductor.

10. The circuit of claim 6, wherein the first and second nodes are configured to operate in a single operation,

the third capacitor is a common ground capacitor.