CN114865890A

CN114865890A - High-anti-interference circuit for GaN power tube half-bridge drive

Info

Publication number: CN114865890A
Application number: CN202210570464.0A
Authority: CN
Inventors: 孙伟锋; 袁清; 魏涛; 郑逸飞; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2022-05-24
Filing date: 2022-05-24
Publication date: 2022-08-05
Anticipated expiration: 2042-05-24
Also published as: CN114865890B

Abstract

The invention discloses a high/low side high anti-interference circuit for GaN power tube half-bridge drive, which is characterized in that a high/low side high anti-interference circuit is respectively arranged between a high/low side drive circuit and a high/low side GaN power tube, crosstalk inhibition auxiliary circuits formed by a positive crosstalk voltage peak absorption circuit and a negative crosstalk voltage peak absorption circuit are respectively arranged in the high/low side high anti-interference circuit, and the positive and negative crosstalk voltage peak absorption circuits are matched with each other, so that a good inhibition effect can be generated on the positive and negative crosstalk problems of the GaN circuit, and the drive circuit can work reliably.

Description

High-anti-interference circuit for GaN power tube half-bridge drive

Technical Field

The invention relates to a half-bridge driving circuit adopting a GaN (gallium nitride) power tube, in particular to a high-noise-rejection circuit for GaN power tube half-bridge driving.

Background

Power semiconductor devices play an important role in the regulatory distribution of world energy and power, and many types of high voltage silicon-based devices are widely used in power electronics and power system design, but with the continuous progress of scientific technology, silicon-based technology has reached physical limits in terms of power density and switching frequency. The emergence of third generation wide bandgap semiconductor devices has made it possible to break this physical limit, among which GaN devices, as a main representative, have the significant advantages of fast switching speed, low off-loss, high withstand voltage, etc., thereby improving the switching frequency and power density of the system.

However, in an actual bridge circuit, as the switching frequency is increased, undesirable factors such as parasitic parameters of GaN itself and parasitic inductances of a power loop and a driving loop generate voltage spikes that may impair the operation of the system due to high dV/dt, specifically: in a bridge circuit, when a GaN power tube in the same bridge arm is turned on or turned off at a high speed, the Miller capacitance of another GaN power tube bears a large dV/dt to generate a large Miller current acting between gate-source voltages, thereby generating a forward crosstalk voltage spike. Because the GaN power tube has a smaller threshold voltage, the positive crosstalk voltage spike can exceed the threshold voltage to a great extent to cause the GaN power tube to be turned on by mistake, and the negative crosstalk voltage spike can exceed the maximum gate-source breakdown negative voltage of the GaN power tube to cause the performance of the GaN power tube to be degraded or damaged. Therefore, the crosstalk problem becomes an important obstacle for restricting the application of the GaN power tube in a higher frequency field, and the study of the crosstalk suppression problem of the circuit also has more important significance.

Currently, the mainstream crosstalk suppression strategies are roughly divided into three types:

1. reducing the switching speed of the power switching tube and thus reducing the higher dV/dt and di/dt mitigates the negative effects of crosstalk misconnection and potential breakdown failure risk, however, the advantageous characteristics of the power switching tube in low frequency applications will be limited and therefore reducing the switching speed is rarely used.

2. The method of controlling gate impedance is, in theory, an embodiment of the basic idea of crosstalk suppression. The control of the gate impedance means that the gate impedance of one of the switches is reduced during the complementary switching transient, and the simplest implementation method is to add a capacitor between the gate and the source of the power switch tube. Although simple and effective, the method reduces the switching speed and increases the switching loss.

3. Negative voltage turn-off and multilevel driving, on one hand, the turn-off speed can be effectively improved by utilizing the negative voltage turn-off, and meanwhile, the positive crosstalk voltage spike can be inhibited, but the problem is that the turn-off of a power tube in a bridge circuit can cause a larger negative voltage spike instantly, so that the maximum gate-source breakdown negative voltage of the power tube is exceeded; on the other hand, the effect of reducing crosstalk voltage is achieved by designing the multilevel conversion circuit to respectively insert the classification voltage in each stage of on and off.

Disclosure of Invention

The invention aims to provide a high-immunity circuit for GaN power tube half-bridge driving on the basis of not slowing down the switching speed of a GaN power tube and increasing the switching loss and the circuit complexity, which can effectively inhibit the crosstalk problem generated by the grid-source voltage of the GaN power tube in the circuit, so that the positive crosstalk voltage and the negative crosstalk voltage are kept within a safety threshold.

In order to achieve the purpose, the invention adopts the following technical scheme: a high-immunity circuit for GaN power tube half-bridge drive is provided with a high-side drive circuit, a high-side GaN power tube MH, a low-side drive circuit and a low-side GaN power tube ML. The method is characterized in that: and a high/low side high-immunity circuit is arranged between the high/low side driving circuit and the high/low side GaN power tube MH/ML respectively, and the high/low side high-immunity circuit is connected between the grid electrode and the source electrode of the high/low side GaN power tube MH/ML in the bridge arm circuit respectively.

A high-side crosstalk suppression auxiliary loop is arranged in the high-side high-immunity circuit and comprises a positive crosstalk voltage peak absorption circuit and a negative crosstalk voltage peak absorption circuit; the forward crosstalk voltage spike absorption circuit comprises a resistor R1_ H, PNP triode T1_ H, a capacitor C1_ H and a diode D2_ H, wherein one end of the resistor R1_ H is connected with the output end of the high-side driving circuit and the base electrode of the PNP triode T1_ H, the other end of the resistor R1_ H is connected with the emitter electrode of the PNP triode T1_ H, the collector electrode of the PNP triode T1_ H is connected with one end of the capacitor C1_ H, the other end of the capacitor C1_ H is connected with the anode of a diode D2_ H, and the cathode of the diode D2_ H is connected with the cathode of the high-side driving power supply VDD _ H and the high-side reference ground floating voltage VS; the negative crosstalk voltage spike absorption circuit comprises a diode D1_ H, NPN, a triode T2_ H, a resistor R2_ H and a capacitor C1_ H shared by the positive crosstalk voltage spike absorption circuit; the cathode of the diode D1_ H is connected to a connection point between the emitter of the PNP transistor T1_ H and the resistor R1_ H in the forward crosstalk voltage spike absorption circuit and the gate of the high-side GaN power tube MH, the anode of the diode D1_ H is connected to a connection point between the collector of the PNP transistor T1_ H and the capacitor C1_ H in the forward crosstalk voltage spike absorption circuit, the emitter of the NPN transistor T2_ H is connected to a connection point between the capacitor C1_ H and the anode of the diode D2_ H in the forward crosstalk voltage spike absorption circuit, the base of the NPN transistor T2_ H is connected to one end of the resistor R2_ H, and the other end of the resistor R2_ H and the collector of the NPN transistor T2_ H are both connected to the high-side reference ground floating voltage VS;

the low-side high-immunity circuit is internally provided with a low-side crosstalk inhibition auxiliary loop, the structure of the low-side crosstalk inhibition auxiliary loop is the same as that of the high-side crosstalk inhibition auxiliary loop, and the low-side crosstalk inhibition auxiliary loop comprises a positive crosstalk voltage spike absorbing circuit and a negative crosstalk voltage spike absorbing circuit; the forward crosstalk voltage spike absorption circuit comprises a resistor R1_ L, PNP triode T1_ L, a capacitor C1_ L and a diode D2_ L, wherein one end of the resistor R1_ L is connected with the output end of the low-side drive circuit and the base electrode of the PNP triode T1_ L, the other end of the resistor R1_ L is connected with the emitter electrode of the PNP triode T1_ L, the collector electrode of the PNP triode T1_ L is connected with one end of the capacitor C1_ L, the other end of the capacitor C1_ L is connected with the positive electrode of the diode D2_ L, and the negative electrode of the diode D2_ L is connected with the low-side reference ground GND; the negative crosstalk voltage spike absorption circuit comprises a resistor R2_ L, a diode D1_ L, NPN, a triode T2_ L and a capacitor C1_ L shared by the positive crosstalk voltage spike absorption circuit; the cathode of the diode D1_ L is connected to a connection point between the emitter of the PNP transistor T1_ L and the resistor R1_ L in the forward crosstalk voltage spike absorption circuit and the gate of the low-side GaN power tube ML, the anode of the diode D1_ L is connected to a connection point between the collector of the PNP transistor T1_ L and the capacitor C1_ L in the forward crosstalk voltage spike absorption circuit, the emitter of the NPN transistor T2_ L is connected to a connection point between the capacitor C1_ L and the anode of the diode D2_ L in the forward crosstalk voltage spike absorption circuit, the base of the NPN transistor T2_ L is connected to one end of the resistor R2_ L, and the other end of the resistor R2_ L and the collector of the NPN transistor T2_ L are both connected to the low-side reference ground GND.

Preferably, the diode D2_ H may be removed from the forward crosstalk voltage spike absorbing circuit in the high-side crosstalk suppression auxiliary loop, and a resistor R3_ H, a resistor R4_ H, a capacitor C3_ H, a capacitor C4_ H, and a diode D4_ H are added, where the connection relationship is: one end of a resistor R1_ H is connected with the output end of the high-side driving circuit, the base electrode of a PNP triode T1_ H, one end of a resistor R4_ H and the anode of a diode D4_ H, the cathode of a diode D4_ H is connected with one end of a capacitor C4_ H, the other end of the capacitor C4_ H is connected with the other end of a resistor R4_ H and one end of a capacitor C3_ H, one end of a resistor R3_ H and one end of a capacitor C1_ H are connected with a high-side reference ground floating voltage VS, the other end of a capacitor C1_ H is connected with the collector electrode of a PNP triode T1_ H, the emitter electrode of the PNP triode T1_ H is connected with the other end of a resistor R1_ H, and the other end of the capacitor C3_ H and the other end of the resistor R3_ H are connected with the cathode of a high-side driving power supply VDD _ H; removing an NPN triode T2_ H and a resistor R2_ H from a negative crosstalk voltage spike absorption circuit in the high-side crosstalk suppression auxiliary loop, wherein the connection relationship is as follows: the cathode of the diode D1_ H is connected with the connection end of the emitter of the PNP triode T1_ H and the resistor R1_ H in the forward crosstalk voltage spike absorption circuit and the grid of the high-side GaN power tube MH, the anode of the diode D1_ H is connected with the connection end of the collector of the PNP triode T1_ H and the capacitor C1_ H in the forward crosstalk voltage spike absorption circuit, one end of the capacitor C1_ H is connected with the connection end of the capacitor C3_ H, the resistor R3_ H, the capacitor C4_ H and the resistor R4_ H in the forward crosstalk voltage spike absorption circuit and the high-side reference ground floating voltage VS;

the structure of the low-side crosstalk suppression auxiliary loop is the same as that of the high-side crosstalk suppression auxiliary loop, a diode D2_ L is removed from a forward crosstalk voltage spike absorption circuit in the low-side crosstalk suppression auxiliary loop, a resistor R3_ L, a resistor R4_ L, a capacitor C3_ L, a capacitor C4_ L and a diode D4_ L are additionally arranged, and the connection relationship is as follows: one end of the resistor R1_ L is connected to the output end of the low-side driver circuit, the base of the PNP transistor T1_ L, one end of the resistor R4_ L and the anode of the diode D4_ L, the cathode of the diode D4_ L is connected to one end of the capacitor C4_ L, the other end of the capacitor C4_ L is connected to the other end of the resistor R4_ L and one end of the capacitor C3_ L, one end of the resistor R3_ L and one end of the capacitor C1_ L, and the low-side ground GND, the other end of the capacitor C1_ L is connected to the collector of the PNP transistor T1_ L, the emitter of the PNP transistor T1_ L is connected to the other end of the resistor R1_ L, and the other end of the capacitor C3_ L and the other end of the resistor R3_ L are connected to the cathode of the low-side driver power supply VDD _ L; removing an NPN triode T2_ L and a resistor R2_ L from a negative crosstalk voltage spike absorption circuit in the low-side crosstalk suppression auxiliary loop, wherein the connection relationship is as follows: the cathode of the diode D1_ L is connected to the connection point between the emitter of the PNP transistor T1_ L and the resistor R1_ L in the forward crosstalk voltage spike absorption circuit and the gate of the high-side GaN power tube ML, the anode of the diode D1_ L is connected to the connection point between the collector of the PNP transistor T1_ L in the forward crosstalk voltage spike absorption circuit and the capacitor C1_ L, and one end of the capacitor C1_ L is connected to the connection point between the capacitor C3_ L and the resistor R3_ L in the forward crosstalk voltage spike absorption circuit, the connection point between the capacitor C4_ L and the resistor R4_ L in the forward crosstalk voltage spike absorption circuit, and the low-side reference ground GND.

The high-side driving circuit comprises a high-side driving power supply VDD _ H, PMOS tube S1_ H and an NMOS tube S2_ H, wherein the high-side driving power supply VDD _ H, PMOS tube S1_ H and the NMOS tube S2_ H are powered by bootstrap track voltage in the high side, the source electrode of the PMOS tube S1_ H is connected with the positive electrode of the high-side driving power supply VDD _ H, the drain electrode of the PMOS tube S1_ H is connected with the drain electrode of the NMOS tube S2_ H and serves as the output end of the high-side driving circuit, the source electrode of the NMOS tube S2_ H is connected with the negative electrode of the high-side driving power supply VDD _ H and is connected with a high-side reference ground floating voltage VS, the grid electrodes of the PMOS tube S1_ H and the NMOS tube S2_ H are respectively connected with high-side driving signals, and the high-side driving signals are connected in a push-pull mode; the low-side driving circuit and the high-side driving circuit have the same structure and comprise a low-side driving power supply VDD _ L, PMOS tube S1_ L and an NMOS tube S2_ L which are directly powered by a direct-current power supply, wherein the source electrode of the PMOS tube S1_ L is connected with the positive electrode of the low-side driving power supply VDD _ L, the drain electrode of the PMOS tube S1_ L is connected with the drain electrode of the NMOS tube S2_ L and serves as the output end of the low-side driving circuit, the source electrode of the NMOS tube S2_ L is connected with the negative electrode of the low-side driving power supply VDD _ L and is connected with the ground GND, the grid electrodes of the PMOS tube S1_ L and the NMOS tube S2_ L are respectively connected with low-side driving signals, and the low-side driving signals are accessed in a push-pull mode.

Further, the PMOS transistor S1_ H and the NMOS transistor S2_ H in the high-side driver circuit and the PMOS transistor S1_ L and the NMOS transistor S2_ L in the low-side driver circuit are both low-voltage transistors.

The invention has the advantages and obvious effects that: the high/low side high-immunity circuit is arranged between the high/low side driving circuit and the high/low side GaN power tube MH/ML, and the high/low side high-immunity circuit is connected between the grid electrode and the source electrode of the high/low side GaN power tube MH/ML in the bridge arm circuit. And the high/low-side high-immunity circuit is internally provided with a crosstalk suppression auxiliary loop consisting of a positive crosstalk voltage peak absorption circuit and a negative crosstalk voltage peak absorption circuit, and the positive and negative crosstalk voltage peak absorption circuits are matched with each other to generate a good suppression effect on the positive and negative crosstalk problems of the GaN circuit, so that the driving circuit can work reliably.

Drawings

FIG. 1 is a schematic diagram of an embodiment of the present invention for a GaN power transistor half-bridge driver with high noise immunity;

FIG. 2 is a waveform diagram illustrating a crosstalk suppression driving circuit of the lower bridge arm of the embodiment of FIG. 1;

FIGS. 3(a) and (b) are equivalent circuit operation diagrams of the embodiment of FIG. 1 during the time periods t 3-t 4 and t 5-t 6, respectively;

FIG. 4 is another embodiment of the present invention for a GaN power transistor half-bridge driven high immunity circuit; (ii) a

FIG. 5 is a waveform diagram illustrating a crosstalk suppression driving circuit of a lower arm of the embodiment of FIG. 4;

FIGS. 6(a) and (b) are equivalent circuit diagrams of the embodiment of FIG. 4 during the time period t 3-t 4 and the time period t 5-t 6, respectively.

Detailed Description

The invention is further described with reference to the following figures and specific examples.

FIG. 1 is a circuit according to an embodiment of the present invention. A high-side crosstalk suppression auxiliary loop 001_ H is arranged in the high-side high-immunity circuit and comprises a resistor R1_ H, a resistor R2_ H, a diode D1_ H, a diode D2_ H, a capacitor C1_ H, NPN triode T2_ H and a PNP triode T1_ H, wherein the resistor R1_ H, PNP triode T1_ H, the capacitor C1_ H and the diode D2_ H form a forward crosstalk voltage spike absorption circuit 002_ H; the diode D1_ H, NPN, the transistor T2_ H, the resistor R2_ H, and the capacitor C1_ H (shared) form a negative crosstalk voltage spike absorbing circuit 003_ H. The low-side high-immunity circuit 001_ L has the same structure as the high-side crosstalk suppression auxiliary loop 001_ H, and comprises a resistor R1_ L, a resistor R2_ L, a diode D1_ L, a diode D2_ L, a capacitor C1_ L, NPN, a triode T2_ L and a PNP triode T1_ L, wherein the resistor R1_ L, PNP, the triode T1_ L, the capacitor C1_ L and the diode D2_ L form a forward crosstalk voltage spike absorption circuit 002_ L; the diode D1_ L, NPN, the transistor T2_ L, the resistor R2_ L, and the capacitor C1_ L (shared) form a negative crosstalk voltage spike absorbing circuit 003_ L. When a voltage spike of the forward crosstalk occurs, a voltage drop is generated at two ends of the resistor R1_ H/L to enable the PNP triode T1_ H/L to be turned on, a low-impedance path formed by the resistor T1_ H/L, C1_ H/L and the resistor D2_ H/L is provided, and the capacitor C1_ H/L absorbs energy of the voltage spike generated by the crosstalk. Similarly, R2_ H/L, T2_ H/L, C1_ H/L and D1_ H/L form a negative crosstalk voltage spike absorption circuit, when a negative crosstalk voltage spike occurs, the NPN transistor T2_ H/L is turned on to provide a low impedance path formed by T2_ H/L, C1_ H/L and D _ H/L, and the capacitor C1_ H/L absorbs energy of a voltage spike generated by crosstalk, thereby suppressing the negative crosstalk voltage. The positive crosstalk voltage spike absorption circuit 002_ H/L and the negative crosstalk voltage spike absorption circuit 003_ H/L share one capacitor C1_ H/L, no additional capacitive load is introduced, and the influence of the crosstalk suppression circuit on the switching speed of the GaN power tube is reduced to the maximum extent.

Fig. 2 is a waveform diagram of a crosstalk suppression driving circuit applied to a lower bridge arm of a half-bridge circuit according to an embodiment of the present invention, and further illustrates a working principle of the first embodiment of the present invention.

In a period from t0 to t1, the MOS transistor S1_ L is switched on, the MOS transistor S2_ L is switched off, the lower driving circuit charges a gate-source capacitor Cgs of the low-side power tube ML through a resistor R1_ L, the low-side power tube ML is in a conducting state, and in the conducting state, the positive and negative crosstalk voltage spike absorption circuits do not work, so that no additional power loss is introduced into the circuit; meanwhile, the MOS tube S1_ H is turned off, the MOS tube S2_ H is turned on, the high-side power tube MH is in a turned-off state, the positive crosstalk voltage spike absorption circuit 002_ L and the negative crosstalk voltage spike absorption circuit 003_ L do not work, and the positive and negative crosstalk voltage spike absorption circuits do not work when the GaN power tube is in a complete turned-on or turned-off state, so that extra power loss is avoided.

In a period from t1 to t2, the MOS transistor S1_ H is turned off, the MOS transistor S2_ H is turned on, the MOS transistor S1_ L is turned off, and the MOS transistor S2_ L is turned on, at this time, the low-side power transistor ML is turned off, the high-side power transistor MH is still in an off state, and the low-side power transistor ML is completely turned off at a time point t 2.

In a period from t2 to t3, the MOS transistor S1_ H is turned off, the MOS transistor S2_ H is turned on, the MOS transistor S1_ L is turned off, and the MOS transistor S2_ L is turned on, and at this time, the high-side power transistor MH and the low-side power transistor ML are both in a turned-off state, which is called dead time, so that high power loss caused by simultaneous conduction of the high-side switching transistor and the low-side switching transistor is avoided.

the time interval t 3-t 4 (see fig. 3(a) for the equivalent diagram of the operation at the moment when the high-side power transistor MH is turned on). The MOS transistor S1_ H starts to be turned on, the MOS transistor S2_ H starts to be turned off, the MOS transistor S1_ L is turned off, the MOS transistor S2_ L is turned on, the low-side power tube ML is turned off, the high-side power tube MH starts to be turned on, at the moment of turning on, the drain-source voltage VDS _ L of the low-side power tube ML suddenly changes to cause a positive large dV/dt change, the high-speed dV/dt acts on two ends of the miller capacitor of the low-side power tube ML to generate a positive displacement current I0, and when the forward crosstalk voltage spike absorption circuit 002 is not introduced, the displacement current I0 will generate an additional gate-source positive crosstalk voltage spike (V crosstalk +), through a lower driving loop. However, due to the introduction of the forward crosstalk voltage spike absorption circuit 002, the displacement current I0 generates a voltage drop through the resistor R1_ L to enable the PNP transistor T1_ L to be turned on to provide a low-resistance path, and the capacitor C1_ L absorbs the energy of the forward crosstalk voltage spike, so that the gate-source forward crosstalk voltage spike (V crosstalk +) is effectively suppressed and is not more than the threshold voltage VTH of the GaN tube, and thus, the forward crosstalk voltage suppression function is realized.

the time period from t4 to t 5. The MOS tube S1_ H is connected, the MOS tube S2_ H is disconnected, the MOS tube S1_ L is disconnected, the MOS tube S2_ L is connected, the high-side power tube MH is in a connected state, the low-side power tube ML is in a disconnected state, and in the state, the circuit works normally and no crosstalk effect is introduced.

In the period from t5 to t6 (see fig. 3(b) the equivalent working diagram at the moment when the high side power tube MH is turned off), the MOS transistor S1_ H starts to turn off, the MOS transistor S2_ H starts to turn on, the MOS transistor S1_ L turns off, the MOS transistor S2_ L turns on, the low side power tube ML is in the off state, the high side power tube MH starts to turn off, at the moment when the high side power tube MH starts to turn off, the drain-source voltage VDS _ L of the low side power tube ML suddenly changes to cause a negative large dV/dt change, the high dV/dt acts on both ends of the miller capacitance of the low side power tube ML to generate a negative displacement current I1, when the negative crosstalk voltage spike absorbing circuit 003_ L is not introduced, the displacement current I1 generates an additional gate-source negative crosstalk voltage spike (V-crosstalk gate-crosstalk) through the lower driving loop, and the gate-source negative crosstalk voltage spike (V-crosstalk) may exceed the maximum gate-source breakdown voltage of the GaN tube, resulting in breakdown of the GaN tube. However, due to the introduction of the negative crosstalk voltage spike absorbing circuit 003_ L, the displacement current I1 will generate a large negative voltage through a first path formed by the MOS transistor S2_ L and the resistor R1_ L, and then the displacement current I1 will generate a voltage drop through the resistor R2_ L, so that the NPN transistor T2_ L is turned on to form the negative crosstalk voltage spike absorbing path 003_ L, and the capacitor C1_ L absorbs the energy of the negative crosstalk voltage spike, thereby effectively suppressing the gate-source negative crosstalk voltage spike (V crosstalk-) and making it not exceed the maximum gate-source breakdown negative voltage of the GaN transistor. Thus, the negative crosstalk voltage suppression function is realized.

In a period from t6 to t7, the MOS transistor S1_ H is turned off, the MOS transistor S2_ H is turned on, the MOS transistor S1_ L is turned off, the MOS transistor S2_ L is turned on, and both the high-side power transistor and the low-side power transistor are in a turned-off state, which is called dead time.

After t7, the low side power tube ML starts to conduct, the high side power tube MH is in off state, and the half bridge circuit starts another cycle.

Fig. 4 is a second preferred embodiment of the present invention improved on the first embodiment. The high-side high-immunity circuit is internally provided with a high-side crosstalk inhibition auxiliary loop 001 '_ H, and the crosstalk inhibition auxiliary loop 001' _ H is internally provided with a positive crosstalk voltage spike absorbing circuit 002 '_ H and a negative crosstalk voltage spike absorbing circuit 003' _ H. The forward crosstalk voltage spike absorption circuit 002' _ H is configured in an embodiment that, on the basis that the forward crosstalk voltage spike absorption circuit 002_ H is provided with a resistor R1_ H, PNP triode T1_ H and a capacitor C1_ H, a resistor R3_ H, a resistor R4_ H, a capacitor C3_ H, a capacitor C4_ H and a diode D4_ H are added, wherein the resistor R3_ H, the resistor R4_ H, the diode D4_ H, the capacitor C3_ H and the capacitor C4_ H cooperate to form a self-recovery adjustable negative voltage generation circuit 0021_ H for generating a negative voltage. The negative crosstalk voltage spike absorbing circuit 003' _ H is provided with only the diode D1_ H and the capacitor C1_ H (shared), except for the NPN transistor T2_ H and the resistor R2_ H in the negative crosstalk voltage spike absorbing circuit 003_ H. The low-side high-immunity circuit 001 '_ L has the same structure as the high-side crosstalk suppression auxiliary loop 001' _ H, wherein the resistor R3_ L, the resistor R4_ L, the diode D4_ L, the capacitor C3_ L and the capacitor C4_ L cooperate to form a self-recovery adjustable negative voltage generation circuit 0021_ L generating negative voltage. The self-recovery adjustable negative voltage generation circuit 0021_ H/0021_ L works when positive voltage spikes appear, positive crosstalk voltage is restrained through generated negative voltage, and the negative voltage can be automatically recovered to zero voltage before the next negative crosstalk voltage spike arrives, so that the defect of the traditional negative voltage generation circuit that the generated unrecoverable negative voltage can increase the negative crosstalk voltage spike before the next negative crosstalk voltage spike arrives is overcome. Meanwhile, the occurrence of negative pressure can accelerate the turn-off speed of the GaN power tube. The positive crosstalk voltage spike absorption circuit 002' _ H/L works when a positive voltage spike occurs, a low impedance path is provided while the self-recovery adjustable negative voltage generation circuit 0021_ H/0021_ L works, and the capacitor C1_ H/L absorbs the energy of the positive crosstalk voltage spike, so that the positive crosstalk voltage is effectively restrained. The positive crosstalk voltage spike absorbing circuit 003' _ H/L operates when a negative voltage spike occurs, providing a low impedance path, and the capacitor C1_ H/L absorbs the energy of the negative crosstalk voltage spike, thereby effectively suppressing the negative crosstalk voltage.

Fig. 5 is a waveform diagram of a crosstalk suppression driving circuit applied to a lower bridge arm of a half-bridge circuit according to a second embodiment, and further illustrates the operating principle of the second embodiment of the present invention.

In a period from t0 to t1, the MOS transistor S1_ L is turned on, the MOS transistor S2_ L is turned off, the MOS transistor S1_ H is turned off, the MOS transistor S2_ H is turned on, the high-side power transistor MH is in a turned-off state, and the low-side power transistor ML is in a turned-on state. When the MOS transistor S1_ L is turned on, the diode D1_ L is turned on, the lower driving circuit charges the gate-source capacitor Cgs of the low-side power transistor ML, the charging current charges the capacitor C4_ L and the capacitor C3_ L through the resistor R4_ L and the resistor R3_ L voltage divider circuit, after charging is finished, the voltage at the two ends of the capacitor C3_ L is negative voltage, and due to the existence of the resistor R4_ L, the negative voltage at the two ends of the capacitor C3_ L is gradually attenuated to zero voltage after charging is finished, so that the self-recovery adjustable negative voltage function is realized. During this time period, the positive and negative crosstalk voltage spike absorption circuits are not introduced into the circuit, and therefore no additional power loss is generated.

In a period from t1 to t2, the MOS transistor S1_ H is turned off, the MOS transistor S2_ H is turned on, the MOS transistor S1_ L starts to be turned off, and the MOS transistor S2_ L starts to be turned on, at this time, the high-side power transistor MH is still in a turned-off state, and the low-side power transistor ML starts to be turned off, because of the introduction of the self-recovery adjustable negative voltage generation circuit 0021_ L, the negative voltage across the capacitor C3_ L accelerates the turn-off of the low-side power transistor ML, the turn-off speed of the power transistor is improved, and at a time t2, the low-side power transistor ML is completely turned off. The generated negative pressure can be restored and attenuated to zero pressure before the low-side power tube ML is started, and the starting speed of the power tube is not influenced.

In a period from t2 to t3, the MOS transistor S1_ H is turned off, the MOS transistor S2_ H is turned on, the MOS transistor S1_ L is turned off, and the MOS transistor S2_ L is turned on, at this time, the high-side power transistor MH and the low-side power transistor ML are both in a turned-off state, which is called dead time, so that a large power loss caused by simultaneous conduction of the high-side power transistor and the low-side power transistor is avoided.

In the period from t3 to t4 (see the working equivalent diagram of fig. 6(a) at the moment when the high-side power tube MH is turned on), the MOS transistor S1_ H starts to be turned on, the MOS transistor S2_ H starts to be turned off, the MOS transistor S1_ L is turned off, the MOS transistor S2_ L is turned on, the low-side power tube ML is in the off state, the high-side power tube MH starts to be turned on, at the moment when the high-side power tube MH is turned on, the drain-source voltage VDS _ L of the low-side power tube ML changes suddenly to cause a positive large dV/dt change, and a high-speed dV/dt acts across the miller capacitance of the low-side power tube ML, thereby generating a positive displacement current I0, and when the forward crosstalk voltage spike absorbing circuit 002' _ L is not introduced, this displacement current I0 will generate additional gate-source positive crosstalk voltage spikes (vbias +) through the lower drive loop, since the threshold voltage VTH of the GaN tube is small, the gate-source positive crosstalk voltage spike (vbias +) easily exceeds the threshold voltage VTH to cause false turn-on. However, due to the introduction of the forward crosstalk voltage spike absorption circuit 002' _ L, on one hand, the self-recovery adjustable negative voltage generation circuit 0021_ L provides negative voltage for suppressing the forward crosstalk voltage, on the other hand, the displacement current I0 generates a voltage drop through the resistor R1_ L to enable the PNP transistor T1_ L to be turned on to provide a low-resistance path, and the capacitor C1_ L absorbs the energy of the forward crosstalk voltage spike. Under the coordination of the self-recovery adjustable negative voltage generating circuit 0021_ L, the forward crosstalk voltage spike absorbing circuit 002' _ L more effectively suppresses the gate-source positive crosstalk voltage spike (vcross +), so that the voltage spike is far lower than the threshold voltage VTH of the GaN tube, and thus, the forward crosstalk voltage suppression function is realized.

In a period from t4 to t5, the MOS transistor S1_ H is turned on, the MOS transistor S2_ H is turned off, the MOS transistor S1_ L is turned off, the MOS transistor S2_ L is turned on, the high-side power transistor MH is in a conducting state, and the low-side power transistor ML is in a turned-off state. In this state, the circuit works normally without introducing crosstalk effect. Meanwhile, in this time period, the self-recovery adjustable negative voltage generation circuit 0021_ L still works, and the resistor R3_ L connected in parallel with the capacitor C3_ L can gradually recover the negative voltage at the two ends of the capacitor to zero voltage, so as to avoid that the fixed negative voltage aggravates the negative crosstalk effect when the next negative crosstalk voltage spike occurs.

In the period from t5 to t6 (see fig. 6(b) the equivalent working diagram at the moment when the high side power tube MH is turned off), the MOS transistor S1_ H starts to turn off, the MOS transistor S2_ H starts to turn on, the MOS transistor S1_ L is turned off, the MOS transistor S2_ L is turned on, the low side power tube ML is in the off state, the high side power tube MH starts to turn off, at the moment when the high side power tube MH starts to turn off, the drain-source voltage VDS _ L of the low side power tube ML suddenly changes to cause a negative large dV/dt change, the high dV/dt acts on both ends of the miller capacitance of the low side power tube ML to generate a negative displacement current I1, when the negative crosstalk voltage spike absorbing circuit 003' _ L is not introduced, the displacement current I1 generates an additional gate-source negative crosstalk voltage spike (V crosstalk-) through the lower driving loop, and the gate-source negative crosstalk voltage spike (V-) may exceed the maximum gate-source breakdown negative voltage of the GaN tube, resulting in breakdown of the GaN tube. However, due to the introduction of the negative crosstalk voltage spike absorption circuit 003' _ L, the diode D1_ L is turned on to provide a low-impedance path, and the capacitor C1_ L absorbs the energy of the negative crosstalk voltage spike, so that the gate-source negative crosstalk voltage spike (vcross-) is effectively suppressed and does not exceed the maximum gate-source breakdown negative voltage of the GaN tube. Meanwhile, compared with the conventional negative voltage generating circuit, the negative voltage generated by the self-recovery adjustable negative voltage generating circuit 0021_ L provided by the second embodiment of the present invention is already attenuated to zero voltage when the negative crosstalk effect acts, so that the self-recovery adjustable negative voltage generating circuit 0021_ L maximally alleviates the influence of the negative voltage on the negative crosstalk voltage. Thus, the negative crosstalk voltage suppression function is realized.

The high/low side driving circuits in the first embodiment of fig. 1 and the second embodiment of fig. 4 both adopt a prior art structure, the high side driving power VDD _ H is supplied by the bootstrap rail voltage in the high side, the low side driving power VDD _ L is directly supplied by the dc power, and the gate driving signals of the MOS transistors in the high/low side driving circuits are all connected in a push-pull manner.

In order to compare the crosstalk suppression effects of the first embodiment and the second embodiment in the half-bridge circuit, simulation analysis is performed on the driving circuits of the first embodiment and the second embodiment and the driving circuits of the auxiliary circuit without crosstalk suppression based on a Cadence spectrum simulation software platform under the test conditions that dV/dt is 50V/ns and 100V/ns respectively, and the simulation results are compared as shown in the following table:

the data comparison in the table shows that the invention is suitable for the high-immunity grid driving circuit of the GaN power switch device, can effectively inhibit the generation of grid crosstalk, and particularly shows more outstanding inhibition effect on the pair of forward crosstalk voltages in the embodiment.

Claims

1. A high-immunity circuit for GaN power tube half-bridge drive is provided with a high-side drive circuit, a high-side GaN power tube MH, a low-side drive circuit and a low-side GaN power tube ML;

the method is characterized in that: a high/low side high-immunity circuit is arranged between the high/low side driving circuit and the high/low side GaN power tube MH/ML, and the high/low side high-immunity circuit is connected between the grid electrode and the source electrode of the high/low side GaN power tube MH/ML in the bridge arm circuit;

2. The high immunity circuit for GaN power transistor half-bridge drive of claim 1, wherein: the diode D2_ H is removed from the forward crosstalk voltage spike absorption circuit in the high-side crosstalk suppression auxiliary loop, the resistor R3_ H, the resistor R4_ H, the capacitor C3_ H, the capacitor C4_ H and the diode D4_ H are additionally arranged, and the connection relationship is as follows: one end of a resistor R1_ H is connected with the output end of the high-side driving circuit, the base electrode of a PNP triode T1_ H, one end of a resistor R4_ H and the anode of a diode D4_ H, the cathode of a diode D4_ H is connected with one end of a capacitor C4_ H, the other end of the capacitor C4_ H is connected with the other end of a resistor R4_ H and one end of a capacitor C3_ H, one end of a resistor R3_ H and one end of a capacitor C1_ H are connected with a high-side reference ground floating voltage VS, the other end of a capacitor C1_ H is connected with the collector electrode of a PNP triode T1_ H, the emitter electrode of the PNP triode T1_ H is connected with the other end of a resistor R1_ H, and the other end of the capacitor C3_ H and the other end of the resistor R3_ H are connected with the cathode of a high-side driving power supply VDD _ H; removing an NPN triode T2_ H and a resistor R2_ H from a negative crosstalk voltage spike absorption circuit in the high-side crosstalk suppression auxiliary loop, wherein the connection relationship is as follows: the cathode of the diode D1_ H is connected with the connection end of the emitter of the PNP triode T1_ H and the resistor R1_ H in the forward crosstalk voltage spike absorption circuit and the grid of the high-side GaN power tube MH, the anode of the diode D1_ H is connected with the connection end of the collector of the PNP triode T1_ H and the capacitor C1_ H in the forward crosstalk voltage spike absorption circuit, one end of the capacitor C1_ H is connected with the connection end of the capacitor C3_ H, the resistor R3_ H, the capacitor C4_ H and the resistor R4_ H in the forward crosstalk voltage spike absorption circuit and the high-side reference ground floating voltage VS;

3. The high immunity circuit for GaN power transistor half-bridge drive of claim 1, wherein the high side drive circuit comprises a high side drive power VDD _ H, PMOS transistor S1_ H and an NMOS transistor S2_ H powered by a bootstrap rail voltage in the high side, the source of the PMOS transistor S1_ H is connected to the positive pole of the high side drive power VDD _ H, the drain of the PMOS transistor S1_ H is connected to the drain of the NMOS transistor S2_ H and serves as the output terminal of the high side drive circuit, the source of the NMOS transistor S2_ H is connected to the negative pole of the high side drive power VDD _ H and is connected to a high side reference ground floating voltage VS, the gates of the PMOS transistor S1_ H and the NMOS transistor S2_ H are respectively connected to the high side drive signal, and the high side drive signal is switched in a push-pull manner; the low-side driving circuit and the high-side driving circuit have the same structure and comprise a low-side driving power supply VDD _ L, PMOS tube S1_ L and an NMOS tube S2_ L which are directly powered by a direct-current power supply, wherein the source electrode of the PMOS tube S1_ L is connected with the positive electrode of the low-side driving power supply VDD _ L, the drain electrode of the PMOS tube S1_ L is connected with the drain electrode of the NMOS tube S2_ L and serves as the output end of the low-side driving circuit, the source electrode of the NMOS tube S2_ L is connected with the negative electrode of the low-side driving power supply VDD _ L and is connected with the ground GND, the grid electrodes of the PMOS tube S1-L and the NMOS tube S2-L are respectively connected with low-side driving signals, and the low-side driving signals are accessed in a push-pull mode.

4. The high immunity circuit for GaN power tube half-bridge driving of claim 3, wherein the PMOS tube S1-H and the NMOS tube S2-H in the high side driving circuit and the PMOS tube S1-L and the NMOS tube S2-L in the low side driving circuit are both low voltage tubes.