CN114860495B - Signal monitoring method, system, equipment and storage medium - Google Patents
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- 238000004590 computer program Methods 0.000 claims description 7
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
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- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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Abstract
The invention provides a method, a system, equipment and a storage medium for monitoring signals, wherein the method comprises the following steps: setting a register in the processor for storing the exception signal and setting a data read address pointer and a data write address pointer; setting a timer in a processor, and in response to detecting an abnormal signal, reading a count value of the timer and storing the count value into the register; storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and responding to the communication interval time between the processor and the BMC exceeding a threshold value, and taking the time for triggering interruption as the occurrence time of the abnormal data received next time. The invention adopts CPLD and BMC bidirectional timing mechanism to record the triggering time of the abnormal signal, so that the subsequent maintainer can position the cause of the abnormality according to the occurrence time of the abnormality.
Description
Technical Field
The present invention relates to the field of servers, and more particularly, to a method, system, device, and storage medium for signal monitoring.
Background
In the server, the motherboard CPLD (Complex Programmable Logic Device ) is mainly used for realizing the power-on and power-off timing control and signal monitoring functions of the board card. During the operation of the server, the server is abnormally powered down due to circuit problems or improper operation and the like. In the subsequent maintenance, the power failure reason needs to be analyzed according to the abnormal power failure point, so that the CPLD is required to record the states of all time sequence signals and alarm signals at the power failure moment.
The prior art method mainly comprises the steps that a CPLD monitors a time sequence signal and an alarm signal in real time, when abnormal power failure or alarm occurs, the state of a current signal is latched into a CPLD register, and then a BMC (Baseboard Management Controller, a baseboard management controller) is triggered by a GPIO (General Purpose Input Output, a general purpose input output interface) to interrupt the signal, so that the BMC is informed to receive data. The BMC reads the data transmitted by the CPLD and records the current time. After the BMC reads successfully, the CPLD is informed to empty the data of the current register. After the data is cleared, the CPLD continues to monitor the signal state. However, the prior art method cannot detect two abnormal signals with shorter intervals at the same time. Because the register storing the signal state is in a latch state in the abnormal data transmission process, if the abnormality occurs again, the signal state cannot be recorded, and abnormal data is lost.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, a system, a computer device and a computer readable storage medium for monitoring signals, in which a CPLD and a BMC bidirectional timing mechanism are used to record the time triggered by an abnormal signal, so that a subsequent maintainer can locate the cause of the abnormality according to the time when the abnormality occurs, and the problem of abnormal signal loss caused by communication delay between the CPLD and the BMC can be avoided.
Based on the above object, an aspect of the embodiments of the present invention provides a signal monitoring method, including the following steps: setting a register in the processor for storing the exception signal and setting a data read address pointer and a data write address pointer; setting a timer in a processor, and in response to detecting an abnormal signal, reading a count value of the timer and storing the count value into the register; storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and responding to the communication interval time between the processor and the BMC exceeding a threshold value, and taking the time for triggering interruption as the occurrence time of the abnormal data received next time.
In some embodiments, the method further comprises: and the BMC reads the current data according to the position of the data reading address pointer, and in response to the completion of BMC reading, clears the current data of the register, and moves the data reading address pointer to a first direction.
In some embodiments, the setting a register in the processor for storing the exception signal includes: and connecting the starting point and the ending point of the register.
In some embodiments, the setting a register in the processor for storing the exception signal includes: the second data read pointer is set to indicate a start or end point of the register to avoid overwriting previously stored data when stored.
In some implementations, moving the data write address pointer in a first direction includes: in response to the data write address pointer moving to a register maximum capacity address, returning to an initial position of the register.
In some embodiments, the setting the data read address pointer and the data write address pointer includes: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
In some embodiments, the method further comprises: and in response to the register not being empty, triggering the BMC to interrupt and inform the BMC of receiving the abnormal signal state.
In another aspect of an embodiment of the present invention, there is provided a system for signal monitoring, including: the application module is configured to set a register in the processor for storing the abnormal signal and set a data reading address pointer and a data writing address pointer; a reading module configured to set a timer in a processor, read a count value of the timer in response to detecting an abnormal signal, and store the count value in the register; a storage module configured to store a state of the abnormal signal to a data write address and move the data write address pointer in a first direction; and the time module is configured to respond to the fact that the communication interval time between the processor and the BMC exceeds a threshold value, and take the time of triggering interruption as the time of occurrence of the abnormal data received next time.
In yet another aspect of the embodiment of the present invention, there is also provided a computer apparatus, including: at least one processor; and a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method as above.
In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has the following beneficial technical effects: the CPLD and BMC bidirectional timing mechanism is adopted to record the triggering time of the abnormal signal, so that the reason of the abnormality is conveniently positioned by subsequent maintenance personnel according to the time of occurrence of the abnormality, the problem of abnormal signal loss caused by communication delay of the CPLD and the BMC can be avoided, meanwhile, the annular register is used to improve the space reuse rate of the register, and compared with the rectangular space storage data form, the data has only two states of reading and writing, and the consumption and the risk caused by data movement are avoided.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a signal monitoring method according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of a system for signal monitoring provided by the present invention;
FIG. 3 is a schematic hardware architecture diagram of an embodiment of a computer device for signal monitoring according to the present invention;
Fig. 4 is a schematic diagram of an embodiment of a computer storage medium for signal monitoring provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
In a first aspect of the embodiments of the present invention, an embodiment of a method for signal monitoring is provided. Fig. 1 is a schematic diagram of an embodiment of a signal monitoring method provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
S1, setting a register in a processor for storing an abnormal signal, and setting a data reading address pointer and a data writing address pointer;
s2, setting a timer in a processor, and responding to the detection of an abnormal signal, reading the count value of the timer and storing the count value into the register;
s3, storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and
And S4, responding to the fact that the communication interval time between the processor and the BMC exceeds a threshold value, and taking the time for triggering interruption as the occurrence time of the abnormal data received next time.
A register is provided in the processor for storing the exception signal and for setting a data read address pointer and a data write address pointer. Processors include, but are not limited to, CPLDs and FPGAs (Field-Programmable gate arrays).
In some embodiments, the setting a register in the processor for storing the exception signal includes: and connecting the starting point and the ending point of the register. The embodiment of the invention can apply a register in the CPLD for storing the abnormal signal.
In some embodiments, the setting the data read address pointer and the data write address pointer includes: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
And applying a block of register in the CPLD for storing an abnormal signal, setting two pointers for indicating a data reading address and a data writing address, wherein the two pointers are positioned at the same position when the program starts. In order to save space occupied by the register, the register is set as a ring register, i.e. the beginning and end of the register are connected.
In some embodiments, the setting a register in the processor for storing the exception signal includes: the second data read pointer is set to indicate a start or end point of the register to avoid overwriting previously stored data when stored.
The registers are physically present in a long strip with "head-to-tail" presence. In order to realize a ring structure of register usage meaning, this can be realized by setting a data write pointer, i.e. returning to the register initial position when the pointer moves to the register maximum capacity address. According to the form of pointer cyclic movement, the register ring storage function is realized. At the same time, a data reading pointer is required to be additionally arranged to indicate the bottom of the ring register, so that the pointer is prevented from overlapping the previously stored data during ring storage.
A timer is set in the processor, and a count value of the timer is read and stored in the register in response to detection of the abnormality signal. Storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction.
When an abnormal signal is detected, the state of the monitor signal is stored to the data writing address while the pointer of the data writing address moves upward. And a storage location for indicating a next abnormal signal.
In some embodiments, the method further comprises: and in response to the register not being empty, triggering the BMC to interrupt and inform the BMC of receiving the abnormal signal state. When the register storing the abnormal signal is not empty, triggering the BMC to interrupt and inform the BMC of receiving the abnormal signal state.
In some implementations, moving the data write address pointer in a first direction includes: in response to the data write address pointer moving to a register maximum capacity address, returning to an initial position of the register. When the pointer moves to the register maximum capacity address, it returns to the register initial position.
In some embodiments, the method further comprises: and the BMC reads the current data according to the position of the data reading address pointer, and in response to the completion of BMC reading, clears the current data of the register, and moves the data reading address pointer to a first direction.
And reading the current data according to the position of the data reading pointer. And after the BMC successfully reads, the CPLD is informed to empty the data in the current register. After the data is successfully cleared, the data reading pointer moves upwards. For indicating the storage location of the next data to be read.
And in response to the communication interval time between the processor and the BMC exceeds a threshold value, taking the time for triggering interruption as the occurrence time of the next received abnormal data.
A timer is arranged in the CPLD, when the monitoring signal is abnormal, the count value of the counter is read, and the count value and the signal state of the abnormal signal are stored in an abnormal signal register. When the timing clock of the timer is set to 1MHz, the clock can be accurate to the us level. Meanwhile, in order to reduce deviation of the timer caused by the precision problem of the CPLD internal clock, a data transmission timeout mechanism is arranged in the BMC. When the BMC and the CPLD do not communicate in a period of time, the abnormal signal received next time and the abnormal signal received this time are not considered to happen continuously in a short time, so the time for triggering interruption can be used as the time for the occurrence of the abnormality for the data received next time.
According to the embodiment of the invention, a CPLD and BMC bidirectional timing mechanism is adopted, the triggering time of an abnormal signal is recorded, the reason of the abnormality is conveniently positioned by subsequent maintenance personnel according to the time of occurrence of the abnormality, the problem of abnormal signal loss caused by communication delay of the CPLD and the BMC can be avoided, meanwhile, the repeated utilization rate of a register space can be improved by using a ring register, and compared with a rectangular space storage data form, the data has only two states of reading and writing, and the consumption and the risk caused by data movement are avoided.
It should be noted that, in the embodiments of the signal monitoring method, the steps may be intersected, replaced, added and subtracted, so that the method of signal monitoring by these reasonable permutation and combination changes should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.
Based on the above object, a second aspect of the embodiments of the present invention proposes a system for signal monitoring. As shown in fig. 2, the system 200 includes the following modules: the application module is configured to set a register in the processor for storing the abnormal signal and set a data reading address pointer and a data writing address pointer; a reading module configured to set a timer in a processor, read a count value of the timer in response to detecting an abnormal signal, and store the count value in the register; a storage module configured to store a state of the abnormal signal to a data write address and move the data write address pointer in a first direction; and the time module is configured to respond to the fact that the communication interval time between the processor and the BMC exceeds a threshold value, and take the time of triggering interruption as the time of occurrence of the abnormal data received next time.
In some embodiments, the system further comprises a purge module configured to: and reading the current data according to the position of the data reading address pointer, and in response to the completion of reading, clearing the current data of the register and moving the data reading address pointer to a first direction.
In some embodiments, the application module is configured to: and connecting the starting point and the ending point of the register.
In some embodiments, the application module is configured to: the second data read pointer is set to indicate a start or end point of the register to avoid overwriting previously stored data when stored.
In some embodiments, the storage module is configured to: in response to the data write address pointer moving to a register maximum capacity address, returning to an initial position of the register.
In some embodiments, the application module is configured to: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
In some embodiments, the system further comprises: and in response to the register not being empty, triggering the BMC to interrupt and inform the BMC of receiving the abnormal signal state.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, setting an application register in a processor for storing an abnormal signal, and setting a data reading address pointer and a data writing address pointer; s2, setting a timer in a processor, and responding to the detection of an abnormal signal, reading the count value of the timer and storing the count value into the register; s3, storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and S4, responding to the fact that the communication interval time between the processor and the BMC exceeds a threshold value, and taking the time of triggering interruption as the occurrence time of the abnormal data received next time.
In some embodiments, the steps further comprise: and reading the current data according to the position of the data reading address pointer, and in response to the completion of reading, clearing the current data of the register and moving the data reading address pointer to a first direction.
In some embodiments, the setting a register in the processor for storing the exception signal includes: and connecting the starting point and the ending point of the register.
In some embodiments, the setting a register in the processor for storing the exception signal includes: the second data read pointer is set to indicate a start or end point of the register to avoid overwriting previously stored data when stored.
In some implementations, moving the data write address pointer in a first direction includes: in response to the data write address pointer moving to a register maximum capacity address, returning to an initial position of the register.
In some embodiments, the setting the data read address pointer and the data write address pointer includes: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
In some embodiments, the steps further comprise: and in response to the register not being empty, triggering the BMC to interrupt and inform the BMC of receiving the abnormal signal state.
Fig. 3 is a schematic hardware structure of an embodiment of the signal monitoring computer device according to the present invention.
Taking the example of the device shown in fig. 3, a processor 301 and a memory 302 are included in the device.
The processor 301 and the memory 302 may be connected by a bus or otherwise, for example in fig. 3.
The memory 302 is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions/modules corresponding to the method of signal monitoring in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., a method of implementing signal monitoring, by running non-volatile software programs, instructions and modules stored in the memory 302.
Memory 302 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the method of signal monitoring, etc. In addition, memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory located remotely from processor 301, which may be connected to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Computer instructions 303 corresponding to one or more methods of signal monitoring are stored in memory 302 that, when executed by processor 301, perform the methods of signal monitoring in any of the method embodiments described above.
Any one embodiment of a computer device that performs the above-described method of signal monitoring may achieve the same or similar effects as any of the previously-described method embodiments corresponding thereto.
The invention also provides a computer readable storage medium storing a computer program which when executed by a processor performs a method of signal monitoring.
Fig. 4 is a schematic diagram of an embodiment of the above signal monitoring computer storage medium according to the present invention. Taking a computer storage medium as shown in fig. 4 as an example, the computer readable storage medium 401 stores a computer program 402 that when executed by a processor performs the above method.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the embodiments described above may be implemented by a computer program to instruct related hardware, and the program of the method for signal monitoring may be stored in a computer readable storage medium, where the program may include processes in the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (7)
1. A method of signal monitoring comprising the steps of:
Setting a register in the processor for storing the exception signal and setting a data read address pointer and a data write address pointer;
setting a timer in a processor, and in response to detecting an abnormal signal, reading a count value of the timer and storing the count value into the register;
Storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and
Responding to the communication interval time between the processor and the BMC exceeding a threshold value, and taking the time of triggering interruption as the occurrence time of the abnormal data received next time;
The method further comprises the steps of:
The BMC reads current data according to the position of the data reading address pointer, and in response to the completion of BMC reading, clears the current data of the register, and moves the data reading address pointer to a first direction;
the setting a register in the processor for storing an exception signal includes:
connecting a starting point and an ending point of the register;
said moving the data write address pointer in a first direction comprises:
In response to the data write address pointer moving to a register maximum capacity address, returning to an initial position of the register.
2. The method of claim 1, wherein setting a register in the processor for storing exception signals comprises:
The data read pointer is set to indicate the start or end point of the register to avoid overwriting previously stored data when stored.
3. The method of claim 1, wherein the setting the data read address pointer and the data write address pointer comprises:
And keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
4. The method according to claim 1, wherein the method further comprises:
and in response to the register not being empty, triggering the BMC to interrupt and inform the BMC of receiving the abnormal signal state.
5. A system for signal monitoring, comprising:
The application module is configured to set a register in the processor for storing the abnormal signal and set a data reading address pointer and a data writing address pointer;
a reading module configured to set a timer in a processor, read a count value of the timer in response to detecting an abnormal signal, and store the count value in the register;
A storage module configured to store a state of the abnormal signal to a data write address and move the data write address pointer in a first direction; and
The time module is configured to respond to the fact that the communication interval time between the processor and the BMC exceeds a threshold value, and the time of triggering interruption is used as the occurrence time of the abnormal data received next time;
the system further comprises means for performing the steps of:
The BMC reads current data according to the position of the data reading address pointer, and in response to the completion of BMC reading, clears the current data of the register, and moves the data reading address pointer to a first direction;
The application module is further configured to: connecting a starting point and an ending point of the register;
the memory module is further configured to: in response to the data write address pointer moving to a register maximum capacity address, returning to an initial position of the register.
6. A computer device, comprising:
At least one processor; and
A memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-4.
7. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any of claims 1-4.
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| WO2017054487A1 (en) * | 2015-09-30 | 2017-04-06 | 中兴通讯股份有限公司 | Power-down protection method and apparatus, and electronic device |
| CN111090545A (en) * | 2019-11-28 | 2020-05-01 | 苏州浪潮智能科技有限公司 | Method, device and medium for recovering failed CPLD |
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