CN114846473A - 数据处理电路、数据处理方法及电子设备 - Google Patents

数据处理电路、数据处理方法及电子设备 Download PDF

Info

Publication number
CN114846473A
CN114846473A CN202080002478.1A CN202080002478A CN114846473A CN 114846473 A CN114846473 A CN 114846473A CN 202080002478 A CN202080002478 A CN 202080002478A CN 114846473 A CN114846473 A CN 114846473A
Authority
CN
China
Prior art keywords
processing
circuit
sequence
data
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080002478.1A
Other languages
English (en)
Inventor
魏祥野
修黎明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of CN114846473A publication Critical patent/CN114846473A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134Register stacks; shift registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Image Processing (AREA)
  • Storage Device Security (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

一种数据处理电路、数据处理方法及电子设备,数据处理电路包括第一数据处理子电路(101)和第二数据处理子电路(102),第一数据处理子电路(101)的输出端与第二数据处理子电路(102)的输入端相连接。第一数据处理子电路(101)被配置为接收原始序列生成第一处理序列,其中,第一处理序列中任一第一处理数由原始数据中的至少两个原始数据计算得到;第二数据处理子电路(102)被配置为接收第一处理序列生成第二处理序列,其中,第二处理序列中的第n个第二处理数由第n个第一处理数以及第n‑1个第二处理数计算得到;n≥2且n为正整数。通过数据处理电路增强了原始序列的随机性和复杂度。

Description

PCT国内申请,说明书已公开。

Claims (13)

  1. PCT国内申请,权利要求书已公开。
CN202080002478.1A 2020-10-27 2020-10-27 数据处理电路、数据处理方法及电子设备 Pending CN114846473A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/124032 WO2022087829A1 (zh) 2020-10-27 2020-10-27 数据处理电路、数据处理方法及电子设备

Publications (1)

Publication Number Publication Date
CN114846473A true CN114846473A (zh) 2022-08-02

Family

ID=81383449

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080002478.1A Pending CN114846473A (zh) 2020-10-27 2020-10-27 数据处理电路、数据处理方法及电子设备

Country Status (3)

Country Link
US (1) US11789897B2 (zh)
CN (1) CN114846473A (zh)
WO (1) WO2022087829A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114978104A (zh) * 2021-02-18 2022-08-30 北京京东方光电科技有限公司 数据互斥滤波电路及数据互斥滤波方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736673A (ja) * 1993-07-20 1995-02-07 Canon Inc 乱数発生器、及びそれを用いた通信システム及びその方法
JPH0990870A (ja) * 1995-09-27 1997-04-04 Nec Corp 基本変換方法、暗号化方法、基本変換回路および暗号装置
US20050204220A1 (en) * 2004-03-02 2005-09-15 Shinichi Yasuda Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device
CN1858722A (zh) * 2006-03-31 2006-11-08 清华大学 用异步电路提高sram工艺fpga设计安全的系统
CN101097245A (zh) * 2006-06-29 2008-01-02 国际商业机器公司 实现高速测试电路的扫描链和方法
CN103839577A (zh) * 2012-11-26 2014-06-04 英飞凌科技股份有限公司 存储电路
CN105354008A (zh) * 2015-12-14 2016-02-24 武汉芯昌科技有限公司 一种随机数生成器的输出电路及输出方法
CN107220545A (zh) * 2017-05-31 2017-09-29 郑州云海信息技术有限公司 一种硬件加密系统、方法及服务器
CN109522605A (zh) * 2018-10-21 2019-03-26 天津大学 基于aes加密电路的功耗泄露型硬件木马
CN109766729A (zh) * 2018-12-12 2019-05-17 西安电子科技大学 一种防御硬件木马的集成电路及其加密方法
CN109885960A (zh) * 2019-03-05 2019-06-14 中国人民解放军32082部队 一种基于电磁旁路分析的嵌入式芯片硬件木马设计方法
US20200241841A1 (en) * 2019-01-24 2020-07-30 Fujitsu Limited Random number generating circuit and semiconductor apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6163563A (en) * 1996-12-31 2000-12-19 Lucent Technologies Inc. Digital communication system for high-speed complex correlation
JP3474794B2 (ja) * 1999-02-03 2003-12-08 日本電信電話株式会社 符号変換回路及び符号変換多重化回路
US7689133B2 (en) * 2005-02-28 2010-03-30 Fujitsu Limited Optical signal reception device and method of controlling optical signal reception
JP5485736B2 (ja) * 2009-02-10 2014-05-07 パナソニック株式会社 送信装置
US9615342B2 (en) * 2015-01-27 2017-04-04 Telefonaktiebolaget Lm Ericsson (Publ) Method of detecting cell identity and frame number information
JP6542171B2 (ja) 2016-09-15 2019-07-10 東芝メモリ株式会社 ランダマイザおよび半導体記憶装置
US10727994B2 (en) * 2017-01-09 2020-07-28 Qualcomm Incorporated Using sequences of pilot repetitions for receiver adaptation
CN109426738B (zh) 2017-08-23 2021-11-12 中芯国际集成电路制造(上海)有限公司 一种硬件加密器及加密方法、电子装置
KR102653018B1 (ko) 2019-01-16 2024-03-29 삼성전자주식회사 랜덤 넘버를 이용하여 나머지 연산을 수행하는 보안 프로세서 및 이의 동작 방법

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736673A (ja) * 1993-07-20 1995-02-07 Canon Inc 乱数発生器、及びそれを用いた通信システム及びその方法
JPH0990870A (ja) * 1995-09-27 1997-04-04 Nec Corp 基本変換方法、暗号化方法、基本変換回路および暗号装置
US20050204220A1 (en) * 2004-03-02 2005-09-15 Shinichi Yasuda Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device
CN1858722A (zh) * 2006-03-31 2006-11-08 清华大学 用异步电路提高sram工艺fpga设计安全的系统
CN101097245A (zh) * 2006-06-29 2008-01-02 国际商业机器公司 实现高速测试电路的扫描链和方法
CN103839577A (zh) * 2012-11-26 2014-06-04 英飞凌科技股份有限公司 存储电路
CN105354008A (zh) * 2015-12-14 2016-02-24 武汉芯昌科技有限公司 一种随机数生成器的输出电路及输出方法
CN107220545A (zh) * 2017-05-31 2017-09-29 郑州云海信息技术有限公司 一种硬件加密系统、方法及服务器
CN109522605A (zh) * 2018-10-21 2019-03-26 天津大学 基于aes加密电路的功耗泄露型硬件木马
CN109766729A (zh) * 2018-12-12 2019-05-17 西安电子科技大学 一种防御硬件木马的集成电路及其加密方法
US20200241841A1 (en) * 2019-01-24 2020-07-30 Fujitsu Limited Random number generating circuit and semiconductor apparatus
CN109885960A (zh) * 2019-03-05 2019-06-14 中国人民解放军32082部队 一种基于电磁旁路分析的嵌入式芯片硬件木马设计方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
RYZEN3: "HDLBits-Circuits 学 习 小 结 ( 四 )D 触 发 器 (latches and flip-flops)", pages 1 - 9, Retrieved from the Internet <URL:https://blog.csdn.net/Adidas112233/article/details/108874866> *

Also Published As

Publication number Publication date
WO2022087829A1 (zh) 2022-05-05
US11789897B2 (en) 2023-10-17
US20220318185A1 (en) 2022-10-06

Similar Documents

Publication Publication Date Title
US8379848B2 (en) Method of providing a portable true random number generator based on the microstructure and noise found in digital images
US20130147511A1 (en) Offline Device Authentication and Anti-Counterfeiting Using Physically Unclonable Functions
US10171229B2 (en) Pseudo-random bit generator based on multim-modal maps
JP3696209B2 (ja) シード生成回路、乱数生成回路、半導体集積回路、icカード及び情報端末機器
KR101566408B1 (ko) 불 마스크와 산술 마스크의 변환 회로 및 변환 방법
CN109614790B (zh) 基于反馈环puf的轻量级认证设备及认证方法
Hu et al. A true random number generator based on mouse movement and chaotic cryptography
US20200044872A1 (en) Apparatus and method for generating physically unclonable functions
US11487505B2 (en) Physical unclonable function based true random number generator, method for generating true random numbers, and associated electronic device
Rajagopalan et al. Networked hardware assisted key image and chaotic attractors for secure RGB image communication
CN114846473A (zh) 数据处理电路、数据处理方法及电子设备
Chen et al. Image encryption using progressive cellular automata substitution and SCAN
Mukherjee et al. Novel hardware trojan attack on activation parameters of FPGA-based DNN accelerators
CN114095182B (zh) 一种基于强puf的动态响应和安全认证方法、系统
CN108021815B (zh) 图像加密方法、装置及电子设备
Ghosh et al. FPGA based implementation of embedding and decoding architecture for binary watermark by spread spectrum scheme in spatial domain
CN113268745B (zh) 基于Camellia加密算法的软PUF
Jeyaram et al. New cellular automata‐based image cryptosystem and a novel non‐parametric pixel randomness test
US20210224041A1 (en) Random number generator, random number generating circuit, and random number generating method
CN114499465A (zh) 散列算法及电路、电子设备
TW202133056A (zh) 基於量子運算的真亂數產生方法
EP4060932B1 (en) Encoding variables using a physical unclonable function module
Patel et al. Design of efficient low power strong PUF for security applications
Chen et al. Architecture design and VLSI hardware implementation of image encryption/decryption system using re-configurable 2D Von Neumann cellular automata
Nalini et al. Encryption on multimodal biometric using hyper chaotic method and inherent binding technique

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination