CN114830326A - 包括双面管芯间接合连接的堆叠式管芯组件及其形成方法 - Google Patents
包括双面管芯间接合连接的堆叠式管芯组件及其形成方法 Download PDFInfo
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- CN114830326A CN114830326A CN202080081821.6A CN202080081821A CN114830326A CN 114830326 A CN114830326 A CN 114830326A CN 202080081821 A CN202080081821 A CN 202080081821A CN 114830326 A CN114830326 A CN 114830326A
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Abstract
提供了多个接合单元,该多个接合单元中的每个接合单元包括相应的正面管芯和背面管芯。每个接合单元中的两个管芯可为存储器管芯和被配置为控制该存储器管芯中的存储器元件的操作的逻辑管芯。替代地,该两个管芯可为存储器管芯。可附接该多个接合单元,使得正面外部接合衬垫具有面朝上的物理暴露表面且每个接合单元的背面外部接合衬垫具有面朝下的物理暴露表面。第一接合引线集合可连接一对相应的正面外部接合衬垫且第二接合引线集合可连接一对相应的背面外部接合衬垫。
Description
相关申请
本申请要求2020年5月28日提交的美国非临时专利申请第16/886,164号和2020年5月28日提交的美国非临时专利申请第16/886,221号的优先权益,这些专利申请的全部内容据此出于所有目的以引用的方式并入本文中。
技术领域
本公开大体上涉及半导体器件领域,且具体地涉及包括双面管芯间接合连接的堆叠式管芯组件及其形成方法。
背景技术
多个半导体管芯可堆叠在一起以形成堆叠式管芯组件。可通过堆叠式管芯组件中的半导体管芯中的每个半导体管芯传输功率信号。然而,功率信号承载高电压,并且将功率信号路由到包括噪声敏感器件(诸如感测放大器)的逻辑电路附近可增加逻辑电路中的噪声水平。另外,随着堆叠式管芯组件中的半导体管芯的数量的增加,管芯间电连接的数量增加。
发明内容
根据本公开的方面,提供一种包括堆叠式管芯组件的结构。所述堆叠式管芯组件包含:多个接合单元的竖直堆叠,其中每个接合单元包含:存储器管芯,所述存储器管芯包括位于所述存储器管芯的相对主表面上的存储器侧管芯间接合衬垫和存储器侧外部接合衬垫;和逻辑管芯,所述逻辑管芯包括逻辑电路,所述逻辑电路被配置为控制所述存储器管芯的操作并且包括位于所述逻辑管芯的相对主表面上的逻辑侧管芯间接合衬垫和逻辑侧外部接合衬垫,其中:所述逻辑侧管芯间接合衬垫接合到所述存储器侧管芯间接合衬垫中的相应存储器侧管芯间接合衬垫;并且其中所述存储器侧外部接合衬垫和所述逻辑侧外部接合衬垫包含面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,所述面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,所述面朝下的外部接合衬垫集合具有面朝下的物理暴露表面;第一接合引线集合,所述第一接合引线集合连接面朝上的外部接合衬垫;和第二接合引线集合,所述第二接合引线集合连接面朝下的外部接合衬垫。
根据本公开的另一方面,提供一种形成包括堆叠式管芯组件的结构的方法。所述方法包括:提供多个接合单元,其中每个接合单元包含存储器管芯并且包含逻辑管芯,所述存储器管芯包括位于所述存储器管芯的相对主表面上的存储器侧管芯间接合衬垫和存储器侧外部接合衬垫,所述逻辑管芯包括逻辑电路,所述逻辑电路被配置为控制所述存储器管芯的操作并且包括位于所述逻辑管芯的相对主表面上的逻辑侧管芯间接合衬垫和逻辑侧外部接合衬垫;通过将所述多个接合单元彼此附接来形成所述多个接合单元的竖直堆叠,使得所述多个接合单元的所述存储器侧外部接合衬垫和所述逻辑侧外部接合衬垫形成面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,所述面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,所述面朝下的外部接合衬垫集合具有面朝下的物理暴露表面;形成第一接合引线集合,所述第一接合引线集合连接所述面朝上的外部接合衬垫集合中的一对相应的面朝上的外部接合衬垫;以及形成第二接合引线集合,所述第二接合引线集合连接所述面朝下的外部接合衬垫集合中的一对相应的面朝下的外部接合衬垫。
根据本公开的又一方面,提供一种包括堆叠式管芯组件的结构。所述堆叠式管芯组件包含:多个接合单元的竖直堆叠,其中每个接合单元包含相应正面半导体管芯和相应背面半导体管芯,所述相应正面半导体管芯包括正面外部接合衬垫,所述相应背面半导体管芯包括背面外部接合衬垫,其中所述相应背面半导体管芯接合到所述相应正面半导体管芯,并且其中每个接合单元的所述正面外部接合衬垫具有面朝上的物理暴露表面,并且每个接合单元的所述背面外部接合衬垫具有面朝下的物理暴露表面;第一接合引线集合,所述第一接合引线集合连接所述正面外部接合衬垫;和第二接合引线集合,所述第二接合引线集合连接所述背面外部接合衬垫。
根据本公开的再一方面,提供一种形成包括堆叠式管芯组件的结构的方法。所述方法包括:提供多个接合单元,其中每个接合单元包含相应正面半导体管芯和相应背面半导体管芯,所述相应正面半导体管芯包括正面外部接合衬垫,所述相应背面半导体管芯包括背面外部接合衬垫,其中所述背面半导体管芯接合到所述相应正面半导体管芯;通过将所述多个接合单元彼此附接来形成所述多个接合单元的竖直堆叠,使得每个接合单元的所述正面外部接合衬垫具有面朝上的物理暴露表面,并且每个接合单元的所述背面外部接合衬垫具有面朝下的物理暴露表面;形成连接一对相应的正面外部接合衬垫的第一接合引线集合;以及形成连接一对相应的背面外部接合衬垫的第二接合引线集合。
附图说明
图1A是根据本公开的第一实施方案的在形成存储器侧管芯间接合衬垫之后的存储器管芯的示意性竖直剖面图。
图1B是图1A的存储器管芯的布局。
图2A是根据本公开的第一实施方案的在形成逻辑侧管芯间接合衬垫之后的逻辑管芯的示意性竖直剖面图。
图2B是图2A的存储器管芯的布局。
图3是图1A的存储器管芯和图2A的逻辑管芯的接合组件的竖直剖面图。
图4是根据本公开的第一实施方案的在形成存储器侧外部接合衬垫之后的存储器管芯和逻辑管芯的接合组件的竖直剖面图。
图5A是根据本公开的第一实施方案的在形成逻辑侧外部接合衬垫之后的半导体管芯和逻辑管芯的接合单元的区的竖直剖面图。
图5B是图5A的接合单元的平面图。
图6是根据本公开的第一实施方案的图5A和图5B的接合单元的竖直剖面图。
图7是根据本公开的第一实施方案的在附接接合引线之后的包括多个接合单元的竖直堆叠和安装衬底的第一示例性结构的竖直剖面图。
图8A是根据本公开的第二实施方案的在附接处理衬底之后的存储器管芯的竖直剖面图。
图8B是图8A的存储器管芯的平面图。
图9A是根据本公开的第二实施方案的包括正面半导体管芯和背面半导体管芯的接合单元的竖直剖面图。
图9B是图9A的接合单元的部分透视俯视图。
图9C是图9A的接合单元的部分透视倒置图。
图10是根据本公开的第二实施方案的在附接接合引线之后的包括多个接合单元的竖直堆叠和安装衬底的第二示例性结构的竖直剖面图。
具体实施方式
本公开涉及一种包括双面管芯间接合连接的堆叠式管芯组件及其形成方法,其各个方面在下文中进行了详细描述。因此,包括多个管芯的堆叠式管芯组件容纳管芯间电连接,而不占据由半导体器件使用的附加晶圆空间,同时使噪声和信号干扰以及寄生耦合最小化。
附图未按比例绘制。在其中示出元件的单个实例的情况下可以重复元件的多个实例,除非明确地描述或以其他方式清楚地指出不存在元件的重复。序号诸如“第一”、“第二”和“第三”仅仅被用于标识类似的元件,并且在本公开的整个说明书和权利要求书中可采用不同序号。术语“至少一个”元件是指包括单个元件的可能性和多个元件的可能性的所有可能性。
如本文所用,“层”是指包括具有厚度的区的材料部分。层可在下层或上覆结构的整体上方延伸,或者可具有小于下层或上覆结构的范围的范围。另外,层可以是均匀或不均匀的连续结构的厚度小于连续结构的厚度的区。例如,层可以定位在连续结构的顶部表面和底部表面之间或在连续结构的顶部表面和底部表面处的任何一对水平平面之间。层可水平地、竖直地和/或沿着锥形表面延伸。衬底可以是层,可以在其中包括一个或多个层,或者可以在其上、在其上方和/或在其下方具有一个或多个层。
如本文所用,如果第二表面在第一表面上面或下面并且如果存在包括第一表面和第二表面的竖直平面或基本上竖直的平面,则第一表面和第二表面彼此“竖直地重合”。基本上竖直的平面是沿偏离竖直方向小于5度的角度的方向直线延伸的平面。竖直平面或基本上竖直的平面沿竖直方向或基本上竖直的方向为直的,并且可包括或可不包括沿垂直于竖直方向或基本上竖直的方向的方向的曲率。
如本文所用,“存储器层级”或“存储器阵列层级”是指对应于包括存储器元件阵列的最顶部表面的第一水平平面(即,平行于衬底的顶表面的平面)与包括存储器元件阵列的最底部表面的第二水平平面之间的一般区的层级。如本文所用,“穿通堆叠”元件是指竖直地延伸穿过存储器层级的元件。
如本文所用,“半导体材料”是指具有在1.0×10-5S/m至1.0×105S/m的范围内的电导率的材料。如本文所用,“半导体材料”是指在其中不存在电掺杂剂的情况下具有在1.0×10-5S/m至1.0S/m的范围内的电导率的材料,并且能够在适当掺杂电掺杂剂时产生具有在1.0S/m至1.0×105S/m的范围内的电导率的掺杂材料。如本文所用,“电掺杂剂”是指将空穴添加到能带结构内的价带的p型掺杂剂,或者将电子添加到能带结构内的导带的n型掺杂剂。如本文所用,“导电材料”是指具有大于1.0×105S/m的电导率的材料。如本文所用,“绝缘体材料”或“介电材料”是指具有小于1.0×10-5S/m的电导率的材料。如本文所用,“重掺杂半导体材料”是指以足够高的原子浓度掺杂有电掺杂剂以在被形成为晶体材料时或在通过退火工艺来转换成晶体材料(例如,从初始非晶态开始)的情况下变成导电材料(即,具有大于1.0×105S/m的电导率)的半导体材料。“掺杂半导体材料”可为重掺杂半导体材料,或者可为包括呈提供在1.0×10-5S/m至1.0×105S/m的范围内的电导率的浓度的电掺杂剂(即,p型掺杂剂和/或n型掺杂剂)的半导体材料。“本征半导体材料”是指不掺杂有电掺杂物的半导体材料。因此,半导体材料可以是半导体的或导电的,并且可以是本征半导体材料或掺杂半导体材料。掺杂半导体材料可以是半导体的或导电的,这取决于在其中的电掺杂剂的原子浓度。如本文所用,“金属材料”是指其中包括至少一种金属元素的导电材料。所有电导率测量都在标准条件下进行。
单体三维存储器阵列是在单个衬底(诸如半导体晶圆)上方形成多个存储器层级而没有居间衬底的存储器阵列。术语“单体”是指阵列的每一级的层直接沉积在阵列的每个下层级的层上。相反,二维阵列可以单独形成,并且然后封装在一起以形成非单体存储器器件。例如,如标题为“三维结构存储器(Three-dimensional Structure Memory)”的美国专利5,915,167中所述,通过在单独的衬底上形成存储器级和竖直地堆叠存储器级来构造非单体堆叠存储器。可在结合前将衬底减薄或从存储器级移除该衬底,但由于存储器级最初是在单独的衬底上方形成的,所以此类存储器不是真正的单体三维存储器阵列。衬底可包括在其上制造的集成电路,诸如用于存储器器件的驱动器电路。
一般来讲,半导体封装(或“封装”)是指可通过一组引脚或焊球附接到电路板的单元半导体器件。半导体封装可包括一个或多个半导体芯片(或“芯片”),该一个或多个半导体芯片例如通过倒装芯片接合或另一种芯片到芯片接合而贯穿接合。封装或芯片可包括单个半导体管芯(或“管芯”)或多个半导体管芯。管芯是可独立地执行外部命令或报告状态的最小单元。通常,具有多个管芯的封装或芯片能够同时执行与其中平面的总数一样多的外部命令。每个管芯包括一个或多个平面。可在同一管芯内的每个平面中执行相同的并发操作,但可能存在一些限制。在管芯是存储器管芯(即,包括存储器元件的管芯)的情况下,可在同一存储器管芯内的每个平面中执行并发读取操作、并发写入操作或并发擦除操作。在存储器管芯中,每个平面包含多个存储块(或“块”),这些存储块是可通过单个擦除操作擦除的最小单元。每个存储块包含多个页面,这些页面是可被选择用于编程的最小单元。页面也是可被选择用于读取操作的最小单元。
参考图1A和图1B,示出了根据本公开的第一实施方案的存储器管芯900。存储器管芯900包括存储器管芯衬底908。存储器管芯900还包括覆盖存储器管芯衬底908上面的存储器管芯半导体器件920、覆盖在存储器管芯半导体器件920上面的存储器管芯介电材料层960和嵌入存储器管芯介电材料层960中的存储器管芯金属互连结构980。在一个实施方案中,存储器管芯衬底908可为厚度在500微米至1mm的范围内的可商购获得的硅晶圆。存储器管芯900可设置于包括存储器管芯900的二维阵列的晶圆中。
一般来讲,存储器管芯半导体器件920可包含本领域中已知的任何半导体存储器器件。在一个实施方案中,存储器管芯900可包括三维存储器阵列,诸如三维NAND存储器阵列。三维存储器器件可包括各种器件区,该器件区包含存储器管芯半导体器件920的各种子集。例如,存储器管芯900可包括多个平面,该多个平面包含相应三维存储器阵列。每个平面可包括存储器阵列区100和至少一个接触区200。
在一个实施方案中,衬底通孔空腔可形成为存储器管芯衬底908的上部部分。每个衬底通孔空腔可填充有介电间隔物914和穿通衬底通孔结构916。每个穿通衬底通孔结构916在随后减薄存储器管芯衬底908后提供竖直导电路径。每个穿通衬底通孔结构916可使用穿通存储器层级通孔结构84电连接到相应存储器侧金属互连结构980。根据本公开的方面,可将存储器管芯900的穿通衬底通孔结构916布置为一行或位于存储器管芯900的边缘中的一个边缘近侧的多行。在一个实施方案中,存储器管芯900可具有直边缘,并且可将存储器管芯900的穿通衬底通孔结构916布置为一行或位于存储器管芯900的直边缘近侧并且以均匀横向偏移距离与直边缘横向间隔开的多行。
在一个实施方案中,存储器管芯半导体器件920可包括绝缘层32和导电层46的竖直交替堆叠和竖直地延伸穿过竖直交替堆叠(32,46)的存储器开口的二维阵列。导电层46可包含三维NAND存储器器件的字线。存储器开口填充结构58可形成在每个存储器开口内。每个存储器开口填充结构58可包括存储器膜和接触该存储器膜的竖直半导体沟道。存储器膜可包括阻挡电介质、隧穿电介质和位于阻挡电介质与隧穿电介质之间的电荷存储材料。电荷存储材料可包含电荷俘获层,诸如氮化硅层;或多个离散电荷俘获区,诸如电荷俘获层的浮栅或离散部分。在这种情况下,每个存储器开口填充结构58和导电层46的邻近部分构成竖直NAND串。替代地,存储器开口填充结构58可包括任何类型的非易失性存储器元件,诸如电阻存储器元件、铁电存储器元件、相变存储器元件等。存储器开口填充结构58可形成在相应存储器阵列区内。可提供多个竖直NAND串。每个竖直NAND串可包括竖直半导体沟道和位于导电层46的层级处的存储器元件(例如存储器膜或浮栅的部分)的竖直堆叠。
可使导电层46图案化以提供每个上覆导电层46具有比任何下层导电层46更小的横向范围的阶梯区。可在每个竖直交替堆叠(32,46)周围形成阶梯式介电材料部分65以提供相邻竖直交替堆叠(32,46)之间的电隔离。阶梯式介电材料部分65可形成在相应竖直交替堆叠(32,46)的阶梯式表面上。层接触通孔结构(例如字线和选择栅极层接触通孔结构)86可形成在阶梯区中的导电层46上以提供与导电层46的电连接。层接触通孔结构86可竖直地延伸穿过相应阶梯式介电材料部分65并且可接触导电层46(例如字线或选择栅极电极)中的相应导电层。
穿通存储器层级通孔结构84可穿过介电材料部分形成于穿通衬底通孔结构916中的相应穿通衬底通孔结构上。存储器管芯介电材料层960和存储器管芯金属互连结构980可形成在存储器管芯半导体器件920和阶梯式介电材料部分65上方。存储器管芯金属互连结构980包括位线982。每个位线982电接触存储器开口填充结构58内的漏极区的相应子集。漏极区可接触竖直半导体沟道60中的相应竖直半导体沟道的顶端。因此,位线982可电连接到多个竖直NAND串的相应子集。存储器管芯金属互连结构980包括互连金属线和互连金属通孔结构。
存储器管芯介电材料层960中的每个存储器管芯介电材料层可包括相应介电材料,诸如未掺杂硅酸盐玻璃、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅、介电金属氧化物或其组合。存储器管芯衬垫层级介电层970可设置于存储器管芯介电材料层960顶部。存储器管芯衬垫层级介电层970可包括随后可接合到随后要提供的逻辑管芯的另一介电接合材料层的介电扩散阻挡层(诸如氮化硅层)或第一介电接合材料层(诸如氧化硅层)。
衬垫空腔可穿过存储器管芯衬垫层级介电层970和存储器管芯介电材料层960的上部部分形成在下层存储器侧金属互连结构980上方。衬垫空腔可填充有至少一种导电材料以形成存储器侧管芯间接合衬垫988。存储器侧管芯间接合衬垫988穿过存储器管芯衬垫层级介电层970和存储器管芯介电材料层960的上部部分形成在衬垫空腔中。如本文所用,“管芯间接合衬垫”是指位于管芯中并且被配置用于通过与位于另一管芯中的另一管芯间接合衬垫直接接触而进行管芯间接合的接合衬垫。
替代地,存储器侧管芯间接合衬垫988首先形成在存储器管芯金属互连结构980上,并且存储器管芯衬垫层级介电层970可形成在存储器侧管芯间接合衬垫988上方和周围。在这种情况下,随后可平坦化存储器管芯衬垫层级介电层970以暴露存储器侧管芯间接合衬垫988的顶表面。
至少一种导电材料可为金属(即,金属或金属合金)材料,该金属材料可通过金属对金属或混合接合而接合到相同金属材料或另一金属材料。例如,存储器侧管芯间接合衬垫988中的每个存储器侧管芯间接合衬垫可包括任选的金属阻挡衬里和金属填充材料部分,该任选的金属阻挡衬里包括TiN、TaN和/或WN,该金属填充材料部分包括金属材料,该金属材料可通过金属对金属接合而接合到相同金属材料或另一金属材料。例如,金属填充材料部分可包括任何材料和/或基本上由任何材料组成,该任何材料选自Cu、包括原子浓度大于70%(其可大于90%和/或95%)的铜的铜合金,或钴或镍合金,诸如CoW、CoWP、CoMoP、NiW和/或NiWP。
存储器侧管芯间接合衬垫988中的每个存储器侧管芯间接合衬垫被存储器管芯衬垫层级介电层970包围,并且接触存储器管芯金属互连结构980中的相应的下层存储器管芯金属互连结构。存储器侧管芯间接合衬垫988中的每个存储器侧管芯间接合衬垫可电连接到存储器管芯半导体器件920的相应节点。嵌入存储器管芯介电材料层960中的存储器管芯金属互连结构980将存储器管芯衬底908上的存储器器件920的相应部件电连接到存储器侧管芯间接合衬垫988中的相应存储器侧管芯间接合衬垫。
参考图2A和图2B,示出了逻辑管芯700。逻辑管芯700包括逻辑管芯衬底708、覆盖在逻辑管芯衬底708上面的逻辑管芯半导体器件720、覆盖在逻辑管芯半导体器件720上面的逻辑管芯介电材料层760和嵌入逻辑管芯介电材料层760中的逻辑管芯金属互连结构780。在一个实施方案中,逻辑管芯半导体器件720可包括至少一个互补金属氧化物半导体(CMOS)电路系统,包括场效应晶体管。在一个实施方案中,逻辑管芯衬底708可为厚度在500微米至1mm的范围内的可商购获得的硅衬底。逻辑管芯700可设置于包括逻辑管芯700的二维阵列的晶圆中。
一般来讲,逻辑管芯半导体器件可包含可与存储器侧半导体管芯900中的存储器侧半导体器件920结合操作以实现其中的存储器器件的操作和/或提供增强的功能性的任何半导体器件。在一个实施方案中,存储器侧半导体管芯900可包括三维存储器器件,该三维存储器器件包括存储器元件的三维阵列、字线(其可包含导电线46的子集)和位线982,逻辑管芯700的逻辑管芯半导体器件720可包括至少一个感测放大器区702、至少一个字线开关区704和至少一个外围器件区706。每个感测放大器区702包括电连接到位线982中的相应位线的感测放大器和位线驱动器。每个位线驱动器可包括一个或多个位线解码器电路,该一个或多个位线解码器电路对位线982和位线联接/连接区的地址进行解码。字线开关区704包括一个或多个字线驱动器电路和一个或多个字线解码器电路,该一个或多个字线驱动器电路驱动存储器侧半导体管芯900的存储器元件的相应三维阵列的字线46,该一个或多个字线解码器电路对字线46的地址进行解码。每个外围器件区706包括可用于操作存储器侧半导体管芯900的三维存储器器件920的电荷泵电路、位线解码器、源电源电路、数据缓冲器和/或锁存器、输入/输出控制电路和/或任何其他半导体电路。
浅沟槽隔离结构712可通过形成浅沟槽并且通过用介电材料(诸如氧化硅)填充浅沟槽而形成在逻辑管芯衬底708的上部部分中。逻辑管芯半导体器件720可包括场效应晶体管、电阻器、二极管、电容器、电感器和/或本领域中已知的任何附加半导体器件。嵌入逻辑管芯金属互连结构780的逻辑管芯介电材料层760可形成在逻辑管芯半导体器件720上方。在一个实施方案中,衬底通孔空腔可形成为存储器管芯衬底908的上部部分。每个衬底通孔空腔可填充有介电间隔物714和穿通衬底通孔结构716。每个穿通衬底通孔结构716在随后减薄逻辑管芯衬底708后提供竖直导电路径。穿通衬底通孔结构716的顶表面可在逻辑管芯衬底708的顶表面上方突出到逻辑管芯介电材料层760中,或可与逻辑管芯衬底708的顶表面共面。每个穿通衬底通孔结构708可电连接到相应逻辑管芯金属互连结构780。根据本公开的方面,可将逻辑管芯700的穿通衬底通孔结构716布置为一行或位于逻辑管芯700的边缘中的一个边缘近侧的多行。在一个实施方案中,逻辑管芯700可具有直边缘,并且可将逻辑管芯700的穿通衬底通孔结构716布置为一行或位于逻辑管芯700的直边缘近侧并且以均匀横向偏移距离与直边缘横向间隔开的多行。
逻辑管芯介电材料层760中的每个逻辑管芯介电材料层可包括相应介电材料,诸如未掺杂硅酸盐玻璃、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅、介电金属氧化物或其组合。逻辑管芯衬垫层级介电层770可设置于逻辑管芯介电材料层760顶部。逻辑管芯衬垫层级介电层770可包括随后可接合到随后要提供的逻辑管芯的另一介电接合材料层的介电扩散阻挡层(诸如氮化硅层)或第一介电接合材料层(诸如氧化硅层)。
衬垫空腔可穿过逻辑管芯衬垫层级介电层770和逻辑管芯介电材料层760的上部部分形成在下层逻辑管芯金属互连结构780上方。衬垫空腔可填充有至少一种导电材料以形成逻辑侧管芯间接合衬垫788。逻辑侧管芯间接合衬垫788穿过逻辑管芯衬垫层级介电层770和逻辑管芯介电材料层760的上部部分形成在衬垫空腔中。
替代地,逻辑侧管芯间接合衬垫788首先形成在逻辑管芯金属互连结构780上,并且逻辑管芯衬垫层级介电层770可形成在逻辑侧管芯间接合衬垫788上方和周围。在这种情况下,随后可平坦化逻辑管芯衬垫层级介电层770以暴露逻辑侧管芯间接合衬垫788的顶表面。
至少一种导电材料可为金属(即,金属或金属合金)材料,该金属材料可通过金属对金属或混合接合而接合到相同金属材料或另一金属材料。例如,逻辑侧管芯间接合衬垫788中的每个逻辑侧管芯间接合衬垫可包括任选的金属阻挡衬里和金属填充材料部分,该任选的金属阻挡衬里包括TiN、TaN和/或WN,该金属填充材料部分包括金属材料,该金属材料可通过金属对金属接合而接合到相同金属材料或另一金属材料。例如,金属填充材料部分可包括任何材料和/或基本上由任何材料组成,该任何材料选自Cu、包括原子浓度大于70%(其可大于90%和/或95%)的铜的铜合金,或钴或镍合金,诸如CoW、CoWP、CoMoP、NiW和/或NiWP。
逻辑侧管芯间接合衬垫788中的每个逻辑侧管芯间接合衬垫被逻辑管芯衬垫层级介电层770包围,并且接触逻辑管芯金属互连结构780中的相应的下层逻辑管芯金属互连结构。逻辑侧管芯间接合衬垫788中的每个逻辑侧管芯间接合衬垫可电连接到逻辑管芯半导体器件720的相应节点。嵌入逻辑管芯介电材料层760中的逻辑管芯金属互连结构780将逻辑管芯衬底708上的相应逻辑器件720电连接到逻辑侧管芯间接合衬垫788中的相应逻辑侧管芯间接合衬垫。
参考图3,将存储器侧半导体管芯900和逻辑管芯700定向和对准为使得存储器侧管芯间接合衬垫988面对逻辑侧管芯间接合衬垫788。使逻辑管芯700与存储器侧半导体管芯900接触,使得每个存储器侧管芯间接合衬垫988接触逻辑侧管芯间接合衬垫788中的相应逻辑侧管芯间接合衬垫。在一个实施方案中,逻辑侧管芯间接合衬垫788的图案可为存储器侧管芯间接合衬垫988的图案的镜像,该镜像具有管芯间接合衬垫(988,788)的大小在存储器侧半导体管芯900与逻辑管芯700之间的任选差异。在一个实施方案中,存储器侧管芯间接合衬垫988和对应逻辑侧管芯间接合衬垫788可具有相同大小(即,横向宽度)。在另一实施方案中,存储器侧管芯间接合衬垫988和对应逻辑侧管芯间接合衬垫788可具有不同大小。在一个实施方案中,存储器侧管芯间接合衬垫988和逻辑侧管芯间接合衬垫788的每个面向对之间的面积重叠可为每个配合对内的存储器侧管芯间接合衬垫988和逻辑侧管芯间接合衬垫788中的较小者的面积的至少80%和/或至少90%,诸如90%到100%。
包括多个存储器管芯900的晶圆和包括多个逻辑管芯700的晶圆可使用任何合适的接合方法彼此接合。例如,可执行退火,使得逻辑侧管芯间接合衬垫788可使用金属对金属接合来接合到存储器侧管芯间接合衬垫988,存储器管芯衬垫层级介电层970可使用介电接合来接合到逻辑管芯衬垫层级介电层770,或两者,逻辑侧管芯间接合衬垫788可接合到存储器侧管芯间接合衬垫988,并且存储器管芯衬垫层级介电层970可使用混合接合来接合到逻辑管芯衬垫层级介电层770。
可基于相应材料(诸如逻辑侧管芯间接合衬垫788和存储器侧管芯间接合衬垫988)的组合物来选择退火温度。例如,如果逻辑侧管芯间接合衬垫788和存储器侧管芯间接合衬垫988包括基本上由铜组成的金属填充部分,则退火温度可在150摄氏度至400摄氏度的范围内。存储器管芯900和逻辑管芯700的接合组件包含接合单元(900,700)。可形成多个接合单元(900,700)。一般来讲,每个接合单元(900,700)内的存储器管芯900和逻辑管芯700通过金属对金属接合彼此接合。
根据本公开的方面,可选择存储器管芯900的穿通衬底通孔结构916和逻辑管芯700的穿通衬底通孔结构716的布局,使得存储器管芯900的穿通衬底通孔结构916在接合时位于逻辑管芯700的穿通衬底通孔结构716的相对侧上。例如,接合单元(900,700)可具有彼此平行并且通过第二对直边缘横向间隔开的第一对直边缘,逻辑管芯700的穿通衬底通孔结构716可位于第一对直边缘中的一个直边缘近侧,并且存储器管芯900的穿通衬底通孔结构916可位于第一对直边缘中的另一个直边缘近侧。
参考图4,可通过移除存储器管芯衬底908的背面部分来减薄存储器管芯衬底908。可采用磨削、湿法蚀刻、干法蚀刻和/或抛光来移除存储器管芯衬底908的背面部分。穿通衬底通孔结构916可用作平坦化停止结构。存储器管芯衬底908可通过蚀刻工艺(诸如湿法蚀刻工艺)相对于穿通衬底通孔结构916选择性地凹陷。介电材料(诸如氧化硅)可沉积在存储器管芯衬底的凹陷背面表面上方并且可被平坦化以物理地暴露穿通衬底通孔结构916的背面表面。介电材料的剩余部分包含存储器管芯背面介电层912。
任选的金属衬里和凸块下金属(UBM)层堆叠可沉积在存储器管芯背面介电层912的背面表面上。金属衬里包括材料,诸如TiN、TaN和/或WN,并且可具有在10nm至100nm的范围内的厚度,但也可采用更小和更大的厚度。UBM层堆叠包括用于将焊料球接合在其上的金属材料堆叠。示例性UBM层堆叠包括但不限于Al/Ni/Au堆叠、Al/Ni/Cu堆叠、Cu/Ni/Au堆叠、Cu/Ni/Pd堆叠、Ti/Ni/Au堆叠、Ti/Cu/Ni/Au堆叠、Ti/W/Cu堆叠、Cr/Cu堆叠和Cr/Cu/Ni堆叠。UBM层堆叠的厚度可在1微米至30微米的范围内,诸如3微米至10微米,但也可采用更小和更大的厚度。
可例如通过将光致抗蚀剂层应用和图案化于UBM层堆叠上方并且通过采用蚀刻工艺将光致抗蚀剂层中的图案转移通过UBM层堆叠和任选的金属衬里来图案化UBM层堆叠和任选的金属衬里。蚀刻工艺可包括各向同性蚀刻工艺或各向异性蚀刻工艺。UBM层堆叠和任选的金属衬里的每个剩余部分包含可容纳引线接合的接合衬垫。每个这种接合衬垫在本文中被称为存储器侧外部接合衬垫998。存储器管芯900内的穿通衬底通孔结构916竖直地延伸穿过存储器管芯衬底908并且电连接到存储器侧外部接合衬垫998中的相应存储器侧外部接合衬垫。存储器侧外部接合衬垫998可定位成邻近于存储器管芯900的背面边缘并且可被布置为单行或多行,诸如两行或三行。每行存储器侧外部接合衬垫998可平行于存储器管芯900的背面边缘。在一个实施方案中,存储器管芯900可具有矩形水平横截面形状,并且存储器管芯900的背面边缘可为直的。在这种情况下,每行存储器侧外部接合衬垫998可以直线布置。至少一行存储器侧外部接合衬垫998所处的区在本文中被称为存储器管芯背面外部衬垫区999。
参考图5A、图5B和图6,可通过移除逻辑管芯衬底708的背面部分来减薄逻辑管芯衬底708。可采用磨削、湿法蚀刻、干法蚀刻和/或抛光来移除逻辑管芯衬底708的背面部分。穿通衬底通孔结构716可用作平坦化停止结构。逻辑管芯衬底708可通过蚀刻工艺(诸如湿法蚀刻工艺)相对于穿通衬底通孔结构716选择性地凹陷。介电材料(诸如氧化硅)可沉积在逻辑管芯衬底的凹陷背面表面上方并且可被平坦化以物理地暴露穿通衬底通孔结构716的背面表面。介电材料的剩余部分包含逻辑管芯背面介电层712。
任选的金属衬里和凸块下金属(UBM)层或层堆叠可沉积在逻辑管芯背面介电层712的背面表面上。金属衬里包括材料,诸如TiN、TaN和/或WN,并且可具有在10nm至100nm的范围内的厚度,但也可采用更小和更大的厚度。UBM层堆叠包括用于将焊料球接合在其上的金属材料堆叠。示例性UBM层包括Al或Al合金层,并且示例性UBM层堆叠包括但不限于Al/Ni/Au堆叠、Al/Ni/Cu堆叠、Cu/Ni/Au堆叠、Cu/Ni/Pd堆叠、Ti/Ni/Au堆叠、Ti/Cu/Ni/Au堆叠、Ti/W/Cu堆叠、Cr/Cu堆叠和Cr/Cu/Ni堆叠。UBM层堆叠的厚度可在1微米至30微米的范围内,诸如3微米至10微米,但也可采用更小和更大的厚度。
可例如通过将光致抗蚀剂层应用和图案化于UBM层堆叠上方并且通过采用蚀刻工艺将光致抗蚀剂层中的图案转移通过UBM层堆叠和任选的金属衬里来图案化UBM层堆叠和任选的金属衬里。蚀刻工艺可包括各向同性蚀刻工艺或各向异性蚀刻工艺。UBM层堆叠和任选的金属衬里的每个剩余部分包含可容纳引线接合的接合衬垫。每个这种接合衬垫在本文中被称为逻辑侧外部接合衬垫798。逻辑管芯700内的穿通衬底通孔结构716竖直地延伸穿过逻辑管芯衬底708并且电连接到逻辑侧外部接合衬垫798中的相应逻辑侧外部接合衬垫。逻辑侧外部接合衬垫798可定位成邻近于逻辑管芯700的背面边缘并且可被布置为单行、两行或三行。每行逻辑侧外部接合衬垫798可平行于逻辑管芯700的背面边缘。在一个实施方案中,逻辑管芯700可具有矩形水平横截面形状,逻辑管芯700的背面边缘可为直的。在这种情况下,每行逻辑侧外部接合衬垫798可以直线布置。至少一行逻辑侧外部接合衬垫798所处的区在本文中被称为逻辑管芯背面外部衬垫区799。
逻辑管芯背面外部衬垫区沿着垂直于存储器管芯900与逻辑管芯700之间的界面的方向在平面图(诸如图5B的视图)中位于存储器管芯背面外部衬垫区的相对侧上。在一个实施方案中,存储器管芯背面外部衬垫区999可沿着第一水平方向hd1(例如位线方向)与逻辑管芯背面外部衬垫区799横向间隔开。逻辑侧外部接合衬垫798可布置成沿着平行于接合单元(900,700)的边缘的第二水平方向hd2横向延伸的行(或多行),并且存储器侧外部接合衬垫998可布置成沿着第二水平方向hd2(例如字线方向)横向延伸并且位于逻辑管芯背面外部衬垫区799的相对侧上的行(或多行)。第二水平方向hd2可垂直于第一水平方向hd1。
存储器管芯900和逻辑管芯700内的输入/输出信号和配电布线的主要方向可沿着第一水平方向hd1,并且存储器管芯900和逻辑管线700内的输入/输出信号和配电布线的第二方向可沿着第二水平方向hd2。如图5B所示,在包含四个存储器平面存储器管芯900的接合单元(900,700)中,外围器件区706定位成邻近于包含相应背面外部衬垫区(999,799)的接合单元(900,700)的逻辑管芯700的侧部(即,边缘),而感测放大器区702位于外围器件区706与边缘字线开关区704之间的接合单元(900,700)的逻辑管芯700中间。因此,功率信号从相应背面外部衬垫区(999,799)直接路由到外围器件区(例如路由到位于外围器件区中的电荷泵电路)706,而不穿过感测放大器区702。这意味着可使将相应背面外部衬垫区(999,799)电连接到外围器件区706的互连结构780更短,这减小了其电阻,从而增加了电荷泵功率效率。此外,此类互连结构780不必在感测放大器区702中围绕接合衬垫788布线,并且在感测放大器区702中不会产生干扰感测放大器操作的噪声。
在一个实施方案中,存储器管芯900中的穿通衬底通孔结构916竖直地延伸穿过存储器管芯衬底908,并且电连接到存储器侧外部接合衬垫998中的相应存储器侧外部接合衬垫。存储器管芯金属互连结构980嵌入存储器管芯介电材料层960中,并且将存储器管芯衬底908上的相应存储器器件920电连接到存储器侧管芯间接合衬垫988中的相应存储器侧管芯间接合衬垫。
在一个实施方案中,逻辑管芯700中的穿通衬底通孔结构716竖直地延伸穿过逻辑管芯衬底708,并且电连接到逻辑侧外部接合衬垫798中的相应逻辑侧外部接合衬垫。逻辑管芯金属互连结构780嵌入逻辑管芯介电材料层760中,并且将逻辑管芯衬底708上的相应逻辑器件720电连接到逻辑侧管芯间接合衬垫788中的相应逻辑侧管芯间接合衬垫。
可形成多个接合单元(900,700)。每个接合单元(900,700)包含存储器管芯900,该存储器管芯包括位于存储器管芯900的相对主表面上的存储器侧管芯间接合衬垫988和存储器侧外部接合衬垫998。另外,每个接合单元(900,700)包含逻辑管芯700,该逻辑管芯包括被配置为控制存储器管芯900的操作的逻辑电路以及位于逻辑管芯700的相对主表面上的逻辑侧管芯间接合衬垫788和逻辑侧外部接合衬垫798。在一个实施方案中,可通过接合相应逻辑管芯700和相应存储器管芯900来提供每个接合单元(900,700),使得相应逻辑管芯700的逻辑侧管芯间接合衬垫788接合到相应存储器管芯900的存储器侧管芯间接合衬垫988中的相应存储器侧管芯间接合衬垫。
在一个实施方案中,可通过将包括多个存储器管芯900的晶圆接合到包括多个逻辑管芯700的晶圆来形成多个接合单元(900,700)。在这种情况下,可沿着切割沟道切割两个晶圆的接合组件以提供多个接合单元(900,700)。
参考图7,示出了根据本公开的第一实施方案的包括堆叠式管芯组件的第一示例性结构。堆叠式管芯组件包括通过采用粘合层550附接竖直相邻的接合单元对而形成的多个接合单元(900,700)的竖直堆叠。在一个实施方案中,堆叠式管芯组件包含通过粘合层550彼此连接的多个接合单元(900,700)的竖直堆叠和安装衬底(例如封装的印刷电路板或基座)300。每对竖直相邻的接合单元(900,700)可通过相应粘合层550彼此附接。安装衬底300可采用附加粘合层550附接到多个接合单元(900,700)的竖直堆叠。替代地,代替粘合层550或除了粘合层550之外,可使用其他附接方法,诸如夹钳、封装或接合层。
一般来讲,多个接合单元(900,700)的竖直堆叠可通过以下步骤来形成:将多个接合单元(900,700)彼此附接,使得多个接合单元(900,700)的存储器侧外部接合衬垫998和逻辑侧外部接合衬垫798形成面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,该面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,该面朝下的外部接合衬垫集合具有相对于安装衬底300的接合侧面朝下的物理暴露表面。例如,接合单元(900,700)可交错,使得存储器侧外部接合衬垫998物理地暴露并且逻辑侧外部接合衬垫798物理地暴露。在一个实施方案中,相对于安装衬底300的接合侧,存储器侧外部接合衬垫998可物理地暴露为面朝上并且逻辑侧外部接合衬垫798可物理地暴露为面朝下。在另一实施方案中,相对于安装衬底300的接合侧,存储器侧外部接合衬垫998可物理地暴露为面朝下并且逻辑侧外部接合衬垫798可物理地暴露为面朝上。
第一接合引线950集合可连接面朝上的外部接合衬垫集合(其可为存储器侧外部接合衬垫998或逻辑侧外部接合衬垫798)的一对相应的面朝上的外部接合衬垫。第二接合引线750集合可连接面朝下的外部接合衬垫集合(其可为存储器侧外部接合衬垫998或逻辑侧外部接合衬垫798)的一对相应的面朝下的外部接合衬垫。
在一个实施方案中,多个接合单元(900,700)可交错,使得每个上覆接合单元(900,700)相对于下层接合单元(900,700)沿着第一水平方向hd1横向偏移。第一水平方向hd1是逻辑管芯700的逻辑管芯外部衬垫区与存储器管芯900的存储器侧外部衬垫区横向间隔开的方向。
可通过将附加接合引线(950,750)附接到位于安装衬底300的安装侧上的接合衬垫398和多个接合单元(900,700)的竖直堆叠的最近端接合单元(900,700)的外部接合衬垫(998,798)来将多个接合单元(900,700)的竖直堆叠电连接到安装衬底300。
在一个实施方案中,多个接合单元(900,700)可彼此附接,使得堆叠式管芯组件内的每个面朝上的外部接合衬垫在沿着接合单元堆叠所沿的方向(诸如竖直方向)的平面图中与堆叠式管芯组件内的任何上覆接合单元不具有面积重叠,堆叠式管芯组件内的每个面朝下的外部接合衬垫在平面图中与堆叠式管芯组件内的任何下层接合单元不具有面积重叠。
参考图1A至图7并且根据本公开的各种实施方案,包括堆叠式管芯组件(900,700,300,950,750)的结构。堆叠式管芯组件(900,700,300,950,750)包含多个接合单元(900,700)的竖直堆叠。每个接合单元(900,700)包含存储器管芯900,该存储器管芯包括位于存储器管芯900的相对主表面上的存储器侧管芯间接合衬垫988和存储器侧外部接合衬垫998。每个接合单元(900,700)还包含逻辑管芯700,该逻辑管芯包括被配置为控制存储器管芯900的操作的逻辑电路并且包括位于逻辑管芯700的相对主表面上的逻辑侧管芯间接合衬垫788和逻辑侧外部接合衬垫798。逻辑侧管芯间接合衬垫788接合到存储器侧管芯间接合衬垫988中的相应存储器侧管芯间接合衬垫。存储器侧外部接合衬垫998和逻辑侧外部接合衬垫798包含面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,该面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,该面朝下的外部接合衬垫集合具有面朝下的物理暴露表面。第一接合引线950集合连接面朝上的外部接合衬垫,并且第二接合引线750集合连接面朝下的外部接合衬垫。
如本文所用,管芯的主表面彼此相对,其中一个主表面包含外部接合衬垫,并且另一个主表面包含管芯间接合衬垫,该管芯间接合衬垫接合到接合单元(900,700)的其他管芯的管芯间接合衬垫。如果一个主表面“向下”指向安装衬底3000,则可将一个主表面视为“下部”主表面,而如果另一个主表面远离安装衬底3000“向上”指向,则可将另一个主表面视为“上部”主表面。然而,应注意,“向上”和“向下”并不一定与“远离”和“朝向”地面的方向对准,这是因为接合单元可在电子器件中侧向或“倒置”定位(安装衬底3000位于接合单元上方)。同样,电子器件可相对于地面在任何方向上定位。
在一个实施方案中,每对竖直相邻的接合单元(900,700)相对于安装衬底3000位置包含上覆接合单元(即,存储器管芯900和逻辑管芯700的上部接合单元)和下层接合单元(即,附加存储器管芯900和附加逻辑管芯700的附加接合单元)。上覆接合单元相对于下层接合单元沿着第一水平方向hd1横向偏移。水平方向平行于管芯的主表面。在一个实施方案中,每个存储器管芯900内的存储器侧外部接合衬垫998沿着第一水平方向hd1以均匀横向偏移距离与存储器管芯900的边缘横向偏移,并且存储器管芯900的边缘沿着垂直于第一水平方向hd1的第二水平方向hd2横向延伸。在一个实施方案中,每个逻辑管芯700内的逻辑侧外部接合衬垫798以均匀横向偏移距离与逻辑管芯700的边缘横向偏移,并且逻辑管芯700的边缘沿着垂直于第一水平方向hd1的第二水平方向hd2横向延伸。
在一个实施方案中,堆叠式管芯组件(900,700,300,950,750)内的每个面朝上的外部接合衬垫(998或798)在沿着接合单元(900,700)堆叠所沿的方向的平面图中与堆叠式管芯组件内的任何上覆接合单元(900,700)不具有面积重叠;并且堆叠式管芯组件(900,700,300,950,750)内的每个面朝下的外部接合衬垫(998或798)在平面图中与堆叠式管芯组件(900,700,300,950,750)内的任何下层接合单元(900,700)不具有面积重叠。
在一个实施方案中,面朝上的外部接合衬垫(998或798)集合包含存储器侧外部接合衬垫998,并且面朝下的外部接合衬垫集合包含逻辑侧外部接合衬垫798,或面朝下的外部接合衬垫(998或798)集合包含逻辑侧外部接合衬垫798,并且面朝下的外部接合衬垫(998或798)集合包含存储器侧外部接合衬垫998。
在一个实施方案中,每对竖直相邻的接合单元(900,700)通过相应粘合层550彼此附接。多个接合单元(900,700)的竖直堆叠可通过附加粘合层550安装到安装衬底300。附加接合引线(950,750)可提供多个接合单元(900,700)之间的最近端接合单元(900,700)的外部接合衬垫(998,798)与位于安装衬底300上的接合衬垫之间电连接。
在一个实施方案中,逻辑侧管芯间接合衬垫788通过金属对金属接合而接合到每个接合单元(900,700)内的存储器侧管芯间接合衬垫988中的相应存储器侧管芯间接合衬垫。
在一个实施方案中,存储器管芯900中的至少一个存储器管芯包含:三维存储器阵列,该三维存储器阵列位于存储器管芯衬底908上方;存储器管芯金属互连结构980,该存储器管芯金属互连结构嵌入存储器管芯介电材料层960中。和穿通衬底通孔结构916,该穿通衬底通孔结构竖直地延伸穿过存储器管芯衬底908并且电连接到存储器侧外部接合衬垫998中的相应存储器侧外部接合衬垫。在一个实施方案中,三维存储器阵列包含:绝缘层32和导电层46的竖直交替堆叠;多个存储器开口填充结构58,该多个存储器开口填充结构各自包括竖直半导体沟道和位于导电层46的层级处的存储器元件(例如存储器膜的部分)的竖直堆叠;位线982,该位线电连接到多个存储器开口填充结构58的相应子集;阶梯式介电材料部分65,该阶梯式介电材料部分位于交替堆叠(32,46)的阶梯式表面上;和层接触通孔结构86,该层接触通孔结构竖直地延伸穿过阶梯式介电材料部分65并且接触导电层46中的相应导电层。
在一个实施方案中,接合到存储器管芯900中的相应存储器管芯的逻辑管芯700中的至少一个逻辑管芯包含:感测放大器区702,该感测放大器区包括电连接到位线982中的相应位线的感测放大器;和外围器件区706,该外围器件区包括电荷泵电路。在一个实施方案中,外围器件区位于感测放大器区702与逻辑侧外部接合衬垫798之间。
在一个实施方案中,逻辑管芯700中的至少一个逻辑管芯包含:穿通衬底通孔结构716,该穿通衬底通孔结构竖直地延伸通过逻辑管芯衬底708并且电连接到逻辑侧外部接合衬垫798中的相应逻辑侧外部接合衬垫。和逻辑管芯金属互连结构780,该逻辑管芯金属互连结构嵌入逻辑管芯介电材料层760中并且将逻辑管芯衬底708上的相应逻辑器件720电连接到逻辑侧管芯间接合衬垫788中的相应逻辑侧管芯间接合衬垫。
参考图8A和图8B,示出了根据本公开的第二实施方案的半导体管芯600。第二实施方案的半导体管芯600包括衬底608,该衬底也被称为第一衬底。半导体管芯600还包括覆盖在衬底608上面的半导体器件620、覆盖在半导体器件620上面的介电材料层660和嵌入介电材料层660中的金属互连结构680。金属互连结构680包括位线682。在一个实施方案中,衬底608可为厚度在500微米至1mm的范围内的可商购获得的硅晶圆。半导体管芯600可设置于包括存储器管芯600的二维阵列的晶圆中。例如,衬底可为半导体晶圆,诸如硅晶圆。
一般来讲,半导体器件620包括存储器器件并且可任选地包括逻辑器件。半导体管芯600可包括至少一个存储器阵列区100和至少一个辅助区202。辅助区202包含连接区200(其可为上面关于图1A描述的区200)并且任选地包含至少一个逻辑器件区800。每个存储器阵列区100包括相应存储器阵列(例如上述存储器管芯半导体器件920)。如果存在,则每个逻辑器件区800包括用于支持相应存储器阵列区100中的存储器元件的操作的上述逻辑器件720。在一个实施方案中,如图8A所示,逻辑器件区800可位于接触区200旁边(例如在位于存储器阵列配置旁边的CMOS中)。在替代实施方案中,逻辑器件区800可位于存储器阵列区100下方和接触区200下方(例如在位于存储器阵列配置下方的CMOS中)。在另一替代实施方案中,逻辑器件区800不存在于衬底608上或衬底608上方。相反,逻辑器件区存在于单独衬底上,诸如上面关于第一实施方案所描述的安装衬底3000(例如在接合到存储器阵列配置的CMOS中)。
每个平面可包括存储器阵列区100和至少一个辅助区202。例如,图8B示出了包含两个存储器平面的管芯,该存储器平面中的每个存储器平面包含两个辅助区202。然而,可使用其他配置。每个存储器阵列区100可包括可设置于第一实施方案的存储器管芯900中的存储器器件920。每个逻辑器件区800(如果存在)可包括可设置于第一实施方案的逻辑管芯700中的逻辑器件720。例如,每个存储器阵列区100可包括三维存储器阵列,诸如三维NAND存储器阵列。三维存储器器件可包括各种器件区,该各种器件区包含半导体器件620的各种子集。
在一个实施方案中,半导体器件620可包括绝缘层32和导电层46的竖直交替堆叠以及竖直地延伸穿过竖直交替堆叠(32,46)的存储器开口的二维阵列。导电层46可包含三维NAND存储器器件的字线。存储器开口填充结构58可形成在每个存储器开口内。每个存储器开口填充结构58可包括存储器膜和接触该存储器膜的竖直半导体沟道。存储器膜可包括阻挡电介质、隧穿电介质和位于阻挡电介质与隧穿电介质之间的电荷存储材料。电荷存储材料可包含电荷俘获层,诸如氮化硅层;或多个离散电荷俘获区,诸如电荷俘获层的浮栅或离散部分。在这种情况下,每个存储器开口填充结构58和导电层46的邻近部分构成竖直NAND串。替代地,存储器开口填充结构58可包括任何类型的非易失性存储器元件,诸如电阻存储器元件、铁电存储器元件、相变存储器元件等。
存储器开口填充结构58可形成在相应存储器阵列区内。可提供多个竖直NAND串。每个竖直NAND串可包括竖直半导体沟道和位于导电层46的层级处的存储器元件(例如存储器膜或浮栅的部分)的竖直堆叠。
可使导电层46图案化以提供每个上覆导电层46具有比任何下层导电层46更小的横向范围的阶梯区(即,接触区200)。可在每个竖直交替堆叠(32,46)周围形成阶梯式介电材料部分65以提供相邻竖直交替堆叠(32,46)之间的电隔离。阶梯式介电材料部分65可形成在相应竖直交替堆叠(32,46)的阶梯式表面上。层接触通孔结构86可形成在阶梯区中的导电层46上以提供与导电层46的电连接。层接触通孔结构86可竖直地延伸穿过相应阶梯式介电材料部分65并且可接触导电层46中的相应导电层。
介电材料层660和金属互连结构680可形成在半导体器件620和阶梯式介电材料部分65上方。金属互连结构680包括位线682。每个位线682电接触存储器开口填充结构58内的漏极区的相应子集。漏极区可接触竖直半导体沟道60中的相应竖直半导体沟道的顶端。因此,位线可电连接到多个竖直NAND串的相应子集。金属互连结构680包括互连金属线和互连金属通孔结构。
介电材料层660中的每个介电材料层可包括相应介电材料,诸如未掺杂硅酸盐玻璃、掺杂硅酸盐玻璃、有机硅酸盐玻璃、氮化硅、介电金属氧化物或其组合。衬垫层级介电层(未示出)可设置于介电材料层660顶部。衬垫层级介电层(如果存在)可包括随后可接合到随后要提供的逻辑管芯的另一介电接合材料层的介电扩散阻挡层(诸如氮化硅层)或第一介电接合材料层(诸如氧化硅层)。
外部衬垫空腔可形成在位于半导体管芯600的边缘处的外部衬垫区中。半导体管芯600的边缘可垂直于第一水平方向hd2并且可平行于第二水平方向hd2。外部衬垫空腔可沿着第二水平方向布置成一行或多行。每行外部衬垫空腔沿着第二水平方向hd2横向延伸。
至少一种导电材料随后可沉积在外部衬垫空腔中。至少一种导电材料可包括任选的金属衬里和凸块下金属(UBM)层或层堆叠。金属衬里包括材料,诸如TiN、TaN和/或WN,并且可具有在10nm至100nm的范围内的厚度,但也可采用更小和更大的厚度。UBM层或层堆叠可包括可在第一实施方案中采用的任何UBM层或层堆叠。UBM层或层堆叠的厚度可在1微米至30微米的范围内,诸如3微米至10微米,但也可采用更小和更大的厚度。
可从介电材料层660的最顶部水平表面上方移除至少一种导电材料的多余部分。至少一种导电材料的剩余部分包含外部接合衬垫698。替代地,包含外部接合衬垫698可形成在介电材料层660上方,并且附加介电材料层可沉积在外部接合衬垫698周围并且随后可被平坦化,使得外部接合衬垫698的顶表面物理地暴露。
在一个实施方案中,存储器管芯900包括区800中的逻辑电路和金属互连结构680,该逻辑电路包含位于衬底608上的半导体器件720并且被配置为控制存储器阵列内的存储器元件的操作,该金属互连结构嵌入介电材料层660中并且提供逻辑电路的半导体器件与存储器阵列内的存储器元件之间的电连接。在一个实施方案中,存储器阵列可包括:绝缘层32和导电层46的竖直交替堆叠;多个竖直NAND串,该多个竖直NAND串各自包括相应竖直半导体沟道和位于导电层46的层级处的存储器元件的相应竖直堆叠;位线682,该位线电连接到多个竖直NAND串的相应子集;阶梯式介电材料部分65,该阶梯式介电材料部分位于交替堆叠(32,46)的阶梯式表面上;和层接触通孔结构86,该层接触通孔结构竖直地延伸穿过阶梯式介电材料部分65并且接触导电层46中的相应导电层。
处理衬底400可例如采用临时粘合层(未示出)附接到半导体管芯600的包括外部接合衬垫698的侧部。处理衬底400可包括介电材料、导电材料或半导体材料,并且可具有在500微米至10mm的范围内的厚度,但也可采用更小和更大的厚度。
参考图9A至图9C,可提供半导体管芯600的组件和处理衬底400的两个实例。可从背面减薄每个半导体管芯600。具体地,可从背面减薄每个衬底608。可通过磨削、化学蚀刻、干法蚀刻和/或抛光来减薄每个衬底608。处理衬底400可在减薄工艺期间向第一晶圆和第二晶圆提供结构支撑。
一般来讲,可提供第一半导体管芯600和第二半导体管芯600。第一半导体管芯600可设置于包括第一多个存储器管芯600的第一晶圆内,并且第二半导体管芯600可设置于包括第二多个存储器管芯600的第二晶圆内。第一半导体管芯600在本文中被称为正面半导体管芯600F,并且第二半导体管芯600在本文中被称为背面半导体管芯600B。
背面半导体管芯600B的减薄衬底608B和正面半导体管芯600F的减薄衬底608F彼此接触并且然后使用晶圆对晶圆接合彼此接合。半导体管芯600F和背面半导体管芯600B的接合组件包含接合单元(600F,600B)。可形成多个接合单元(600F,600B)。在一个实施方案中,正面半导体管芯600F可设置于第一晶圆中,并且背面半导体管芯600B可设置于第二晶圆中。在这种情况下,可在将第二晶圆接合到第一晶圆时形成多个接合单元(600F,600B)。
在一个实施方案中,没有穿通衬底通孔结构延伸穿过减薄衬底(608B,608F)中的任一减薄衬底,并且背面半导体管芯600B和正面半导体管芯600F的接合对通过其相应减薄衬底(608B,608F)彼此电连接。在其他实施方案中,背面半导体管芯600B和正面半导体管芯600F的接合对完全不通过引线接合或接合衬垫彼此直接电连接。然而,该背面半导体管芯和该正面半导体管芯通过共同安装衬底300彼此间接电连接,如下面将更详细地描述。
随后可沿着切割沟道切割第一晶圆和第二晶圆的接合组件以提供多个接合单元(600F,600B)。在一个实施方案中,每个接合单元(600F,600B)包含相应正面半导体管芯600F和相应背面半导体管芯600B,该相应正面半导体管芯包括正面存储器阵列和正面外部接合衬垫698F,该相应背面半导体管芯包括背面存储器阵列和背面外部接合衬垫698B并且接合到相应正面半导体管芯600F。
根据本公开的方面,正面半导体管芯600F和背面半导体管芯600B在接合期间定向为使得正面半导体管芯600F的外部接合衬垫698(在下文中被称为正面外部接合衬垫698F)在平面图中位于背面半导体管芯600B的外部接合衬垫698(在下文中被称为背面外部接合衬垫698B)的相对侧(即,接合单元(600F,600B)的相对主表面)上。平面图为沿着竖直方向的视图,即,沿着垂直于正面半导体管芯600F与背面半导体管芯600B之间的界面的方向的视图。
正面半导体管芯600F和背面半导体管芯600B可位于接合单元(600F,600B)的相对边缘上。例如,接合单元(600F,600B)可具有彼此平行并且通过第二对直边缘横向间隔开的第一对直边缘,正面外部接合衬垫698F可位于第一对直边缘中的一个直边缘近侧并且背面外部接合衬垫698B可位于第一对直边缘中的另一个直边缘近侧。正面外部接合衬垫698F和背面外部接合衬垫698B可沿着第一水平方向hd2横向间隔开,并且正面外部接合衬垫698F和背面外部接合衬垫698B中的每一者可布置在沿着垂直于第一水平方向hd1的第二水平方向hd2横向延伸的相应行(或多行)中。
参考图10,示出了根据本公开的第二实施方案的包括堆叠式管芯组件的第二示例性结构。堆叠式管芯组件包括通过将竖直相邻的接合单元对彼此附接而形成的多个接合单元(600F,600B)的竖直堆叠。可使用粘合层、机械夹钳和/或将竖直堆叠的接合单元压缩在一起的封装来形成附接。在一个实施方案中,堆叠式管芯组件包含多个接合单元(600F,600B)的竖直堆叠和通过粘合层550彼此连接的安装衬底300。每对竖直相邻的接合单元(600F,600B)可通过相应粘合层550彼此附接。安装衬底300可采用附加粘合层550附接到多个接合单元(600F,600B)的竖直堆叠。
一般来讲,多个接合单元(600F,600B)的竖直堆叠可通过以下步骤来形成:将多个接合单元(600F,600B)彼此附接,使得多个接合单元(600F,600B)的外部接合衬垫(698F,698B)形成面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,该面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,该面朝下的外部接合衬垫集合具有面朝下的物理暴露表面。例如,接合单元(600F,600B)可交错,使得外部接合衬垫(698F,698B)物理地暴露。正面半导体管芯600F的正面外部接合衬垫698F可物理地暴露为面朝上,并且背面半导体管芯600B的背面外部接合衬垫698B可物理暴露为面朝下。
第一接合引线950集合可连接面朝上的外部接合衬垫集合(其可为正面外部接合衬垫698F)之间的一对相应的面朝上的外部接合衬垫。第二接合引线750集合可连接面朝下的外部接合衬垫集合(其可为背面外部接合衬垫698F)之间的一对相应的面朝下的外部接合衬垫。
在一个实施方案中,多个接合单元(600F,600B)可交错,使得每个上覆接合单元(600F,600B)相对于下层接合单元(600F,600B)沿着第一水平方向hd1横向偏移。第一水平方向hd1为每个接合单元(600F,600B)的正面外部衬垫区与每个接合单元(600F,600B)的背面外部衬垫区横向间隔开的方向。
可通过将附加接合引线(950、750)附接到位于安装衬底300上的接合衬垫398和多个接合单元(600F,600B)的竖直堆叠之间的最近端接合单元(600F,600B)的外部接合衬垫(698F,698B)来将多个接合单元(600F,600B)的竖直堆叠电连接到安装衬底700。
在一个实施方案中,多个接合单元(600F,600B)可彼此附接,使得堆叠式管芯组件内的每个面朝上的外部接合衬垫在沿着接合单元堆叠所沿的方向(诸如竖直方向)的平面图中与堆叠式管芯组件内的任何上覆接合单元不具有面积重叠,堆叠式管芯组件内的每个面朝下的外部接合衬垫在平面图中与堆叠式管芯组件内的任何下层接合单元不具有面积重叠。
虽然图10示出了将包含三十二个半导体管芯600的十六个接合单元(600F,600B)附接到安装衬底300的实施方案,但本文明确考虑了将任何多个接合单元(600F,600B)附接到安装衬底300的实施方案。安装衬底300可为任何封装衬底。如果半导体管芯600不包含相应专用逻辑器件区800,则逻辑器件720可位于安装衬底300上。在所说明实例中,将每个正面半导体管芯600F标记为偶数管芯,并且将每个背面半导体管芯600B标记为奇数管芯。分配给每个半导体管芯600的数量可为任意的。
参考图8A至图10和相关附图并且根据本公开的各种实施方案,提供了包括堆叠式管芯组件(600F,600B,300,950,750,550)的结构。堆叠式管芯组件(600F,600B,300,950,750,550)包含:多个接合单元(600F,600B)的竖直堆叠,其中每个接合单元(600F,600B)包含相应正面半导体管芯600F和相应背面半导体管芯600B,该相应正面半导体管芯包括正面外部接合衬垫698F,该相应背面半导体管芯包括背面外部接合衬垫698B,其中相应背面半导体管芯600B接合到相应正面半导体管芯600F,并且其中每个接合单元(600F,600B)的正面外部接合衬垫698F具有面朝上的物理暴露表面,并且每个接合单元(600F,600B)的背面外部接合衬垫698B具有面朝下的物理暴露表面;第一接合引线950集合,该第一接合引线集合连接正面外部接合衬垫698F;和第二接合引线750集合,该第二接合引线集合连接背面外部接合衬垫698B。
在一个实施方案中,正面半导体管芯600F还包含正面存储器阵列620,并且背面半导体管芯还包含背面存储器阵列620。
在一个实施方案中,每个接合单元(600F,600B)内的正面半导体管芯600F包含嵌入正面介电材料层660中的正面金属互连结构680,其中正面金属互连结构680的子集连接到每个接合单元(600F,600B)内的正面外部接合衬垫698F;并且每个接合单元(600F,600B)内的背面半导体管芯600B包含嵌入背面介电材料层660中的背面金属互连结构680,其中背面金属互连结构680的子集连接到每个接合单元(600F,600B)内的背面外部接合衬垫698B。
在一个实施方案中,每个接合单元内的正面半导体管芯600F包含正面衬底608F;每个接合单元内的背面半导体管芯600B包含背面衬底608B;并且正面衬底接合到背面衬底。在一个实施方案中,相同接合单元中的背面半导体管芯600B和正面半导体管芯600F彼此不直接电连接。
在一个实施方案中,每对竖直相邻的接合单元(600F,600B)包含上覆接合单元(600F,600B)和下层接合单元(600F,600B);并且上覆接合单元(600F,600B)相对于下层接合单元(600F,600B)沿着第一水平方向hd1横向偏移。在一个实施方案中,每个正面半导体管芯600F内的正面外部接合衬垫698F沿着第一水平方向hd1以均匀横向偏移距离与正面半导体管芯600F的边缘横向偏移;并且正面半导体管芯600F的边缘沿着垂直于第一水平方向hd1的第二水平方向hd2横向延伸。在一个实施方案中,背面半导体管芯600B内的背面外部接合衬垫698B以均匀横向偏移距离与背面半导体管芯600B的边缘横向偏移;并且背面半导体管芯600B的边缘沿着垂直于第一水平方向hd1的第二水平方向hd2横向延伸。
在一个实施方案中,堆叠式管芯组件(600F,600B,300,950,750,550)内的每个正面外部接合衬垫698F在沿着接合单元(600F,600B)堆叠所沿的方向的平面图中与堆叠式管芯组件(600F,600B,300,950,750,550)内的任何上覆接合单元(600F,600B)不具有面积重叠;并且堆叠式管芯组件(600F,600B,300,950,750,550)内的每个背面外部接合衬垫698B在平面图中与堆叠式管芯组件(600F,600B,300,950,750,550)内的任何下层接合单元(600F,600B)不具有面积重叠。
在一个实施方案中,每对竖直相邻的接合单元(600F,600B)通过相应粘合层550彼此附接。在一个实施方案中,多个接合单元(600F,600B)的竖直堆叠可通过附加粘合层550安装在安装衬底300上;并且附加接合引线(950,750)可提供位于安装衬底300上的接合衬垫398与堆叠式管芯组件(600F,600B,300,950,750,550)的接合单元(600F,600B)之间的最近端接合单元(600F,600B)的正面外部接合衬垫698F和背面外部接合衬垫698B之间的电连接。
在一个实施方案中,正面半导体管芯600F和背面半导体管芯600B中的每一者包含:相应逻辑电路,该相应逻辑电路包括位于相应衬底608上并且被配置为控制相应存储器阵列内的存储器元件的操作的半导体器件;和相应金属互连结构680,该相应金属互连结构嵌入相应介电材料层660中并且提供相应逻辑电路的半导体器件与相应存储器阵列内的存储器元件之间的电连接。在一个实施方案中,相应存储器阵列包含:绝缘层32和导电层46的竖直交替堆叠;多个存储器开口填充结构58,该多个存储器开口填充结构各自包括相应竖直半导体沟道和位于导电层46的层级处的存储器元件的相应竖直堆叠;位线,该位线电连接到多个存储器开口填充结构58的相应子集;阶梯式介电材料部分65,该阶梯式介电材料部分位于交替堆叠(32,46)的阶梯式表面上;和层接触通孔结构86,该层接触通孔结构竖直地延伸穿过阶梯式介电材料部分65并且接触导电层46中的相应导电层。
本公开的各种实施方案在无限数量的堆叠式接合单元上同时将正面引线接合设置于正面外部接合衬垫上和将背面引线接合设置于背面外部接合衬垫上,从而提供多层级管芯堆叠。双面连接配置可增加总外部衬垫面积,该总外部衬垫面积可用于引线接合,而不牺牲用于附加引线接合衬垫的宝贵器件空间。
尽管前面提及特定实施方案,但是应该理解本公开不限于此。本领域的普通技术人员将会想到,可对所公开的实施方案进行各种修改,并且此类修改旨在落在本公开的范围内。在不是彼此的另选方案的所有实施方案中假定相容性。除非另外明确说明,否则词语“包含”或“包括”设想其中词语“基本上由...组成”或词语“由...组成”替换词语“包含”或“包括”的所有实施方案。在本公开中示出使用特定结构和/或构型的实施方案,应当理解,本公开可以以功能上等同的任何其他兼容结构和/或构型来实践,前提条件是此类取代不被明确地禁止或以其他方式被本领域的普通技术人员认为是不可能的。本文引用的所有出版物、专利申请和专利均以引用方式全文并入本文。
Claims (40)
1.一种包括堆叠式管芯组件的结构,其中所述堆叠式管芯组件包含:
多个接合单元的竖直堆叠,其中每个接合单元包含:
存储器管芯,所述存储器管芯包括位于所述存储器管芯的相对主表面上的存储器侧管芯间接合衬垫和存储器侧外部接合衬垫;和
逻辑管芯,所述逻辑管芯包括逻辑电路,所述逻辑电路被配置为控制所述存储器管芯的操作并且包括位于所述逻辑管芯的相对主表面上的逻辑侧管芯间接合衬垫和逻辑侧外部接合衬垫,
其中:
所述逻辑侧管芯间接合衬垫接合到所述存储器侧管芯间接合衬垫中的相应存储器侧管芯间接合衬垫;并且
所述存储器侧外部接合衬垫和所述逻辑侧外部接合衬垫包含面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,所述面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,所述面朝下的外部接合衬垫集合具有面朝下的物理暴露表面;
第一接合引线集合,所述第一接合引线集合连接面朝上的外部接合衬垫;和
第二接合引线集合,所述第二接合引线集合连接面朝下的外部接合衬垫。
2.根据权利要求1所述的结构,其中:
每对竖直相邻的接合单元包含上覆接合单元和下层接合单元;并且
所述上覆接合单元相对于所述下层接合单元沿着第一水平方向横向偏移。
3.根据权利要求2所述的结构,其中:
每个存储器管芯内的存储器侧外部接合衬垫沿着所述第一水平方向以均匀横向偏移距离与所述存储器管芯的边缘横向偏移;并且
所述存储器管芯的所述边缘沿着垂直于所述第一水平方向的第二水平方向横向延伸。
4.根据权利要求3所述的结构,其中:
每个逻辑管芯内的逻辑侧外部接合衬垫以均匀横向偏移距离与所述逻辑管芯的边缘横向偏移;并且
所述逻辑管芯的所述边缘沿着垂直于所述第一水平方向的所述第二水平方向横向延伸。
5.根据权利要求1所述的结构,其中:
所述堆叠式管芯组件内的每个面朝上的外部接合衬垫在沿着所述接合单元堆叠所沿的方向的平面图中与所述堆叠式管芯组件内的任何上覆接合单元不具有面积重叠;并且
所述堆叠式管芯组件内的每个面朝下的外部接合衬垫在所述平面图中与所述堆叠式管芯组件内的任何下层接合单元不具有面积重叠。
6.根据权利要求1所述的结构,其中:
所述面朝上的外部接合衬垫集合包含所述存储器侧外部接合衬垫,并且所述面朝下的外部接合衬垫集合包含所述逻辑侧外部接合衬垫;或者
所述面朝下的外部接合衬垫集合包含所述逻辑侧外部接合衬垫,并且所述面朝下的外部接合衬垫集合包含所述存储器侧外部接合衬垫。
7.根据权利要求1所述的结构,所述结构还包含:
安装衬底,多个接合单元的所述竖直堆叠通过附加粘合层安装在所述安装衬底上;和
附加接合引线,所述附加接合引线提供所述多个接合单元中的最近端接合单元的外部接合衬垫与位于所述安装衬底上的接合衬垫之间的电连接,其中每对竖直相邻的接合单元通过相应粘合层彼此附接。
8.根据权利要求1所述的结构,其中所述逻辑侧管芯间接合衬垫通过金属对金属接合来接合到每个接合单元内的所述存储器侧管芯间接合衬垫中的所述相应存储器侧管芯间接合衬垫。
9.根据权利要求1所述的结构,其中所述存储器管芯中的一个存储器管芯包含:
三维存储器阵列,所述三维存储器阵列位于存储器管芯衬底上方;
存储器管芯金属互连结构,所述存储器管芯金属互连结构嵌入存储器管芯介电材料层中;和
穿通衬底通孔结构,所述穿通衬底通孔结构竖直地延伸穿过所述存储器管芯衬底并且电连接到所述存储器侧外部接合衬垫中的相应存储器侧外部接合衬垫。
10.根据权利要求9所述的结构,其中所述三维存储器阵列包含:
绝缘层和导电层的竖直交替堆叠;
多个存储器开口填充结构,所述多个存储器开口填充结构各自包括竖直半导体沟道和位于所述导电层的层级处的存储器元件的竖直堆叠;
位线,所述位线电连接到所述多个存储器开口填充结构的相应子集;
阶梯式介电材料部分,所述阶梯式介电材料部分位于所述交替堆叠的阶梯式表面上;和
层接触通孔结构,所述层接触通孔结构竖直地延伸穿过所述阶梯式介电材料部分并且接触所述导电层中的相应导电层。
11.根据权利要求10所述的结构,其中接合到所述存储器管芯中的所述一个存储器管芯的所述逻辑管芯中的一个逻辑管芯包含:
感测放大器区,所述感测放大器区包括电连接到所述位线中的相应位线的感测放大器;和
外围器件区,所述外围器件区包括电荷泵电路。
12.根据权利要求11所述的结构,其中所述外围器件区位于所述感测放大器区与所述逻辑侧外部接合衬垫之间。
13.根据权利要求1所述的结构,其中所述逻辑管芯中的至少一个逻辑管芯包含:
穿通衬底通孔结构,所述穿通衬底通孔结构竖直地延伸穿过逻辑管芯衬底并且电连接到所述逻辑侧外部接合衬垫中的相应逻辑侧外部接合衬垫;和
逻辑管芯金属互连结构,所述逻辑管芯金属互连结构嵌入逻辑管芯介电材料层中并且将所述逻辑管芯衬底上的相应逻辑器件电连接到所述逻辑侧管芯间接合衬垫中的相应逻辑侧管芯间接合衬垫。
14.一种形成包括堆叠式管芯组件的结构的方法,所述方法包括:
提供多个接合单元,其中每个接合单元包含存储器管芯并且包含逻辑管芯,所述存储器管芯包括位于所述存储器管芯的相对主表面上的存储器侧管芯间接合衬垫和存储器侧外部接合衬垫,所述逻辑管芯包括逻辑电路,所述逻辑电路被配置为控制所述存储器管芯的操作并且包括位于所述逻辑管芯的相对主表面上的逻辑侧管芯间接合衬垫和逻辑侧外部接合衬垫;
通过将所述多个接合单元彼此附接来形成所述多个接合单元的竖直堆叠,使得所述多个接合单元的所述存储器侧外部接合衬垫和所述逻辑侧外部接合衬垫形成面朝上的外部接合衬垫集合和面朝下的外部接合衬垫集合,所述面朝上的外部接合衬垫集合具有面朝上的物理暴露表面,所述面朝下的外部接合衬垫集合具有面朝下的物理暴露表面;
形成第一接合引线集合,所述第一接合引线集合连接所述面朝上的外部接合衬垫集合中的一对相应的面朝上的外部接合衬垫;以及
形成第二接合引线集合,所述第二接合引线集合连接所述面朝下的外部接合衬垫集合中的一对相应的面朝下的外部接合衬垫。
15.根据权利要求14所述的方法,其中通过接合相应逻辑管芯和相应存储器管芯来提供每个接合单元,使得所述相应逻辑管芯的逻辑侧管芯间接合衬垫接合到所述相应存储器管芯的存储器侧管芯间接合衬垫中的相应存储器侧管芯间接合衬垫。
16.根据权利要求14所述的结构,其中所述多个接合单元交错,使得每个上覆接合单元相对于下层接合单元沿着第一水平方向横向偏移。
17.根据权利要求14所述的方法,所述方法还包括通过采用粘合层附接竖直相邻的接合单元对来形成所述多个接合单元的所述竖直堆叠。
18.根据权利要求17所述的方法,所述方法还包括:
采用附加粘合层将安装衬底附接到所述多个接合单元的所述竖直堆叠;以及
通过将附加接合引线附接到位于所述安装衬底上的接合衬垫和所述多个接合单元的所述竖直堆叠之间的最近端接合单元的外部接合衬垫来将所述多个接合单元的所述竖直堆叠电连接到所述安装衬底。
19.根据权利要求14所述的方法,其中提供多个接合单元包括通过将相应存储器管芯和相应逻辑管芯彼此接合来形成所述多个接合单元中的每个接合单元。
20.根据权利要求14所述的方法,所述方法还包括将所述多个接合单元彼此附接,使得:
所述堆叠式管芯组件内的每个面朝上的外部接合衬垫在沿着所述接合单元堆叠所沿的方向的平面图中与所述堆叠式管芯组件内的任何上覆接合单元不具有面积重叠;并且
所述堆叠式管芯组件内的每个面朝下的外部接合衬垫在所述平面图中与所述堆叠式管芯组件内的任何下层接合单元不具有面积重叠。
21.一种包含堆叠式管芯组件的结构,其中所述堆叠式管芯组件包含:
多个接合单元的竖直堆叠,其中每个接合单元包含相应正面半导体管芯和相应背面半导体管芯,所述相应正面半导体管芯包括正面外部接合衬垫,所述相应背面半导体管芯包括背面外部接合衬垫,其中所述相应背面半导体管芯接合到所述相应正面半导体管芯,并且其中每个接合单元的所述正面外部接合衬垫具有面朝上的物理暴露表面,并且每个接合单元的所述背面外部接合衬垫具有面朝下的物理暴露表面;
第一接合引线集合,所述第一接合引线集合连接所述正面外部接合衬垫;和
第二接合引线集合,所述第二接合引线集合连接所述背面外部接合衬垫。
22.根据权利要求21所述的结构,其中所述正面半导体管芯还包含正面存储器阵列,并且所述背面半导体管芯还包含背面存储器阵列。
23.根据权利要求22所述的结构,其中:
每个接合单元内的所述正面半导体管芯包含嵌入正面介电材料层中的正面金属互连结构,其中所述正面金属互连结构的子集连接到每个接合单元内的所述正面外部接合衬垫;并且
每个接合单元内的所述背面半导体管芯包含嵌入背面介电材料层中的背面金属互连结构,其中所述背面金属互连结构的子集连接到每个接合单元内的所述背面外部接合衬垫。
24.根据权利要求21所述的结构,其中:
每个接合单元内的所述正面半导体管芯包含正面衬底;
每个接合单元内的所述背面半导体管芯包含背面衬底;并且
所述正面衬底接合到所述背面衬底。
25.根据权利要求24所述的结构,其中相同接合单元中的所述背面半导体管芯和所述正面半导体管芯彼此不直接电连接。
26.根据权利要求21所述的结构,其中:
每对竖直相邻的接合单元包含上覆接合单元和下层接合单元;并且
所述上覆接合单元相对于所述下层接合单元沿着第一水平方向横向偏移。
27.根据权利要求26所述的结构,其中:
每个正面半导体管芯内的正面外部接合衬垫沿着所述第一水平方向以均匀横向偏移距离与所述正面半导体管芯的边缘横向偏移;并且
所述相应正面半导体管芯的所述边缘沿着垂直于所述第一水平方向的第二水平方向横向延伸。
28.根据权利要求26所述的结构,其中:
背面半导体管芯内的背面外部接合衬垫以均匀横向偏移距离与所述背面半导体管芯的边缘横向偏移;并且
所述背面半导体管芯的所述边缘沿着垂直于所述第一水平方向的第二水平方向横向延伸。
29.根据权利要求21所述的结构,其中:
所述堆叠式管芯组件内的每个正面外部接合衬垫在沿着所述接合单元堆叠所沿的方向的平面图中与所述堆叠式管芯组件内的任何上覆接合单元不具有面积重叠;并且
所述堆叠式管芯组件内的每个背面外部接合衬垫在所述平面图中与所述堆叠式管芯组件内的任何下层接合单元不具有面积重叠。
30.根据权利要求21所述的结构,其中每对竖直相邻的接合单元通过相应粘合层彼此附接。
31.根据权利要求30所述的结构,所述结构还包含:
安装衬底,多个接合单元的所述竖直堆叠通过附加粘合层安装在所述安装衬底上;和
附加接合引线,所述附加接合引线提供位于所述安装衬底上的接合衬垫与所述堆叠式管芯组件的所述接合单元之间的最近端接合单元的正面外部接合衬垫和背面外部接合衬垫之间的电连接。
32.根据权利要求21所述的结构,其中所述正面半导体管芯和所述背面半导体管芯中的每一者还包含:
相应逻辑电路,所述相应逻辑电路包括位于相应衬底上并且被配置为控制所述相应存储器阵列内的存储器元件的操作的半导体器件;和
相应金属互连结构,所述相应金属互连结构嵌入相应介电材料层中并且提供所述相应逻辑电路的所述半导体器件与所述相应存储器阵列内的所述存储器元件之间的电连接。
33.根据权利要求32所述的结构,其中所述相应存储器阵列包含:
绝缘层和导电层的竖直交替堆叠;
多个存储器开口填充结构,所述多个存储器开口填充结构各自包括相应竖直半导体沟道和位于所述导电层的层级处的存储器元件的相应竖直堆叠;
位线,所述位线电连接到所述多个存储器开口填充结构的相应子集;
阶梯式介电材料部分,所述阶梯式介电材料部分位于所述交替堆叠的阶梯式表面上;和
层接触通孔结构,所述层接触通孔结构竖直地延伸穿过所述阶梯式介电材料部分并且接触所述导电层中的相应导电层。
34.一种形成包括堆叠式管芯组件的结构的方法,所述方法包括:
提供多个接合单元,其中每个接合单元包含相应正面半导体管芯和相应背面半导体管芯,所述相应正面半导体管芯包括正面外部接合衬垫,所述相应背面半导体管芯包括背面外部接合衬垫,其中所述相应背面半导体管芯接合到所述相应正面半导体管芯;
通过将所述多个接合单元彼此附接来形成所述多个接合单元的竖直堆叠,使得每个接合单元的所述正面外部接合衬垫具有面朝上的物理暴露表面,并且每个接合单元的所述背面外部接合衬垫具有面朝下的物理暴露表面;
形成连接一对相应的正面外部接合衬垫的第一接合引线集合;以及
形成连接一对相应的背面外部接合衬垫的第二接合引线集合。
35.根据权利要求34所述的方法,其中所述正面半导体管芯还包含正面存储器阵列,并且所述背面半导体管芯还包含背面存储器阵列。
36.根据权利要求35所述的方法,其中:
每个接合单元内的所述正面半导体管芯包含正面衬底;
每个接合单元内的所述背面半导体管芯包含背面衬底;并且
所述正面衬底接合到所述背面衬底。
37.根据权利要求36所述的方法,其中相同接合单元中的所述背面半导体管芯和所述正面半导体管芯彼此不直接电连接。
38.根据权利要求34所述的结构,其中所述多个接合单元交错,使得每个上覆接合单元相对于下层接合单元沿着第一水平方向横向偏移。
39.根据权利要求34所述的方法,所述方法还包括通过采用粘合层附接竖直相邻的接合单元对来形成所述多个接合单元的所述竖直堆叠。
40.根据权利要求39所述的方法,所述方法还包括:
采用附加粘合层将安装衬底附接到所述多个接合单元的所述竖直堆叠;以及
通过将附加接合引线附接到位于所述安装衬底上的接合衬垫和所述多个接合单元的所述竖直堆叠之间的最近端接合单元的正面外部接合衬垫或背面外部接合衬垫来将所述多个接合单元的所述竖直堆叠电连接到所述安装衬底。
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PCT/US2020/067424 WO2021242322A1 (en) | 2020-05-28 | 2020-12-30 | Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same |
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