CN114826849A - DSP local reconstruction method and system for communication signal identification processing - Google Patents
DSP local reconstruction method and system for communication signal identification processing Download PDFInfo
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Abstract
The invention belongs to the technical field of general signal processing, and discloses a communication signal identification processing-oriented DSP local reconstruction method and system. The invention mainly utilizes the multi-core characteristic of the DSP of the signal processing platform to realize the parallel processing of the signal processing algorithm. The work flow of the algorithm core is simple, and the algorithm core is only responsible for processing the algorithm and outputting the result after the result processing is finished. All algorithm cores are in a parallel mode, data and results among the algorithm cores are not interfered with each other, and normal operation of other cores is not influenced by breakdown of one core. The invention fully utilizes the multi-core characteristic of the DSP and greatly improves the parallel efficiency of the system.
Description
Technical Field
The invention belongs to the technical field of general signal processing, and particularly relates to a communication signal identification processing-oriented DSP local reconstruction method and system.
Background
At present, the new generation of avionics system needs to face the problems of complex digital signal types, large data volume, high real-time requirement, limited volume and the like. Although hardware processing equipment is high in updating speed and performance index of a processor is improved, application requirements such as instantaneity, high efficiency and expandability are simultaneously met on one platform, a single-core processing platform cannot meet the processing requirements, a DSP chip of a current mainstream digital signal processing platform has strong floating point computing capability and real-time processing capability, development of multi-core DSP enables the DSP chip to have excellent processing capability under the scenes of multi-condition operation and complex algorithm, and system heat dissipation, resource saving and computing efficiency are considered while the overall performance of a system is improved.
In the aspect of modulation identification technology, along with the complicated development of modern signal types and the increasing scarcity of communication environment resources, the identification of communication signals becomes especially critical. Modulation mode identification has received widespread attention in civilian and military applications. Due to the complexity and diversity of the current signal modulation modes and channel transmission environments, signal modulation mode identification for uncooperative communication becomes particularly important.
Through the above analysis, the problems and defects of the prior art are as follows: because real-time performance, high efficiency and expandability are simultaneously met on one platform, the existing single-core processing platform cannot meet the processing requirements. At present, the mainstream digital signal processing hardware platform comprises three types, namely a field programmable array FPGA, a special ASIC chip and a digital signal processor DSP, wherein the former two types can only process relatively fixed tasks in signal processing due to the limitation of a hardware system, and the flexible algorithm adjustment cannot be realized. Complex algorithm deployments in multi-conditional operations and complex transaction management application scenarios are difficult to accomplish. If the multiprocessor architecture interconnection scheme is used for overcoming the hardware defects by using the quantity advantage, the overall computing performance and the task concurrency capability of the signal processing platform can be improved theoretically, but more interfaces and scheduling schemes are needed for cooperative work among the multiprocessors. The system hardware resource and power consumption overhead are greatly increased, the difficulty of layout and wiring among processors is brought, the board card is overlarge in size, the most serious problem is that the multiprocessor causes the difficulty of heat dissipation of the board card, and the stability and reliability of a chip are greatly reduced due to overhigh temperature of the board card.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a communication signal identification processing-oriented DSP local reconstruction method and a system.
The invention is realized in such a way that a communication signal identification processing-oriented DSP local reconstruction method comprises the following steps:
the method combines the modulation mode identification of signals, the local reconstruction of multi-core and the parallelization algorithm processing, reasonably distributes the three tasks to a bottom core, and takes a core 0 as a main control to be responsible for the communication and the scheduling of the system; the core 1 is used as an identification core to identify and process external signals; the remaining 6 cores are processed in parallel and are responsible for the execution of specific demodulation algorithms.
Modulation mode identification
The invention is oriented to the modulation mode identification of general signals, researches the current mainstream signal modulation mode identification algorithm, combines the hardware characteristics of the system and the application requirements, and selects an extraction identification method based on the modulation signal characteristic value. After simulation experiments, the recognition performance of the signal is not high under the condition of low signal-to-noise ratio, so that the method provides that the high-order cumulant parameter and the spectral characteristic parameter of the signal are added on the basis of the original recognition mode to enhance the recognition characteristic, and the experimental result proves that the scheme can effectively reduce noise interference and improve the recognition accuracy. The influence of noise in the transmission process is perfectly avoided by using the high-order characteristic of the signal.
② local reconstruction of multiple nuclei
The local reconstruction is adopted, the algorithm identification core can send an identification result to the main control core after identifying the modulation mode, the main control core immediately selects a corresponding demodulation reconstruction algorithm, and the selection of the reconstruction algorithm mainly depends on an algorithm matching mechanism: and after the identification result is delivered to the main control core by the identification core, the main control core matches the identification result with the algorithm characteristic ID set in advance to find the entry address of the algorithm to be reconstructed. The core to be reconfigured is selected based on the busy-idle status of the bottom core, which will poll the bottom core sequentially and assign the algorithm task to the first idle core. This flow is an automated processing logic and therefore does not require a decision to be made by the upper level system. Meanwhile, the real-time requirement of the system can be ensured by using local reconstruction of the local mode.
Further, the communication signal identification processing-oriented DSP local reconstruction method comprises the following steps:
firstly, an SPI interface starting mode is adopted, a main control core is started first and is responsible for normal operation of the whole system, after the system is powered on, the main control core operates normally, other cores are in an IDLE state, and the main control core starts initialization work of various communication interfaces and peripheral equipment of the system;
step two, the core 0 starts an algorithm to identify the core 1, the core 1 identifies the modulation mode of the signal through the obtained modulation identification mode after receiving the signal to be identified, the identification result is delivered to the main control core after the identification is finished, and the main control core matches a demodulation algorithm corresponding to the modulation mode through analyzing the identification result;
step three, when the main control core receives the reconfiguration command, the identification result is compared with the program information which is well distributed, and the comparison is based on that the ID number of the modulation mode corresponds to the corresponding demodulation algorithm, so that the entry address of the demodulation algorithm is found;
analyzing the busy-idle state of the bottom core, and distributing a reconstruction algorithm to the idle core with the minimum core number; and writing an entry address of a new algorithm program in the BootMagic _ addr address of the core, and sending IPC interrupt to the core by the main control core to wake up the core to run a corresponding demodulation algorithm after the writing is finished.
Further, the BootMagic _ addr address is an entry address after the core reruns.
Further, the work flow of the main control core comprises:
(1) after the system runs, a plurality of task threads are created, a Bios _ start () function is run to start the real-time operating system, and a number 0 main control core is started to start running;
(2) initializing all global variables, semaphores and hardware resources of the system by a system main task thread, and creating a monitoring interrupt thread; monitoring whether a reconstruction instruction arrives or not, and performing reconstruction operation after receiving the reconstruction instruction;
(3) triggering hardware interruption after a reconfiguration command arrives, and enabling the main control core to enter a reconfiguration flow and analyze the command; judging a kernel needing to be reconstructed, a mirror image reconstruction algorithm and whether a remote transmission mirror image is adopted or a mirror image is read from a local Flash through an instruction; if the mirror image is read from the remote end, triggering the network communication task to read the mirror image data from the remote end; if the local mode is reconstructed, loading a corresponding mirror image from Flash; the selection of the kernel for loading the reconstruction algorithm is based on the kernel which is idle at the current moment.
Further, the workflow of the identification core comprises:
(1) the software of the identification core is awakened and started by the main control core after the main control core is electrified and loaded on the DSP, and is used for operating a modulation identification algorithm for realizing programming and carrying out classification identification on signals to be identified;
(2) while monitoring interrupt information, initializing global variables and semaphores, and then configuring SRIO hardware, wherein external data is input through SRIO bus transmission, and the method waits for the availability of semaphores circularly and waits for external interrupt to inform that a new signal comes;
(3) when an external signal comes temporarily, hardware interruption is generated, the system releases semaphore, the main task carries out communication signal modulation mode identification, and an identification result is delivered to the main control core after the identification is finished; and after the main control core carries out corresponding reconfiguration scheduling, the main task continues to be suspended until a new signal comes.
Further, the workflow of the algorithm core comprises:
(1) initializing a task running environment after establishing synchronization with a master control core, wherein global variables are initialized;
(2) and continuously monitoring, processing the data through an algorithm flow after the data are read, and sending a processing result back to the main control core or directly outputting the processing result after the processing is finished.
Another object of the present invention is to provide a communication signal identification processing-oriented DSP local reconstruction system applying the communication signal identification processing-oriented DSP local reconstruction method, including:
8 cores at the bottom layer of the DSP are allocated with relevant tasks; aiming at the multi-core characteristic of the DSP, the modulation mode identification of signals, the local reconstruction of multi-core and the parallelization algorithm processing are combined, tasks are distributed to a bottom core, and a 0 core is used as a master control to be responsible for the communication and scheduling of the system; the core 1 is used as an identification core to identify and process external signals; the remaining 6 cores are processed in parallel and are responsible for the execution of specific demodulation algorithms.
The main control core is responsible for scheduling other slave cores, identifies communication signals through the No. 1 core and then informs the No. 0 core to reconstruct, and further dynamically updates software on other cores, wherein the software on the main control core consists of a system reconstruction main task, a reconstruction command for receiving the No. 1 core and two interrupts;
the core number of the identification core is 1, and the identification core is used for operating a communication signal identification algorithm, identifying a new signal, delivering an identification result to the main control core, and further performing local reconstruction of the idle core;
the algorithm cores are used for processing various signal processing tasks distributed by the main control core, and the plurality of algorithm cores are issued with different algorithm processing tasks at idle time; the main control core controls the operation and stop of each algorithm core, and the specific algorithm file is updated by the main control core; only one task thread is arranged on the algorithm core, and a dead loop is responsible for continuously polling and monitoring a new task.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of:
and (3) reconstructing by adopting a local mode, identifying the modulation mode by using the algorithm identification core, sending an identification result to the main control core, and dynamically updating the algorithm of the idle algorithm core at the bottom layer by selecting a corresponding demodulation algorithm by the main control core.
It is another object of the present invention to provide a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
and (3) reconstructing by adopting a local mode, identifying the modulation mode by using the algorithm identification core, sending an identification result to the main control core, and dynamically updating the algorithm of the idle algorithm core at the bottom layer by selecting a corresponding demodulation algorithm by the main control core.
Another object of the present invention is to provide an information data processing terminal, which is used for implementing the communication signal identification processing-oriented DSP local reconstruction system.
In combination with the technical solutions and the technical problems to be solved, please analyze the advantages and positive effects of the technical solutions to be protected in the present invention from the following aspects:
first, aiming at the technical problems existing in the prior art and the difficulty in solving the problems, the technical problems to be solved by the technical scheme of the present invention are closely combined with results, data and the like in the research and development process, and some creative technical effects are brought after the problems are solved. The specific description is as follows:
the invention designs and realizes a DSP dynamic reconstruction system based on communication signal modulation mode identification by taking communication signal modulation mode identification as background, utilizing the multi-core characteristic of DSP and taking the dynamic scheduling and parallel architecture of DSP as core, and utilizes the multi-core characteristic of DSP while realizing modulation mode identification. Meanwhile, the characteristic value selection of the modulation signal identification is improved to a certain extent based on the hardware characteristic of the DSP, and the instantaneous characteristic of the modulation signal, the high-order characteristic of the signal and the cyclic spectrum envelope characteristic value of the signal are combined, so that the effective identification of the intra-class and inter-class modulation modes of the general digital signal is realized.
Firstly, the identification task of the conventional modulation signal is realized. The identification process comprises the steps of signal noise estimation, signal carrier frequency estimation, signal time-frequency characteristic parameter extraction and decision tree-based classifier identification classification, and 90% of identification accuracy can be achieved when the signal-to-noise ratio is larger than 5 dB. Meanwhile, the experimental result is analyzed, and the parameter characteristics of the signal under the condition of low signal-to-noise ratio are not obvious and are seriously interfered by noise, so that the method for classifying the in-class modulation mode by respectively extracting obvious characteristic values and enveloping mean value characteristics by using the high-order cumulant and the cyclic spectrum of the signal is provided. Experimental results show that noise interference can be significantly reduced using these two approaches.
Secondly, by utilizing the hardware characteristics of a multi-core DSP, selecting a TMS320C6678 chip of TI as a processing board card, and matching 8 industrial-level cores C66x on the bottom layer of the DSP, because the models of the cores are completely the same, 8 cores on the chip can execute one task at the same time and execute a plurality of tasks in parallel, the invention takes a core 0 as a main control core and is responsible for completing the control and task issuing of the remaining 7 cores, when reconstruction is needed, a reconstruction file sent by external equipment can be received in a remote reconstruction mode, a prestored mirror image file can be read from a local cache, and then the busy and idle state of the core at the bottom layer is inquired, the new and old algorithm of the core is replaced, so that the dynamic switching of the core algorithm program is realized, the reconstruction process is a local behavior and the normal work of other cores cannot be influenced; the core 1 is used as a modulation mode identification core and is responsible for the identification of the modulation mode; and 2-7 cores are used as processing cores and are responsible for completing demodulation processing logic of the allocation task.
Secondly, considering the technical scheme as a whole or from the perspective of products, the technical effect and advantages of the technical scheme to be protected by the invention are specifically described as follows:
the invention mainly utilizes the multi-core characteristic of the DSP of the signal processing platform to realize the parallel processing of the signal processing algorithm. The flow of the invention is an automatic processing logic, so the distribution choice of the upper-layer system is not needed, and the real-time requirement of the system can be ensured by using the local reconstruction of the local mode.
The work flow of the algorithm core is simple, and the algorithm core is only responsible for processing the algorithm and outputting the result after the result processing is finished. All algorithm cores are in a parallel mode, data and results among the algorithm cores are not interfered with each other, and normal operation of other cores is not influenced by breakdown of one core. The invention fully utilizes the multi-core characteristic of the DSP and greatly improves the parallel efficiency of the system.
Third, as an inventive supplementary proof of the claims of the present invention, there are also presented several important aspects:
(1) the expected income and commercial value after the technical scheme of the invention is converted are as follows:
for civil use, the government needs to monitor signal transmission in real time in order to scientifically and reasonably manage radio spectrum, so as to ensure timely analysis and processing when special conditions occur. All identification work in the process requires the use of modulation identification technology. The identification processing process can be more efficient by matching with an integrated signal processing platform.
The method has very key effects on the aspects of military affairs and national safety which have great influence on China, particularly in the process of electronic countermeasure against foreign countries. In the electronic countermeasure, the communication countermeasure has a very important position in the electronic warfare, mainly comprises two parts of communication reconnaissance and communication interference, is mainly responsible for interception, analysis, identification and the like in the application scene, and finally, an effective processing scheme is made, so that the aim of destroying enemies is fulfilled. The safety coefficient of the flexible and miniaturized multi-standard signal processing platform is improved to the greatest extent.
(2) The technical scheme of the invention fills the technical blank in the industry at home and abroad:
the current signal processing platform mainly has the following defects:
firstly, after the modulation mode of the signal is identified, a demodulation algorithm is programmed into the signal processing platform again by manpower, and the programming process in the process can cause poor real-time performance of the system.
Secondly, the integration level of the system is not enough, most modulation recognition algorithms run on a computer, signal processing algorithms run on hardware equipment, and the data interaction problem between the two and the size problem of the platform are not beneficial to the technical development under the current situation.
The invention combines the two processes, and realizes the research of the modulation recognition algorithm with high recognition rate and the flexible hardware processing logic under the same platform.
(3) The technical scheme of the invention solves the technical problems which are always desired to be solved but are not successfully achieved: and (4) the integration development of a signal processing platform.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a local DSP reconstruction method for communication signal identification processing according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a DSP local reconstruction method for communication signal identification processing according to an embodiment of the present invention;
fig. 3 is a flowchart of the operation of a master core according to an embodiment of the present invention;
FIG. 4 is a detailed flow chart of an algorithm identifying core provided by an embodiment of the present invention;
fig. 5 is a schematic waveform diagram of a 2ASK modulation signal provided by an embodiment of the present invention;
fig. 6 is a schematic diagram of a 2ASK recognition result provided in the embodiment of the present invention;
fig. 7 is a schematic diagram of a 2ASK demodulation waveform provided by an embodiment of the present invention;
fig. 8 is a schematic diagram of a 2FSK modulation signal waveform provided by an embodiment of the present invention;
fig. 9 is a schematic diagram of a 2FSK identification result according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a demodulation waveform of 2FSK according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a waveform of a 2PSK modulation signal according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a 2PSK identification result according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a demodulation waveform of 2PSK according to an embodiment of the present invention;
FIG. 14 is a diagram illustrating a modulation waveform before kernel 2 reconstruction according to an embodiment of the present invention;
FIG. 15 is a diagram illustrating a modulation waveform after kernel 2 reconstruction according to an embodiment of the present invention;
fig. 16 is a diagram illustrating the improved accuracy of modulated signal identification provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In view of the problems in the prior art, the present invention provides a method and a system for local reconstruction of a DSP oriented to communication signal identification processing, which are described in detail below with reference to the accompanying drawings.
First, an embodiment is explained. This section is an explanatory embodiment expanding on the claims so as to fully understand how the present invention is embodied by those skilled in the art.
As shown in fig. 1, the method for local reconstruction of a DSP for communication signal identification processing according to an embodiment of the present invention includes the following steps:
s101, an SPI interface starting mode is adopted, a main control core is started first and is responsible for normal operation of the whole system, after the system is powered on, the main control core operates normally, other cores are in an IDLE state, and the main control core starts initialization work of various communication interfaces and peripheral equipment of the system;
s102, a core 1 is identified by a core 0 starting algorithm, after the core 1 receives a signal to be identified, the modulation mode of the signal is identified by the obtained modulation identification mode, after the identification is finished, the identification result is delivered to a main control core, and the main control core analyzes the identification result and matches a demodulation algorithm corresponding to the modulation mode;
s103, when the main control core receives the reconfiguration command, the identification result is compared with the program information which is well distributed, and the comparison is based on that the ID number of the modulation mode corresponds to the corresponding demodulation algorithm, so that the entry address of the demodulation algorithm is found;
s104, analyzing the busy and idle state of the bottom core, and distributing a reconstruction algorithm to the idle core with the minimum core number; and writing an entry address of a new algorithm program in the BootMagic _ addr address of the core, and sending IPC interrupt to the core by the main control core to wake up the core to run a corresponding demodulation algorithm after the writing is finished.
The DSP local reconstruction system for communication signal identification processing provided by the embodiment of the invention comprises:
8 cores at the bottom layer of the DSP are allocated with relevant tasks; aiming at the multi-core characteristic of the DSP, the modulation mode identification of signals, the local reconstruction of multi-core and the parallelization algorithm processing are combined, tasks are distributed to a bottom core, and a 0 core is used as a master control to be responsible for the communication and scheduling of the system; the core 1 is used as an identification core to identify and process external signals; the remaining 6 cores are processed in parallel and are responsible for the execution of specific demodulation algorithms.
The master control core is responsible for scheduling other slave cores, identifies communication signals through the core No. 1 and then informs the core No. 0 to reconstruct, and further dynamically updates software on other cores, wherein the software on the master control core consists of a system reconstruction main task, a reconstruction command for receiving the core No. 1 and two interrupts;
the core number of the identification core is 1, and the identification core is used for operating a communication signal identification algorithm, identifying a new signal, delivering an identification result to the main control core, and further performing local reconstruction of the idle core;
the algorithm cores are used for processing various signal processing tasks distributed by the main control core, and the plurality of algorithm cores are issued with different algorithm processing tasks at idle time; the main control core controls the operation and stop of each algorithm core, and the specific algorithm file is updated by the main control core; the algorithm core is provided with only one task thread, and a dead loop is responsible for continuously polling and monitoring a new task.
Example 1: rule design for dynamic reconfiguration
The reconstruction mode adopted by the invention is the reconstruction of a local mode, because the algorithm identification core can send the identification result to the main control core after identifying the modulation mode, and the main control core immediately selects a corresponding demodulation algorithm to dynamically update the algorithm for the idle algorithm core at the bottom layer. This flow is an automated processing logic and therefore does not require a decision to be made by the upper level system. Meanwhile, the real-time requirement of the system can be ensured by using local reconstruction of the local mode.
The invention adopts the SPI interface starting mode, firstly, the main control core is started first to be responsible for the normal operation of the whole system, after the system is electrified, the main control core operates normally, other cores are in an IDLE state, and at the moment, the main control core can start to carry out initialization work of various communication interfaces, peripheral equipment and the like of the system. Then, the 0 core starts an algorithm identification core 1, the 1 core identifies the modulation mode of the signal through the modulation identification mode provided in the previous section after receiving the signal to be identified, the identification result is handed to the main control core after the identification is finished, the main control core matches a demodulation algorithm corresponding to the modulation mode through analyzing the identification result, and the identification process is as shown in fig. 2.
When the main control core receives the reconfiguration command, the identification result is compared with the program information which is well distributed, and the basis of comparison is that the ID number of the modulation mode corresponds to the corresponding demodulation algorithm, so that the entry address of the demodulation algorithm is found. And then analyzing the busy-idle state of the bottom layer core, allocating the reconstruction algorithm to the idle core with the minimum core number, writing an entry address of a new algorithm program into the BootMagic _ addr address of the core (the address is the entry address of the core after the core is rerun), and sending IPC interrupt to the core by the main control core after the writing is finished so as to awaken the core to run a corresponding demodulation algorithm.
Example 2
The invention designs and realizes a DSP dynamic reconfiguration system based on communication signal modulation mode identification by taking communication signal modulation mode identification as background, utilizing the multi-core characteristic of DSP and taking the dynamic scheduling and parallel architecture of DSP as core, and utilizes the multi-core characteristic of DSP while realizing modulation mode identification. Meanwhile, the characteristic value selection of the modulation signal identification is improved to a certain extent based on the hardware characteristic of the DSP, and the instantaneous characteristic of the modulation signal, the high-order characteristic of the signal and the cyclic spectrum envelope characteristic value of the signal are combined, so that the effective identification of the intra-class and inter-class modulation modes of the general digital signal is realized.
And 8 cores at the bottom of the DSP are allocated with relevant tasks. Aiming at the multi-core characteristic of the DSP, the modulation mode identification of signals, the local reconstruction of multi-core and the parallelization algorithm processing are combined, the three tasks are reasonably distributed to a bottom core, and a 0 core is used as a main control to be responsible for the communication and the scheduling of the system; the core 1 is used as an identification core to identify and process external signals; the remaining 6 cores are processed in parallel and are responsible for the execution of specific demodulation algorithms.
Firstly, designing functions of a master control core:
in the multi-core system, the master control core is responsible for scheduling other slave cores, and notifies the core No. 0 to reconstruct after identifying the communication signal through the core No. 1. And then dynamically updating the software on other cores, wherein the software on the main control core mainly comprises two tasks (a system reconstructs a main task and receives a reconstruction command of the No. 1 core) and two interrupts.
As shown in fig. 3, the main control core work flow is as follows:
1. after the system runs, a plurality of task threads are firstly created, then a Bios _ start () function is run to start the real-time operating system, and the number 0 master control core starts to run.
2. The system main task thread firstly initializes all global variables, semaphores and hardware resources of the system, and then creates a monitoring interrupt thread; monitoring whether a reconstruction instruction arrives or not, and performing reconstruction operation after receiving the reconstruction instruction.
3. And triggering hardware interruption after a reconfiguration command arrives, and then enabling the main control core to enter a reconfiguration flow to analyze the command. And judging which core needs to be reconstructed through the instruction, and using which algorithm to reconstruct the mirror image, wherein the remote transmission mirror image is adopted or the mirror image is read from the local Flash. And if the image is read from the remote end, triggering the network communication task to read the image data from the remote end. If the local mode is reconstructed, loading the corresponding mirror image from Flash. The selection of the kernel for loading the reconstruction algorithm is based on the kernel which is idle at the current moment.
Second, design of recognition core function
In the present system, the core number of the identification core is 1. The identification core mainly runs a communication signal identification algorithm, identifies a new signal, and then delivers an identification result to the main control core so as to perform local reconstruction of the idle core. The core is crucial to realizing the intellectualization and automation of the system, and the corresponding demodulation algorithm can be selected to obtain the information content only if the modulation signal type is accurately identified.
As shown in fig. 4, the specific flow of the algorithm to identify the kernel is as follows:
1. the software of the identification core is started by the main control core after the DSP is powered on and loaded. The working content of the method is to run a programmed modulation recognition algorithm to classify and recognize signals to be recognized.
2. While monitoring the interrupt information, the initialization of global variables and the initialization of semaphores are carried out, and then the configuration of the SRIO hardware is carried out, because the input of external data is transmitted through the SRIO bus, and then the cyclic waiting semaphores are available. Waiting for an external interrupt to signal the arrival of a new signal.
3. When an external signal comes temporarily, hardware interruption is generated, the system releases semaphore, the main task carries out communication signal modulation mode identification, after the identification is finished, the identification result is delivered to the main control core, and then the main control core carries out corresponding reconfiguration scheduling. The main task then continues to suspend until a new signal comes.
Third, algorithm kernel function design
The specific work content of the algorithm cores is responsible for processing various signal processing tasks distributed by the main control core, and the plurality of algorithm cores are issued with different algorithm processing tasks at idle time. The main control core controls the operation and stop of each algorithm core, and the specific algorithm file is updated by the main control core. Only one task thread is arranged on the algorithm core, and a dead loop is responsible for continuously polling and monitoring a new task.
The work flow of the algorithm core is as follows:
1. initializing the task execution environment after establishing synchronization with the master core, including initializing global variables.
2. And continuously monitoring, processing the data through an algorithm flow after the data are read, and sending a processing result back to the main control core or directly outputting the processing result after the processing is finished.
The work flow of the algorithm core is simple, and the algorithm core is only responsible for processing the algorithm and outputting the result after the result processing is finished. All algorithm cores are in a parallel mode, data and results among the algorithm cores are not interfered with each other, and normal operation of other cores is not influenced by breakdown of one core. The multi-core characteristic of the DSP is fully utilized, and the parallel efficiency of the system is greatly improved.
And II, application embodiment. In order to prove the creativity and the technical value of the technical scheme of the invention, the part is the application example of the technical scheme of the claims on specific products or related technologies.
The invention mainly aims at a processor architecture taking DSP + FPGA as a core.
The FPGA module is used for receiving external signals and preprocessing the signals, and the DSP module is used for extracting the characteristics of the signals, classifying and identifying the signals and demodulating the signals. The demodulation algorithm file in the DSP can be burnt into an external Flash in advance for storage and can also be dynamically reconstructed in a remote mode, and the upper computer or other equipment sends the new algorithm file to an operating memory of a core to be reconstructed without the need of running a moving program by a main control core.
It should be noted that embodiments of the present invention can be realized in hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus and its modules of the present invention may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of hardware circuits and software, e.g., firmware.
And thirdly, evidence of relevant effects of the embodiment. The embodiment of the invention achieves some positive effects in the process of research and development or use, and has great advantages compared with the prior art, and the following contents are described by combining data, diagrams and the like in the test process.
Improvement of recognition accuracy
As shown in fig. 16, the improved identification scheme can effectively improve the identification accuracy at a low signal-to-noise ratio, and proves that the signal modulation identification performance can be improved by using the characteristic parameters of the signal in combination with the high-order statistics and the mean value of the cyclic spectrum envelope of the signal.
Bottom layer dynamic reconfiguration of two or more core DSPs
In order to test the scheduling and processing results of tasks in parallel mode. The core 0 and the core 1 respectively run respective scheduling and modulation mode identification algorithms, the core 3 and the core 5 are enabled to run partial algorithms, the core 2, the core 4 and the core 6 are firstly placed in an idle state and are distributed according to the algorithm of the figure, and when the tasks come, the core 2, the core 4 and the core 6 sequentially run 2ASK demodulation, 2FSK demodulation and 2PSK demodulation tasks according to the sequential distribution principle.
The carrier frequency estimation or the identification of the modulation mode of the signal is actually the calculation of the time frequency of the signal. Compared with Matlab, a program written by the DSP has poor precision, and the number of sampling bits is limited, so that the program has a certain deviation from actual data, but the error size needs to be analyzed whether the error size is in a reasonable range.
The experimental procedure was as follows:
(1) firstly, the Graph function of the DSP is used to extract the modulation signal waveform of 2ASK to obtain the modulation signal waveform shown in fig. 5, at this time, the signal data of 2ASK is delivered to the identification core to identify the modulation mode, the identification result is obtained and then output through the console as shown in fig. 6, the master control core schedules the current idle core No. 2 core to demodulate the 2ASK signal, and the demodulation waveform is shown in fig. 7.
(2) Firstly, the Graph function of the DSP is used for extracting the 2FSK modulation signal waveform to obtain the modulation signal waveform shown in figure 8, at the moment, the 2FSK signal data is delivered to the identification core to be identified in a modulation mode, the identification result is obtained and then output in figure 9 through the control console, the main control core schedules the current idle core No. 4 core to demodulate the 2FSK signal, and the demodulation waveform is shown in figure 10.
(3) Firstly, the Graph function of the DSP is used for extracting the modulation signal waveform of the 2PSK to obtain the modulation signal waveform shown in figure 11, at the moment, the signal data of the 2PSK is delivered to an identification core for identification of the modulation mode, the identification result is obtained and then output through a control console as figure 12, the main control core schedules the current idle core No. 4 core to demodulate the 2FSK signal, and the demodulation waveform is shown in figure 13.
When all cores are idle at the moment, if a new task to be identified appears at the moment, the new task is distributed to the core No. 2 again, and the core No. 2 carries out reconstruction task and outputs a demodulation signal waveform. The kernel 2 modulation waveforms before and after reconstruction are as shown in fig. 14 and 15.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A communication signal identification processing-oriented DSP local reconstruction method, comprising: combining signal modulation mode identification, multi-core local reconstruction and parallelization algorithm processing, reasonably allocating the three tasks to a bottom core, and taking a core 0 as a master control to be responsible for communication and scheduling of the system; the core 1 is used as an identification core to identify and process external signals; the remaining 6 cores are processed in parallel and are responsible for the execution of specific demodulation algorithms.
2. The communication signal identification process-oriented DSP local reconstruction method of claim 1, wherein said communication signal identification process-oriented DSP local reconstruction method comprises the steps of:
firstly, an SPI interface starting mode is adopted, a main control core is started first and is responsible for normal operation of the whole system, after the system is powered on, the main control core operates normally, other cores are in an IDLE state, and the main control core starts initialization work of various communication interfaces and peripheral equipment of the system;
step two, the core 0 starts an algorithm to identify the core 1, the core 1 identifies the modulation mode of the signal through the obtained modulation identification mode after receiving the signal to be identified, the identification result is delivered to the main control core after the identification is finished, and the main control core matches a demodulation algorithm corresponding to the modulation mode through analyzing the identification result;
step three, when the main control core receives the reconfiguration command, the identification result is compared with the program information which is well distributed, and the comparison is based on that the ID number of the modulation mode corresponds to the corresponding demodulation algorithm, so that the entry address of the demodulation algorithm is found;
analyzing the busy-idle state of the bottom core, and distributing a reconstruction algorithm to the idle core with the minimum core number; and writing an entry address of a new algorithm program in the BootMagic _ addr address of the core, and sending IPC interrupt to the core by the main control core to wake up the core to run a corresponding demodulation algorithm after the writing is finished.
3. The DSP local reconstruction method oriented to communication signal identification processing of claim 2, wherein the BootMagic _ addr address is an entry address after the core is re-run.
4. The communication signal recognition processing-oriented DSP local reconstruction method of claim 1, wherein the work flow of the master core includes:
(1) after the system runs, a plurality of task threads are created, a Bios _ start () function is run to start the real-time operating system, and a number 0 main control core is started to start running;
(2) initializing all global variables, semaphores and hardware resources of the system by a system main task thread, and creating a monitoring interrupt thread; monitoring whether a reconstruction instruction arrives or not, and performing reconstruction operation after receiving the reconstruction instruction;
(3) triggering hardware interruption after a reconfiguration command arrives, and enabling the main control core to enter a reconfiguration flow and analyze the command; judging a kernel needing to be reconstructed, a mirror image reconstruction algorithm and whether a remote transmission mirror image is adopted or a mirror image is read from a local Flash through an instruction; if the mirror image is read from the remote end, triggering the network communication task to read the mirror image data from the remote end; if the local mode is reconstructed, loading a corresponding mirror image from Flash; the selection of the kernel for loading the reconstruction algorithm is based on the kernel which is idle at the current moment.
5. The communication signal recognition processing-oriented DSP local reconstruction method of claim 1, wherein the workflow of the recognition core includes:
(1) the software of the identification core is awakened and started by the main control core after the main control core is electrified and loaded on the DSP, and is used for operating a modulation identification algorithm for realizing programming and carrying out classification identification on signals to be identified;
(2) while monitoring interrupt information, initializing global variables and semaphores, and then configuring SRIO hardware, wherein external data is input through SRIO bus transmission, and the method waits for the availability of semaphores circularly and waits for external interrupt to inform that a new signal comes;
(3) when an external signal comes temporarily, hardware interruption is generated, the system releases semaphore, the main task carries out communication signal modulation mode identification, and an identification result is delivered to the main control core after the identification is finished; and after the main control core carries out corresponding reconfiguration scheduling, the main task continues to be suspended until a new signal comes.
6. The communication signal recognition processing-oriented DSP local reconstruction method of claim 1, wherein the workflow of the algorithm core includes:
(1) initializing a task running environment after establishing synchronization with a master control core, wherein global variables are initialized;
(2) and continuously monitoring, processing the data through an algorithm flow after the data are read, and sending a processing result back to the main control core or directly outputting the processing result after the processing is finished.
7. A communication signal recognition processing-oriented DSP local reconstruction system for implementing the communication signal recognition processing-oriented DSP local reconstruction method according to any one of claims 1 to 6, characterized by comprising:
8 cores at the bottom layer of the DSP are allocated with relevant tasks; aiming at the multi-core characteristic of the DSP, the modulation mode identification of signals, the local reconstruction of multi-core and the parallelization algorithm processing are combined, tasks are distributed to a bottom core, and a 0 core is used as a master control to be responsible for the communication and scheduling of the system; the core 1 is used as an identification core to identify and process external signals; the rest 6 cores are processed in parallel and are responsible for executing a specific demodulation algorithm;
the main control core is responsible for scheduling other slave cores, identifies communication signals through the No. 1 core and then informs the No. 0 core to reconstruct, and further dynamically updates software on other cores, wherein the software on the main control core consists of a system reconstruction main task, a reconstruction command for receiving the No. 1 core and two interrupts;
the core number of the identification core is 1, and the identification core is used for running a communication signal identification algorithm, identifying a new signal, and then delivering an identification result to the main control core so as to perform local reconstruction of an idle core;
the algorithm cores are used for processing various signal processing tasks distributed by the main control core, and the plurality of algorithm cores are issued with different algorithm processing tasks at idle time; the main control core controls the operation and stop of each algorithm core, and the specific algorithm file is updated by the main control core; only one task thread is arranged on the algorithm core, and a dead loop is responsible for continuously polling and monitoring a new task.
8. A computer device, characterized in that the computer device comprises a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of:
and (3) reconstructing by adopting a local mode, identifying the modulation mode by using the algorithm identification core, sending an identification result to the main control core, and dynamically updating the algorithm of the idle algorithm core at the bottom layer by selecting a corresponding demodulation algorithm by the main control core.
9. A computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
and (3) reconstructing by adopting a local mode, identifying the modulation mode by using the algorithm identification core, sending an identification result to the main control core, and dynamically updating the algorithm of the idle algorithm core at the bottom layer by selecting a corresponding demodulation algorithm by the main control core.
10. An information data processing terminal characterized by being used for implementing the communication signal identification process-oriented DSP local reconstruction system according to claim 7.
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