CN104503939A - General information integrated processing system based on board-level high-speed bus - Google Patents

General information integrated processing system based on board-level high-speed bus Download PDF

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CN104503939A
CN104503939A CN 201410658682 CN201410658682A CN104503939A CN 104503939 A CN104503939 A CN 104503939A CN 201410658682 CN201410658682 CN 201410658682 CN 201410658682 A CN201410658682 A CN 201410658682A CN 104503939 A CN104503939 A CN 104503939A
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module
interface
data
information
processing module
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CN 201410658682
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CN104503939B (en
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费智婷
王倩
曹建文
张凤
王�华
顾鑫
张尧
李潇
邓志均
岑小锋
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中国运载火箭技术研究院
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling

Abstract

The invention discloses a general information integrated processing system based on a board-level high-speed bus. The general information integrated processing system adopts VPX bus architecture and consists of an integrated chassis, an interconnection module, a power module, an interface module, a master control module and a functional module. According to different task targets, different types of master control modules and functional modules are installed on the general information integrated processing system, and the VPX architecture-based hardware high-speed reconstruction before a task is executed is realized.

Description

一种基于板级高速总线的综合信息集成处理系统 An integrated information board high speed bus based integrated processing system

技术领域 FIELD

[0001] 本发明涉及一种基于板级高速总线的综合信息集成处理系统,属于信息技术领域。 [0001] The present invention relates to an integrated system board information-integration processing based on high speed bus, belonging to the field of information technology.

背景技术 Background technique

[0002] 传统的综合信息集成处理系统多采用CPCI总线与FPGA+DSP芯片组成并行处理系统,通常需要结合实际需求和性能指标自主设计一套集CPCI总线与FPGA、DSP等高速芯片于一体的专用系统,模块化和通用化水平较低,对外接口的标准不统一。 [0002] traditional integrated information processing system to use the integrated CPCI bus FPGA + DSP chips and parallel processing systems typically require the actual needs and performance of a set of independent design CPCI bus and FPGA, DSP chip in one of the high-speed dedicated system, low level of modularity and versatility, standard external interface is not uniform. CPCI并行处理系统在各个应用系统中体系结构不同,处理速率比较低(仅支持33MHz/66MHz的工作频率和32bit/64bit的数据位宽),环境适应性差,一般用于地面处理系统,在环境条件比较严苛(例如冲击较大)时易发生各种问题。 CPCI parallel processing systems in various applications in different system architectures, relatively low processing rate (operating frequency only supports 33MHz / 66MHz data bit and 32bit / 64bit), the difference in environmental adaptability, typically used for ground treatment systems, at ambient conditions Compare demanding various problems likely to occur when (eg greater impact).

[0003]目前,航空、航天、电子信息等领域的发展需要设计信号处理、图像处理、对外通信等多功能一体化的信息集成系统,需要信息集成系统具备统一的体系结构和较高的处理速度,具备模块化、通用化和功能可重构的能力,需要适应比较严苛的环境条件。 [0003] Currently, the development in the field of aviation, aerospace, electronics and information need to design signal processing, image processing, external communications and other functions integrated information system integration, information integration system needs to have a unified architecture and high processing speed , with modular, versatile and functional capacity reconfigurable, we need to adapt to relatively harsh environmental conditions.

[0004]目前国内还没有直接利用VPX架构设计严苛环境下综合信息集成处理系统的报道,相关的高速综合信息处理平台及其系统设计主要是针对地面和机载设备,其环境条件并不严苛,如《VPX架构及其模块在通信系统中的应用》一文,采用了VPX架构设计某通信设备,实现了某种通信算法和数据的处理,但该文并未提及设计信号处理、图像处理等多功能一体化信息集成系统,也不具备功能可重构的能力,并且其针对的应用对象是地面通信设备。 [0004] Currently no reported directly integrated information processing system of integrated VPX architecture under harsh environment, high-speed integrated information processing platform and its associated system design mainly for ground and airborne equipment, the environmental conditions are not strict harsh, such as "application module VPX architecture in a communication system and" a text, using the VPX architecture of a communication device, to achieve a certain processing algorithms and data communication, but this article does not mention the design signal processing, image integrated multifunction integrated information processing systems do not have the ability to function reconfigurable, and which application object is a ground for the communication device.

发明内容 SUMMARY

[0005] 本发明的技术解决问题:克服现有技术的不足,提供了一种基于板级高速总线的综合信息集成处理系统,可以满足严苛环境下信号处理、图像处理、对外通信等多功能一体化的信息集成需求。 [0005] The techniques of the present invention to solve the problem: to overcome the deficiencies of the prior art, there is provided an integrated information system integrated processing board based on a high-speed bus, signal processing, image processing, and other external communications meet the severe environments multifunction the integration of information integration needs.

[0006] 本发明的技术解决方案: [0006] The technical solution of the present invention:

[0007] 一种基于板级高速总线的综合信息集成处理系统,包括:VPX机箱、电源模块、互联模块、接口模块、主控模块、基带信号处理模块、图像处理模块、导航处理模块、射频模块和天线。 [0007] An integrated information processing integrated system on board a high-speed bus, comprising: VPX chassis, power modules, network module, interface module, a control module, a baseband signal processing module, an image processing module, the navigation processing module, a radio frequency module and antenna.

[0008] VPX机箱为符合VPX架构的金属导热方式的标准3U板卡7槽机箱,电源模块、互联模块、接口模块、主控模块、基带信号处理模块、图像处理模块、导航处理模块和射频模块装在VPX机箱内部,电源模块用于实现对外部输入+DC28V到VPX机箱内部所需直流电源的转换,并为其它各模块提供工作电源及过流、过压、欠压保护。 [0008] VPX VPX chassis to conform to the standard architecture of a thermally conductive metal boards embodiment 3U 7-slot chassis, power modules, network module, interface module, a control module, a baseband signal processing module, an image processing module, the processing module and the RF module navigation VPX mounted inside the chassis, a power module for enabling external DC power input + DC28V conversion desired to the internal chassis VPX and provide operating power to each of the other modules and overcurrent, overvoltage, undervoltage protection.

[0009] 接口模块、主控模块、基带信号处理模块、图像处理模块和导航处理模块通过插槽与互联模块连接,互联模块用于实现接口模块、主控模块、基带信号处理模块、图像处理模块和导航处理模块之间的信息交互;射频模块也通过插槽与互联模块连接,电源模块为射频模块供电,射频模块与其它模块之间有金属板隔离,防止电磁干扰。 [0009] interface module, control module, a baseband signal processing module, an image processing module and the navigation processing module socket module connected to the interconnection, interconnect module implements the interface module, a control module, a baseband signal processing module, an image processing module and information exchange between the navigation processing module; RF module is also connected to the network via the socket module, the power supply module is a radio frequency module, a metal plate between the RF isolation module with other modules, to prevent electromagnetic interference.

[0010] 接口模块用于实现信息交互,基带信号处理模块完成基带信号的扩频调制和扩频信号的接收解调,图像处理模块完成图像的压缩,导航处理模块将接收到的导航信号进行解算得到数字导航信息。 Navigation signal [0010] interface module for realizing the interactive information, the baseband signal processing module completes receiving and demodulating a spread spectrum signal spread spectrum modulated base band signal, an image processing module to complete the compression of images, navigation processing module received de Operators get digital navigation information.

[0011]当执行前向指令信息传输功能时,远端外部系统向综合信息集成处理系统发送的前向指令信息经过天线和射频模块接收,再通过接口模块将信息经互联模块送到主控模块,主控模块对数据进行解密处理后再经过互联模块将数据发送到基带信号处理模块和导航处理模块,基带信号处理模块和导航处理模块将进行相应处理后的信号再通过接口模块传输至本地外部系统。 [0011] When the information transmission function to execute this command, the forward distal end instruction information is transmitted to the external system integrated information processing system has been integrated antennas and RF receiving module, then the information through the network interface module to module via the master module , the main control module to decrypt the data processing and then through interconnect module sends data to the signal after baseband signal processing module and the navigation processing module, the baseband signal processing module and the navigation processing module corresponding processing for transfer to the local outside through the interface module system.

[0012]当执行返向信息传输功能时,本地外部系统的数据经接口模块进入到综合信息集成处理系统,接口模块接收到数据后,经互联模块送至基带信号处理模块和图像处理模块,基带信号处理模块和图像处理模块处理完后的数据再送到主控模块进行加密和组帧处理,最后经接口模块将返向数据通过射频模块和天线发送至远端外部系统。 [0012] When execution returns to the information transmission function, outside the local system data via an interface module into the integrated information integrated processing system, the interface module after receiving the data, via the network module to the baseband signal processing module and an image processing module, the baseband data signal processing module and an image processing module to the control module after the re-encryption and framing, and finally through the interface module will be returned sent to the remote system via the external antenna to the radio frequency module and data.

[0013] 所述互联模块上包括7个提供VPX接口的槽位,第一槽位至第六槽位的结构相同,均包括PO、Pl和P2三部分,第七槽位仅包括PO,第一槽位用于连接接口模块,第二槽位用于连接主控模块,第三槽位至第五槽位依次连接基带信号处理模块、图像处理模块和导航处理模块,第六槽位为扩展槽位,第七槽位连接射频模块;P0为各模块提供电源,各槽位上的Pl部分采用SRapid1总线协议或I2C总线协议,各槽位上的P2部分采用以太网通信协议。 [0013] 7 comprising providing said VPX interface slot, the first slot to the same slot on the sixth module interconnect structure includes PO, P2, and Pl is of three parts, a seventh slot includes only PO, the first Interface module for connection to a slot, a second slot for connecting the main control module, the third to fifth slots slot are sequentially connected a baseband signal processing module, an image processing module and the navigation processing module, the sixth slot extension slot, the seventh slot to connect the RF module; P0 provides power to each module, each slot portion Pl is employed SRapid1 I2C bus protocol or bus protocol, P2 of each slot portion on the Ethernet communication protocol.

[0014] 所述接口模块包括RS422接口、LVDS接口、1553B接口、以太网口,图像信息通过LVDS接口传输。 [0014] The interface module includes RS422 interface, LVDS interface, 1553B interface, an Ethernet port, image information is transmitted through the LVDS interface.

[0015] 所述主控模块包括FPGA、CPU、FLASH、DDR3、电源单元、PO接口、P1接口和P2接口。 The [0015] main control module comprises a FPGA, CPU, FLASH, DDR3, the power supply unit, PO interfaces, P1 and P2 interfaces interfaces.

[0016] 电源单元与PO接口连接,为FPGA、CPU、FLASH和DDR3供电,当主控模块处于前向指令信息传输状态时,指令信息从P2接口接收,经过FPGA进行数据帧头和帧长度判断,将数据从数据帧中提取,再将提取出的数据送到CPU进行解密处理,解密处理时取出存放在FLASH中的预存密钥,解密解算过程产生的数据通过DDR3进行缓存。 [0016] The power supply unit is connected to the interface PO as a FPGA, CPU, FLASH and DDR3 power, when the control module is in the forward transmission state instruction information, instruction information, via the FPGA data header and frame length determining P2 received from the interface , the data extracted from the data frame, then the extracted data to the CPU decrypts the removed pre-stored in the storage in the FLASH key decryption process, decryption process produces resolver cache data by DDR3. 解密完成后将数据通过SRapid1总线送到Pl接口。 After completion of the decrypted data to the interface via Pl SRapid1 bus.

[0017] 当主控模块处于返向信息传输状态时,基带信号处理模块和图像处理模块处理完后的数据从Pl接口接收,经过CPU进行加密处理,加密处理时取出存放在FLASH中的预存密钥,加密解算过程产生的数据通过DDR3进行缓存。 [0017] When the control module is in the transmission state information back to the data processing module and a baseband signal processing after the image processing module receives from the interface Pl, through CPU is encrypted, stored in the FLASH taken prestored secret encryption process key, the encrypted data generated during the resolver cache by DDR3. 加密完成后将数据送到FPGA,对数据进行组帧,再将形成数据帧的数据送到P2接口。 After completion of the encrypted data to the FPGA, data framing, and then the data frame is formed to the P2 connector.

[0018] 所述CPU采用PowerPC实现。 [0018] The CPU implemented using PowerPC.

[0019] 本发明与现有技术相比具有的有益效果是: [0019] the present invention over the prior art having beneficial effects:

[0020] (I)本发明采用模块化设计实现系统的灵活配置,采用总线方式实现了即插即用及系统的一体化设计,基于本设计方法开发的系统具有可扩展性,具有多种应用模式,对外接口包括RS422接口、LVDS接口、1553B接口、以太网口和预留可扩展接口,与外系统接口类型丰富,可以用于航空、航天、电子信息等领域的综合信息集成处理; [0020] (I) of the present invention is to realize a flexible system configuration modular design, using integrated design approach to achieve the bus and the plug and play system, scalable systems based on the present design method development, have a variety of applications mode, external interfaces include RS422 interface, LVDS interfaces, 1553B interface, an Ethernet port and set aside extensible interface, with rich external system interface types can be used for comprehensive information in the field of aviation, aerospace, electronics and information-integration processing;

[0021] (2)本发明基于VPX总线架构,可以适应严苛的使用环境,同时,大幅降低了系统连接关系的复杂度,具备良好的可靠性、通用性和可扩展性; [0021] (2) The present invention is based VPX bus architecture may be used in a harsh environment, while significantly reducing the complexity of the connection relationship of the system, with good reliability, versatility and scalability;

[0022] (3)本发明采用面向任务的硬件快速重构设计方法,可根据任务需求的不同快速完成主控模块和功能模块的配置安装,进而实现快速的硬件重构能力; [0022] (3) the present invention uses the task-oriented hardware design fast reconstruction method, according to different requirements of the task quickly and functional master module installation configuration module, so as to realize fast hardware reconfiguration;

[0023] (4)各模块通过I2C总线实时上报本模块温度、资源占用率等工作状态数据,主控模块根据上述工作状态数据对各功能模块进行监测、管理,确保系统正常工作,提高了系统的可靠性; [0023] (4) of each module through the I2C bus time reporting of this module temperature, etc. resource usage status data, the main control module based on the operating state of each functional module data monitoring, management, to ensure that the system is working properly, improving the system reliability;

[0024] (5)所设计的主控模块,使得综合信息集成处理系统具有层次性和可管理性,使得各模块的数据源、数据处理结果以及状态信息具有统一的管理者,解决了传统综合信息集成处理系统中数据流向不清晰的问题。 [0024] (5) designed control module, such that the integrated processing system having hierarchical information integration and manageability, so that the data source for each module, the data processing results and status information manager having a uniform, comprehensive solution to the traditional integrated information processing system data flow is not a clear issue.

附图说明 BRIEF DESCRIPTION

[0025]图1为本发明基于板级高速总线的综合信息集成处理系统组成示意图; [0025] FIG. 1 integrated information processing system of the integrated board-level schematic diagram illustrating a high speed bus of the present invention is based;

[0026] 图2为本发明符合VPX VITA46标准协议的信号拓扑结构; [0026] FIG 2 comply with the topology of the signal VPX VITA46 standard protocol of the present invention;

[0027]图3为本发明综合信息集成处理系统的前向指令信息流程图; Forward instruction information flow diagram [0027] FIG. 3 integrated information processing system of the present invention is integrated;

[0028]图4为本发明综合信息集成处理系统的返向数据信息流程图; Return information to the data processing flowchart of Information Integration System [0028] FIG. 4 of the present invention;

[0029] 图5为本发明主控模块组成框图。 [0029] FIG. 5 a block diagram of the main control module of the present invention.

具体实施方式 Detailed ways

[0030] 如图1所示,本发明提供了一种基于板级高速总线的综合信息集成处理系统,包括:VPX机箱、电源模块、互联模块、接□模块、主控模块、基带信号处理模块、图像处理模块、导航处理模块、射频模块和天线。 [0030] As shown in FIG. 1, the present invention provides an information-integration processing based on the integrated board-level high-speed bus system, comprising: VPX chassis, power modules, network module, then □ module, control module, the baseband signal processing module The image processing module, the navigation processing module, a radio frequency module and an antenna. 综合信息集成处理系统能够根据任务不同,安装面向任务需求的功能扩展模块,实现功能扩展或主要功能备份,在任务执行前实现基于VPX架构的硬件快速重构能力。 Comprehensive information integrated processing system capable according to the task, the installation function expansion module for mission requirements, expand the functions of backup or primary function, the ability to achieve rapid reconfiguration of hardware-based VPX architecture before task execution.

[0031] 一种基于板级高速总线的综合信息集成处理系统采用符合VPX VITA46标准协议,同时结合本发明的具体需求,制定了符合VPX标准要求的信号拓扑。 [0031] A standard protocol used in line with comprehensive information VITA 46 VPX integrated processing system on board a high-speed bus, combined with the specific needs of the present invention to develop a signal VPX topology meet standard requirements. VPX(VersatileProtocol Switch 多协议交换)架构是米用VITA (VME bus Internat1nal TradeAssociat1n)组织制定的用以满足恶劣环境下高可靠性、高带宽要求的高级计算平台标准,能够实现对PC1-Express,Gigabit Ethernet, Serial Rapid1 (以下简称SRapid1)等多种通信协议的兼容,理论合计带宽为lOGbps。 VPX (VersatileProtocol Switch multi-protocol switching) architecture is an advanced computing platform standards to meet the high reliability, high bandwidth requirements of harsh environments rice with VITA (VME bus Internat1nal TradeAssociat1n) developed by the Organization can achieve PC1-Express, Gigabit Ethernet , Serial Rapid1 (hereinafter referred to as SRapid1) and other communication protocols compatible with the total theoretical bandwidth of lOGbps.

[0032] VPX机箱为符合VPX架构的金属导热方式的标准3U板卡7槽机箱,用于实现各模块的固定、安装、防护以及接线等,其内部所用的连接器及板卡设计满足严苛环境下的散热、冲击、震动等要求。 [0032] VPX VPX chassis to conform to the standard architecture of a thermally conductive metal boards embodiment 3U 7-slot chassis, fixed for implementing each module, installation, wiring and protection and the like, which is used inside the connector and the board design the demanding It requires heat, shock and vibration in the environment. 电源模块、互联模块、接口模块、主控模块、基带信号处理模块、图像处理模块、导航处理模块和射频模块装在VPX机箱内部。 Power modules, network module, interface module, a control module, a baseband signal processing module, an image processing module, the processing module and the navigation module mounted inside the RF enclosure VPX.

[0033] 电源模块通过DC-DC转换实现对外部输入+DC28V到VPX机箱内部所需直流电源的转换,并为其它各模块提供工作电源及过流、过压、欠压保护。 [0033] The power supply module to achieve DC-DC converter converts the external DC power input + DC28V is required to the inside of the chassis VPX and provide operating power to each of the other modules and overcurrent, overvoltage, undervoltage protection.

[0034] 接口模块、主控模块、基带信号处理模块、图像处理模块和导航处理模块通过插槽与互联模块连接,使用RT2接插件。 [0034] interface module, control module, a baseband signal processing module, an image processing module and the navigation processing module socket module connected to the Internet, using RT2 connector. 互联模块用于实现接口模块、主控模块、基带信号处理模块、图像处理模块和导航处理模块之间的信息交互。 Interconnection module for realizing the information exchange between the interface module, a control module, a baseband signal processing module, an image processing module and the navigation processing module. 射频模块也通过插槽与互联模块连接,电源模块为射频模块供电,射频模块与其它模块之间有金属板隔离,防止电磁干扰。 RF module is also connected to the network via the socket module, the power supply module is a radio frequency module, a metal plate isolated to prevent electromagnetic interference between the RF module and the other modules.

[0035] 接口模块用于实现综合信息集成处理系统和外部系统之间的信息交互,主要包括RS422接口、LVDS接口、1553B接口、以太网接口以及预留可扩展接口。 [0035] The interface module is used to implement information exchange between the integrated information integrated processing system and an external system, including RS422 interface, LVDS interfaces, 1553B interface, Ethernet interface, and may be reserved for expansion interface.

[0036] 所述主控模块是综合信息集成处理系统的信息调度控制模块,负责各功能模块的状态监控、系统工作策略制定、系统数据流控制和系统工作时序制定等功能,主要由PowerPC、FPGA> Flash 等构成。 [0036] The scheduling control information of the main control module is integrated module integrated information processing system, each functional module is responsible for condition monitoring, the system strategy development work, the system data flow control and timing system operates to develop other functions, mainly by the PowerPC, FPGA > Flash and the like.

[0037] 基带信号处理模块、图像处理模块、导航处理模块、功能扩展模块用于实现针对不同任务而完成的信号处理、图像处理、导航处理等功能。 [0037] The baseband signal processing module, an image processing module, a navigation processing module, the function expansion module for implementing tasks completed for different signal processing, image processing, navigation processing and other functions. 基带信号处理模块完成基带信号的扩频调制和扩频信号的接收解调。 The baseband signal processing module completes receiving and demodulating a spread spectrum signal spread spectrum modulated baseband signal. 图像处理模块完成图像的压缩。 The image processing module to complete the compressed image. 导航处理模块将接收到的导航信号进行解算得到数字导航信息。 Navigation processing module received navigation signal to obtain a digital resolver navigation information. 功能扩展模块提供综合信息集成处理系统的功能扩展或者主要功能模块的功能备份。 Function expansion module provides comprehensive information functionality integrated processing system expansion or backup function of the main modules. 基带信号处理模块、图像处理模块、导航处理模块、功能扩展模块由PowerPC、FPGA, DSP、CPLD, SDRAM 等构成。 The baseband signal processing module, an image processing module, a navigation processing module, the function expansion module consists PowerPC, FPGA, DSP, CPLD, SDRAM and the like.

[0038] 如图3所示,当执行前向指令信息传输功能时,远端外部系统(例如地面指控系统)向综合信息集成处理系统发送的前向指令信息经过天线和射频模块接收,再通过接口模块将信息经互联模块送到主控模块,主控模块对数据进行解密处理后再经过互联模块将数据发送到基带信号处理模块和导航处理模块,基带信号处理模块和导航处理模块将进行相应处理后的信号再通过接口模块传输至本地外部系统。 [0038] As shown in FIG forward command information, when the information transmission function to execute this command, the distal end of the external system 3 (e.g. Ground Command and Control System) information transmitted to the integrated integrated processing system via an antenna and RF module receives, through the information via network interface module to the module control module, control module then decrypts the data through the network module sends data to the baseband signal processing module and the navigation processing module, the baseband signal processing module and a processing module corresponding navigation re-transmitting the processed signals to the external system via the local interface module.

[0039] 如图4所示,当执行返向信息传输功能时,本地外部系统(例如飞机等飞行器)的数据经接口模块进入到综合信息集成处理系统,接口模块接收到数据后,经互联模块送至基带信号处理模块和图像处理模块,基带信号处理模块和图像处理模块处理完后的数据再送到主控模块进行加密和组帧处理,最后经接口模块将返向数据通过射频模块和天线发送至远端外部系统。 After [0039] As shown, when execution returns to the information transmission function, a local external data systems (e.g. aircraft, aircraft, etc.) via the interface module integrated into the integrated information processing system, the data received by the interface module, the network module to the baseband signal processing module and an image processing module, the data baseband signal processing module and an image processing module to the control module after the re-encryption and framing, and finally sent through the RF module and the antenna will be returned via the data interface module to the distal end of the external system.

[0040] 如图2所示,互联模块上包括7个提供VPX接口的槽位,第一槽位至第六槽位的结构相同,均包括P0、P1和P2三部分,第七槽位仅包括PO,第一槽位用于连接接口模块,第二槽位用于连接主控模块,第三槽位至第五槽位依次连接基带信号处理模块、图像处理模块和导航处理模块,第六槽位为扩展槽位,第七槽位连接射频模块;P0为各模块提供电源,各槽位上的Pl部分采用SRapid1总线协议或I2C总线协议,各槽位上的P2部分采用以太网通信协议。 [0040] As shown in FIG 7 including providing VPX interface slot, the slot of the first to sixth slot 2 on the same module interconnect structure includes P0, P1 and P2 of three parts, only the seventh slot comprising PO, a first interface module for connection slot, a second slot for connecting the main control module, the third to fifth slots slot are sequentially connected a baseband signal processing module, an image processing module and the navigation processing module, the sixth slot for the expansion slot, the seventh slot to connect the RF module; P0 provides power to each module, each slot portion Pl is employed SRapid1 I2C bus protocol or bus protocol, P2 of each slot portion on the Ethernet protocol . 互联模块的信号拓扑结构使得主控模块与其它模块间形成流水链路及环形通路,实现主控模块对其它模块的数据进行管理和分发。 Signal interconnection topology control module so that the module with other modules and links between the annular flow passage is formed, to achieve control module to manage and distribute the data to other modules. SRapid1总线用于实现各模块间的大数据量高速信号传输,传输速率可达到3.125Gbps。 SRapid1 bus for achieving large amount of data among the various modules speed signal transmission, the transmission rate can reach 3.125Gbps. I2C总线主要完成功能模块向主控模块工作状态数据上报和主控模块对功能模块的控制数据传输。 The main functional blocks to complete the I2C bus data reporting and control module controls data transmission to the main control module to the functional module operation state. 以太网通信协议用于完成各模块间的各种控制信号和低速数据交互。 Ethernet communications protocol for performing various control signals between the modules and the low speed data exchange.

[0041] 所述接口模块包括RS422接口、LVDS接口、1553B接口、以太网口,图像信息通过LVDS接口传输。 [0041] The interface module includes RS422 interface, LVDS interface, 1553B interface, an Ethernet port, image information is transmitted through the LVDS interface.

[0042] 如图5所示,主控模块包括FPGA、CPU、FLASH、DDR3、电源单元、PO接口、Pl接口和P2接口。 As shown in [0042] FIG. 5, the main control module comprises a FPGA, CPU, FLASH, DDR3, the power supply unit, PO interfaces, P2, and Pl is the interface interfaces. 主控模块是综合信息集成处理系统的控制核心,该模块主要完成各模块间的数据调度管理,通过数据总线实现对各模块的参数配置及数据流控制。 Master module is the core of an integrated processing system integrated information, the schedule management module to implement data between modules, each module parameters to achieve the configuration and data flow control via a data bus.

[0043] 电源单元与PO接口连接,为FPGA、CPU、FLASH和DDR3供电。 [0043] The power supply unit is connected to the interface PO as a FPGA, CPU, FLASH and DDR3 power. 所述CPU采用PowerPC实现,负责加解密处理和对I2C总线的管理。 The CPU implemented using PowerPC, responsible for management of the cryptographic processing and I2C bus. FPGA负责数据组帧和接口管理。 FPGA is responsible for framing and data interface management.

[0044]当主控模块处于前向指令信息传输状态时,指令信息从P2接口接收,经过FPGA进行数据帧头和帧长度判断,将数据从数据帧中提取,再将提取出的数据送到CPU进行解密处理,解密处理时取出存放在FLASH中的预存密钥,解密解算过程产生的数据通过DDR3进行缓存。 [0044] When the control module is in the forward transmission instruction information, the instruction information received from the interface P2, via the FPGA data header and the frame length is determined, the data extracted from the data frame, then the extracted data to CPU is decrypted, stored in the FLASH remove the stored key for decrypting process, the decryption process produces resolver cache data by DDR3. 解密完成后将数据通过SRapid1总线送到Pl接口。 After completion of the decrypted data to the interface via Pl SRapid1 bus.

[0045] 当主控模块处于返向信息传输状态时,基带信号处理模块和图像处理模块处理完后的数据从Pl接口接收,经过CPU进行加密处理,加密处理时取出存放在FLASH中的预存密钥,加密解算过程产生的数据通过DDR3进行缓存。 [0045] When the control module is in the transmission state information back to the data processing module and a baseband signal processing after the image processing module receives from the interface Pl, through CPU is encrypted, stored in the FLASH taken prestored secret encryption process key, the encrypted data generated during the resolver cache by DDR3. 加密完成后将数据送到FPGA,对数据进行组帧,再将形成数据帧的数据送到P2接口。 After completion of the encrypted data to the FPGA, data framing, and then the data frame is formed to the P2 connector.

[0046] 本发明的基于VPX架构的互联模块可以支持PC1-Express,Gigabit Ethernet,Serial Rapid1等多种通信协议。 [0046] VPX-based network architecture according to the present invention may support module PC1-Express, Gigabit Ethernet, Serial Rapid1 other communication protocols.

[0047] 以上所述,仅为本发明最佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。 [0047] The above are only preferred embodiments of the present invention, the particular embodiment, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the scope of the invention disclosed can be easily thought variations or replacements shall fall within the protection scope of the present invention.

[0048] 本发明说明书未作详细描述的内容属于本领域专业技术人员公知技术。 [0048] The description of the present invention have not been described in detail content is professional skill in the art known techniques.

Claims (5)

1.一种基于板级高速总线的综合信息集成处理系统,其特征在于包括:VPX机箱、电源模块、互联模块、接口模块、主控模块、基带信号处理模块、图像处理模块、导航处理模块、射频模块和天线; VPX机箱为符合VPX架构的金属导热方式的标准3U板卡7槽机箱,电源模块、互联模块、接口模块、主控模块、基带信号处理模块、图像处理模块、导航处理模块和射频模块装在VPX机箱内部,电源模块用于实现对外部输入+DC28V到VPX机箱内部所需直流电源的转换,并为其它各模块提供工作电源及过流、过压、欠压保护; 接口模块、主控模块、基带信号处理模块、图像处理模块和导航处理模块通过插槽与互联模块连接,互联模块用于实现接口模块、主控模块、基带信号处理模块、图像处理模块和导航处理模块之间的信息交互;射频模块也通过插槽与互联模块连接,电 An integrated information processing integrated system on board a high-speed bus, comprising: VPX chassis, power modules, network module, interface module, a control module, a baseband signal processing module, an image processing module, a navigation processing module, RF module and an antenna; VPX chassis is a metal heat-conducting manner consistent with standard architecture VPX 3U chassis card slot 7, the power module, interconnect module, interface module, a control module, a baseband signal processing module, an image processing module, and the navigation processing module VPX RF module mounted inside the chassis, a power module for enabling the external input to the internal VPX + DC28V chassis DC power required for the conversion, and supplies power to each of the other modules and overcurrent, overvoltage, undervoltage protection; interface module , the main control module, a baseband signal processing module, an image processing module and the navigation processing module socket module connected to the interconnection, interconnect module implements the interface module, a control module, a baseband signal processing module, an image processing module and the navigation processing modules, information exchange between; RF module is also connected, via the slot with electrically interconnect module 模块为射频模块供电,射频模块与其它模块之间有金属板隔离,防止电磁干扰; 接口模块用于实现信息交互,基带信号处理模块完成基带信号的扩频调制和扩频信号的接收解调,图像处理模块完成图像的压缩,导航处理模块将接收到的导航信号进行解算得到数字导航信息; 当执行前向指令信息传输功能时,远端外部系统向综合信息集成处理系统发送的前向指令信息经过天线和射频模块接收,再通过接口模块将信息经互联模块送到主控模块,主控模块对数据进行解密处理后再经过互联模块将数据发送到基带信号处理模块和导航处理模块,基带信号处理模块和导航处理模块将进行相应处理后的信号再通过接口模块传输至本地外部系统; 当执行返向信息传输功能时,本地外部系统的数据经接口模块进入到综合信息集成处理系统,接口模块接收到数据后 RF module power module, a metal plate isolated to prevent electromagnetic interference between the radio module and other modules; implement information interaction interface module, a baseband signal processing module completes receiving and demodulating a spread spectrum signal spread spectrum modulated base band signal, the image processing module to complete the compression of images, navigation processing module received navigation signal to obtain a digital resolver navigation information; when the information transfer function to execute this command, the distal end of the external system sends an integrated processing system integrated information forward command information received via an antenna and a radio frequency module, through the information via the network interface module to the module control module, control module then decrypts the data through the network module sends data to the baseband signal processing module and the navigation processing module, the baseband signal after the signal processing module and the navigation processing module corresponding processing and then transmitted via the interface module to the outside of the local system; when execution returns to the information transmission function, outside the local system data via an interface module into the integrated information integrated processing system, the interface after receiving the data module ,经互联模块送至基带信号处理模块和图像处理模块,基带信号处理模块和图像处理模块处理完后的数据再送到主控模块进行加密和组帧处理,最后经接口模块将返向数据通过射频模块和天线发送至远端外部系统。 , The network module to the data baseband processing module and an image signal processing module, the baseband signal processing module and an image processing module to the control module after the re-encryption and framing process, the final return to the interface module via a radio frequency data The antenna module and sent to the remote external system.
2.根据权利要求1所述的一种基于板级高速总线的综合信息集成处理系统,其特征在于:所述互联模块上包括7个提供VPX接口的槽位,第一槽位至第六槽位的结构相同,均包括PO、P1和P2三部分,第七槽位仅包括P0,第一槽位用于连接接口模块,第二槽位用于连接主控模块,第三槽位至第五槽位依次连接基带信号处理模块、图像处理模块和导航处理模块,第六槽位为扩展槽位,第七槽位连接射频模块;P0为各模块提供电源,各槽位上的P1部分采用SRapid1总线协议或I2C总线协议,各槽位上的P2部分采用以太网通信协议。 According to one of the claims 1 integrated information integrated processing system on board a high-speed bus, characterized by: providing VPX 7 comprises an interface slot on the interconnect module, the first to sixth slot groove same bit structure, each including PO, P1 and P2 of three parts, only the seventh slot including P0, a first interface module for connection slot, a second slot for connecting the main control module, the third through slot five slots are sequentially connected to the baseband signal processing module, an image processing module and the navigation processing module, a sixth expansion slot of the slot, the seventh slot to connect the RF module; P0 provides power to each module, each slot part is P1 SRapid1 I2C bus protocol or bus protocol, P2 of each slot portion on the Ethernet communication protocol.
3.根据权利要求1所述的一种基于板级高速总线的综合信息集成处理系统,其特征在于:所述接口模块包括RS422接口、LVDS接口、1553B接口、以太网口,图像信息通过LVDS接口传输。 According to one of the claim 1, an integrated processing system integrated information board based on high speed bus, wherein: said interface module includes RS422 interface, LVDS interface, 1553B interface, an Ethernet port, the image information through an interface LVDS transmission.
4.根据权利要求1所述的一种基于板级高速总线的综合信息集成处理系统,其特征在于:所述主控模块包括FPGA、CPU、FLASH、DDR3、电源单元、P0接口、P1接口和P2接口; 电源单元与P0接口连接,为FPGA、CPU、FLASH和DDR3供电,当主控模块处于前向指令信息传输状态时,指令信息从P2接口接收,经过FPGA进行数据帧头和帧长度判断,将数据从数据帧中提取,再将提取出的数据送到CPU进行解密处理,解密处理时取出存放在FLASH中的预存密钥,解密解算过程产生的数据通过DDR3进行缓存。 According to one of the claim 1, an integrated processing system integrated information board based on high speed bus, wherein: the main control module comprises a FPGA, CPU, FLASH, DDR3, the power supply unit, an interface P0, Pl, and interfaces Interface P2; P0 the power supply unit is connected to the interface, as FPGA, CPU, FLASH and DDR3 power, when the control module is in the forward transmission state instruction information, instruction information, via the FPGA data header and frame length determining P2 received from the interface , the data extracted from the data frame, then the extracted data to the CPU decrypts the removed pre-stored in the storage in the FLASH key decryption process, decryption process produces resolver cache data by DDR3. 解密完成后将数据通过SRapid1总线送到P1接口; 当主控模块处于返向信息传输状态时,基带信号处理模块和图像处理模块处理完后的数据从P1接口接收,经过CPU进行加密处理,加密处理时取出存放在FLASH中的预存密钥,加密解算过程产生的数据通过DDR3进行缓存。 After completion of the decrypted data to the bus via SRapid1 interfaces P1; when the control module is in the transmit status information back to the data processing module and a baseband signal processing module after the image P1 of the interface received from the CPU through the encrypted encryption remove the pre-existing stored in FLASH key processing, the encrypted data generated during the resolver cache by DDR3. 加密完成后将数据送到FPGA,对数据进行组帧,再将形成数据帧的数据送到P2接口。 After completion of the encrypted data to the FPGA, data framing, and then the data frame is formed to the P2 connector.
5.根据权利要求4所述的一种基于板级高速总线的综合信息集成处理系统,其特征在于:所述CPU采用PowerPC实现。 5. According to one claim 4, wherein an integrated processing system integrated information board based on high speed bus, wherein: said CPU implemented using PowerPC.
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