CN110399221A - Data processing method, system and terminal device - Google Patents
Data processing method, system and terminal device Download PDFInfo
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- CN110399221A CN110399221A CN201910664463.0A CN201910664463A CN110399221A CN 110399221 A CN110399221 A CN 110399221A CN 201910664463 A CN201910664463 A CN 201910664463A CN 110399221 A CN110399221 A CN 110399221A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
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Abstract
The present invention provides a kind of data processing method, system and terminal device, this method includes the data task processing request for receiving source and sending, and master control FPGA is at least logically mutually indepedent with source；It is requested based on data task processing, data task is decomposed into i data subtask；Based on i data subtask, i data processing FPGA is dispatched, corresponding data subtask in i data subtask is based respectively on to control i data processing FPGA, generates i objective result data；The objective result data that i data processing FPGA is sent are received, by i objective result data feedback to source.The present invention, which solves the problems, such as that prior art FPGA accelerator card needs to be inserted into the hosts such as PC machine, just can be carried out work and FPGA accelerator card is caused to lack capacity of working on one's own.
Description
Technical field
The present invention relates to field of computer data processing more particularly to a kind of data processing methods, system and terminal device.
Background technique
Currently, can realize that the calculating of field application accelerates by three kinds of modes.First, ASIC method, i.e., using dedicated
Specific integrated circuit realizes calculating task in a manner of complete hardware.This method is mainly characterized by as specific calculation
Task specially designs, and the concurrency of abundant Mining Problems itself is calculated using large-scale parallel circuit, can be obtained very high
Arithmetic speed and efficiency, but the greatest drawback of this method is it almost without any flexibility, or perhaps non-programmable,
Task, which varies slightly, must just modify circuit.Second, general purpose microprocessor method, the instruction of selection processor is according to certain algorithm structure
As soon as at a new instruction sequence, at the software for completing specific calculation task.Change system can be reached by modifying software
The purpose of function, and hardware is without doing any change, this method strong flexibility, or perhaps programmable, however it is this can
Programmatic is brought using the performance of sacrificial system and speed as cost.Third, the Reconfigurable Computation based on FPGA
(Reconfigurable Computing), this method supplements the above two defect just, is counted using FPGA hardware circuit
It calculates, there is high system performance, while also programmable, can be according to application or intermediate result, dynamically configuration is electric
The way of realization on road, different applying can obtain relatively high calculating on same Reconfigurable Computation hardware platform and accelerate
Than.
The key feature of restructurable computing system is to complete to calculate to improve performance by hardware, and retain software approach
Flexibility, the high-performance of restructurable computing system obtains by Large-scale parallel computing circuit, can not hold parallel in processing
Under efficiency is often very low when capable task, therefore, it is necessary to Reconfigurable Computation component is combined group with general purpose microprocessor
At a system, the flexibility of system had both been maintained, very high performance can be obtained again when handling specific application.But
Restructurable computing system is built to form a tool generally by FPGA accelerator card is increased on the PCIE slot of PC or server
The computer system of standby FPGA hardware acceleration capacity.
FPGA accelerator card is that most typical FPGA calculates acceleration solution at present, still, when in use, generally by FPGA
Accelerator card is installed on the PCIE slot of PC or server host as expansion equipment, and completes to calculate under the control of host
Task, therefore, when realizing calculating task using FPGA accelerator card, FPGA accelerator card lacks capacity of working on one's own.
Summary of the invention
The purpose of the present invention is to provide a kind of data processing method, system and terminal devices, to solve the prior art
FPGA accelerator card, which needs to be inserted into the hosts such as PC machine, just can be carried out work and FPGA accelerator card is caused to lack capacity of working on one's own
Problem.
To achieve the above object, the present invention is implemented as follows:
In a first aspect, providing a kind of data processing method, it is applied to master control FPGA, which comprises
It receives the data task that source is sent and handles request, the master control FPGA is at least logically mutual with the source
It is independent；
Task processing request based on the data, is decomposed into i data subtask for data task；
Based on i data subtask, i data processing FPGA is dispatched, to control the i data processing FPGA points
Not Ji Yu in i data subtask corresponding data subtask, generate i objective result data；
The objective result data that the i data processing FPGA is sent are received, by the i objective result data feedbacks
To the source.
Second aspect, the present invention also provides a kind of data processing systems, comprising:
Master control FPGA is handled with task based on the data and is asked for receiving the data task processing request of source transmission
It asks, data task is decomposed into i data subtask, to dispatch the difference base of i data processing FPGA in data processing FPGA
I objective result data are generated in i data subtask, and receive the target knot that the i data processing FPGA is sent
Fruit data, by the i objective result data feedbacks to the source, the master control FPGA is at least with the source in logic
It is upper mutually indepedent；
I data processing FPGA in data processing FPGA is appointed in response to the master control FPGA based on i data
The scheduling request of business is based respectively on corresponding data subtask in i data subtask, generates i objective result data.
The third aspect, the present invention also provides a kind of terminal devices, comprising:
Task receiving unit, for receive source transmission data task processing request, the master control FPGA at least with institute
It is logically mutually indepedent to state source；
Data task is decomposed into i data and appointed by Task-decomposing unit for the processing request of task based on the data
Business；
Scheduling unit dispatches i data processing FPGA, for being based on i data subtask to control the i
Data processing FPGA is based respectively on corresponding data subtask in i data subtask, generates i objective result data；
Data feedback unit, the objective result data sent for receiving the i data processing FPGA, by i institute
Objective result data feedback is stated to the source.
Fourth aspect, the present invention also provides a kind of terminal devices, comprising: memory, processor and is stored in the storage
On device and the computer program that can run on the processor, realized such as when the computer program is executed by the processor
The step of method described in first aspect.
5th aspect, also a kind of computer readable storage medium of the present invention store on the computer readable storage medium
Computer program, the step of method as described in relation to the first aspect is realized when the computer program is executed by processor.
Master control FPGA in data processing method of the invention is independently of source, in the data task for receiving source transmission
After processing request, data task is decomposed, and dispatch data processing FPGA and the data subtask after decomposition is handled,
The objective result data obtained after processing are back to source, to complete data processing.As it can be seen that master control FPGA is without installation
In source, request can be handled in the data task for receiving source, data processing can be independently executed, therefore, can solve existing
Having in technology FPGA accelerator card need to be inserted into the hosts such as PC machine just can be carried out work and FPGA accelerator card is caused to lack independent work
The problem of making ability.
Detailed description of the invention
Fig. 1 is the schematic flow chart according to the data processing method of one embodiment of the invention；
Fig. 2 is the schematic flow chart according to the data processing method of another embodiment of the present invention；
Fig. 3 is the schematic flow chart according to the data processing method of further embodiment of the present invention；
Fig. 4 is the schematic diagram according to the data processing system of one embodiment of the invention；
Fig. 5 is the schematic structure schematic diagram of logic control element in the data processing system of Fig. 4；
Fig. 6 is the schematic structure schematic diagram of processing unit in the data processing system of Fig. 4；
Fig. 7 is the schematic diagram according to the data processing system of a specific embodiment of the invention；
Fig. 8 is the schematic diagram according to the data processing system of another embodiment of the present invention；
Fig. 9 is the schematic diagram according to the terminal device of one embodiment of the invention.
Specific embodiment
The present invention is described in detail for each embodiment shown in reference to the accompanying drawing, but it should be stated that, these
Embodiment is not limitation of the present invention, those of ordinary skill in the art according to these embodiments made by function, method,
Or equivalent transformation or substitution in structure, all belong to the scope of protection of the present invention within.
The technical solution provided below in conjunction with attached drawing, each embodiment that the present invention will be described in detail.
Fig. 1 is according to the schematic diagram of the data processing equipment of one embodiment of the invention, to solve the prior art
Middle FPGA accelerator card, which needs to be inserted into, just can be carried out work in the hosts such as PC machine, and the problem of lack capacity of working on one's own.The present invention
The method of embodiment is applied to master control FPGA, this method can include:
Step 102. master control FPGA receives the data task that source is sent and handles request.
Wherein, master control FPGA is at least logically mutually indepedent with source.It is understood that master control FPGA is without installation
In source, can be communicated by network communication mode with source, for example, master control FPGA can by its Ethernet interface with
Source is communicated.It is of course also possible to the communication of master control FPGA and source be realized by other means, as long as guaranteeing master control FPGA
It is at least logically mutually indepedent with source.
Step 104. master control FPGA is based on data task processing request, and data task is decomposed into i data subtask.
Specifically, generally will include the quantity M and data of data task in the data task processing request that source is sent
Task draws packet count N, and is then decomposed according to M and N to the process of data Task-decomposing, therefore, based at data task
Data task is decomposed into the operation of i data subtask by reason request, comprising:
Quantity M and data task of the master control FPGA based on data task draws packet count N, and data task is decomposed into i
Data subtask, wherein i is the quantity of data task and the ratio of data task drawn between packet count, i.e. i=M/N.
It for example, include a series of lists on webpage, user can match task parameters if source is a webpage
It sets, task can be submitted with postponing, being submitted for task becomes data task processing request and is sent to the end master control FPGA, therefore,
During configuration task, the quantity of data task and stroke packet count of data task can be set, in subsequent step
The data processing FPGA of data subtask control free time in rapid by master control FPGA based on decomposition is to corresponding data subtask
It is handled.
Step 106. master control FPGA is based on i data subtask, i data processing FPGA is dispatched, to control at i data
Reason FPGA is based respectively on corresponding data subtask in i data subtask, generates i objective result data.
It should be understood that master control FPGA can be to scheduled data processing after master control FPGA scheduling data processing FPGA work
FPGA marks, and to mark scheduled data processing FPGA to be in " busy " state, therefore, is in " busy " in data processing FPGA
When state, data processing FPGA work can not be dispatched again.And when data processing FPGA handles data subtask and will place
After the result of reason is back to master control FPGA, master control FPGA marks data processing FPGA to be in " free time " state at this time, in this way, In
When data processing FPGA is in " free time " state, data processing FPGA work can be dispatched again.
Wherein, master control FPGA may include processing unit and logic control element.
As shown in Fig. 2, being based on i data subtask, i data processing FPGA is dispatched, to control i data processing FPGA
It is based respectively on corresponding data subtask in i data subtask, generates i objective result data, comprising:
The logic control element of step 202. master control FPGA receives the data task that processing unit is sent and handles request, logarithm
Request is handled according to task to be parsed.
The logic control element of step 204. master control FPGA is based on parsing as a result, generating the control of i data subtask
Instruction.
Control instruction of the logic control element based on i data subtask of step 206. master control FPGA dispatches i data
Processing FPGA is based respectively on corresponding data subtask in i data subtask, generates i objective result data.
As it can be seen that master control FPGA, which receives the data task that source is sent by its internal processing unit, handles request, then
Request analysis is handled to data task by its internal logic control element, is appointed with generating i data according to parsing result
The control instruction of business, thus from i data processing FPGA of scheduling carries out corresponding data subtask in data processing FPGA
Reason obtains i objective result data, completes data handling procedure.
Step 108. master control FPGA receives the objective result data that i data processing FPGA is sent, by i objective result
Data feedback is to source.
It further, will as shown in figure 3, master control FPGA receives the objective result data that i data processing FPGA is sent
I objective result data feedback is to source, it may include:
I objective result of correspondence that the logic control element of step 302. master control FPGA sends i data processing FPGA
Data are sent to processing unit.
The processing unit of step 304. master control FPGA is by i objective result data feedback to source.
It should be understood that master control FPGA can dispatch i idle data by logic control element handles FPGA to i data times
Business is handled, and the objective result data obtained after processing then pass through the processing list that Logical processing unit is sent in master control FPGA
Member, objective result data are sent to source in a manner of network communication etc. through the processing unit, to complete data processing sum number
According to the process of transmission.
It can be seen that master control FPGA in the data processing method of the embodiment of the present invention is independently of source, in the source of reception
After the data task processing request that end is sent, data task is decomposed, and dispatch data processing FPGA to the number after decomposition
It is handled according to subtask, the objective result data obtained after processing is back to source, to complete data processing.Due to
Master control FPGA can handle request in the data task for receiving source, can independently execute data processing without being installed on source,
Therefore, can solve FPGA accelerator card in the prior art and need to be inserted into just can be carried out work and FPGA is caused to add in the hosts such as PC machine
The problem of speed card lacks capacity of working on one's own.
In addition, the data processing method of the embodiment of the present invention needs the data task sent by master control FPGA based on source
Request is dispatched to the idle data processing FPGA of data subtask quantity Matching from data processing FPGA to corresponding data
Task is handled.It can be seen that, on the one hand, multiple data can be connected according to the calculating demand of application by master control FPGA
Handle FPGA, to realize the extension of computing capability, the significantly computing capability of lifting system.On the other hand, traditional FPGA adds
Speed card is only made of single FPGA, which needs while realizing calculating and control function, and complicated control process will lead to
The waste of FPGA on piece hardware resource, to reduce the working efficiency of FPGA.And the method for the embodiment of the present invention passes through master control
FPGA control or manage and dispatch task realize the processing such as calculating by data processing FPGA to each corresponding data processing FPGA
Therefore function can separate control and calculating, thus the further data-handling efficiency of lifting system.
In order to which the realization process of any of the above-described method is further described, the embodiment of the present invention also provides a kind of data
Processing system 400, as shown in figure 4, its can include: master control FPGA 600, for receiving the data task processing of the transmission of source 500
Request, data task is decomposed into i data subtask, to dispatch data processing FPGA based on data task processing request
In i data processing FPGA 700 be based respectively on i data subtask and generate i objective result data, and receive i data
The objective result data that FPGA700 is sent are handled, by i objective result data feedback to source 500, master control FPGA600 is extremely
It is few logically mutually indepedent with source；I data processing FPGA in data processing FPGA 700 is in response to master control FPGA
600 scheduling requests based on i data subtask are based respectively on corresponding data subtask in i data subtask, generate i
A objective result data.
Wherein, data task processing request includes the quantity of data task and stroke packet count of data task, master control FPGA
Then can quantity M based on data task and data task draw packet count N, data task is decomposed into i data subtask,
In, i is the quantity of data task and the ratio of data task drawn between packet count, i.e. i=M/N.
Master control FPGA600 in the data processing system of the embodiment of the present invention is receiving source independently of source 500
After the 500 data tasks processing requests sent, data task is decomposed, and after dispatching data processing FPGA700 to decomposition
Data subtask handled, obtained objective result data source 500 will be back to after processing, to complete at data
Reason.Since master control FPGA 600 is without being installed on source 500, request can be handled in the data task for receiving source, it can be only
Vertical to execute data processing, therefore, can solve FPGA accelerator card in the prior art and need to be inserted into just can be carried out in the hosts such as PC machine
The problem of working and FPGA accelerator card caused to lack capacity of working on one's own.
In the above-described embodiments, as shown in figure 5, master control FPGA 600 includes processing unit 602 and logic control element
604.Wherein, the processing unit 602 in master control FPGA is a kind of general purpose processor core, as shown in figure 5, its periphery connection memory
(DDR) interface, memory (Flash) interface, Ethernet (EthernetPHY) interface, CPU work clock input interface, calculating
FPGA burning interface, reset signal input interface and temperature sensor interface.Processing unit 602 is mainly used for receiving source 500
The data task of transmission handles request.Logic control element 604 receives the data task that processing unit is sent and handles request, logarithm
It handles request according to task to be parsed, and the result based on parsing generates the control instruction of i data subtask, based on i
The control instruction of data subtask, i data processing FPGA of scheduling are based respectively on corresponding data in i data subtask and appoint
Business generates i objective result data.
It is handled in this way, master control FPGA 600 receives the data task that source 500 is sent by its internal processing unit 602
Then request handles request analysis to data task by its internal logic control element 604, to generate according to parsing result
The control instruction of i data subtask, to dispatch i data processing FPGA from data processing FPGA 700 to corresponding number
It is handled according to subtask, obtains i objective result data, complete data handling procedure.
It should be noted that there is independent control sum number between each data processing FPGA 700 and master control FPGA 600
According to access, structure is as shown in Figure 4.Wherein, bidirectional linked list high-speed data path uses the link layer protocol of lightweight, by double
Serially high-speed data path realizes that point-to-point high speed data transfer, transmission rate can achieve 10Gbps or more.Two-way string
The compatible AXI Stream interface protocol of the user-interface of row high-speed data path, controls two using the flow-control mechanism of link layer
Hold the data transmission between FPGA.Bidirectional parallel control access supports signal customized, can pass through reconstruct according to needs are applied
Interface control logic dynamically changes signal transmission direction, Handshake Protocol, data format etc..By bidirectional parallel control access and
Bidirectional high speed serial data matches, and can efficiently realize the cooperated computing of more FPGA.
Logic control element 604 is also used to for i objective result data of correspondence that i data processing FPGA is sent being sent to
Processing unit 602；Processing unit 602 is used for i objective result data feedback to source 500.That is, master control FPGA can be by patrolling
It collects i idle data processing FPGA of the scheduling of control unit 604 to handle i data subtask, the target obtained after processing
Result data then passes through the processing unit 602 that logic control element 604 is sent in master control FPGA, with through the processing unit 602
Objective result data are sent to source 500 in a manner of network communication etc., to complete the process of data processing and data transmission.
It works it is worth noting that, the logic control element 604 in master control FPGA 600 dispatches data processing FPGA 700
Afterwards, master control FPGA can mark to scheduled data processing FPGA, to mark scheduled data processing FPGA to be in " busy "
Therefore state when data processing FPGA is in " busy " state, can not dispatch data processing FPGA work again.And when number
After handling according to processing FPGA data subtask and the result of processing being back to master control FPGA, master control FPGA marks the number at this time
It is in " free time " state according to processing FPGA, in this way, the data can be dispatched again when data processing FPGA is in " free time " state
Handle FPGA work.
As it can be seen that since master control FPGA 600 is without being installed on source 500 in the data processing system of the embodiment of the present invention, master
Controlling FPGA can be independent by logic control element 604 through the processing unit 602 after receiving the data task processing request of source
Scheduling data processing FPGA executes data processing and therefore can solve FPGA accelerator card in the prior art and need to be inserted into PC machine etc.
The problem of just can be carried out work in host, and lacking capacity of working on one's own.
As shown in figure 5, logic control element 604 includes data processing and control module 6042 and order generation module 6044,
The periphery of logic control element 604 is connected with FPGA work clock input interface, JTAG debugging interface, bidirectional linked list high-speed data
Interface, IEEE Std serial highway reference clock input interface and bidirectional parallel control access interface etc..Wherein, data processing and control mould
The data task processing request that block 6042 is used to send based on processing unit 602, parses data task processing request, and
I data processing FPGA is dispatched based on the control instruction that order generation module 6044 exports to be based respectively in i data subtask
Corresponding data subtask generates i objective result data；Order generation module 6044 is used to be based on data processing and control module
The parsing result of the 6042 data processing module outputs sent, generates the control instruction of i data subtask.
Due to master control FPGA through the processing unit 602 receive source data task processing request after, pass through logic control
Data processing and control module 6042 in unit 604 processed handles request analysis to data task, then passes through order generation module
6044 generate the control instruction for being handled data subtask according to parsing result, and pass through data processing and control module
6042 carry out calculation process to corresponding data subtask according to the idle data processing FPGA of control instruction scheduling.As it can be seen that main
Control FPGA 600 without be installed on source 500 can independent scheduling of data processing FPGA execute data processing therefore can solve
FPGA accelerator card, which needs to be inserted into the hosts such as PC machine, in the prior art just can be carried out work and FPGA accelerator card is caused to lack independently
The problem of ability to work.
Specifically, data processing and control module 6042 further includes bus marco submodule, DDR memory access control submodule, number
According to transmission control submodule, calculate FPGA burning control submodule.
Wherein, bus marco submodule is received at the data task that processing unit 602 is sent by AXI bus interface
Reason request parses data task processing request, and parsing result is then used for internal register configuration and generates control command.
DDR memory access control submodule is then interacted with the DDR controller of processing unit 602, realizes the read-write to external system DDR data.
Data Transmission Controlling submodule be responsible for each data processing FPGA data interaction control, the control process by read-write buffering come
It completes, corresponding Write post is written after external control command decoding, Data Transmission Controlling submodule is responsible for completing the reading of order
It takes and sends, the reply data of read command will be stored in response buffering.FPGA burning control submodule is calculated to be responsible for from outside
Recordable paper is read in system DDR, configuration file is burnt to according to FPGA burning agreement and calculates FPGA burning control submodule
In.
Order generation module 6044 generates corresponding each control life for calculating FPGA according to the parsing result of task requests
It enables.When there is data processing task to need to be implemented, the control command of generation is sent at corresponding data by control interface
Manage FPGA.By taking 16 data processing FPGA as an example, command format is as shown in the table:
Wherein, in [17], 1 indicates write order, and 0 indicates read command.In [16:12], then it represents that data processing FPGA
Chip number.0x1~0x16 indicates 16 data processing FPGA, and complete " 1 " then instruction is to broadcasting command.
[11:6]: calculating FPGA internal pipeline number, indicates effective when chip number is non-zero.Own in " 1 " instruction single-chip entirely
Assembly line broadcast.
[5:0]: 64 custom commands may be implemented in customized explosion command number, and custom command is given birth to by master control FPGA
At, and parsed and used by data processing FPGA.
In any of the above-described embodiment, as shown in fig. 6,700 periphery configuration of data processing FPGA has reset signal input
Interface, FPGA work clock input interface, JTAG debugging interface, FPGA burning interface, IEEE Std serial highway reference clock input interface,
Bidirectional linked list high-speed data path interface and bidirectional parallel control access interface.Data processing FPGA 700 includes Interface Controller list
Member 702 and Data Computation Unit 704；Wherein, interface control unit 702 is referred to based on received master control FPGA 600 control exported
It enables, i Data Computation Unit 704 of scheduling is respectively handled corresponding data subtask in i data subtask, and by i
A objective result data are transmitted to master control FPGA；The control instruction that Data Computation Unit 704 is exported based on interface control unit 702
I data subtask is handled, and exports i objective result data to interface control unit 702.
It can be appreciated that interface control unit 702 mainly includes two functions: one is responsible for receiving and handle from master control
The order of FPGA, according to the control register of order configuration data arithmetic element；Two are responsible at master control FPGA 600 and data
Manage FPGA 700 between data transmission, receive the data from master control FPGA 600 and be transmitted to Data Computation Unit 704 into
Row processing, is transmitted to master control FPGA 600 for processing result.
Include the calculating assembly line being made of multiple Data Computation Units 704, every calculating in data processing FPGA 700
Assembly line supports separate configurations and autonomous working.Data Computation Unit 704 is responsible for the execution of data processing task, for different
Using, different calculating assembly lines can be reconstructed by data processing FPGA burning interface, thus realize be directed to different application
Calculating acceleration function.
In a specific embodiment of the invention, as shown in fig. 7, the data processing system of the embodiment of the present invention is by 1
The calculating subcard of a master control FPGA and 8 data processing FPGA composition.Wherein, master control FPGA is using XilinxZynq7035
Chip is internally integrated ARM Cortex-A9 dual core processor and Kintex-7FPGA logical resource, externally provides and calculates subcard
External control interface, while data processing FPGA is controlled by GTX high-speed transceiver and carries out operation.What data processing FPGA was used
It is XilinxKintex-7 325T, is connected by GTX interface with master control FPGA, the control instruction for receiving master control FPGA is realized
Accelerate to calculate.
It should be understood that since master control FPGA is without being installed on source request can be handled in the data task for receiving source, i.e.,
Data processing can be independently executed, therefore, FPGA accelerator card in the prior art is can solve and needs to be inserted into ability in the hosts such as PC machine
The problem of working, and lacking capacity of working on one's own.Also, it can be according to the calculating demand of application, even by master control FPGA
Multiple data processing FPGA are met, to realize the extension of computing capability, the significantly computing capability of lifting system.In addition, passing through master
FPGA control or manage and dispatch task are controlled to each corresponding data processing FPGA, calculating etc. is realized by data processing FPGA
Function is managed, therefore, control and calculating can be separated, thus the further data-handling efficiency of lifting system.
As shown in figure 8, the data processing system of the embodiment of the present invention can by 1 master control FPGA, N number of data processing FPGA and
The center that a set of star schema high speed interference networks (abbreviation Star Network) form the system is 1 master control FPGA, is responsible for
Data processing task scheduling calculates data distribution, data processed result recycling and the interaction with external system.Star Network
Each endpoint respectively has data processing FPGA, is responsible for the processing of data subtask.Master control FPGA and data processing FPGA is using point-to-point
Mode connect, realize calculate control with data transmit.Single master control FPGA can be connected multiple according to the calculating demand of application
Data processing FPGA realizes the extension of computing capability.
In addition, central hub of the master control FPGA as data processing system, master control FPGA is by processing unit and logic control
Unit two parts composition.The control of all data processing FPGA is responsible for by master control FPGA in data processing system, realizes control
It is separated with calculating.When so as to solve single FPGA chip on traditional FPGA accelerator card while realizing data processing and control logic
The problem of hardware resource utilization is low, chip operation low efficiency.
The embodiment of the present invention also provides a kind of terminal device, as shown in figure 9, the terminal device may include task receiving unit
902, for receiving the data task processing request of source transmission, master control FPGA is at least logically mutually indepedent with source；Appoint
Business decomposition unit 904, for based on data task processing request, data task to be decomposed into i data subtask；Scheduling unit
906, for being based on i data subtask, i data processing FPGA is dispatched, is based respectively on i to control i data processing FPGA
Corresponding data subtask in a data subtask generates i objective result data；Data feedback unit 908, for receiving i
The objective result data that a data processing FPGA is sent, by i objective result data feedback to source.
Master control FPGA in the terminal device of the embodiment of the present invention is being connect independently of source by task receiving unit 902
After receiving the data task processing request that source is sent, data task is decomposed by Task-decomposing unit 904, and pass through tune
Degree unit 906 is dispatched data processing FPGA and is handled the data subtask after decomposition, will to pass through data feedback unit 908
The objective result data obtained after processing are back to source, to complete data processing.Since master control FPGA is without being installed on source
End can handle request in the data task for receiving source, can independently execute data processing, therefore, can solve existing skill
FPGA accelerator card, which needs to be inserted into, in art just can be carried out work in the hosts such as PC machine, and the problem of lack capacity of working on one's own.
In the above-described embodiments, terminal device further includes task resolution unit 910, for receiving the number of processing unit transmission
It handles and requests according to task, data task processing request is parsed；Instruction generation unit 912, it is based on parsing as a result, generating
The control instruction of i data subtask；Scheduling unit 906 is used for the control instruction based on i data subtask, dispatches i number
It is based respectively on corresponding data subtask in i data subtask according to processing FPGA, generates i objective result data.Data are anti-
Feedback unit 908 is used to i objective result data of correspondence that i data processing FPGA is sent being sent to processing unit, to pass through
The processing unit of master control FPGA is by i objective result data feedback to source.
It can be seen that due in the data processing system of the embodiment of the present invention master control FPGA 600 without being installed on source
500, master control FPGA can be handled data task after the data task processing request for receiving source by task resolution unit 910
Request is parsed, and generates the control instruction of i data subtask based on the result of parsing by instruction generation unit 912, is led to
It crosses scheduling unit 906 and dispatches data processing FPGA execution data processing, therefore, can solve FPGA accelerator card in the prior art needs
The problem of just can be carried out work and FPGA accelerator card is caused to lack capacity of working on one's own, is inserted into the hosts such as PC machine.
Terminal device described in any of the above-described embodiment is configurable to virtual machine, application program, the calculating for running UI
Machine device etc..
Preferably, the embodiment of the present invention also provides a kind of terminal device, may include processor, and memory is stored in and deposits
On reservoir and the computer program that can run on the processor, the computer program realize above-mentioned figure when being executed by processor
Each process of embodiment of the method shown in 1-3, and identical technical effect can be reached, to avoid repeating, which is not described herein again.
The embodiment of the present invention also provides a kind of computer readable storage medium, and meter is stored on computer readable storage medium
Calculation machine program, the computer program realize each process of method shown in above-mentioned Fig. 1-3 when being executed by processor, and can reach
Identical technical effect, to avoid repeating, which is not described herein again.Wherein, the computer readable storage medium is deposited Ru read-only
Reservoir (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or
CD etc..
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiments being understood that.
Claims (13)
1. a kind of data processing method is applied to master control FPGA, which is characterized in that the described method includes:
It receives the data task that source is sent and handles request, the master control FPGA is at least logically mutual solely with the source
It is vertical；
Task processing request based on the data, is decomposed into i data subtask for data task；
Based on i data subtask, i data processing FPGA is dispatched, to control the i data processing FPGA difference base
The corresponding data subtask in i data subtask generates i objective result data；
The objective result data that the i data processing FPGA is sent are received, by the i objective result data feedbacks to institute
State source.
2. the method as described in claim 1, which is characterized in that the master control FPGA includes processing unit and logic control list
Member, it is described to be based on i data subtask, i data processing FPGA is dispatched, to control the i data processing FPGA points
Not Ji Yu in i data subtask corresponding data subtask, generate i objective result data, comprising:
The logic control element of the master control FPGA receives the data task processing request that the processing unit is sent, to institute
Data task processing request is stated to be parsed；
The logic control element of the master control FPGA is based on parsing as a result, generating the control instruction of i data subtask；
The logic control element of the master control FPGA dispatches the i data based on the control instruction of i data subtask
Processing FPGA is based respectively on corresponding data subtask in i data subtask, generates i objective result data.
3. method according to claim 2, which is characterized in that the target for receiving the i data processing FPGA and sending
Result data, by the i objective result data feedbacks to the source, comprising:
I objective result data of correspondence that the logic control element of the master control FPGA sends the i data processing FPGA
It is sent to the processing unit；
The processing unit of the master control FPGA is by the i objective result data feedback to the source.
4. the method as described in claim 1, which is characterized in that the data task processing request includes the data task
Stroke packet count of quantity and the data task, the processing of the task based on the data request, is decomposed into i for data task
Data subtask, comprising:
Stroke packet count of the quantity of task and the data task based on the data, is decomposed into i number for the data task
According to subtask, wherein i is the quantity of the data task and the ratio of the data task drawn between packet count.
5. a kind of data processing system characterized by comprising
Master control FPGA, the data task processing request for receiving source transmission will with the processing request of task based on the data
Data task is decomposed into i data subtask, is based respectively on the i data processing FPGA dispatched in data processing FPGA described
I data subtask generates i objective result data, and receives the objective result data that the i data processing FPGA is sent,
With by the i objective result data feedbacks, to the source, the master control FPGA is at least logically mutual with the source
It is independent；
I data processing FPGA in data processing FPGA is in response to the master control FPGA based on i data subtask
Scheduling request is based respectively on corresponding data subtask in i data subtask, generates i objective result data.
6. system as claimed in claim 5, it is characterised in that:
The master control FPGA includes processing unit and logic control element, wherein
The processing unit is used to receive the data task processing request that the source is sent；
The logic control element receives the data task processing request that the processing unit is sent, to the data task
Processing request is parsed, and the result based on parsing generates the control instruction of i data subtask, to be based on the i number
According to the control instruction of subtask, dispatches the i data processing FPGA and be based respectively on corresponding number in i data subtask
According to subtask, i objective result data are generated.
7. system as claimed in claim 6, it is characterised in that:
I objective result data of correspondence that the logic control element is also used to send the i data processing FPGA are sent
To the processing unit；
The processing unit is used for the i objective result data feedback to the source.
8. system as claimed in claim 5, which is characterized in that the data task processing request includes the data task
Stroke packet count of quantity and the data task, wherein
The quantity of task and the data task draw packet count to the master control FPGA based on the data, by the data task
It is decomposed into i data subtask, wherein i is the quantity of the data task and drawing between packet count for the data task
Ratio.
9. system as claimed in claim 6, which is characterized in that the logic control element includes order generation module and data
Processing and control module；Wherein,
The data task processing request that data processing and control module is used to send based on the processing unit, to the data
Task processing request is parsed, and the control instruction based on order generation module output dispatches the i data processing
FPGA is based respectively on corresponding data subtask in i data subtask, generates i objective result data；
The data processing module output that the order generation module is sent for processing and control module based on the data
Parsing result generates the control instruction of i data subtask.
10. system as claimed in claim 5, which is characterized in that the data processing FPGA includes interface control unit sum number
According to arithmetic element；Wherein,
Control instruction of the interface control unit based on the received master control FPGA output, dispatches i Data Computation Unit
Corresponding data subtask in i data subtask is handled respectively, and i objective result data are transmitted to the master
Control FPGA；
The control instruction that the Data Computation Unit is exported based on the interface control unit to i data subtask at
Reason, and i objective result data are exported to the interface control unit.
11. a kind of terminal device characterized by comprising
Task receiving unit, for receive source transmission data task processing request, the master control FPGA at least with the source
It holds logically mutually indepedent；
Data task is decomposed into i data subtask for the processing request of task based on the data by Task-decomposing unit；
Scheduling unit dispatches i data processing FPGA, for being based on i data subtask to control the i data
Processing FPGA is based respectively on corresponding data subtask in i data subtask, generates i objective result data；
Data feedback unit, the objective result data sent for receiving the i data processing FPGA, by the i mesh
Mark result data feeds back to the source.
12. a kind of terminal device, comprising: memory, processor and be stored on the memory and can be on the processor
The computer program of operation is realized when the computer program is executed by the processor such as any one of claims 1 to 4 institute
The step of method stated.
13. a kind of computer readable storage medium, computer program, the calculating are stored on the computer readable storage medium
The step of machine program realizes method according to any one of claims 1 to 4 when being executed by processor.
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