CN105045566B - A kind of embedded type parallel computation system and the parallel calculating method using it - Google Patents
A kind of embedded type parallel computation system and the parallel calculating method using it Download PDFInfo
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Abstract
The invention discloses a kind of embedded type parallel computation system and using its parallel calculating method, the system comprises a data input module, multiple identical cabinets and a data outputting modules；Each described cabinet includes two Switching Modules, multiple computing modules, a bottom plate and a power management module；Each described Switching Module includes an optic fiber converter, a SRIO exchange chip and a GbE exchange chip, each described computing module includes two panels multi-core DSP, a SRIO exchange chip and a FPGA.Through the invention, it is capable of providing the embedded type parallel computation system of a kind of strong operational capability, highly reliable, modularization, expansible, miniaturization, low-power consumption, high bandwidth, and the system can automatic equalization distribute computing resource, and provide the Parallel Computation interface of standard.
Description
Technical field
The present invention relates to technical field of data processing, and in particular to a kind of embedded type parallel computation system and using its and
Row calculation method.
Background technique
Currently, especially in terms of space star boat-carrying computing system, FPGA is mostly used to add monolithic list in embedding assembly field
The operational capability of the structure of core DSP, unit time is lower, is difficult to meet data volume and increasingly increases, and algorithm complexity increasingly mentions
High demand.
In the structure that some communications or field of radar, some systems are handled using multiple monokaryon DSP collaboration, but each
Different tasks is run on DSP, and the mode of task flowing water is taken to handle data.In this way, needing each project according to need
The task of repartitioning is sought, and is difficult to will lead to wooden pail effect and waste computing resource multiple and different task load equilibriums.
Traditional multiple DSP system using task flowing water will lead to the paralysis of whole system once some DSP breaks down.
And traditional concurrent computational system mostly uses the large-scale cluster system based on Ethernet, bulky, power consumption is high, leads to
Believe that bandwidth is low, is very difficult to apply in built-in field.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of embedded type parallel computation system and using its parallel meter
Calculation method is able to solve problem of the existing technology.
The present invention provides following schemes：
Based on one aspect of the present invention, a kind of embedded type parallel computation system is provided, the system comprises a numbers
According to input module, multiple identical cabinets and a data outputting module；Each described cabinet includes two interchange modes
Block, multiple computing modules, a bottom plate and a power management module；Each described Switching Module includes an optical fiber conversion
Device, a SRIO exchange chip and a GbE exchange chip, each described computing module include two panels multi-core DSP, one
SRIO exchange chip and a FPGA；SRIO exchange chip in each described Switching Module with calculating mould described in each
SRIO exchange chip in block is connected, the GbE exchange chip in each described Switching Module respectively with each computing module
In multi-core DSP be connected, the GbE exchange chip in each described Switching Module is also connected with power management module, each
Optic fiber converter in the Switching Module is connected with other cabinets or data input module or data outputting module；
Outer input interface inputs pending data to Master by the data input module, will be described by Master
Pending data is averagely allocated to available slave, each slave receives corresponding pending data, according to slave's
Corresponding pending data is averagely allocated to the kernel of the slave to be carried out accordingly by corresponding kernel by interior nucleus number
It executes, and implementing result is returned into Master, merged by the implementing result that Master returns to all slave, and pass through number
It is exported according to output module through external output interface, wherein Masetr is one in all DSP, and other DSP are slave.
Based on another aspect of the present invention, a kind of parallel calculating method is provided, the method includes：
S1, outer input interface input pending data to Master by the data input module；
The pending data is averagely allocated to available slave by S2, Master, each slave is received accordingly
Pending data, corresponding pending data is averagely allocated to the kernel of the slave according to the interior nucleus number of the slave
To be executed accordingly by corresponding kernel, and implementing result is returned into Master；
The implementing result that S3, Master return to all slave merges, and is connect by data outputting module through outside output
Mouth output；
Wherein, Masetr is one in all DSP, and other DSP are slave.
A kind of embedded type parallel computation system provided by the invention and the parallel calculating method for using it, according to number to be processed
According to operand selection cabinet quantity and computing module in each cabinet quantity, improve the calculating effect of whole system
Rate, scalability are strong；Each cabinet inside includes 2 Switching Modules, can be used for forming dual star topology SIRO network, can carry out inside
The data of high speed are transmitted, and dual star network not only increases communication bandwidth, and also adds redundancy, once one of those
Switching Module failure, then dual star topology SRIO network, which becomes single star-like SRIO network, to work on；It is counted using multiple DSP
According to parallel computation, improve data calculating efficiency, and each DSP calculate same quantity of data data, avoid wooden barrel
The generation of effect, and each DSP is multi-core DSP, operational capability is strong；In addition, being powered off for the DSP of failure, function is reduced
Consumption.
Detailed description of the invention
Fig. 1 is a kind of embedded type parallel computation system schematic diagram of the embodiment of the present invention one；
Fig. 2 is the schematic diagram of internal structure of each cabinet in the embodiment of the present invention one；
Fig. 3 is a kind of parallel calculating method flow chart of the embodiment of the present invention two；
The process flow diagram flow chart of Master is determined in Fig. 4 embodiment of the present invention two.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
Embodiment one, a kind of embedded type parallel computation system.Below in conjunction with Fig. 1 and Fig. 2 to system provided in this embodiment
It is described in detail.
Referring to Fig. 1, provided in this embodiment the system comprises a data input modules, multiple identical cabinets
With a data outputting module.In addition, referring to fig. 2, each described cabinet include two Switching Modules, multiple computing modules,
One bottom plate and a power management module；Each described Switching Module includes an optic fiber converter, a SRIO
(Serial Rapid I/O) exchange chip and GbE (Gigabit Ethernet, a gigabit Ethernet) exchange chip, it is each
A computing module includes two panels multi-core DSP (Digital Signal Processing, Digital Signal Processing), one
SRIO exchange chip and a FPGA (Field Programmable Gate Array, field programmable gate array).Often
SRIO exchange chip in one Switching Module is connected with the SRIO exchange chip in computing module described in each, often
GbE exchange chip in one Switching Module is connected with the multi-core DSP in each computing module respectively, described in each
GbE exchange chip in Switching Module is also connected with power management module, the optic fiber converter in each described Switching Module
It is connected with other cabinets or data input module or data outputting module.Specifically, the SRIO in each described Switching Module
Exchange chip passes through 1 road SRIO respectively and is connected by chassis backplane with the SRIO exchange chip in each computing module, described
SRIO exchange chip in Switching Module inputs mould by optic fiber converter and the other cabinets or data of uplink by 2 road SRIO
Block is connected, and is separately connected by optic fiber converter with the other cabinets or data outputting module of downlink by 2 road SRIO.Each institute
The GbE exchange chip stated in Switching Module is connected by 2 road GbE with 2 DSP in each computing module, and 1 tunnel is separately passed through
GbE is connected to other cabinets, and is connected to the power management module by 1 road GbE.2 DSP in each computing module
It is connected by SRIO all the way with the SRIO exchange chip in the computing module；In the data input module and all cabinets
Master in all DSP is connected by SRIO interface, and the data outputting module passes through SRIO interface phase with the Master
Even.
It should be noted that 2 Switching Modules are set in each cabinet, it, can be into for forming dual star topology SRIO network
The data of row inner high speed are transmitted, and dual star network not only increases communication bandwidth, and also adds redundancy, once wherein
The failure of a Switching Module, then dual star topology SRIO network, which becomes single star-like SRIO network, to work on.GbE exchange chip
It is mainly used for internal affairs management (for example, the heartbeat judgement of all DSP, computing module management, power management and host are cut automatically
Change) bus.FPGA in each computing module is mainly used for the electric sequence management of DSP and the management of peripheral logic.
Use system provided in this embodiment carry out the process of data calculating for：Outer input interface is defeated by the data
Enter module and input pending data to Master, the pending data is averagely allocated to available slave by Master, often
One slave receives corresponding pending data, according to the interior nucleus number of slave by corresponding pending data average mark
Implementing result is returned to Master to be executed accordingly by corresponding kernel by the kernel of the dispensing slave, by
The implementing result that Master returns to all slave merges, and is exported by data outputting module through external output interface,
In, Masetr is one in all DSP, and other DSP are slave.
Wherein, the quantity of the cabinet and the quantity of the computing module in each cabinet are all in accordance with pending data
Operand determines that, that is, according to specific application demand, selection constitutes high performance parallel using the most 8 cabinets interconnections of at least one
Computing system (efficiency that more than 8 cabinets will lead to parallel computation reduces, therefore uses appropriate number of cabinet).Each cabinet
It is respectively that (power consumption is about by 5120GMAC and 2560GFLOPS that computing capability when including 8 computing modules, which can reach fixed point/floating-point,
For 260W), computing capability of the whole system in 8 cabinet is respectively 40906GMAC and 20480GFLOPS up to fixed point/floating-point
(power consumption about 2080W).
In cabinet all DSP be all made of the high-performance of TI company, low-power consumption, technical grade 8 core dsp processors
TMS32OC6678, working frequency 1.25GHz, fixed point/floating-point operation performance are respectively 320GMAC and 160GFLOPS,
Support a variety of high-speed interfaces：Such as GbE interface, DDR3 interface and SRIO interface etc..The outer input interface and external output
Interface is CameraLink, LVDS, TLK2711,10GbE, InfiniBand or customized high-speed interface.
Embodiment two, a kind of parallel calculating method.Method provided in this embodiment is carried out below in conjunction with Fig. 3 and Fig. 4 detailed
Thin description.
Referring to Fig. 3, method provided in this embodiment includes：S1, outer input interface by the data input module to
Master inputs pending data.
Specifically, determining that the process of Master is from all DSP of embedded type parallel computation system：After powering on, own
DSP pass through GbE and broadcast itself unique ID number to other DSP, after broadcast reception, be stored in each DSP
The ID number of all DSP；Each DSP is ranked up the ID number of all DSP according to pre-defined rule, and by sort first ID number
Master of the corresponding DSP as all DSP, other DSP are as Slave.
It should be noted that outer input interface be usually CameraLink, LVDS, TLK2711,10GbE,
InfiniBand or customized high-speed interface etc., and data input module with Master is connected by SRIO interface, therefore, number
It according to input module needs that SRIO will be converted to by the input interface signal (i.e. pending data) of outer input interface input and connect
Message number, and by the SRIO interface signal transfer after conversion to Master.
The pending data is averagely allocated to available slave by S2, Master, each slave is received accordingly
Pending data, corresponding pending data is averagely allocated to the kernel of the slave according to the interior nucleus number of the slave
To be executed accordingly by corresponding kernel, and implementing result is returned into Maste.
Specifically, reference can be made to Fig. 4, Master before the distribution for carrying out pending data, are periodically sent to all Slave
Heartbeat signal determines that the slave is available if receiving the heartbeat response of slave return within the first predetermined time, otherwise,
Determine that the slave fails.After having determined the working condition of all slave, Master records available slave quantity again,
And inform that power management module powers off the computing module where the slave of failure by GbE, to reduce power consumption.In addition, if
Slave is not received by the heartbeat signal of Master transmission in second predetermined time, then determines that the Master fails, and from all
Slave in redefine Master.
Then, pending data is divided into x parts, and lead to by calling the MPI standard routine interface provided by Master
It crosses SRIO interface and is sent to corresponding slave, wherein x is available slave quantity, and x is positive integer.Slave passes through offer
Corresponding pending data data are divided into y parts according to the interior nucleus number of slave by OpenMP standard interface program, and are sent to
Corresponding kernel executes calculation processing by the interior corresponding pending data of verification, and implementing result is returned to Master.
The implementing result that S3, Master return to all slave merges, and is exported by data outputting module through outside
Interface output.
Since external output interface is usually CameraLink, LVDS, TLK2711,10GbE, InfiniBand or is made by oneself
Adopted high-speed interface etc., therefore, after the implementing result that Master returns to all slave merges, data outputting module will merge
Implementing result data afterwards are converted to external output interface form from SRIO form and export through external output interface.
A kind of embedded type parallel computation system provided by the invention and the parallel calculating method for using it, can be according to be processed
The quantity of computing module, improves the calculating effect of whole system in the quantity of the operand selection cabinet of data and each cabinet
Rate, scalability are strong；Each cabinet inside includes 2 Switching Modules, can be used for forming dual star topology SIRO network, can carry out inside
The data of high speed are transmitted, and dual star network not only increases communication bandwidth, and also adds redundancy, once one of those
Switching Module failure, then dual star topology SRIO network, which becomes single star-like SRIO network, to work on；It is counted using multiple DSP
According to parallel computation, improve data calculating efficiency, and each DSP calculate same quantity of data data, avoid wooden barrel
The generation of effect, and each DSP is multi-core DSP, operational capability is strong；In addition, being powered off for the DSP of failure, function is reduced
Consumption.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of embedded type parallel computation system, which is characterized in that the system comprises a data input module, it is multiple completely
Identical cabinet and a data outputting module；Each described cabinet includes two Switching Modules, multiple computing modules, one
Bottom plate and a power management module；Each described Switching Module includes an optic fiber converter, a SRIO exchange chip
With a GbE exchange chip, each described computing module includes two panels multi-core DSP, a SRIO exchange chip and one
FPGA；SRIO exchange chip in each described Switching Module with the SRIO exchange chip in computing module described in each
It is connected, the GbE exchange chip in each described Switching Module is connected with the multi-core DSP in each computing module respectively, often
GbE exchange chip in one Switching Module is also connected with power management module, the light in each described Switching Module
Fine converter is connected with other cabinets or data input module or data outputting module；
Outer input interface by the data input module to Master input pending data, by Master by it is described to
Reason data are averagely allocated to available slave, each slave receives corresponding pending data, according to the kernel of slave
Corresponding pending data is averagely allocated to the kernel of the slave to be held accordingly by corresponding kernel by number
Row, and implementing result is returned into Master, merged by the implementing result that Master returns to all slave, and pass through data
Output module is exported through external output interface, wherein Master is one in all DSP of all cabinets, and other DSP are equal
For slave.
2. a kind of embedded type parallel computation system as described in claim 1, which is characterized in that in each described Switching Module
SRIO exchange chip pass through 1 road SRIO respectively by chassis backplane and the SRIO exchange chip phase in each computing module
Even, the SRIO exchange chip in the Switching Module passes through other cabinets or the institute of optic fiber converter and uplink by 2 road SRIO
It states data input module to be connected, another other cabinets or the data by 2 road SRIO by optic fiber converter and downlink export
Module is connected；GbE exchange chip in each described Switching Module passes through 2 in 2 road GbE and each computing module
DSP is connected, and is separately connected to other cabinets by 1 road GbE, and be connected to the power management module by 1 road GbE；Each
2 DSP in computing module pass through SRIO all the way and are connected with the SRIO exchange chip in the computing module；The data input
Module is connected with the Master in all DSP in all cabinets by SRIO interface, the data outputting module with it is described
Master is connected by SRIO interface.
3. embedded type parallel computation system as described in claim 1, which is characterized in that the quantity of the cabinet and each
The quantity of computing module in cabinet is determined all in accordance with the operand of pending data.
4. a kind of embedded type parallel computation system as described in claim 1, which is characterized in that all DSP are all made of 8 cores
DSP, working frequency 1.25GHz support GbE interface, DDR3 interface or SRIO interface, the outer input interface and outside
Output interface is CameraLink, LVDS, TLK2711,10GbE, InfiniBand or customized high-speed interface.
5. a kind of parallel calculating method of the described in any item embedded type parallel computation systems of claim 1-4, which is characterized in that
The method includes：
S1, outer input interface input pending data to Master by the data input module；
The pending data is averagely allocated to available slave by S2, Master, each slave receive accordingly to
Handle data, according to the slave interior nucleus number by corresponding pending data be averagely allocated to the kernel of the slave so as to
It is executed accordingly by corresponding kernel, and implementing result is returned into Master；
The implementing result that S3, Master return to all slave merges, and defeated through external output interface by data outputting module
Out；
Wherein, Master is one in all DSP of all cabinets, and other DSP are slave.
6. parallel calculating method as claimed in claim 5, which is characterized in that determined in all DSP in the following manner
Master：
After powering on, all DSP pass through GbE and broadcast itself unique ID number to other DSP, each after broadcast reception
The ID number of all DSP is stored in a DSP；
Each DSP is ranked up the ID number of all DSP according to pre-defined rule, and by sort first the corresponding DSP of ID number
As the Master of all DSP, other DSP are as Slave.
7. parallel calculating method as claimed in claim 6, which is characterized in that the method also includes：
The Master timing sends heartbeat signal to all Slave, if receiving slave return within the first predetermined time
Heartbeat response, then determine that the slave is available, otherwise, it is determined that the slave fails；
After having determined the working condition of all slave, Master records available slave quantity again, and is informed by GbE
Power management module powers off the computing module where the slave of failure.
8. parallel calculating method as claimed in claim 7, which is characterized in that the method also includes：
If slave is not received by the heartbeat signal of Master transmission within second scheduled time, determine that the Master fails,
And Master is redefined from all slave.
9. parallel calculating method as claimed in claim 5, which is characterized in that the step S1 is specifically included：
Data input module will be converted to SRIO interface signal by the input interface signal of outer input interface input, and will turn
SRIO interface signal transfer after changing is to Master；
The step S3 is specifically included：
The implementing result that Master returns to all other DSP merges, and data outputting module is by the implementing result data after merging
External output interface form is converted to from SRIO interface signal form and is exported through external output interface.
10. parallel calculating method as claimed in claim 5, which is characterized in that Master is by described wait locate in the step S2
Reason data are averagely allocated to available slave and specifically include：
Pending data is divided into x parts, and connect by SRIO by calling the MPI standard routine interface provided by Master
Mouth is sent to corresponding slave, wherein x is available slave quantity, and x is positive integer；
Corresponding pending data is averagely allocated to the slave's according to the interior nucleus number of the slave in the step S2
Kernel specifically includes：
Slave is by the OpenMP standard interface program that provides according to the interior nucleus number of slave by corresponding pending data
Y parts are divided into, and is sent to corresponding kernel.
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| TWI620074B (en) * | 2016-07-12 | 2018-04-01 | 緯創資通股份有限公司 | Server system and control method for storage unit |
| CN108020996B (en) * | 2016-10-31 | 2020-04-10 | 上海微电子装备（集团）股份有限公司 | Bus synchronous control architecture and control method |
| CN109213684B (en) * | 2018-09-18 | 2022-01-28 | 北京工业大学 | Program detection method based on OpenMP thread heartbeat detection technology and application |
| CN110297661B (en) * | 2019-05-21 | 2021-05-11 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Parallel computing method, system and medium based on AMP framework DSP operating system |
| CN112631986B (en) * | 2020-12-28 | 2024-04-02 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Large-scale DSP parallel computing device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101089840A (en) * | 2007-07-12 | 2007-12-19 | 浙江大学 | Matrix multiplication parallel computing system based on multi-FPGA |
| CN101702721A (en) * | 2009-10-26 | 2010-05-05 | 北京航空航天大学 | Reconfigurable method of multi-cluster system |
| CN101819651A (en) * | 2010-04-16 | 2010-09-01 | 浙江大学 | Method for parallel execution of particle swarm optimization algorithm on multiple computers |
| CN102646223A (en) * | 2012-02-17 | 2012-08-22 | 中国电力科学研究院 | Multi-user remote parallel computation system |
| CN102710477A (en) * | 2012-05-15 | 2012-10-03 | 浙江大学 | Data processing system based on VPX bus structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101480867B1 (en) * | 2013-05-31 | 2015-01-09 | 삼성에스디에스 주식회사 | System and method for accelerating mapreduce operation |
-
2015
- 2015-08-13 CN CN201510496959.3A patent/CN105045566B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101089840A (en) * | 2007-07-12 | 2007-12-19 | 浙江大学 | Matrix multiplication parallel computing system based on multi-FPGA |
| CN101702721A (en) * | 2009-10-26 | 2010-05-05 | 北京航空航天大学 | Reconfigurable method of multi-cluster system |
| CN101819651A (en) * | 2010-04-16 | 2010-09-01 | 浙江大学 | Method for parallel execution of particle swarm optimization algorithm on multiple computers |
| CN102646223A (en) * | 2012-02-17 | 2012-08-22 | 中国电力科学研究院 | Multi-user remote parallel computation system |
| CN102710477A (en) * | 2012-05-15 | 2012-10-03 | 浙江大学 | Data processing system based on VPX bus structure |
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