CN108009074B

CN108009074B - Multi-core system real-time evaluation method based on model and dynamic analysis

Info

Publication number: CN108009074B
Application number: CN201711192032.6A
Authority: CN
Inventors: 王世海; 李垚男; 刘斌
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2017-11-24
Filing date: 2017-11-24
Publication date: 2020-04-17
Anticipated expiration: 2037-11-24
Also published as: CN108009074A

Abstract

The invention discloses a multi-core system real-time evaluation method based on a model and dynamic analysis, belonging to the technical field of embedded multi-core system real-time evaluation; the method comprises the steps of firstly obtaining resource parameters of the embedded multi-core system, defining the generation mode of tasks, the use state of BUS on a shared resource SoC chip and the relationship between the use state of the tasks and the shared resource. And then establishing a petri-net model, and calculating the hit rate of the simulated cache. Receiving task access when the bus is idle, and indicating that a task occupies resources and is in the state synchronously with the resources when the bus is busy; the time read in by the task obeys exponential distribution with a parameter of lambda; the time length of the implicit communication of the task is fixed, and the number of the implicit communication is subject to the uniform distribution of the parameters a and b. And finally, operating the model within a set time, and performing real-time analysis after the operation. The real-time evaluation result of the invention is more consistent with the real running condition, and the execution model of the multi-core IMA task is objectively and visually provided.

Description

Multi-core system real-time evaluation method based on model and dynamic analysis

Technical Field

The invention belongs to the technical field of embedded multi-core system real-time assessment, and relates to a multi-core system real-time assessment method based on a model and dynamic analysis.

Background

The integrated Modular avionics system ima (integrated Modular avinics) integration hierarchy can be divided into three layers of architecture, namely resource integration, function integration and management integration.

The resource integration comprises physical integration and data integration, wherein the physical integration refers to the integration of equipment resources in the whole avionics system structure, such as computing resources, network communication resources and IO resources, the equipment resource allocation mode in the complete avionics distributed environment is determined, and the analysis and evaluation of the resource allocation are carried out on the basis, so that the design capability of the IMA system is improved; and a large amount of data resources exist at the bottom layer of the whole IMA system, the data sources are different, the meanings are different, the storage organization modes are different, and even the organization modes of the data of the same type are different, so that unified data semantic representation and capability description need to be formulated, data resource fusion is carried out based on capability operation, and technical support is provided for upper-layer function synthesis and management synthesis.

A function, i.e., information processing, is a process of changing the state of one or more resources. The purpose of function synthesis is to improve the system efficiency on the basis of the existing resources, and the main means comprises execution process multiplexing and result sharing. The method comprises the steps of decomposing functions of upper-layer applications, establishing basic functional components with clear classification, standard process, standard interface and universal result to construct a task sharing platform, and executing task scheduling by a unified task scheduling engine, so that the most powerful efficiency service is provided for the system with the least activities, and the function synthesis is realized.

The functions of all avionic systems, such as navigation, detection, atmospheric data, friend or foe identification, flight management, fire control, display control and the like, are completed through cooperation on the basis of the existing resources and functions. The purpose of management integration is to reduce defects and errors of the system and effectively manage faults through integrated management, thereby improving the effectiveness and stability of the system. The residual effective capacity of the current system is integrated through operations such as task construction, function organization, resource allocation and the like, and the organic organization of tasks, functions and resources based on state monitoring is realized, so that the overall efficiency of the system is improved. The above requirements require unified management, monitoring and configuration of all resources, tasks and functions within the system scope, and an effective execution scheme is customized to meet flight requirements and combat tasks.

Avionics systems are becoming more complex and integrated. Integration has advanced from displays to data processing to sensor systems where the desire for system computing power has become increasingly strong. Experience in the consumer electronics field has shown that multiple cores are an important way to improve processor performance in cases where processor frequency, process, is in the bottleneck. From another perspective, the multi-core also embodies the important development prospect of resource synthesis in IMA synthesis level.

Multi-core systems have been developed for many years in the field of commercial electronics. In the situation that the processing frequency and size of the processor have reached a bottleneck, multi-core has been proved to be a development direction capable of effectively improving the processing capacity of the system. From the perspective of the IMA system, the appearance of multiple cores is also an important development direction for the resource fusion of the IMA system. The basic partitioning and process concept described in ARINC 653 is a hardware unit related to what is referred to as a single core module. The authentication of the multi-core processor is also in a relatively preliminary case, and historically authenticated processing systems are all single-core systems.

At present, the task execution time of the embedded multi-core system is uncertain due to the cache hit rate, and the industry has not provided a good solution, and the problem is a hot spot of recent research in the industry.

Disclosure of Invention

The invention provides a model-based real-time evaluation method for dynamic analysis aiming at shared IO (input/output) resources on a chip, aiming at solving the problem that the real-time performance of a task is uncertain due to the fact that the hit rate of an embedded multi-core system in cache is limited, and a multi-core real-time performance is evaluated in a timed petri net modeling mode.

The invention provides a multi-core system real-time evaluation method based on a model and dynamic analysis, which comprises the following steps:

step 1, acquiring resource parameters of an embedded multi-core system, wherein the resource parameters comprise the number of cores, cache hit rate and types of computing resources shared by the cores; defining the generation mode of the task; according to the generated tasks, giving a scheduling mode of the multi-core processor; giving the use strategy of IO; and the use state of the tasks on the BUS on the SoC chip of the shared resource and the relationship between the use states of the tasks on the shared resource are clear.

Step 2, establishing a petri-net model for the task execution process of the embedded multi-core system, wherein the model comprises four parts: the system comprises a task generating module, a task waiting queue, a task processing and service module and a task completion list.

Step 3, simulating the hit rate c of the cache by the following formula_h；

Wherein the content of the first and second substances,setting the time t occupied by the bus read-in phase_rObeying exponential distribution with parameter lambda, and the time t occupied by bus implicit communication phase caused by cache_icObeying a uniform distribution of the parameters a, b.

Step 4, when the bus is in idle state, the access of the task can be received, and when the bus is in busy state, the task occupies the resource and is in the state synchronously with the resource; when the task is in a reading-in stage, the reading-in time obeys exponential distribution with a parameter of lambda; when the task is in the implicit communication stage, the time length of the implicit communication is fixed, and the times of the implicit communication obey the uniform distribution of the parameters a and b;

and 5, operating the model within set time, and performing real-time analysis after the model is operated.

Step 5, carrying out real-time analysis, comprising the following steps: analyzing whether a task queue of a single core generates a blocking condition or not; analyzing the task generation time and the task completion time in the total task completion list, calculating the difference value between the task completion time and the task generation time, analyzing whether the difference value is increasing, and counting the mathematical expectation and the variance of the difference value if the difference value is not increasing.

Compared with the prior art, the invention has the advantages and positive effects that:

(1) a model construction method based on timesharing hierarchy petri-net utilizes a mathematical modeling method to construct a multi-core IMA task processing model, and objectively and visually provides an execution model of the multi-core IMA task.

(2) A cache hit rate conversion method based on cache hit rate converts cache hit rate into kernel reading task time and cache hit rate conversion of the number of times of a cache, utilizes mathematical expectation analysis conditions of related generation functions and related mathematical deduction to structure the influence of the cache hit rate on a system, and realizes modeling in the model, so that real-time evaluation results are more consistent with real operation conditions.

(3) A multi-core IMA task real-time analysis and evaluation method based on a model dynamically analyzes the task blocking condition in the task execution process by giving a longer time to dynamically operate the model. After the task is executed, the real-time analysis of the completed task can be displayed and visually analyzed.

Drawings

FIG. 1 is a diagram of a physical model of a hardware architecture of a multi-core shared memory processor;

FIG. 2 is a time-resolved task-based execution of a multi-core shared memory processor;

FIG. 3 is a schematic diagram of a task generation and service model modeling method based on queuing theory according to the present invention;

FIG. 4 is a schematic diagram of a task generation model modeling method based on queuing theory according to the present invention;

FIG. 5 is a schematic diagram of a task processing model modeling method using a statistical theory and a Bus scheduling strategy as FIFO according to the present invention;

FIG. 6 is a schematic diagram of a Bus scheduling strategy according to the present invention, which is a task fusion queue replacement based on priority scheduling;

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings.

When the model is established for the cache of the embedded multi-core system, the following information needs to be determined and obtained:

explicit resource parameters are required, including the number of compute cores, the hit rate of the cache, and the type of compute resources shared by the cores, among others.

The method needs to define the generation mode of the task, and the generation mode of the task has two modes, one mode is a given task set, and the satisfaction condition of the real-time performance of the task set is analyzed for the given task set. The second case is that the generation of the task is random. In case the task generation is random, a distribution of the arrival of tasks per unit time is required. If the distribution of the arrival of the tasks is not specified, the Poisson distribution is adopted by default.

According to the generated tasks, the scheduling mode of the multi-core processor is given, such as the scheduling mode of time sharing (timeharing), the scheduling mode of space sharing (space sharing) and the mode of collective scheduling (gang sharing). And scheduling the task generated in the last step by using a selected scheduling mode, namely selecting a core to be executed by the task.

Given the usage policy of IO, there are generally three types: fixed Priority (Fixed Priority), Round Robin (Round Robin), time sliced (TDMA). Tasks that want to use IO come from locking tasks to run on the core.

And the use state of the tasks on the BUS on the shared resource slice SoC and the relationship between the use states of the tasks on the shared resource slice SoC are clarified. The use states of the BUS by the task are divided into unused (idle), read-in, implicit communication and write-out. The unused state will transition to the written state. After the written state is finished, the communication state is transferred to an implicit communication state. The implicit communication state may transition to a write-out phase, or the implicit communication may transition to the implicit communication state itself, and the write-out state may transition to an idle state.

Embodiments of the present invention are described in connection with a shared memory processor. The shared cache level may be different on different versions of the multi-core processor. For simplicity, the present invention will describe a real multi-core shared memory processor with an abstract model of some key elements.

As shown in FIG. 1, the core (core) is bound to a Level1 cache (Level1_ cache), which in the example of FIG. 1 contains two cores core1 and core 2. In the entire model, cores and caches are always taken into account. In effect, the core portion of the cache is the underlying model described below. The coherency structure is also reduced to a Shared Bus (Shared Bus), which is a key element. The peripheral devices and the memory are connected to the memory through a shared bus. It should be noted that the Memory is divided into several parts, including a Memory for core1 (Memory for core1), a Memory for core2 (Memory for core2) and a shared Memory (SharedMemory). The spatial separation may be accomplished in a manner that different core-cache portions have different memories. The shared memory is used for information exchange. One core cache portion writes to the shared memory and then the other core cache portion reads the shared memory. For devices, the device can be classified into 2 types, one type is a Preemptive device (Preemptive devices), and the other type is a Non-Preemptive device (Non-Preemptive devices). A preemptive device is a device that cannot take over during use. If the principle is violated, some unrecoverable results may occur.

From the top level, the entire bus access phase can be divided into two phases, as shown in FIG. 2. One is a scheduling Phase (schedule Phase) and the other is an interrupt Phase (interrupt Phase). In the scheduling phase it contains several blocks (blocks), different blocks representing different tasks. It is really important that the relative positions of these blocks result in data dependencies, which have a large impact on the WCET (Worst-Case execution Time) that is really of interest. There are several approaches that can be addressed if the Bus schedule is determined at design time. The interrupt phase is a phase that cannot be ignored when applied to IMA systems. Only during the interrupt phase can the IMA system handle event triggered tasks. The interrupt priority is related to the scheduling scheme of the IMA system and is affected by the safety requirements of the particular aircraft. Within each schedule block time period, the access phase may be divided into 3 phases: read phase (R), execute phase (TE), write phase (W).

In the read phase, the core cache portion retrieves information from memory through Explicit Communication (EC). The core cache portion then performs the local tasks in Implicit Communication (IC) with the memory. There is a problem here. WCET cannot be particularly suitable for the interrupt phase if implicit communication still requires the use of the bus. Since preemption of Bus must cause delays in the following tasks. If this particular implicit communication is done by using another bus, Commercial Off-The-Shelf (COTS) rules may be violated to some extent. To circumvent this problem, the present invention assumes that the core cache portion communicates with the memory using only one bus. In the read phase, the core cache portion sets information to memory through explicit communication.

In the stage of real-time analysis and evaluation of the multi-core IMA, by analyzing a scheduling mode of a bus on a chip and performing mathematical formal transformation on attributes such as key characteristics of a core and hit rate of cache, after a transformed model of a multi-core IMA task processing component is obtained, a real-time evaluation method for performing model-based task real-time statistical analysis and key characteristic evaluation on the transformed evaluation model is used, and a task real-time evaluation method for a timing layer petri-net model based on a multi-core IMA system structure is formed.

The invention discloses a multi-core IMA architecture-based real-time assessment method for a timesharing hierarchy petri-net model, which is shown in figure 3. The invention firstly divides the system into four parts according to the relevant information of the queuing theory, the relevant relation between the task generation and the service calculation, and the four parts are respectively: the task generating module Arrivals, the task waiting Queue, and the processing and service module CPU _ Model of the task complete the task list.

The task has the following attributes:

● JobType, which represents the type of task (jobs), and depends on the priority of jobs, the data type is Int, and the value is 1 or 2;

● At, representing the current time of joba, with the data type Int;

● Core, representing the Core that the work/task will execute, the data type is Int;

● StartAT, which represents the start time of joba, and the data type is Int;

●, cache Miss, representing the failure rate of cache, wherein the data type is Int;

● phase, representing the next phase that a work/task will encounter, including completing F, reading R, computing C, and writing W.

All processes of task (Job) can easily know the time span of the work by comparing the StartAT attribute and the At attribute.

Fig. 3, 4, 5 and 6 are all made by CPN tools software.

In fig. 3, Arrivals represents a task generation module, which functions to continuously generate tasks at certain time intervals. Tasks are generated by hierarchically migrating Arrivals. And the generated tasks are sequentially added to the tail part of the task Queue according to the generated sequence. And the task processing and service module CPU _ Model processes the tasks in Queue according to a specific rule. The processed task finally enters the Completed task list for analysis. The initial state of the transition is identified as an empty queue by 1' [ ] in fig. 3.

As shown in FIG. 4, a modeling method of the module Arrivals is generated for a task. The Init library and the Init transition are the enabling modules of the task generating module, that is, the start of the work of the whole task generating module is controlled. Next _ Job is a task generation interval control library that can control the time interval of task generation by expressions on the incoming arc. The Job _ Arrival transition is a task-generated transition that has two functions: one is to generate a new task through the newjob () function; the other is an output () function, whose function is to output the task. Job _ Arrival is connected to the queue transition to implement the input of the task.

In fig. 4, (-) - @ + expTime (100) means that the time interval during which the task is generated is expTime (100), and expTime (100) is a function defined as follows:

frompoint mean denotes the conversion of an input value mean of int type to a value of real type.

In FIG. 4, the representation of jobs ^ jobis that the queue of jobs is merged with the queue of jobs, and the element jobis placed at the end of the queue of jobs

FIG. 5 is an internal detailed illustration of CPU _ Model transition; the method comprises the following specific steps:

FIG. 5 is a diagram of how a task is handled, considering the shared resource-BUS, with both cores caching with themselves. To understand this pattern, it is inevitable to look at the entire model at one time. The entire model receives tasks from the Queue one by one. A distributedBrand transition is a distributor and can distribute tasks through their Core properties Core. If the core attribute of the job is 1, the job is forwarded to a core1 distribution of a distribution library of the core 1. The transition core1Q and the library core1QTran cooperate to form a task queue of the core1 cache core _ cache _1, and ensure that the task is First-come First-serve (FIFO). Setting two libraries, a busy library and a free idle library, and setting transitions between the two libraries, a free to busy transition idleTobusy and a busy to free transition busy. For core1, for example, the transitions core1idleTobusy, core1busy and libraries busy1, idle 1. The combination of the relocation core1idleTobusy and core1busy, and the library busy1 and idle1 has only one function, and the function is to reject any other task to be processed by the core _ cache _1 when a joba is processed by the core _ cache _ 1. To accomplish this, the combination of these four things acts like a switch. When the switch is idle, the token is allowed to be accepted. After accepting the token, the switch enters a busy state. The switch can only be restored to the idle state after the jobis completed by the transition jobcomp 1. The task is executed through the transition jobcomp 1. jobcomp 1 indicates that core1 is currently done with its task. It is noted that the arcs between jobcompT1 are different from the other arcs. This is an inherited constrained arc whose pointed end must be executed immediately after the start of the arc. When the jobtoken is located in the core _ cache _1, it does not mean that the jobhas been loaded into the core-cache. This means that this job is preempted by core. Only those preempted jobs have access to Queue2 for preemptive access to bus resources. In the simplified model of the present invention shown in FIG. 1, there are only 2 cores, so the maximum length of Queue2 is 2. In this model, the bus scheduling policy is "first come first served".

As the model shows, the bus has four states, Idle (Idle), read (reading), Implicit Communication (IC) and write (writing). The read, IC, and write out phases are considered busy as opposed to idle. It can only be accessed by the core when the bus is idle. The Start transition may determine how long the bus may be used. When a jobtoken transitions through Start, it can decide which way according to the phase attribute it has. After read, the bus returns to the idle state. Meanwhile, the phase of job becomes "C", which represents calculation. When a job is in the compute phase, the only case where the bus is used is implicit communication. After an implicit communication, the after _ computer function will change the phase of the jobs.

The key component of the entire model is the generateTime function in the Start transition. The hit rate of the cache may affect the duration of the task execution. The missing part must be fetched via the bus. When this occurs, the bus is in the implicit communication phase. Thus, the hit rate can be translated into the number of times the job uses the bus in the implicit communication phase. When job completes the computation, the result must be written over the bus. When a jobis written out over the bus, the bus is in the write phase. After the composition phase, the job is reassigned according to its core attributes to enable new job entries.

As shown in fig. 6, when a task occupies a Bus, and the scheduling policy of the Bus is a priority-based scheduling policy, the queue2 inserts the alternative modeling. In fig. 6, the task comes from the wanna _ use _ bus library, and is inserted into the Queue2 by means of priority preemption through send transition. The graph depicted in FIG. 6 may be used to replace the portion of wanna _ use _ bus to Queue2 in FIG. 5 to replace the manner in which tasks use core resources.

The time length of the described implicit communication state is in a functional relation with the hit rate of the cache, and the transition probability of the implicit communication state is in a certain functional relation with the hit rate of the cache. Both relationships are embodied in the generateTime function.

The following is a parameter and form derivation for the generateTime function:

the bus reads in data with d_rThe amount of data read in during the implicit communication phase is d_iTheir hit rate with cache c_hIn a relationship of

Since the bandwidth of the BUS is constant, the above formula can be simplified to

Wherein, t_rTime taken for read-in phase, t_icThe time taken for the implicit communication phase.

In case of task uncertainty, t can be assumed_rObeying an exponential distribution with a parameter λ, namely:

obtaining t from (3)_rThe mathematical expectation of (d) is λ.

Time length t of implicit communication due to cache_icAssuming a uniform distribution of compliance parameters a, b, namely:

t_ic～U(a,b)(4)

from equation (2), we can obtain:

then obtaining t_rIs λ, t_icThe mathematical expectation of (a + b)/2 can be found:

in the model, the simulation of the cache hit rate of the model is realized by controlling parameters a and b and an exponential distribution parameter lambda to satisfy a formula (6).

The parameters a and b are generated in the task generation stage, namely a newJob function is used for generating the parameters, and the cache miss times of the task generated by the newJob are uniform and take all integers between a and b, including a and b. In the generateTime function, the service time of the BUS is one time unit for each cache miss; for the time of the generateTime read-in phase, the read-in duration follows an exponential distribution expected to be λ. Thus, equation (6) can be satisfied.

An example is given below:

the time interval for task generation is exponentially distributed with a parameter of 200. After 3154 time units, the results are as follows:

{jobType＝1,AT＝287,core＝1,startAT＝23}

{jobType＝1,AT＝961,core＝2,startAT＝839}

{jobType＝1,AT＝1847,core＝2,startAT＝1747}

{jobType＝1,AT＝2388,core＝2,startAT＝2272}

{jobType＝1,AT＝2618,core＝2,startAT＝2288}

{jobType＝1,AT＝2811,core＝2,startAT＝2378}

{jobType＝1,AT＝3132,core＝2,startAT＝2676}

{jobType＝2,AT＝1207,core＝1,startAT＝1058}

{jobType＝2,AT＝1537,core＝2,startAT＝1397}

{jobType＝2,AT＝2977,core＝1,startAT＝2605}

where the units of At and startAT are units of time, depending on the settings of the system.

After the task is completed, cacheMiss is 0 and phase F is two pieces of common information and is not an analysis item of interest for the present invention, so these are omitted.

The time interval between tasks is subject to an exponential distribution with a parameter of 100. After 3150 time units, at step 765, the results are as follows:

{jobType＝1，AT＝451，core＝1，startAT＝170}

{jobType＝1，AT＝634，core＝1，startAT＝314}

{jobType＝1，AT＝1222，core＝2，startAT＝689}

{jobType＝1，AT＝1274，core＝1，startAT＝822}

{jobType＝1，AT＝1818，core＝2，startAT＝1395}

{jobType＝1，AT＝2126，core＝2，startAT＝1582}

{jobType＝1，AT＝2618，core＝2，startAT＝1785}

{jobType＝2，AT＝613，core＝2，startAT＝368}

{jobType＝2，AT＝891，core＝2，startAT＝679}

{jobType＝2，AT＝1646，core＝1，startAT＝932}

{jobType＝2，AT＝1937，core＝1，startAT＝1104}

{jobType＝2，AT＝2361，core＝1，startAT＝1124}

{jobType＝2，AT＝2875，core＝1，startAT＝1554}

{jobType＝2，AT＝3150，core＝2，startAT＝2482}

comparing the two above cases, it can be easily deduced that AT-startAT is increasing when the time interval between tasks is exponentially distributed following a parameter of 100, which indicates that the tasks are blocked. However, AT-startAT is stable when the time interval between tasks is subject to an exponential distribution with a parameter of 200. The average value of AT-startAT was 248.2.

As described above, when the state of the shared resource, i.e., the bus, is idle, the access of the task can be accepted, and when the state is busy, it is said that the task occupies the shared resource and is in the state in synchronization with the resource. When the task is in a reading-in stage, the reading-in time obeys exponential distribution with a parameter of lambda; when the task is in the implicit communication phase, the length of time of the implicit communication is fixed. However, the number of implicit communications obeys a uniform distribution of the parameters a, b. Wherein the parameters a, b and λ should satisfy equation (6).

The running time set for running the petri-net model of the invention should be relatively long. After the operation, whether the task queue of a single core generates a blocking condition is analyzed; and analyzing the task generation time and the task completion time in the total task completion list, and calculating the difference value of the task completion time and the task generation time. It is analyzed whether the difference is increasing. If the difference is not increased, statistical data such as mathematical expectation, variance, etc. of the difference is obtained.

Claims

1. A multi-core system real-time assessment method based on model and dynamic analysis is characterized by comprising the following steps:

step 1, acquiring resource parameters of an embedded multi-core system, wherein the resource parameters comprise the number of cores, cache hit rate and types of computing resources shared by the cores; defining the generation mode of the task; according to the generated tasks, giving a scheduling mode of the multi-core processor; giving the use strategy of IO; defining the use state of the task on the shared resource on-chip bus and the relationship between the use state of the task on the shared resource;

step 2, establishing a petri-net model for the task execution process of the embedded multi-core system, wherein the model comprises four parts: the system comprises a task generating module, a task waiting queue, a task processing and service module and a task completion list;

step 3, simulating the hit rate c of the cache by the following formula_h；

Wherein, the time t occupied by the bus read-in phase is set_rObeying exponential distribution with parameter lambda, and the time t occupied by bus implicit communication phase caused by cache_icObeying a uniform distribution of parameters a, b;

2. The method of claim 1, wherein the tasks are generated in two ways, a first way being a given set of tasks and a second way being a randomly generated task; for the first type, analyzing the real-time satisfaction condition of the task set; for the second distribution of the arrival of tasks in a given unit of time, if the distribution of the arrival of tasks is not specified, a poisson distribution is adopted by default.

3. The method according to claim 1, wherein the using state of the bus by the task is divided into idle state, read-in state, implicit communication state and write-out state; the idle state will transition to the write state; after the writing state is finished, the communication system is transferred to an implicit communication state; the implicit communication state is transferred to a writing-out stage or to the implicit communication state itself; the write-out state will transition to the idle state.

4. The method of claim 1, wherein the task comprises the following attributes:

the type of task, JobType, depends on the priority of the task;

the current time At of the task;

a Core, which is a Core that is to perform a task;

the start time of the task StartAt;

cache failure rate cacheMiss;

the next phase to be encountered by the task takes values including finish F, read R, compute C, and write W.

5. The method of claim 1, wherein the task generation module modeling method comprises: setting an Init library and an Init transition of an enabling module, and controlling the start of the work of a task generating module; setting Next _ Job of a task generation interval control library; the task generates the transition Job _ Arrival, and two functions are realized, wherein one function is to generate a new task through a newjob function, and the other function is to output the task through a function output.

6. The method according to claim 1 or 4, characterized in that the processing and service module of the task has internal transition procedures: sequentially receiving tasks from the task waiting queue, and forwarding the tasks to a distribution library of a corresponding core according to the core attribute of the tasks; the task of the distribution library of the core is sent to a task queue of the core cache, and the task is ensured to be first in and first out; setting busy and idle of two libraries and transition idleTobusy and busy between the busy and idle, wherein the function of completing the combination of the four is that when a task is processed by a core cache, any other task is rejected to be processed by the core cache, the combination of the four is like a switch, and the switch is restored to an idle state only after the core completes the current task; queuing Queue2 after the task is preempted by the core to preempt the bus resource; the transition Start determines the time that the bus can be used, when one task token in Queue2 transitions through Start, the bus is used according to the phase attribute phase of the task, and when the task is in the computation phase, the bus state is implicit communication.

7. The method according to claim 1, wherein in step 3, the function for simulating the hit rate of the cache is obtained by the following process:

the cache hit rate is converted into the number of times that a bus is used by a task in an implicit stage, and the time and the transfer probability of the implicit communication state of the bus have a functional relation with the cache hit rate;

let d be the amount of data read by the bus in the read-in phase_rThe amount of data read in during the implicit communication phase is d_iTheir hit rate with cache c_hThe relationship of (1) is:

since the bandwidth of the bus is fixed, the above formula is simplified to

In case of task uncertainty, let t_rAn exponential distribution obeying a parameter λ, expressed as:

to obtain t_rMathematics of (2)Desirably λ;

set time t_icA uniform distribution obeying the parameters a, b, expressed as: t is t_ic～U(a,b)；

Deriving time t_icSatisfy the requirement of

Then from t_rIs λ, t_icThe mathematical expectation of (a + b)/2 yields:

8. the method according to claim 1, wherein in step 3, the parameters a, b are generated in the task generation stage, wherein the number of cache misses of the task is generated by using the newjob generating function, and the number of cache misses of the task is uniformly integer within the range of [ a, b ].

9. The method of claim 1, wherein said step 5, performing a real-time analysis, comprises: analyzing whether a task queue of a single core generates a blocking condition or not; analyzing the task generation time and the task completion time in the total task completion list, calculating the difference value between the task completion time and the task generation time, analyzing whether the difference value is increasing, and counting the mathematical expectation and the variance of the difference value if the difference value is not increasing.