CN114825046B - Semiconductor light-emitting structure and preparation method thereof - Google Patents

Semiconductor light-emitting structure and preparation method thereof Download PDF

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CN114825046B
CN114825046B CN202210732852.4A CN202210732852A CN114825046B CN 114825046 B CN114825046 B CN 114825046B CN 202210732852 A CN202210732852 A CN 202210732852A CN 114825046 B CN114825046 B CN 114825046B
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layer
initial
waveguide layer
etching
contact
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CN114825046A (en
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程洋
赵武
王俊
郭银涛
夏明月
方砚涵
谭少阳
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Suzhou Everbright Photonics Co Ltd
Suzhou Everbright Semiconductor Laser Innovation Research Institute Co Ltd
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Suzhou Everbright Photonics Co Ltd
Suzhou Everbright Semiconductor Laser Innovation Research Institute Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/3013—AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management
    • H01S5/02461—Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management
    • H01S5/02469—Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0421—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Geometry (AREA)
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Abstract

A semiconductor light-emitting structure and a preparation method thereof are provided, wherein the preparation method of the semiconductor light-emitting structure comprises the following steps: sequentially forming an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial upper confinement layer and an initial contact layer on the semiconductor substrate layer; etching the initial contact layer and the initial upper limiting layer to enable the initial contact layer to form a contact layer and the initial upper limiting layer to form an upper limiting layer; etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer by using the upper limiting layer and the contact layer as masks, so that the upper waveguide layer forms the upper waveguide layer, the active layer forms the active layer, the lower waveguide layer forms the lower waveguide layer, and the side walls of the lower waveguide layer, the active layer and the upper waveguide layer are recessed inwards relative to the side walls of the contact layer and the upper limiting layer; and forming a front electrode layer on the contact layer. The method can give consideration to the narrow active layer and the good contact performance of the front electrode and the contact layer.

Description

Semiconductor light-emitting structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor light-emitting structure and a preparation method thereof.
Background
The light-emitting semiconductor device is a device which takes a certain semiconductor material as a working substance to generate stimulated emission, and the working principle is as follows: through a certain excitation mode, the population inversion of non-equilibrium carriers is realized, and the stimulated emission effect is generated. Light-emitting semiconductor devices are widely used because of their small size and high photoelectric conversion efficiency.
At present, the prior art cannot give consideration to a narrow active layer and better contact performance with a front electrode and a contact layer.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the problem that the prior art cannot consider both a narrow active layer and a good contact performance with a front electrode and a contact layer, thereby providing a semiconductor light emitting structure and a method for manufacturing the same.
The invention provides a preparation method of a semiconductor light-emitting structure, which comprises the following steps: providing a semiconductor substrate layer; sequentially forming an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial upper confinement layer and an initial contact layer on the semiconductor substrate layer; etching the initial contact layer and the initial upper limiting layer to enable the initial contact layer to form a contact layer and the initial upper limiting layer to form an upper limiting layer; etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer by taking the upper limiting layer and the contact layer as masks, so that the initial upper waveguide layer forms the upper waveguide layer, the initial active layer forms the active layer, and the initial lower waveguide layer forms the lower waveguide layer, wherein the side walls of the lower waveguide layer, the active layer and the upper waveguide layer are recessed inwards relative to the side walls of the contact layer and the upper limiting layer; and forming a front electrode layer on the contact layer.
Optionally, the method further includes: and before the front electrode layer is formed, forming an insulating epitaxial layer on the semiconductor substrate layer and covering the side walls of the upper waveguide layer, the active layer, the lower waveguide layer, the upper limiting layer and the contact layer, wherein the thermal conductivity of the insulating epitaxial layer is greater than that of the active layer.
Optionally, the ratio of the thermal conductivity of the insulating epitaxial layer to the thermal conductivity of the active layer is 30-70.
Optionally, the method further includes: forming a lower confinement layer on the semiconductor substrate layer prior to forming an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial upper confinement layer and an initial contact layer; the lower waveguide layer, the active layer and the upper waveguide layer are positioned on part of the lower limiting layer; the insulating epitaxial layer is also located on the lower confinement layer.
Optionally, the method further includes: forming a passivation layer on the insulating epitaxial layer and a part of the contact layer, wherein the passivation layer exposes the contact layer above the active layer; the step of forming a front electrode layer on the contact layer comprises the following steps: and forming a front electrode layer on the contact layer exposed by the passivation layer.
Optionally, the process of etching the initial contact layer and the initial upper limit layer is an anisotropic etching process, and the parameters include: the etching solution used comprises HCl and CH 3 Mixed solution of COOH, HCl and CH 3 The molar ratio of COOH is 1:1 to 1: 10.
Optionally, in the step of etching the initial upper waveguide layer, the initial active layer, and the initial lower waveguide layer, a ratio of an etching rate of the initial upper waveguide layer, the initial active layer, and the initial lower waveguide layer to an etching rate of the upper confinement layer and the contact layer is 50 to 1000.
Optionally, the initial upper waveguide layer is made of InGaAs, the initial active layer is made of one or a combination of InGaAs and InAlAs, and the initial lower waveguide layer is made of InGaAs; the process parameters for etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer comprise: the adopted etching solution comprises HBr and HNO 3 HBr and HNO 3 The molar ratio of (A) to (B) is 0.2 to 10.
Optionally, before etching the initial upper waveguide layer, the initial active layer, and the initial lower waveguide layer, a standing treatment is performed on the etching solution used for etching the initial upper waveguide layer, the initial active layer, and the initial lower waveguide layer, where the standing treatment time is 5 days to 10 days.
Optionally, the method further includes: before etching the initial contact layer and the initial upper limiting layer, the method further comprises the following steps: forming a mask layer on part of the initial contact layer; the step of etching the initial contact layer and the initial upper limiting layer comprises the following steps: etching the initial contact layer and the initial upper limiting layer by taking the mask layer as a mask; and after the insulating epitaxial layer is formed, removing the mask layer.
Optionally, the step of forming the insulating epitaxial layer includes: a temperature rising step is carried out, and protective gas is introduced in the temperature rising step; and after the temperature rise step is carried out, introducing reaction gas into the chamber to form the insulating epitaxial layer.
Optionally, the material of the active layer, the material of the upper waveguide layer and the material of the lower waveguide layer all have arsenic atoms therein, and the material of the insulating epitaxial layer comprises InP doped with Fe; the protective gas comprises PH 3 Protective gas and AsH 3 Protective gas, the AsH 3 The flow of the protective gas is far less than the PH 3 The flow of the shielding gas.
Optionally, the AsH 3 The flow of the protective gas occupies the PH 3 The flow rate of the protective gas is 0.01% -1%.
Optionally, the temperature is increased to 550-650 ℃ in the temperature increasing step.
Optionally, the method further includes: before forming the insulating epitaxial layer, at least the side wall of the active layer is subjected to in-situ corrosion treatment, wherein the parameters of the in-situ corrosion treatment comprise: CBr 4 And CCl 4 Mixed gas of (2), CBr 4 The flow rate of (C) is 10sccm to 100sccm, CCl 4 The flow rate of the etching solution is 10sccm to 100sccm, and the etching depth of the side wall is 1nm to 10 nm.
The present invention provides a semiconductor light emitting structure, comprising: a semiconductor substrate layer; the semiconductor substrate layer is provided with a lower waveguide layer, an active layer, an upper waveguide layer, an upper limiting layer and a contact layer which are sequentially stacked, and the side walls of the lower waveguide layer, the active layer and the upper waveguide layer are recessed inwards relative to the side walls of the contact layer and the upper limiting layer; and the front electrode layer is positioned on the contact layer.
Optionally, the method further includes: and the insulating epitaxial layer is positioned on the semiconductor substrate layer and covers the side walls of the upper waveguide layer, the active layer, the lower waveguide layer, the upper limiting layer and the contact layer, and the thermal conductivity of the insulating epitaxial layer is greater than that of the active layer.
Optionally, the material of the insulating epitaxial layer includes InP doped with Fe.
Optionally, the width of the insulating epitaxial layer covering the side wall of the active layer is 50 μm to 400 μm.
Optionally, the width of the active layer is 0.5-15 μm.
Optionally, the sidewalls of the lower, active and upper waveguide layers are recessed with respect to the sidewalls of the contact and upper confinement layers to a depth of 1 to 3 times a total thickness of the lower, active and upper waveguide layers.
Optionally, the total thickness of the upper waveguide layer, the active layer and the lower waveguide layer is less than the thickness of the upper confinement layer.
The technical scheme of the invention has the following beneficial effects:
according to the preparation method of the semiconductor light-emitting structure provided by the technical scheme of the invention, the upper limiting layer and the contact layer are used as masks, the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer are etched, so that the initial upper waveguide layer forms the upper waveguide layer, the initial active layer forms the active layer, the initial lower waveguide layer forms the lower waveguide layer, and the side walls of the lower waveguide layer, the active layer and the upper waveguide layer are recessed inwards relative to the side walls of the contact layer and the upper limiting layer. The side walls of the lower waveguide layer, the active layer and the upper waveguide layer are recessed inwards relative to the side walls of the contact layer and the upper limiting layer, so that the size of the active layer is smaller than the width of the contact layer, the width of the active layer can be relatively smaller, and the purpose of relatively smaller width of the active layer is to increase the side heat dissipation capacity of the active layer, reduce the junction temperature of the active layer in the working process and improve the photoelectric conversion efficiency. Secondly, on the basis that the size of the active layer is relatively small, the width of the contact layer is large, so that the contact area between the contact layer and the front electrode layer is large, the contact performance between the contact layer and the front electrode layer is good, and the contact resistance is reduced.
Further, before the front electrode layer is formed, an insulating epitaxial layer covering the sidewalls of the upper waveguide layer, the active layer, the lower waveguide layer, the upper confinement layer and the contact layer is formed on the semiconductor substrate layer, and the thermal conductivity of the insulating epitaxial layer is greater than that of the active layer. The formation of the insulating epitaxial layer can provide a flat process surface for forming the front electrode layer, so that the preparation of the front electrode layer is easier. And secondly, as the thermal conductivity of the insulating epitaxial layer is greater than that of the active layer, the insulating epitaxial layer can lead out the heat in the active layer in time, and the lower junction temperature of the active layer in the working process is ensured.
Further, before the insulating epitaxial layer is formed, at least the side wall of the active layer is subjected to in-situ corrosion treatment, so that an oxide layer on the surface of the side wall of the active layer is removed, and the growth nucleation of the insulating epitaxial layer is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 4 are schematic structural views illustrating a process of manufacturing a semiconductor light emitting structure;
fig. 5 to 11 are schematic structural views illustrating a manufacturing process of a semiconductor light emitting structure according to an embodiment of the invention.
Detailed Description
A preparation method of a semiconductor light-emitting structure comprises the following steps: referring to fig. 1, a substrate layer 100 is provided; forming a lower confinement layer 110, a lower waveguide layer 120, an active layer 130, an upper waveguide layer 140, an upper confinement layer 150 and a contact layer 160 on the substrate layer 100 in sequence; referring to fig. 1, a mask layer 170 is formed on a portion of the contact layer 160, wherein the mask layer 170 exposes a portion of the contact layer 160; referring to fig. 2, a first anisotropic etching is performed on the contact layer 160 and the upper limiting layer 150 using the mask layer 170 as a mask; referring to fig. 3, a second isotropic etching is performed on the upper waveguide layer 140, the active layer 130, the lower waveguide layer 120 and the lower confinement layer 110 using the mask layer 170 as a mask; referring to fig. 4, the mask layer 170 is removed; forming an insulating layer (not shown) on sidewalls of the lower confinement layer, the lower waveguide layer, the active layer, the upper waveguide layer, the upper confinement layer and the contact layer and on a portion of a top surface of the contact layer; forming a front electrode (not shown) on the surface of the contact layer exposed by the insulating layer; after the back surface of the substrate layer 100 is thinned, a back surface electrode (not shown) is formed on the back surface of the substrate layer 100.
The active layer 130 is usually composed of several layers, and for some active layers 130 with a larger number of layers, such as the active layer of a quantum cascade laser, the thermal conductivity of the active layer exhibits anisotropy, i.e., the thermal conductivity of the active layer along the epitaxial growth direction of the active layer is small, and the thermal conductivity of the active layer along the direction perpendicular to the epitaxial growth direction is large. In order to improve the heat dissipation capability of the semiconductor light emitting structure and lower the junction temperature of the active layer 130, a lateral heat dissipation method is usually adopted, so that the current quantum cascade laser continuously working at room temperature usually adopts a narrow active layer, and the width of the active layer does not exceed 15 micrometers. The electro-optic conversion efficiency of the semiconductor light emitting structure generally increases gradually as the width of the active layer decreases. Although reducing the width of the active layer is beneficial for improving the electro-optic conversion efficiency of the semiconductor light emitting structure, the fabrication of the semiconductor light emitting structure has certain difficulties, thereby limiting the actual width of the active layer. Specifically, referring to fig. 3, in the second isotropic etching, since there is a certain lateral etching phenomenon, the width of the ridge region composed of the lower confinement layer 110, the lower waveguide layer 120, the active layer 130, the upper waveguide layer 140, the upper confinement layer 150, and the contact layer 160 tends to be narrow at the top and wide at the bottom. The width of the contact layer 160 is typically 1 to 6 microns smaller than the width of the active layer, which means that if the width of the active layer is further reduced to below 3 microns, the width of the contact layer 160 will be almost close to 0. Whereas the front electrode has to be made on the contact layer. Once the width of the contact layer is too small or even no longer present, the gold half-contact between the front electrode and the contact layer may cause problems, resulting in increased device resistance and degraded performance. The minimum width of the active region is limited if it is ensured that the front electrode must be in contact with the gold half between the contact layers.
On the basis, the invention provides a preparation method of a semiconductor light-emitting structure, which can give consideration to the narrow active layer, the good contact performance of the front electrode and the contact layer.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
This is described in detail below with reference to fig. 5 to 11.
Referring to fig. 5, a semiconductor substrate layer 200 is provided.
In this embodiment, the semiconductor substrate layer 200 is an InP substrate layer. It should be noted that, in other embodiments, the semiconductor substrate layer may also be made of other materials.
With continued reference to fig. 5, a lower confinement layer 210 is formed on the semiconductor substrate layer 200; an initial lower waveguide layer 220a, an initial active layer 230a, an initial upper waveguide layer 240a, an initial upper confinement layer 250a, and an initial contact layer 260a are sequentially formed on the lower confinement layer 210.
In this embodiment, the material of the initial contact layer 260a includes an InP contact layer, and the material of the initial upper confinement layer 250 includes an InP upper confinement layer. The material of initial upper waveguide layer 240a comprises InGaAs. The material of the preliminary active layer 230a includes one or a combination of InGaAs and InAlAs. The material of the initial lower waveguide layer 220a comprises InGaAs. The lower confinement layer 210 includes an InP lower confinement layer.
With continued reference to fig. 5, a mask layer 270 is formed on a portion of the initial contact layer 260 a.
The material of the mask layer 270 includes silicon oxide.
In one embodiment, the width of the mask layer 270 is 5 μm to 25 μm.
The width of the masking layer 270 refers to the lateral dimension parallel to the page in fig. 5.
Referring to fig. 6, the initial contact layer 260a and the initial upper confinement layer 250a are etched such that the initial contact layer 260a forms the contact layer 260 and the initial upper confinement layer 250a forms the upper confinement layer 250.
Specifically, the mask layer 270 is used as a mask to etch the initial contact layer 260a and the initial upper limiting layer 250 a.
The process of etching the initial contact layer 260a and the initial upper limiting layer 250a is an anisotropic etching process, so that the sidewalls of the contact layer 260 and the upper limiting layer 250 have good verticality.
In a specific embodiment, the parameters of the anisotropic etching process for etching the initial contact layer and the initial upper limiting layer include: the etching solution used comprises HCl and CH 3 Of COOHMixed solution of HCl and CH 3 The molar ratio of COOH is 1:1 to 1:10, for example 1: 3. in the anisotropic etching process for etching the initial contact layer and the initial upper limiting layer, when HCl and CH are adopted 3 The molar ratio of COOH was 1: 3, the verticality of the sidewalls of the contact layer 260 and the upper limiting layer 250 is the best.
Referring to fig. 7, the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a are etched using the upper confinement layer 250 and the contact layer 260 as masks, so that the preliminary upper waveguide layer 240a forms the upper waveguide layer 240, the preliminary active layer 230a forms the active layer 230, and the preliminary lower waveguide layer 220a forms the lower waveguide layer 220, and sidewalls of the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240 are recessed inward with respect to sidewalls of the contact layer 260 and the upper confinement layer 250.
In the step of etching the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a, the mask layer 270 also protects the top surface of the contact layer 260.
In the step of etching the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a, the etching rate of the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a is greater than the etching rate of the upper confinement layer 250 and the contact layer 260. This makes the etching solution used in this step less etch the sidewalls of the upper limiting layer 250 and the contact layer 260, and the upper limiting layer 250 and the contact layer 260 can serve as a mask for etching.
The step of etching the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a includes: a first stage and a second stage; in a first stage, etching the initial upper waveguide layer 240a, the initial active layer 230a and the initial lower waveguide layer 220a laterally while etching downward to form a transition upper waveguide layer, a transition active layer and a transition lower waveguide layer, wherein sidewalls of the transition upper waveguide layer, the transition active layer and the transition lower waveguide layer are inclined, a portion of the sidewalls of the transition upper waveguide layer is recessed inward relative to sidewalls of the upper confinement layer 250 and the contact layer 260, a portion of the sidewalls of the transition lower waveguide layer is protruded outward relative to sidewalls of the upper confinement layer 250 and the contact layer 260, that is, a portion of the transition lower waveguide layer is not covered by the upper confinement layer 250 and the contact layer 260, the inclination of the sidewalls of the transition upper waveguide layer, the transition active layer and the transition lower waveguide layer increases from top to bottom, and the inclination refers to an included angle of the sidewalls with a normal direction perpendicular to a surface of the semiconductor substrate layer; in the second stage, under the spatial limitation of the upper limiting layer 250 and the lower limiting layer 210, the transition upper waveguide layer, the transition active layer and the transition lower waveguide layer are laterally etched, because the sidewalls of a part of the transition lower waveguide layer protrude outwards relative to the sidewalls of the upper limiting layer 250 and the contact layer 260, the lateral etching rate of the transition upper waveguide layer, the transition active layer and the transition lower waveguide layer increases from top to bottom, specifically, the surface area of the sidewall surface of the transition lower waveguide layer is larger, the degree of corrosion of the sidewall surface of the transition lower waveguide layer by the etching solution is larger, and as the second stage is performed, the verticality of the sidewall surfaces of the transition upper waveguide layer, the transition active layer and the transition lower waveguide layer is continuously increased, so that the verticality of the sidewalls of the formed lower waveguide layer 220, the active layer 230 and the upper waveguide layer 240 is higher.
In one embodiment, the sidewall surfaces of the lower waveguide layer 220, the active layer 230 and the upper waveguide layer 240 are at an angle of 0-10 degrees with respect to the surface normal direction of the semiconductor substrate layer.
The sidewall verticality of the active layer 230 is good, so that the current density difference inside the active layer 230 is small, and the performance of the semiconductor light-emitting device is stable. The included angle between the side wall surface of the active layer 230 and the surface normal direction of the semiconductor substrate layer is 0-10 degrees.
Because the verticality of the side wall of the active layer 230 is good, the limitation on the width reduction of the active layer 230 is reduced, the width of the active layer 230 can be reduced, the width of the contact layer cannot be influenced, and the contact performance between the contact layer and the subsequent front electrode layer cannot be influenced. The fabrication of the front electrode layer is no longer limited by the width of the active layer 230.
In one embodiment, the total thickness of the initial upper waveguide layer 240a, the initial active layer 230a and the initial lower waveguide layer 220a is less than the thickness of the upper confinement layer 250. In a specific embodiment, the combined thickness of the initial upper waveguide layer 240a, the initial active layer 230a, and the initial lower waveguide layer 220a is 1.5-2.5 microns.
It should be noted that, since the total thickness of the initial upper waveguide layer 240a, the initial active layer 230a and the initial lower waveguide layer 220a is small, the inclination of the sidewalls of the transition upper waveguide layer, the transition active layer and the transition lower waveguide layer formed in the first stage is not so large, which is helpful for improving the verticality of the lower waveguide layer 220, the active layer 230 and the upper waveguide layer 240.
In one embodiment, the contact layer 260 and the upper confinement layer 250 have a total thickness of 4 microns to 5 microns. The total thickness of the lower waveguide layer 220, the active layer 230 and the upper waveguide layer 240 is 1.5-2.5 microns.
The thermal conductivity of the active layer 230 in a plane perpendicular to the epitaxial growth direction of the active layer 230 is greater than the thermal conductivity of the active layer in the epitaxial growth direction of the active layer 230.
In one embodiment, the width of the active layer 230 is 0.5-15 microns. Since the width of the active layer 230 is small, the degree of heat dissipation from the side of the active layer 230 is increased, which can lower the junction temperature of the active layer 130 during operation. The electro-optic conversion efficiency of the semiconductor light emitting structure gradually increases as the width of the active layer 230 decreases.
In one embodiment, the sidewalls of the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240 are recessed relative to the sidewalls of the contact layer 260 and the upper confinement layer 250 to a depth that is 1 to 3 times the total thickness of the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240.
Specifically, in one embodiment, the sidewalls of the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240 are recessed relative to the sidewalls of the contact layer 260 and the upper confinement layer 250 to a depth of 2 microns to 6 microns.
In one embodiment, in the step of etching the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a, a ratio of an etching rate of the preliminary upper waveguide layer 240a, the preliminary active layer 230a, and the preliminary lower waveguide layer 220a to an etching rate of the upper stopper layer 250 and the contact layer 260 is 50 to 1000.
In this embodiment, the initial upper waveguide layer is made of InGaAs, the initial active layer is made of one or a combination of InGaAs and InAlAs, and the initial lower waveguide layer is made of InGaAs; the process parameters for etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer comprise: the adopted etching solution comprises HBr and HNO 3 HBr and HNO 3 The molar ratio of (A) to (B) is 0.2 to 10, for example 1: 1.
In one embodiment, before the initial upper waveguide layer 240a, the initial active layer 230a and the initial lower waveguide layer 220a are etched, the etching solution used for etching the initial upper waveguide layer 240a, the initial active layer 230a and the initial lower waveguide layer 220a is subjected to a standing treatment, and the standing treatment time is 5 days to 10 days. Has the advantages that: the concentration of the solution after standing treatment gradually tends to be stable, and the corrosion rate is controllable. If the solution is not kept still or the stabilization time is not enough, the corrosion rate of the solution is unstable, and the control of the corrosion depth is influenced.
Referring to fig. 8, an insulating epitaxial layer 280 covering sidewalls of the upper waveguide layer 240, the active layer 230, the lower waveguide layer 220, the upper confinement layer 250 and the contact layer 260 is formed on the semiconductor substrate layer 200, and a thermal conductivity of the insulating epitaxial layer 280 is greater than a thermal conductivity of the active layer 230.
The insulating epitaxial layer 280 is also located on the lower confinement layer 210.
In a specific embodiment, the ratio of the thermal conductivity of the insulating epitaxial layer 280 to the thermal conductivity of the active layer 230 is 30 to 70, such as 30, 40, 50, 60, or 70.
In one embodiment, the material of the insulating epitaxial layer 280 comprises Fe-doped InP. The insulating epitaxial layer 280 is not conductive, and carriers in the active layer 230 do not pass through the insulating epitaxial layer 280.
The molar concentration of doped Fe in the material of the insulating epitaxial layer 280 is 1 × 10 16 atom/cm 3 ~1×10 18 atom/cm 3 . The reason why the insulating epitaxial layer 280 is doped with Fe is that Fe is a deep acceptor in the InP material and can effectively bind the Fe in the intrinsic InP materialThe electrons are dissociated, causing the InP material to change from an intrinsic semiconductor material to a semi-insulating material.
In the process of forming the insulating epitaxial layer 280, the mask layer 270 protects the top surface of the contact layer 260 and prevents the material of the insulating epitaxial layer 280 from growing on the top surface of the contact layer 260.
The apparatus used for forming the insulating epitaxial layer 280 is HVPE apparatus (hydride vapor phase epitaxy apparatus). The insulating epitaxial layer 280 is grown in the HVPE equipment, so that the insulating epitaxial layer 280 has good growth selectivity and cavities at all positions can be eliminated.
The step of forming the insulating epitaxial layer 280 includes: a temperature rising step is carried out, and protective gas is introduced in the temperature rising step; after the temperature raising step, a reaction gas is introduced into the chamber to form the insulating epitaxial layer 280.
In this embodiment, the material of the active layer 230, the material of the upper waveguide layer 240 and the material of the lower waveguide layer 220 each have arsenic atoms, and the material of the insulating epitaxial layer 280 includes InP doped with Fe; the protective gas comprises PH 3 Protective gas and AsH 3 Shielding gas of said AsH 3 The flow of the protective gas is far less than the PH 3 The flow of the shielding gas. The protective gas protection effect is shown as follows: with the increase of the temperature, the original chemical equilibrium of the surface of the material is broken, the surface of the arsenide and the surface of the phosphide are gradually decomposed, the surface is degraded, and the chemical equilibrium state can be reconstructed by introducing protective gas in the temperature increasing step, so that the surface is prevented from being degraded.
AsH 3 The cracking temperature of the protective gas is far lower than PH 3 Cracking temperature of the protective gas, i.e. at the same temperature, e.g. 600 degrees C, AsH 3 Protective gas and pH 3 The actual decomposition rate of the protective gas is not uniform, AsH 3 The proportion of protective gas decomposed is significantly higher than the pH 3 The proportion of the protective gas decomposed. Once AsH 3 Relative pH of shielding gas 3 The concentration of the protective gas actually decomposed exceeds a certain value, and the surface of the phosphide is subjected to AsH 3 The corrosion of the protective gas causes degradation. And if AsH 3 Protective gas against pH 3 If the concentration of the shielding gas is too low, the surface of the arsenide will lack protection at high temperatures. Therefore, the AsH must be strictly controlled 3 Relative pH of shielding gas 3 Gas flow rate ratio of shielding gas such that the AsH 3 The flow of the protective gas is far less than the PH 3 The flow of the shielding gas.
In one embodiment, the AsH 3 The flow of the protective gas occupies the PH 3 The flow rate of the shielding gas is 0.01% to 1%, for example 0.01%, 0.05%, 0.1%, 0.3%, 0.5%, 0.8%, or 1.0%.
In one embodiment, the temperature raising step raises the temperature to 550-650 ℃.
In one embodiment, since the material of the active layer 230 contains Al, the sidewall surface of the active layer 230 is easily oxidized to form an oxide layer, which affects the epitaxial nucleation growth of the insulating epitaxial layer 280, and thus the oxide layer needs to be removed.
In one embodiment, at least the sidewalls of the active layer 230 are subjected to an in-situ etching process prior to forming the insulating epitaxial layer 280.
In one embodiment, the parameters of the in-situ etch process include: CBr 4 And CCl 4 Mixed gas of (CBr) 4 The flow rate of (2) is 10sccm to 100sccm, CCl 4 The flow rate of the etching solution is 10sccm to 100sccm, and the etching depth of the side wall is 1nm to 10 nm.
Referring to fig. 9, the mask layer 270 is removed.
Referring to fig. 10, a passivation layer 290 is formed on the insulating epitaxial layer 280 and a portion of the contact layer 260, the passivation layer 290 exposing the contact layer 260 above the active layer 230; a front electrode layer 300 is formed on the contact layer 260 exposed by the passivation layer 290.
Referring to fig. 11, the back side of the semiconductor substrate layer 200 is thinned; after that, a back electrode layer 310 is formed on the back surface of the semiconductor substrate layer 200.
Accordingly, another embodiment of the present invention further provides a semiconductor light emitting structure, referring to fig. 11, including: a semiconductor substrate layer 200; a lower waveguide layer 220, an active layer 230, an upper waveguide layer 240, an upper confinement layer 250 and a contact layer 260, which are sequentially stacked on the semiconductor substrate layer 200, wherein sidewalls of the lower waveguide layer 220, the active layer 230 and the upper waveguide layer 240 are recessed inward with respect to sidewalls of the upper confinement layer 250 and the contact layer 260; a front electrode layer 300 on the contact layer 260.
The semiconductor light emitting structure further includes: an insulating epitaxial layer 280 on the semiconductor substrate layer 200 and covering sidewalls of the upper waveguide layer 240, the active layer 230, the lower waveguide layer 220, the upper confinement layer 250, and the contact layer 260, the insulating epitaxial layer 280 having a thermal conductivity greater than a thermal conductivity of the active layer 230.
The material of the insulating epitaxial layer 280 comprises Fe-doped InP.
In one embodiment, the width of the insulating epitaxial layer 280 covering the sidewall of the active layer 230 is 50 μm to 400 μm.
In one embodiment, the width of the active layer 230 is 0.5 μm to 15 μm, such as 0.5 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, 10 μm, 12 μm, or 15 μm.
The semiconductor light emitting structure further includes: a lower confinement layer 210 on the semiconductor substrate layer 200; the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240 are located on a portion of the lower confinement layer 210; the insulating epitaxial layer 280 is also positioned on the lower confinement layer 210; and the back electrode layer 310 is positioned on the surface of the semiconductor substrate layer 200 on the side away from the lower limiting layer 210.
In one embodiment, the material of the upper waveguide layer 240 is InGaAs, the material of the active layer 230 includes one or a combination of InGaAs and InAlAs, and the material of the lower waveguide layer 220 is InGaAs.
In one embodiment, the sidewalls of the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240 are recessed relative to the sidewalls of the contact layer 260 and the upper confinement layer 260 to a depth that is 1 to 3 times, for example 2 times, the total thickness of the lower waveguide layer 220, the active layer 230, and the upper waveguide layer 240.
In one embodiment, the total thickness of the upper waveguide layer 240, the active layer 230, and the lower waveguide layer 220 is less than the thickness of the upper confinement layer 250.
In one embodiment, the angle between the sidewall surface of the active layer 230 and the surface normal direction of the semiconductor substrate layer 200 is 0-10 degrees.
In this embodiment, a semiconductor light emitting structure is described as an example of a side-emitting semiconductor laser, for example, a quantum cascade side-emitting semiconductor laser.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (15)

1. A method for manufacturing a semiconductor light emitting structure comprises the following steps:
providing a semiconductor substrate layer;
sequentially forming an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial upper confinement layer and an initial contact layer on the semiconductor substrate layer;
etching the initial contact layer and the initial upper limiting layer to enable the initial contact layer to form a contact layer and enable the initial upper limiting layer to form an upper limiting layer;
etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer by taking the upper limiting layer and the contact layer as masks, so that the initial upper waveguide layer forms the upper waveguide layer, the initial active layer forms the active layer, and the initial lower waveguide layer forms the lower waveguide layer, wherein the side walls of the lower waveguide layer, the active layer and the upper waveguide layer are recessed inwards relative to the side walls of the contact layer and the upper limiting layer;
and forming a front electrode layer on the contact layer.
2. The method of manufacturing a semiconductor light emitting structure according to claim 1, further comprising: and before the front electrode layer is formed, forming an insulating epitaxial layer on the semiconductor substrate layer and covering the side walls of the upper waveguide layer, the active layer, the lower waveguide layer, the upper limiting layer and the contact layer, wherein the thermal conductivity of the insulating epitaxial layer is greater than that of the active layer.
3. The method for manufacturing a semiconductor light emitting structure according to claim 2, wherein a ratio of a thermal conductivity of the insulating epitaxial layer to a thermal conductivity of the active layer is 30 to 70.
4. The method of manufacturing a semiconductor light emitting structure according to claim 2, further comprising: forming a lower confinement layer on the semiconductor substrate layer prior to forming an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial upper confinement layer and an initial contact layer;
the lower waveguide layer, the active layer and the upper waveguide layer are positioned on part of the lower limiting layer; the insulating epitaxial layer is also located on the lower confinement layer.
5. The method of manufacturing a semiconductor light emitting structure according to claim 2, further comprising: forming a passivation layer on the insulating epitaxial layer and a part of the contact layer, wherein the passivation layer exposes the contact layer above the active layer; the step of forming a front electrode layer on the contact layer comprises the following steps: and forming a front electrode layer on the contact layer exposed by the passivation layer.
6. The method of claim 1, wherein the etching process for the initial contact layer and the initial upper confinement layer is an anisotropic etching process, and the parameters include: the etching solution used comprises HCl and CH 3 Mixed solution of COOH, HCl and CH 3 The molar ratio of COOH is 1:1 to 1: 10.
7. The method of claim 1, wherein the step of etching the preliminary upper waveguide layer, the preliminary active layer and the preliminary lower waveguide layer has a ratio of an etching rate of the preliminary upper waveguide layer, the preliminary active layer and the preliminary lower waveguide layer to an etching rate of the upper confinement layer and the contact layer of 50 to 1000.
8. The method of claim 7, wherein the step of forming the semiconductor light emitting structure comprises the steps of,
the initial upper waveguide layer is made of InGaAs, the initial active layer is made of one or a combination of InGaAs and InAlAs, and the initial lower waveguide layer is made of InGaAs;
the process parameters for etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer comprise: the adopted etching solution comprises HBr and HNO 3 HBr and HNO 3 The molar ratio of (A) to (B) is 0.2 to 10.
9. The method of claim 1 or 8, wherein the etching solution used for etching the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer is subjected to a standing treatment before the etching of the initial upper waveguide layer, the initial active layer and the initial lower waveguide layer, wherein the standing treatment is performed for 5 days to 10 days.
10. The method of manufacturing a semiconductor light emitting structure according to claim 2, further comprising: before etching the initial contact layer and the initial upper limiting layer, the method further comprises: forming a mask layer on part of the initial contact layer; the step of etching the initial contact layer and the initial upper limiting layer comprises the following steps: etching the initial contact layer and the initial upper limiting layer by taking the mask layer as a mask; and after the insulating epitaxial layer is formed, removing the mask layer.
11. The method of manufacturing a semiconductor light emitting structure according to claim 2 or 10, wherein the step of forming the insulating epitaxial layer includes: a temperature rising step is carried out, and protective gas is introduced in the temperature rising step; and after the temperature rise step is carried out, introducing reaction gas into the chamber to form the insulating epitaxial layer.
12. The method as claimed in claim 11, wherein the active layer, the upper waveguide layer and the lower waveguide layer each have arsenic atoms therein, and the insulating epitaxial layer comprises InP doped with Fe;
the protective gas comprises PH 3 Protective gas and AsH 3 Protective gas, the AsH 3 The flow of the protective gas is far less than the PH 3 The flow of the shielding gas.
13. The method for manufacturing the semiconductor light-emitting structure according to claim 12, wherein the AsH is 3 The flow of the protective gas occupies the PH 3 The flow rate of the protective gas is 0.01% -1%.
14. The method of claim 11, wherein the step of raising the temperature raises the temperature to 550-650 ℃.
15. The method of manufacturing a semiconductor light emitting structure according to claim 2, further comprising: before forming the insulating epitaxial layer, at least the side wall of the active layer is subjected to in-situ corrosion treatment, wherein the parameters of the in-situ corrosion treatment comprise: CBr 4 And CCl 4 Mixed gas of (CBr) 4 The flow rate of (C) is 10sccm to 100sccm, CCl 4 The flow rate of the etching solution is 10sccm to 100sccm, and the etching depth of the side wall is 1nm to 10 nm.
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