CN114823924A - Schottky diode with junction terminal extension structure and preparation method thereof - Google Patents
Schottky diode with junction terminal extension structure and preparation method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 6
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 22
- 229910002601 GaN Inorganic materials 0.000 abstract description 20
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052751 metal Inorganic materials 0.000 description 36
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- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
Abstract
The invention discloses a Schottky diode with a junction terminal extension structure and a preparation method thereof + ‑Ga 2 O 3 Substrate layer, n ‑ ‑Ga 2 O 3 A buffer layer, a P-type region and an anode; wherein, the cathode, n + ‑Ga 2 O 3 Substrate layer, n ‑ ‑Ga 2 O 3 The buffer layers are arranged from bottom to top in sequence; n is ‑ ‑Ga 2 O 3 The left end and the right end of the buffer layer are respectively provided with a group of groove structures, and the P-type region covers n in the groove structures and above the groove structures ‑ ‑Ga 2 O 3 The surface of the buffer layer is provided with a buffer layer,to form a junction termination extension structure; the anode is covered with n ‑ ‑Ga 2 O 3 The middle upper surface of the buffer layer extends to the upper surface covering a part of the P-type region. Wherein, the P-type region adopts gallium nitride material. The invention adopts a junction terminal extension structure, introduces the P-type groove with gradually increased depth, disperses the electric field at the edge of the Schottky junction by utilizing the generated transverse PN junction, ensures that the device has smoother equipotential profile, reduces the peak electric field, and avoids P-type Ga by taking P-type GaN as a P-type region 2 O 3 The preparation is difficult.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a Schottky diode with a junction terminal extension structure and a preparation method thereof.
Background
Ga 2 O 3 Large forbidden band width (E) g 4.9eV) brings a theoretically high critical breakdown field strength (E) br 8MV/cm), combined with electron mobility (μ 300 cm) 2 V · s), which makes it a high quality factor in power switch applications. Vertical type Ga as a hotspot of current research 2 O 3 The Schottky diode (SBD) device is simple in structure, the breakdown voltage of the device can be improved by increasing the thickness of the drift layer and reducing the doping concentration of the drift layer, the transverse size of the device cannot be influenced, and the wafer utilization rate is improved. And meanwhile, the SBD is a unipolar device, the reverse recovery time is short, and the frequency characteristic is excellent.
Since Ga is 2 O 3 The breakdown of the SBD mainly occurs at the edge of the schottky junction where the electric field distribution is concentrated, and in order to alleviate the electric field concentration at the edge of the schottky junction, an effective termination technique is required to adjust the electric field at the edge of the schottky junctionAnd distribution is realized, and the purpose of improving the breakdown voltage of the device is realized. For the traditional junction termination structure, the device mainly adjusts the electric field distribution at the edge of the Schottky junction in the vertical direction, and the adjusting effect on the electric field is limited. Furthermore, Ga 2 O 3 Easily introduce donor energy level such as oxygen vacancy and the like, resulting in P-type Ga 2 O 3 It is difficult to prepare.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a schottky diode having a junction termination extension structure and a method for manufacturing the same. The technical problem to be solved by the invention is realized by the following technical scheme:
in one aspect, the present invention provides a schottky diode having a junction termination extension structure, comprising: cathode, n + -Ga 2 O 3 Substrate layer, n - -Ga 2 O 3 A buffer layer, a P-type region and an anode; wherein the content of the first and second substances,
the cathode, n + -Ga 2 O 3 Substrate layer, n - -Ga 2 O 3 The buffer layers are arranged from bottom to top in sequence;
n is - -Ga 2 O 3 A group of groove structures are respectively arranged at the left end and the right end of the buffer layer, and the P-type region covers the n in the groove structures and above the groove structures - -Ga 2 O 3 A buffer layer surface to form a junction termination extension structure;
the anode is covered on the n - -Ga 2 O 3 The middle upper surface of the buffer layer extends to two ends to cover part of the upper surface of the P-type region.
In an embodiment of the invention, each of the groove structures includes a plurality of grooves, and the depth of the grooves gradually increases from the inner side of the device to the left and right sides.
In one embodiment of the invention, the width of each groove is 0.5-2 μm, and the distance between two adjacent grooves is 1-3 μm.
In an embodiment of the present invention, each of the groove structures includes three rectangular trenches, and the aspect ratios of the three rectangular trenches are 1, 2, and 3 in order from the inside to the outside of the device.
In one embodiment of the invention, the growth thickness of the P-type region is 0.2-3 μm.
In one embodiment of the present invention, the doping ions of the P-type region are Mg ions with a doping concentration of 1 × 10 17 ～1×10 19 cm -3 。
In an embodiment of the present invention, the material of the P-type region is P-type gallium nitride.
In one embodiment of the invention, said n + -Ga 2 O 3 Substrate layer and said n - -Ga 2 O 3 The doping ions of the buffer layer are Si ions or Sn ions; wherein the content of the first and second substances,
n is + -Ga 2 O 3 The doping concentration of the substrate layer is 1 x 10 18 ～1×10 20 cm -3 N is said n - -Ga 2 O 3 The doping concentration of the buffer layer is 1 × 10 16 ～1×10 17 cm -3 。
On the other hand, the invention also provides a preparation method of the Schottky diode with the junction terminal extension structure, which comprises the following steps:
selecting n + -Ga 2 O 3 Cleaning the substrate;
at n + -Ga 2 O 3 Epitaxial growth of low doped n on one side of substrate - -Ga 2 O 3 A buffer layer;
for said n - -Ga 2 O 3 Etching the buffer layer for multiple times to form a group of groove structures at the left end and the right end of the buffer layer respectively;
depositing P-type material on the whole sample surface and etching to form n covering the groove structure and the upper part of the groove structure - -Ga 2 O 3 A P-type region on the surface of the buffer layer;
at said n + -Ga 2 O 3 And manufacturing a cathode on the other side of the substrate, and manufacturing an anode on the surface of the obtained sample, thereby completing the preparation of the device.
In one embodiment of the invention, for said n - -Ga 2 O 3 The buffer layer carries out a lot of corrasions to both ends form a set of groove structure respectively about it, include:
at said n - -Ga 2 O 3 Photoresist is spin-coated on the buffer layer, and first groove region patterns are respectively photoetched on the left side and the right side of the buffer layer;
etching the first groove by adopting an ICP device; wherein, the etching conditions are as follows: the power of the upper electrode is 260-300W, the power of the lower electrode is 40-80W, the pressure of the chamber is 10mTorr, Cl 2 The gas flow is 20-60 sccm, and the tray temperature is 20 ℃;
repeating the above steps, and etching the rest grooves in sequence to form n - -Ga 2 O 3 The left end and the right end of the buffer layer respectively form a group of symmetrical groove structures.
The invention has the beneficial effects that:
1. the structure realizes a junction terminal extension structure by introducing a plurality of P-type grooves with gradually increased depths, a plurality of PN junctions are introduced in the transverse direction by adding a plurality of P-type grooves with gradually increased depths, and the electric field at the edge of the Schottky junction is further dispersed by utilizing the transverse electric field generated by the PN junctions, so that the device has a smoother equipotential profile, the peak electric field is reduced, the electric field distribution at the edge of the Schottky junction is adjusted, and the breakdown voltage of the device is improved; in addition, by adopting the design structure, the improvement on the forward on-resistance can be reduced while the peak electric field at the edge of the Schottky junction is ensured to be reduced;
2. the invention adopts the P-type gallium nitride material as the preparation material of the P-type area, the preparation process is mature, and the P-type Ga is avoided 2 O 3 The prepared P-type gallium nitride has excellent quality, the doping concentration can be specifically characterized and accurately controlled, and the performance of the device is improved.
The present invention will be described in further detail with reference to the drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a schottky diode having a junction termination extension structure according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a schottky diode with a junction termination extension structure according to an embodiment of the present invention;
fig. 3a to 3h are process diagrams of a schottky diode having three rectangular trenches on left and right sides thereof according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a schottky diode with a junction termination extension structure according to an embodiment of the present invention, which sequentially includes, from bottom to top: the method comprises the following steps: cathode 1, n + -Ga 2 O 3 Substrate layer 2, n - -Ga 2 O 3 A buffer layer 3, a P-type region 4 and an anode 5; wherein the content of the first and second substances,
the cathode 1, n + -Ga 2 O 3 Substrate layer 2, n - -Ga 2 O 3 The buffer layers 3 are arranged from bottom to top in sequence;
n is - -Ga 2 O 3 A group of groove structures are respectively arranged at the left end and the right end of the buffer layer 3, and the P-type region 4 covers the n in the groove structures and above the groove structures - -Ga 2 O 3 The surface of the buffer layer 3 is provided with a junction terminal extension structure;
the anode 5 is covered on the n - -Ga 2 O 3 The middle upper surface of the buffer layer 3 extends to cover part of the upper surface of the P-type region 4.
Further, in this embodiment, each of the groove structures includes a plurality of grooves, and the depth of each groove gradually increases from the inner side of the device to the left and right sides. Wherein the width of each groove is 0.5-2 μm, and the distance between two adjacent grooves is 1-3 μm.
In particular, the P-type region 4 is at n - -Ga 2 O 3 Thickness on the buffer layer 3The degree of the doped ion is 0.2 to 3 μm, the doped ion is Mg ion, and the doping concentration is 1 × 10 17 ～1×10 19 cm -3 。
Optionally, as an implementation manner of the present invention, each of the groove structures includes three rectangular grooves, and the depth-to-width ratios (the ratios of the depth to the width) of the three rectangular grooves are 1, 2, and 3 in sequence from the inner side to the outer side of the device, as shown in fig. 1.
In addition, the junction terminal extension structure of the present application may also be implemented by using two or four rectangular trenches, and the aspect ratio of the junction terminal extension structure may also be adaptively adjusted according to actual situations, which is not specifically limited in this embodiment.
The invention realizes a junction terminal extension structure by introducing a plurality of P-type grooves with gradually increased depths. Compared with the traditional junction terminal extension structure, on one hand, the P-type grooves are added, the PN junctions are introduced in the transverse direction, and the transverse electric field generated by the PN junctions further disperses the electric field at the edges of the Schottky junctions, so that the device has a smoother equipotential profile, the peak electric field is reduced, the electric field distribution at the edges of the Schottky junctions is adjusted, and the breakdown voltage of the device is improved. On the other hand, the depth of the P-type groove forming the junction terminal adopts gradient change, and the depth of the P-type groove is gradually reduced along the direction from the edge of the device electrode to the center of the device electrode. By adopting the design, the improvement on the forward on-resistance can be reduced while the peak electric field at the edge of the Schottky junction is reduced.
Further, in the embodiment, the P-type gallium nitride is used as the material of the P-type region (4), the preparation process is mature, the prepared P-type gallium nitride has excellent quality, the doping concentration can be specifically characterized and accurately controlled, the device performance is improved, and the P-type Ga in the prior art is avoided 2 O 3 Difficult preparation. In addition, other P-type substitutes such as P-type NiO can be used to realize the P-type region.
As an implementation of the present invention, the n + -Ga 2 O 3 Substrate layer 2 and said n - -Ga 2 O 3 The doped ions of the buffer layer 3 are Si ions or Sn ions; wherein the content of the first and second substances,
n is + -Ga 2 O 3 The substrate layer 2 has a doping concentration of 1 × 10 18 ～1×10 20 cm -3 The thickness is 300-650 μm; n is - -Ga 2 O 3 The doping concentration of the buffer layer 3 is 1 × 10 16 ～1×10 17 cm -3 The thickness is 5 to 15 μm.
Optionally, in this embodiment, the metal of the cathode 1 is Ti/Au or a combination of Ti/Al/Ni/Au metals. The metal of the anode 5 is a Ni/Au or Pt/Au metal combination.
Specifically, if the cathode metal is a Ti/Au combination, the growth thickness of the first layer of metal Ti is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-200 nm. If the cathode metal is a Ti/Al/Ni/Au combination, the growth thickness of the first layer of metal Ti is 20-100 nm, the growth thickness of the second layer of metal Al is 20-100 nm, the growth thickness of the third layer of metal Ni is 20-100 nm, and the growth thickness of the fourth layer of metal Au is 50-200 nm.
The anode metal can adopt Ni/Au combination or Pt/Au combination, wherein the growth thickness of the first layer of metal Ni or Pt is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-200 nm.
In addition, the present embodiment may also use other metal combinations to realize the anode and the cathode, and the present invention is not limited thereto.
Optionally, in this embodiment, n + -Ga 2 O 3 The substrate layer 2 has doping ions of Si or Sn with a doping concentration of 1 × 10 18 ～1×10 20 cm -3 The thickness is 300 to 650 mu m; n is a radical of an alkyl radical - -Ga 2 O 3 The drift layer 3 is doped with Si ions or Sn ions at a doping concentration of 1X 10 16 ～1×10 17 cm -3 The growth thickness is 5-15 μm.
In the embodiment, the P-type trenches with gradually increased depths are utilized to realize the junction terminal extension structure, on one hand, a plurality of PN junctions are introduced in the transverse direction by adding the P-type trenches with gradually increased depths, and the transverse electric field generated by the PN junctions further disperses the electric field at the edges of the Schottky junctions, so that the device has a smoother equipotential profile, and the peak value is reducedAnd the electric field adjusts the electric field distribution at the edge of the Schottky junction, and the breakdown voltage of the device is improved. In addition, by adopting the design structure, the improvement on the forward on-resistance can be reduced while the peak electric field at the edge of the Schottky junction is ensured to be reduced. On the other hand, the P-type groove is filled with the P-type gallium nitride material, so that P-type Ga is avoided 2 O 3 The prepared P-type gallium nitride has excellent quality, the doping concentration can be specifically characterized and accurately controlled, and the performance of the device is improved.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a schottky diode having a junction termination extension structure. Referring to fig. 2, fig. 2 is a flow chart illustrating a method for manufacturing a schottky diode with a junction termination extension structure according to an embodiment of the present invention.
S1: selecting n + -Ga 2 O 3 The substrate is cleaned.
Specifically, the dopant ions may be Si ions or Sn ions with a doping concentration of 1 × 10 18 ～1×10 20 cm -3 N is 300 to 650 mu m in thickness + -Ga 2 O 3 The material acts as a substrate material. Reference can be made to the existing standard cleaning method for this n + -Ga 2 O 3 The substrate is cleaned, and the specific cleaning process is not described in detail in this embodiment.
S2: at n + -Ga 2 O 3 Epitaxial growth of low doped n on one side of substrate - -Ga 2 O 3 A buffer layer.
Specifically, this embodiment adopts the MOCVD method to clean n + -Ga 2 O 3 The substrate was placed in an MOCVD apparatus at a TMGa flow of 3.0X 10 -6 ～8.0×10 -6 mol/min，O 2 The flow rate is 1.5 multiplied by 10 -2 ～3.0×10 -2 At the process conditions of mol/min, temperature of 70-90 ℃ and pressure of 500Pa under the conditions of n + -Ga 2 O 3 The epitaxial growth thickness of one side of the substrate is 5-15 mu m, the doping ions are Si ions or Sn ions, and the doping concentration rangeIs 1 × 10 16 ～1×10 17 cm -3 Low doped n-type Ga of 2 O 3 Film to form n - -Ga 2 O 3 A buffer layer.
S3: for said n - -Ga 2 O 3 And etching the buffer layer for multiple times to form a group of groove structures at the left end and the right end of the buffer layer respectively.
In particular, in said n - -Ga 2 O 3 Photoresist is spin-coated on the buffer layer, and first groove region patterns are respectively photoetched on the left side and the right side of the buffer layer;
etching the first groove by adopting an ICP device; wherein, the etching conditions are as follows: the upper electrode power is 260-300W/the lower electrode power is 40-80W, the chamber pressure is 10mTorr, and the gas flow rate is Cl 2 20-60 sccm and the temperature of the tray is 20 ℃;
repeating the above steps, and etching the rest grooves in sequence to form n - -Ga 2 O 3 A group of symmetrical groove structures are formed at the left end and the right end of the buffer layer respectively.
In this embodiment, the trench structure may be etched sequentially from the inner side of the device to the outer side, may also be etched sequentially from the outer side of the device to the inner side, and may also adopt other manners, which is not specifically limited in this embodiment.
S4: depositing P-type material on the whole sample surface and etching to form n covering the groove structure and the upper part of the groove structure - -Ga 2 O 3 A P-type region on the surface of the buffer layer.
Preferably, the P-type gallium nitride material is used to form the P-type region in this embodiment.
Firstly, by using an MOCVD method, a P-type gallium nitride material is epitaxially grown on the surface of the sample obtained in the step S3 to fill the groove of each groove structure, and meanwhile, P-type gallium nitride with the thickness of 0.2-3 μm is formed on the surface of the device. Wherein, the doping ion of the P-type gallium nitride is Mg ion, the doping concentration range is 1 × 10 17 ～1×10 19 cm -3 。
Then opening etching is carried out. Spin-coating photoresist on P-type GaN and photoetching to obtain Schottky contact region, and removingPhotoresist to be in n - -Ga 2 O 3 The left and right ends of the buffer layer form a P-type region.
The specific parameters of the etching process are as follows: the power of the upper electrode is 260-300W, the power of the lower electrode is 40-80W, the pressure of the chamber is 9mTorr, BCl 3 /Cl 2 The gas flow rate is 20-30/20-30 sccm, the He pressure is 10torr, the He leakage is 10sccm, and the tray temperature is 20 ℃.
At said n + -Ga 2 O 3 And manufacturing a cathode on the other side of the substrate, and manufacturing an anode on the surface of the obtained sample, thereby completing the preparation of the device.
First, a bottom electrode (cathode) is fabricated. At n + -Ga 2 O 3 And the cathode of the Schottky diode is grown on the other side surface of the substrate. Using electron beam evaporation stage at Ga 2 O 3 The back of the substrate is sequentially evaporated with Ti/Au or Ti/Al/Ni/Au metal combination. After evaporation of the electrode metal, N at 500-800 DEG C 2 And performing rapid thermal annealing for 50-80 s in the environment to form ohmic contact.
Specifically, the cathode metal can be a Ti/Au combination, the growth thickness of the first layer of metal Ti is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-200 nm.
In addition, the cathode metal can also be a Ti/Al/Ni/Au combination, the growth thickness of the first layer of metal Ti is 20-100 nm, the growth thickness of the second layer of metal Al is 20-100 nm, the growth thickness of the third layer of metal Ni is 20-100 nm, and the growth thickness of the fourth layer of metal Au is 50-200 nm.
Then, a top electrode (anode) was produced. And (3) evaporating the Ni/Au combination or the Pt/Au combination on the surface of the device in sequence by using an electron beam to serve as an anode.
The anode metal can adopt Ni/Au combination or Pt/Au combination, wherein the growth thickness of the first layer of metal Ni or Pt is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-200 nm.
Thus, the preparation of the Schottky diode with the junction terminal extension structure is completed.
EXAMPLE III
On the basis of the second embodiment, the following takes the example of manufacturing a schottky diode having three rectangular trenches on the left and right sides, and details the manufacturing process of the present invention are described with reference to the drawings. Referring to fig. 3a to 3h, fig. 3a to 3h are process diagrams of a schottky diode having three rectangular trenches on left and right sides thereof according to an embodiment of the present invention, which specifically include:
step 1: selecting n + -Ga 2 O 3 The substrate is cleaned.
Step 2: at n + -Ga 2 O 3 Epitaxial growth of low doped n on one side of substrate - -Ga 2 O 3 A buffer layer.
Specifically, n after washing is added + -Ga 2 O 3 The substrate was placed in an MOCVD apparatus at a TMGa flow of 3.0X 10 -6 ～8.0×10 -6 mol/min，O 2 The flow rate is 1.5X 10 -2 ～3.0×10 -2 At the process conditions of mol/min, temperature of 70-90 ℃ and pressure of 500Pa under the conditions of n + -Ga 2 O 3 The epitaxial growth thickness of one side of the substrate is 5-15 μm, the doping ions are Si ions or Sn ions, and the doping concentration range is 1 × 10 16 ～1×10 17 cm -3 Low doped n of - -Ga 2 O 3 Film to form n - -Ga 2 O 3 Buffer layer, as shown in fig. 3 a.
And step 3: a first rectangular trench is lithographically etched.
Firstly, photoresist is coated on the buffer layer in a spinning mode, and the innermost side groove region graph is photoetched.
Then, etching an innermost side groove by adopting ICP equipment, wherein the etching conditions are as follows: the power of the upper electrode is 260-300W, the power of the lower electrode is 40-80W, the pressure of the chamber is 10mTorr, Cl 2 The gas flow is 20-60 sccm, and the tray temperature is 20 ℃. Wherein, the depth-to-width ratio of the rectangular groove is 1.
Finally, removing the photoresist after the etching is finished so as to remove the photoresist on the n - -Ga 2 O 3 The buffer layer has rectangular grooves formed at the left and right ends thereof, respectively, as shown in fig. 3 b.
And 4, step 4: a second rectangular trench is lithographed as shown in figure 3 c.
And 5: a third rectangular trench is lithographed as shown in figure 3 d.
Specifically, the process of steps 4 and 5 is the same as that of step 3, wherein the second rectangular trench is a middle trench and has an aspect ratio of 2. The third rectangular trench is the outermost trench and has an aspect ratio of 3.
Thus, a group of symmetrical arrangements at n is obtained - -Ga 2 O 3 The groove structures at the left end and the right end of the buffer layer.
Step 6: using the MOCVD method, at n - -Ga 2 O 3 A P-type gallium nitride layer is epitaxially grown on the buffer layer, as shown in fig. 3 e.
Specifically, the P-type gallium nitride material is epitaxially grown on the surface of the device obtained in step 5, so that all the trenches are filled with the P-type gallium nitride and n is formed - -Ga 2 O 3 The buffer layer forms a P-type gallium nitride layer with the thickness of 0.2-3 mu m. Wherein, the doping ion of the P-type gallium nitride is Mg ion, the doping concentration range is 1 × 10 17 ～1×10 19 cm -3 。
And 7: and opening etching.
Specifically, a photoresist is spun on P-type GaN and a Schottky contact region is photoetched, and the photoresist is removed to form a trench in n - -Ga 2 O 3 The left and right ends of the buffer layer form P-type regions as shown in fig. 3 f.
The specific parameters of the etching process are as follows: the power of the upper electrode is 260-300W, the power of the lower electrode is 40-80W, the pressure of the chamber is 9mTorr, BCl 3 /Cl 2 The gas flow is 20-30/20-30 sccm, the He pressure is 10torr, the He leakage is 10sccm, and the tray temperature is 20 ℃.
And 8: a bottom electrode (cathode) was fabricated.
At n + -Ga 2 O 3 And growing a cathode of the Schottky diode on the other side surface of the substrate. Using electron beam evaporation stage at Ga 2 O 3 The back of the substrate is sequentially evaporated with a Ti/Au metal combination. After evaporation of the electrode metal, N at 500-800 DEG C 2 Performing rapid thermal annealing for 50-80 s in the environment to form ohmic contact,as shown in fig. 3 g.
Wherein the growth thickness of the first layer of metal Ti is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-200 nm.
And step 9: a top electrode (anode) was fabricated.
The Ni/Au combination is evaporated in sequence as an anode on the device surface using an electron beam as shown in fig. 3 h. The anode metal is a Ni/Au combination or a Pt/Au combination, the growth thickness of the first layer of metal Ni or Pt is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-200 nm.
So far, the preparation of the Schottky diode with three rectangular grooves on the left side and the right side is completed.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A schottky diode having a junction termination extension structure, comprising: cathode (1), n + -Ga 2 O 3 Substrate layer (2), n - -Ga 2 O 3 The buffer layer (3), the P-type region (4) and the anode (5); wherein the content of the first and second substances,
the cathode (1), n + -Ga 2 O 3 Substrate layer (2), n - -Ga 2 O 3 The buffer layers (3) are arranged from bottom to top in sequence;
n is - -Ga 2 O 3 The left end and the right end of the buffer layer (3) are respectively provided with a group of groovesStructure, the P-type region (4) covers n in and above the groove structure - -Ga 2 O 3 The surface of the buffer layer (3) is used for forming a junction terminal extension structure;
the anode (5) is covered on the n - -Ga 2 O 3 The middle upper surface of the buffer layer (3) extends to two ends to cover part of the upper surface of the P-type region (4).
2. The schottky diode of claim 1 wherein each of the recess structures includes a plurality of trenches, and the trenches have depths that gradually increase from the inside of the device to the left and right sides.
3. The Schottky diode with the junction termination extension structure according to claim 1, wherein each of the trenches has a width of 0.5-2 μm, and a distance between two adjacent trenches is 1-3 μm.
4. The schottky diode with the junction termination extension structure of claim 1, wherein each of the recess structures comprises three rectangular trenches, and the aspect ratios of the three rectangular trenches are 1, 2 and 3 in sequence from the inner side to the outer side of the device.
5. The Schottky diode with junction termination extension structure according to claim 1, wherein the P-type region (4) is grown to a thickness of 0.2-3 μm.
6. The schottky diode with junction termination extension structure of claim 1, wherein the P-type region (4) has Mg ions as dopant ions at a concentration of 1 x 10 17 ～1×10 19 cm -3 。
7. The schottky diode with junction termination extension structure according to claim 1, wherein the material of the P-type region (4) is P-type gan.
8. The schottky diode of claim 1 wherein n is n + -Ga 2 O 3 A substrate layer (2) and said n - -Ga 2 O 3 The doping ions of the buffer layer (3) are Si ions or Sn ions; wherein the content of the first and second substances,
n is + -Ga 2 O 3 The doping concentration of the substrate layer (2) is 1 x 10 18 ～1×10 20 cm -3 N is said n - -Ga 2 O 3 The doping concentration of the buffer layer (3) is 1 x 10 16 ～1×10 17 cm -3 。
9. A preparation method of a Schottky diode with a junction terminal extension structure is characterized by comprising the following steps:
selecting n + -Ga 2 O 3 Cleaning the substrate;
at n + -Ga 2 O 3 Epitaxial growth of low doped n on one side of substrate - -Ga 2 O 3 A buffer layer;
for said n - -Ga 2 O 3 Etching the buffer layer for multiple times to form a group of groove structures at the left end and the right end of the buffer layer respectively;
depositing P-type material on the whole sample surface and etching to form n covering the groove structure and the upper part of the groove structure - -Ga 2 O 3 A P-type region on the surface of the buffer layer;
at said n + -Ga 2 O 3 And manufacturing a cathode on the other side of the substrate, and manufacturing an anode on the surface of the obtained sample, thereby completing the preparation of the device.
10. The method of claim 9, wherein n is the same as n - -Ga 2 O 3 The buffer layer carries out a lot of corrasions to both ends form a set of groove structure respectively about it, include:
at said n - -Ga 2 O 3 Photoresist is spin-coated on the buffer layer, and first groove region patterns are respectively photoetched on the left side and the right side of the buffer layer;
etching the first groove by adopting an ICP device; wherein, the etching conditions are as follows: the power of the upper electrode is 260-300W, the power of the lower electrode is 40-80W, the pressure of the chamber is 10mTorr, Cl 2 The gas flow is 20-60 sccm, and the tray temperature is 20 ℃;
repeating the above steps, and etching the rest grooves in sequence to form n - -Ga 2 O 3 The left end and the right end of the buffer layer respectively form a group of symmetrical groove structures.
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