CN114823843A - Manufacturing process of all-dielectric isolation silicon magnetic sensitive triode - Google Patents

Manufacturing process of all-dielectric isolation silicon magnetic sensitive triode Download PDF

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CN114823843A
CN114823843A CN202110402723.4A CN202110402723A CN114823843A CN 114823843 A CN114823843 A CN 114823843A CN 202110402723 A CN202110402723 A CN 202110402723A CN 114823843 A CN114823843 A CN 114823843A
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silicon
dielectric isolation
triode
dielectric
wafer
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赵晓锋
李苏苏
于志鹏
温殿忠
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Heilongjiang University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors

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Abstract

The invention discloses an all-dielectric isolation silicon magnetic sensitive triode and a manufacturing process thereof, wherein the all-dielectric isolation silicon magnetic sensitive triode comprises an SOI silicon magnetic sensitive triode and a dielectric isolation ring, the SOI silicon magnetic sensitive triode comprises device silicon (1), substrate silicon (2) and buried layer silicon dioxide (3), the silicon magnetic sensitive triode is arranged on the device silicon (1), and the dielectric isolation ring and the buried layer silicon dioxide (3) form an all-dielectric isolation structure. The all-dielectric isolation silicon magnetic sensitive triode disclosed by the invention is wrapped by the dielectric layer, so that the isolation between components is effectively realized, the deflection degree of a current carrier under the action of a magnetic field is limited, and the magnetic sensitivity and the temperature characteristic of the silicon magnetic sensitive triode are improved. In addition, the invention also discloses the silicon magnetosensitive triode prepared by fusing the micro-electromechanical system technology and the SOI technology, realizes miniaturization and integration, and lays a foundation for batch production of the high-performance silicon magnetosensitive triode.

Description

Manufacturing process of all-dielectric isolation silicon magnetic sensitive triode
Technical Field
The invention relates to the technical field of sensors, in particular to a magnetic field sensor, and particularly relates to a manufacturing process of a silicon magnetic sensitive triode with an all-dielectric isolation structure.
Background
The silicon magnetic sensitive triode is a bipolar semiconductor triode with magnetic sensitive effect on an applied magnetic field, and the magnetic sensitive characteristic is the result of double actions of carrier injection effect and Lorentz force, so that the deflection degree of carriers in the magnetic field has great influence on the characteristics of the silicon magnetic sensitive triode, such as magnetic sensitivity, cross interference and the like.
Theoretical analysis shows that the silicon magnetosensitive triode with the three-dimensional structure has better magnetic sensitivity characteristic, the germanium magnetosensitive triode with the three-dimensional structure can be manufactured by adopting an alloy method, but the silicon magnetosensitive triode with the three-dimensional structure has smaller size and can only be manufactured into a planar structure by a microelectronic process. With the development of Micro Electro Mechanical System (MEMS) technology, the key process technology is broken through, the three-dimensional structure of the silicon magnetosensitive triode is realized, but the silicon magnetosensitive triode with the three-dimensional structure has the phenomena of parasitic effect and the like, the performances of the magnetosensitive characteristic, the temperature characteristic and the like are seriously influenced, the deflection of a carrier under the action of a magnetic field is effectively limited, the parasitic effect is reduced, and the performance of the carrier can be improved. In summary, the silicon magnetosensitive triode with the three-dimensional structure needs to consider element isolation, and the deflection degree of the current carrier in the silicon magnetosensitive triode with the three-dimensional structure in the magnetic field can be limited by combining the MEMS technology and the isolation process.
The isolation in the bipolar integrated circuit comprises PN junction isolation, medium isolation, PN junction-medium mixed isolation and the like, wherein the PN junction isolation is a common isolation method, but the depth of the PN junction isolation performed by the silicon magnetic sensitive triode with the three-dimensional structure needs to reach 20-40 mu m, the diffusion time of the junction reaching the depth is longer, longitudinal diffusion and transverse diffusion can be generated in the diffusion process, the isolation region is widened, and the integration of the device is seriously influenced.
Therefore, it is an urgent need to solve the problem of manufacturing a miniaturized and integrated silicon magnetosensitive triode, so that the silicon magnetosensitive triode can effectively limit the deflection degree of a carrier in a magnetic field, reduce the influence of spurious effects on the silicon magnetosensitive triode, and has good radiation resistance, magnetic sensitivity and temperature characteristics.
Disclosure of Invention
In order to overcome the problems, the inventor of the invention makes a keen study and designs an all-dielectric isolation silicon magnetosensitive triode and a manufacturing process thereof, the silicon magnetosensitive triode with an all-dielectric isolation structure is manufactured on device silicon by fusing an MEMS technology and a Silicon On Insulator (SOI) technology on an insulating substrate, the isolation among devices is effectively realized while the three-dimensional structure of the silicon magnetosensitive triode is realized, the deflection degree of a current carrier under the action of a magnetic field is limited, and the magnetic sensitivity and the temperature characteristic of the silicon magnetosensitive triode are improved, thereby completing the invention.
Specifically, the present invention aims to provide the following:
in a first aspect, an all-dielectric isolation silicon magnetic sensitive triode comprises an SOI silicon magnetic sensitive triode and a dielectric isolation ring, wherein the SOI silicon magnetic sensitive triode comprises device silicon 1, substrate silicon 2 and buried layer silicon dioxide 3, a silicon magnetic sensitive triode is arranged on the device silicon 1,
the dielectric isolation ring and the buried silicon dioxide 3 form an all-dielectric isolation structure.
In a second aspect, a process for manufacturing an all-dielectric isolated silicon magnetosensitive triode is provided, and is preferably used for manufacturing the all-dielectric isolated silicon magnetosensitive triode of the first aspect, and the process for manufacturing the all-dielectric isolated silicon magnetosensitive triode includes the following steps:
step 1, cleaning a first wafer, photoetching the upper surface of the first wafer for one time, and etching a register mark;
step 2, cleaning the second wafer, and growing silicon dioxide layers on two sides;
step 3, bonding the lower surface of the wafer and the upper surface of the wafer II;
step 4, secondary photoetching is carried out, and the register mark on the upper surface of the first wafer is transferred to the lower surface of the second wafer;
step 5, thinning the upper surface of the first wafer, polishing and cleaning to form an SOI wafer;
step 6, carrying out third photoetching, and etching an isolation groove and a base region deep groove of the medium isolation ring on the upper surface of the device silicon 1;
step 7, injecting boron ions into the deep groove of the base region to form p + A heavily doped region;
and 8, growing a silicon dioxide layer on the upper surface of the device silicon 1, and filling the isolation groove and the base region deep groove to form a dielectric isolation ring and a base region.
In a third aspect, an all-dielectric isolation silicon magnetosensitive triode prepared by the manufacturing process of the second aspect is provided.
The invention has the advantages that:
(1) according to the all-dielectric isolation silicon magnetosensitive triode provided by the invention, the medium isolating ring is manufactured on the device silicon, so that the medium isolating ring and the buried layer silicon dioxide form an all-dielectric isolation structure, the silicon magnetosensitive triode is wrapped, the silicon magnetosensitive triode is effectively isolated from a load resistor and a substrate, the deflection of a current carrier is limited, the parasitic effect of the substrate is reduced, the anti-irradiation capability of the silicon magnetosensitive triode is improved, and the magnetic sensitivity and the temperature characteristic are improved;
(2) the manufacturing process of the all-dielectric isolation silicon magnetic sensitive triode provided by the invention integrates the MEMS technology and the SOI technology, and the manufactured all-dielectric isolation structure can be compatible with the integration process, thereby realizing the miniaturization and integration of the silicon magnetic sensitive triode;
(3) the all-dielectric isolation silicon magnetic sensitive triode prepared by the manufacturing process provided by the invention realizes the silicon magnetic sensitive triode with a three-dimensional structure, simultaneously limits the deflection degree of a current carrier under the action of a magnetic field, and lays a foundation for the batch production of high-performance silicon magnetic sensitive triodes.
Drawings
Fig. 1 shows a schematic diagram of the overall structure of an all-dielectric isolation silicon magnetosensitive triode according to a preferred embodiment of the present invention;
fig. 2 shows a schematic top view of an all-dielectric isolated silicon magnetotriode according to a preferred embodiment of the present invention;
FIG. 3 shows an equivalent circuit diagram of an all-dielectric isolated silicon magnetotriode according to a preferred embodiment of the present invention;
4-1 to 4-10 show a flow chart of a manufacturing process of an all-dielectric isolation silicon magnetic sensitive triode according to a preferred embodiment of the invention;
FIGS. 5-1 to 5-3 show the isolation structure-free silicon magnetosensitive triode, the PN junction isolation structure silicon magnetosensitive triode, and the all-dielectric isolation structure silicon magnetosensitive triode I in Experimental example 1 of the present invention C -V CE A characteristic curve graph;
FIGS. 6-1 to 6-3 show silicon magnetosensitive triodes without isolation structures, silicon magnetosensitive triodes with PN junction isolation structures and silicon magnetosensitive triodes with all-dielectric isolation structures in Experimental example 1 of the present invention C -V CE A characteristic curve graph;
FIGS. 7-1 to 7-3 show the silicon magnetosensitive triode without isolation structure, the silicon magnetosensitive triode with PN junction isolation structure and the silicon magnetosensitive triode with all-dielectric isolation structure I in Experimental example 1 of the present invention C -V CE Characteristic curve diagram.
The reference numbers illustrate:
1-device silicon;
2-substrate silicon;
3-buried layer silicon dioxide;
4-an emission area;
51-dielectric spacer ring one;
52-dielectric spacer ring two;
53-dielectric spacer ring three;
6-a collector region;
7-base region;
8-a silicon dioxide layer;
91-metal Al layer one;
92-metal Al layer two;
b-base electrode;
c-a collector;
an E-emitter;
R b -a base load resistance;
R L -a collector electrodeA load resistance;
V DD -a power source;
GND-ground;
V out -an output voltage;
SMST-silicon magnetosensitive triode.
Detailed Description
The invention is explained in more detail below with reference to the figures and examples. The features and advantages of the present invention will become more apparent from the description. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In a first aspect of the invention, an all-dielectric isolation silicon magnetosensitive triode comprises an SOI silicon magnetosensitive triode and a dielectric isolation ring, wherein the SOI silicon magnetosensitive triode comprises device silicon 1, substrate silicon 2 and buried layer silicon dioxide 3, the device silicon 1 is provided with the silicon magnetosensitive triode,
the dielectric isolation ring and the buried layer silicon dioxide form a full-dielectric isolation structure to realize full-dielectric isolation of the silicon magnetosensitive triode, as shown in fig. 1.
Wherein the SOI is silicon on an insulating substrate.
According to a preferred embodiment of the invention, the device silicon 1 is a <100> crystal orientation double-sided polished high-resistance p-type monocrystalline silicon wafer with the thickness of 20-40 μm.
Preferably, the device silicon 1 has a thickness of 30 μm;
more preferably, the resistivity of the device silicon 1 is greater than 100 Ω · cm.
According to a preferred embodiment of the invention, the substrate silicon 2 is a <100> crystal orientation double-sided polished high-resistance p-type monocrystalline silicon wafer with the thickness of 450-600 μm.
Preferably, the substrate silicon 2 has a thickness of 500 μm and a resistivity greater than 100 Ω · cm.
In a further preferred embodiment, the buried silicon dioxide 3 is formed between the device silicon 1 and the substrate silicon 2, and has a thickness of 500-1000 nm, preferably 800 nm.
According to a preferred embodiment of the present invention, the dielectric isolation ring includes a first dielectric isolation ring 51, a second dielectric isolation ring 52 and a third dielectric isolation ring 53, as shown in fig. 1, all disposed in the device silicon 1.
Preferably, the first dielectric isolation ring is arranged in the middle of the device silicon 1, the second dielectric isolation ring and the third dielectric isolation ring are arranged on two sides of the first dielectric isolation ring, and the three dielectric isolation rings are independent of each other.
More preferably, the distance between the first dielectric isolation ring and the second dielectric isolation ring is greater than or equal to 2 μm, preferably 2 μm, and the distance between the second dielectric isolation ring and the third dielectric isolation ring is greater than or equal to 2 μm, preferably 2 μm.
In the invention, due to the limitation of photoetching and process, the distance between adjacent dielectric isolation rings can not be too small, and the integration degree of the whole structure can be influenced if the distance is too large.
In a further preferred embodiment, the spacer ring dielectrics of the first dielectric spacer ring, the second dielectric spacer ring and the third dielectric spacer ring are all silicon dioxide.
In a further preferred embodiment, the depth of the first dielectric isolation ring, the second dielectric isolation ring and the third dielectric isolation ring is consistent with the thickness of the device silicon 1, and is 20-40 μm, preferably 30 μm.
Preferably, the width of the medium isolation ring is 1-2 μm, and preferably 1.5 μm.
The width of the dielectric isolation ring refers to the width of the isolation groove of the dielectric isolation ring, that is, the width of the medium filled in the x-axis and y-axis directions of the isolation groove, as shown in fig. 1 (x, y, z represents coordinate axes).
In the invention, the first dielectric isolation ring, the second dielectric isolation ring and the third dielectric isolation ring form a full-dielectric isolation structure with the buried layer silicon dioxide 3, thereby realizing effective isolation among the silicon magnetic sensitive triode, the load resistor and the substrate.
According to a preferred embodiment of the invention, the silicon magnetosensitive triode comprises an emitter region 4, a collector region 6 and a base region 7 which are all arranged inside a dielectric isolation ring I.
In a further preferred embodiment, the collector region 6 is formed on the upper surface of the device silicon 1 and has a doping type n + Heavily doped with a doping concentration of 1E 15-1E 16cm -3 Preferably 1E15cm -3 ；
The base region 7 is manufactured on the upper surface of the device silicon 1, and the doping type of the base region is p + Heavily doped with a doping concentration of 1E 18-1E 19cm -3 Preferably 1E18cm -3 。
Preferably, ICP (inductively coupled plasma) is adopted to etch a base deep groove on the upper surface of the device silicon 1, boron ions are injected into the base deep groove to form p + And the heavily doped region is used as a base region, wherein the deep groove etching depth of the base region is 25-30 μm, preferably 25 μm, and the width is 2-4 μm, preferably 3 μm.
The inventor researches and discovers that the base region manufactured by the method can increase the injection depth of boron ions, effectively modulate the recombination of carriers in the base region and improve the magnetic sensitivity of the silicon magnetic sensitive triode.
In a further preferred embodiment, said emitter region 4 is made on the lower surface of the device silicon 1, with a doping type n + Heavily doped with a doping concentration of 1E 18-1E 20cm -3 Preferably 1E20cm -3 。
Preferably, an emitting area corrosion pit is formed on the lower surface of the substrate silicon 2 in an etching mode, the etching position corresponds to the collector area 6 on the upper surface of the device silicon 1, phosphorus ions are injected through the emitting area corrosion pit, and n can be formed on the lower surface of the device silicon 1 + A heavily doped region as an emitter region 4;
wherein the depth of the etching pits of the emitting region is consistent with the thickness of the substrate silicon 2, and the etching pits are 450-600 μm, preferably 500 μm.
More preferably, the base region length of the silicon magnetosensitive triode is the distance between the emitter region 4 and the base region 7, preferably 150 and 180 μm, such as 180 μm;
the base width is the distance between the emitter region 4 and the collector region 6, preferably 20-40 μm, such as 30 μm.
The length and width of the base region are in the preferable range, so that the magnetic sensitivity of the magnetic sensitive triode is better.
According to a preferred embodiment of the invention, a base load resistor R is also fabricated on the device silicon 1 b Collector load resistance R L Wherein the base load resistance R b A collector load resistor R arranged in the dielectric isolation ring II L And is arranged inside the medium isolating ring III.
In a further preferred embodiment, the base load resistor R b Collector load resistance R L Are all n - Doping, wherein the types of the doped ions are phosphorus ions, and the doping concentration is 5E 14-5E 15cm -3 Preferably 5E14cm -3 ；
Base load resistor R b Collector load resistance R L The resistance value of (A) is 1.5 to 3.0k omega, preferably 1.5k omega.
The inventor researches and discovers that the base load resistor R is arranged inside the second dielectric isolation ring and the third dielectric isolation ring b Collector load resistance R L Are all n - The doped region is formed, and the three medium isolating rings are mutually independent, so that the carrier over-deflection under the action of a magnetic field can be effectively inhibited, and the electrical isolation among components can be realized.
According to a preferred embodiment of the invention, a silicon dioxide layer 8 is arranged on the upper surface of the device silicon 1 and the lower surface of the substrate silicon 2 to play a role of insulation or passivation;
the thickness of the silicon dioxide layer 8 is 500-1000 nm, and is preferably 800 nm.
In a further preferred embodiment, a lead hole is etched on the surface of the silicon dioxide layer 8 on the upper surface of the device silicon 1, a first metal Al layer 91 is vacuum-evaporated on the upper surface of the lead hole,
and a second metal Al layer 92 is evaporated on the surface of the silicon dioxide layer 8 on the lower surface of the substrate silicon 2 in vacuum.
Preferably, the first metal Al layer is etched back to form a collector C, a base B, a metal interconnecting wire and a pressure welding point, and the evaporated metal Al layer forms an emitter E.
In a further preferred embodiment, as shown in fig. 2, the base and base load resistor R b Is connected with the collector load resistor R L One end of the first and second connecting rods is connected,
the base load resistor R b Another end of (3), collector load resistance R L Respectively connected with a power supply V DD The connection is carried out by connecting the two parts,
the emitter is grounded GND.
Wherein the collector is connected with R L The junction is used as an output voltage V out And (4) an end.
In the present invention, as shown in FIG. 3, when V is DD When a magnetic field is applied along the magnetic sensitive direction, the collector current of the silicon magnetosensitive triode SMST is changed, so that R is constant L The voltages at the two ends can also change, namely the collector voltage can change along with the change of the external magnetic field, and the magnitude of the external magnetic field along the magnetic sensitivity direction can be obtained through the change condition of the collector voltage.
The silicon magnetosensitive triode provided by the invention adopts an all-dielectric isolation structure to realize effective isolation among the silicon magnetosensitive triode, the load resistor and the substrate, effectively realize isolation among components, limit the deflection degree of a current carrier under the action of a magnetic field and improve the magnetic sensitivity and temperature characteristics of the silicon magnetosensitive triode.
In a second aspect of the present invention, a manufacturing process of an all-dielectric isolation silicon magnetosensitive triode is provided, and is preferably used for manufacturing the silicon magnetosensitive triode described in the first aspect, where the manufacturing process includes the following steps, as shown in fig. 4-1 to 4-10:
step 1, cleaning a first wafer, photoetching the upper surface of the first wafer once, and etching the register mark.
The first wafer is a <100> crystal orientation double-sided polished high-resistance p-type monocrystalline silicon wafer, and the resistivity is larger than 100 omega cm.
Preferably, the wafer is cleaned using RCA standard cleaning.
And 2, cleaning the second wafer, and growing silicon dioxide layers on two sides, as shown in figure 4-1.
Preferably, the two <100> crystal orientation double-sided polished high-resistance p-type monocrystalline silicon wafer has the resistivity larger than 100 omega cm.
More preferably, a thermal oxidation method is adopted to grow silicon dioxide layers on two sides, buried layer silicon dioxide 3 is grown on the upper surface of the second wafer, and a silicon dioxide layer 8 is grown on the lower surface of the second wafer;
the thickness is 500-1000 nm, preferably 800 nm.
And 3, bonding the lower surface of the wafer with the upper surface of the wafer II.
And 4, carrying out secondary photoetching, and transferring the register mark on the upper surface of the first wafer to the lower surface of the second wafer.
Wherein, the double-sided photoetching process is preferably adopted to transfer the register mark.
And 5, thinning the upper surface of the wafer, polishing and cleaning to form the SOI wafer, as shown in FIG. 4-2.
Wherein, the upper surface of the wafer is thinned to 20-40 μm, preferably 30 μm by using a wafer thinning machine.
The thinned wafer I is device silicon 1, and the wafer II is substrate silicon 2.
And 6, carrying out third photoetching, and etching the isolation groove and the base region deep groove of the medium isolation ring on the upper surface of the device silicon 1, as shown in fig. 4-3.
Wherein, dry etching is preferably adopted to isolate the groove and the base region deep groove.
In the invention, the base region width of the silicon magnetosensitive triode with a three-dimensional structure is 20-40 μm, and the problem of insufficient single etching depth exists when a medium isolating ring is manufactured in the silicon magnetosensitive triode in the prior art.
According to a preferred embodiment of the invention, the depth of the etched isolation groove is consistent with the thickness of device silicon, and is 20 μm-40 μm, preferably 30 μm; the width of the isolation groove is 1-2 μm, preferably 1.5 μm;
the depth of the etched base region deep groove is 25-30 μm, preferably 25 μm; the width of the deep trench of the base region is 2-4 μm, preferably 3 μm.
Step 7, injecting boron ions into the deep groove of the base region to form p + And a heavily doped region.
Preferably, an ICP (inductively coupled plasma) technology is adopted to etch the deep grooves of the base region, and the doping concentration of the base region is 1E 18-1E 19cm -3 Preferably 1E18cm -3 。
More preferably, the inner side surface of the etched base region is an inclined surface, and the included angle between the inner side surface of the etched base region and the z axis is 5-10 degrees.
The inventor finds that the deep groove of the base region is etched by adopting ICP (inductively coupled plasma), so that the depth of boron ion injection is increased, the recombination of carriers in the base region is effectively modulated, and the magnetic sensitivity of the silicon magnetosensitive triode is improved.
And 8, growing a silicon dioxide layer on the upper surface of the device silicon 1, and filling the isolation groove and the base region deep groove to form a dielectric isolation ring and a base region, as shown in fig. 4-4.
Preferably, a silicon dioxide layer is grown on the upper surface of the device silicon 1 by adopting a vapor phase epitaxy method, and silicon dioxide is filled in the isolation groove and the base region deep groove, so that effective isolation among all components is realized.
After filling the isolation grooves and the base region deep grooves, polishing the upper surface of the device silicon 1 to form a first dielectric isolation ring, a second dielectric isolation ring, a third dielectric isolation ring and a base region 7.
And 9, cleaning the SOI wafer, and growing a layer of thin oxygen on the upper surface of the device silicon 1.
Wherein the thickness of the thin oxygen is 30 to 50 nm.
Step 10, four times of photoetching are carried out, and collector load resistors R are respectively etched on the upper surface of the device silicon 1 L Window and base load resistor R b Window, and implanting phosphorus ions to form n - Doped region as collector load resistor R L And base load resistance R b Such asAs shown in fig. 4-5.
Preferably, the collector load resistance R L And base load resistance R b The doping concentration of the silicon nitride is 5E 14-5E 15cm -3 Preferably 5E14cm -3 ；
Base load resistor R b Collector load resistance R L The resistance values of (A) are all 1.5-3.0 k omega, and preferably 1.5k omega.
Step 11, five times of photoetching, etching a collector region window on the upper surface of the device silicon 1, and injecting phosphorus ions to form n + The heavily doped region, acting as collector region 6, is shown in fig. 4-6.
Preferably, the doping concentration of the collector region is 1E 15-1E 16cm -3 Preferably 1E15cm -3 。
And step 12, cleaning the SOI wafer, carrying out high-temperature annealing treatment, respectively forming the collector region 6, the base region 7 and the load resistor, and removing the thin oxygen layer.
And step 13, cleaning the SOI wafer, and growing a silicon dioxide layer on the upper surface of the device silicon 1.
Preferably, a silicon dioxide layer is grown as an insulating layer on the upper surface of the device silicon 1 by Chemical Vapor Deposition (CVD).
More preferably, the thickness of the silicon dioxide layer is 400-800 nm, and preferably 500 nm.
And step 14, performing six times of photoetching, and etching pin holes on the upper surface of the device silicon 1 to form the collector region 6, the base region 7 and the pin holes of the load resistor, as shown in fig. 4-7.
Step 15, seven times of photoetching are carried out, the window of the emitting area is etched on the lower surface of the substrate silicon 2 to form an etch pit, and phosphorus ions are injected to form n + The heavily doped region, as the emitter region 4, is shown in fig. 4-8.
Etching an emission region window by adopting ICP (inductively coupled plasma), wherein the etching position of an etching pit of the emission region corresponds to a collector region 6 on the upper surface of the device silicon 1;
preferably, the doping concentration of the phosphorus ions in the emission region is 1E 18-1E 20cm -3 Preferably 1E20cm -3 。
And step 16, cleaning the SOI wafer, and carrying out high-temperature annealing treatment to form the emitter region 4.
And step 17, cleaning the SOI wafer, and growing an Al layer on the upper surface of the device silicon 1.
Preferably, a first metal Al layer is grown on the upper surface of the device silicon 1 by adopting a vacuum evaporation method,
the thickness is 400nm to 600nm, preferably 500 nm.
And step 18, performing eight times of photoetching, reversely etching the first metal Al layer, and forming a metal Al interconnection line and an electrode on the upper surface of the device silicon 1, as shown in FIGS. 4-9.
Step 19, cleaning the SOI wafer, and growing a second metal Al layer on the lower surface of the substrate silicon 2, as shown in FIGS. 4-10.
And growing a second metal Al layer on the lower surface of the substrate silicon 2 by adopting a vacuum evaporation method.
And 20, alloying to form ohmic contact.
Preferably, the alloying is preferably carried out for 30min under vacuum or nitrogen atmosphere at 420 ℃.
In a third aspect of the present invention, there is provided an all-dielectric isolated silicon magnetosensitive triode prepared by the manufacturing process of the second aspect.
The silicon magnetic-sensing triode adopts a non-magnetized packaging process to package a chip, and the manufacturing of the all-dielectric isolation silicon magnetic-sensing triode is completed.
The silicon magnetic sensitive triode with the all-dielectric isolation structure, which is manufactured by fusing the MEMS technology and the SOI technology, can effectively realize isolation among components, simultaneously limits the deflection degree of a current carrier under the action of a magnetic field, improves the magnetic sensitivity and the temperature characteristic of the silicon magnetic sensitive triode, realizes miniaturization and integration of the silicon magnetic sensitive triode, and lays a foundation for batch production of high-performance silicon magnetic sensitive triodes.
Examples
Example 1
The all-dielectric isolation silicon magnetic sensitive triode is manufactured according to the following steps:
step 1, cleaning a first wafer, photoetching the upper surface of the first wafer once, and etching the register mark.
The first wafer is a <100> crystal orientation double-sided polished high-resistance p-type monocrystalline silicon wafer, and the resistivity is larger than 100 omega cm.
Preferably, the wafer is cleaned using RCA standard cleaning methods.
And 2, cleaning the second wafer, and growing silicon dioxide layers on two sides.
The two <100> crystal orientation double-sided polished high-resistance p-type monocrystalline silicon wafer has the resistivity larger than 100 omega cm.
And growing silicon dioxide layers on two sides by a thermal oxidation method, growing buried silicon dioxide on the upper surfaces of the two wafers, and growing silicon dioxide layers on the lower surfaces of the two wafers.
The thickness is 800 nm.
And 3, bonding the lower surface of the wafer with the upper surface of the wafer II.
And 4, carrying out secondary photoetching, and transferring the register mark on the upper surface of the first wafer to the lower surface of the second wafer.
Wherein, the register mark is transferred by adopting a double-sided photoetching process.
And 5, thinning the upper surface of the wafer, polishing and cleaning to form the SOI wafer.
Wherein, a wafer thinning machine is adopted to thin the upper surface of the wafer to 30 μm.
And the thinned first wafer is device silicon, and the second wafer is substrate silicon.
And 6, carrying out third photoetching, and etching the isolation groove and the base region deep groove of the medium isolation ring on the upper surface of the device silicon 1.
Wherein, dry etching is adopted to separate the groove and the deep groove of the base region.
According to a preferred embodiment of the invention, the depth of the etched isolation groove is consistent with the thickness of device silicon, and both the depth and the thickness are 30 μm; the width of the isolation groove is 1.5 mu m;
the depth of the etched base region deep groove is 25 mu m; the width of the deep trench of the base region is 3 μm.
Step 7, injecting boron ions into the deep groove of the base region to form p + And a heavily doped region.
Preferably, the ICP technology is adopted to etch the deep grooves of the base region, and the doping concentration of the base region is 1E18cm -3 。
The inner side surface of the etched base region is an inclined surface, and the included angle between the inner side surface of the etched base region and the z axis is 5-10 degrees.
The inventor finds that the deep groove of the base region is etched by adopting ICP (inductively coupled plasma), so that the depth of boron ion injection is increased, the recombination of carriers in the base region is effectively modulated, and the magnetic sensitivity of the silicon magnetosensitive triode is improved.
And 8, growing a silicon dioxide layer on the upper surface of the device silicon, and filling the isolation groove and the base region deep groove to form a dielectric isolation ring and a base region.
And growing a silicon dioxide layer on the upper surface of the device silicon by adopting a vapor phase epitaxy method, and filling silicon dioxide into the isolation groove and the base region deep groove so as to realize effective isolation among all devices.
After filling the isolation groove and the base region deep groove, polishing the upper surface of the device silicon to form a first dielectric isolation ring, a second dielectric isolation ring, a third dielectric isolation ring and a base region.
And 9, cleaning the SOI wafer, and growing a layer of thin oxygen on the upper surface of the device silicon.
Wherein the thin oxygen has a thickness of 30 nm.
Step 10, four times of photoetching is carried out, and collector load resistors R are respectively etched on the upper surface of the device silicon L Window and base load resistor R b Window, and implanting phosphorus ions to form n - Doped region as collector load resistor R L And base load resistance R b 。
Preferably, the collector load resistance R L And base load resistance R b All doping concentrations of (1) are 5E14cm -3 ；
Base load resistor R b Collector load resistance R L Are all 1.5k omega.
Step 11, five times of photoetching, etching a collector region window on the upper surface of the device silicon, and injecting phosphorus ions to form n + And the heavily doped region is used as a collector region.
Preferably, the doping concentration of the collector region is 1E15cm -3 。
And step 12, cleaning the SOI wafer, carrying out high-temperature annealing treatment, respectively forming a collector region, a base region and a load resistor, and removing the thin oxygen layer.
And step 13, cleaning the SOI wafer, and growing a silicon dioxide layer on the upper surface of the device silicon.
And growing a silicon dioxide layer on the upper surface of the device silicon by adopting a CVD method to serve as an insulating layer.
More preferably, the thickness of the silicon dioxide layer is 500 nm.
And step 14, six times of photoetching is carried out, and pin holes are etched on the upper surface of the device silicon to form pin holes of the collector region, the base region and the load resistor.
Step 15, seven times of photoetching is carried out, an emitting area window is etched on the lower surface of the substrate silicon to form an etching pit, and phosphorus ions are injected to form n + And the heavily doped region is used as an emitting region.
Etching an emission region window by adopting ICP (inductively coupled plasma), wherein the etching position of an etching pit of the emission region corresponds to a collector region on the upper surface of the device silicon;
preferably, the doping concentration of the phosphorus ions in the emission region is 1E20cm -3 。
And step 16, cleaning the SOI wafer, and carrying out high-temperature annealing treatment to form an emitter region.
And step 17, cleaning the SOI wafer, and growing an Al layer on the upper surface of the device silicon.
And growing a first metal Al layer on the upper surface of the device silicon by a vacuum evaporation method, wherein the thickness of the first metal Al layer is 500 nm.
And step 18, carrying out photoetching eight times, reversely etching the first metal Al layer, and forming a metal Al interconnection line and an electrode on the upper surface of the device silicon.
And step 19, cleaning the SOI wafer, and growing a second metal Al layer on the lower surface of the substrate silicon.
And growing a second metal Al layer on the lower surface of the substrate silicon 2 by adopting a vacuum evaporation method.
And 20, alloying to form ohmic contact.
Wherein, the alloying is preferably carried out for 30min under the vacuum or nitrogen environment at 420 ℃.
And packaging the chip by adopting a non-magnetized packaging process to finish the preparation of the silicon magnetic sensitive triode.
Examples of the experiments
Experimental example 1
In this experimental example, TCAD-Athena software was used to construct a silicon magnetosensitive triode without an isolation structure, a silicon magnetosensitive triode with a PN junction isolation structure, and a process simulation model of a silicon magnetosensitive triode with an all-dielectric isolation structure according to embodiment 1 of the present invention, so as to study the I-shape of the silicon magnetosensitive triode at different magnetic fields and temperatures C -V CE Characteristic (I) C Is the collector current, V CE Is the collector voltage), the comparison results are shown in FIGS. 5-1 to 5-3, 6-1 to 6-3 and 7-1 to 7-3.
Wherein, fig. 5-1 to 5-3 respectively show a silicon magnetosensitive triode without an isolation structure, a silicon magnetosensitive triode with a PN junction isolation structure and a silicon magnetosensitive triode with an all-dielectric isolation structure I described in embodiment 1 of the present invention C -V CE In the case of room temperature (T300K) and no applied magnetic field, the following conditions were set: collector voltage V CE In the range of 0V to 5V, the step length is 0.25V, and the base injection current I B The range of (1) is 0mA to 5mA, and the step length is 1 mA.
As can be seen from FIGS. 5-1 to 5-3, the amplification factor beta of the silicon magnetosensitive triodes with the three structures is less than 1, and the collector current I of the silicon magnetosensitive triodes without the isolation structures is equal to that of the silicon magnetosensitive triodes with the three structures C (2.3mA), comparing, and collecting electrode current I of silicon magnetic sensitive triode with all-dielectric isolation structure C (2.4mA) larger, and the collector current I of the silicon magnetic sensitive triode with the PN junction isolation structure C (2.2mA) is reduced, so that the silicon magnetic sensitive triode I manufactured based on the all-dielectric isolation structure C -V CE The characteristics are better.
FIGS. 6-1 to 6-3 show the silicon magnetosensitive triode without isolation structure, the silicon magnetosensitive triode with PN junction isolation structure and the silicon magnetosensitive triode with all-dielectric isolation structure under different magnetic fields I C -V CE The conditions set at room temperature (T300K) were as follows: collector voltage V CE Is in the range of 0V to 5V, the step length is 0.25V, and the base injection current I B And the magnetic field is 5mA, and +/-0.3T magnetic fields are respectively applied to the magnetic sensitivity directions of the silicon magnetosensitive triodes with the three structures.
As can be seen from FIGS. 6-1 to 6-3, the magnetic sensitivity S (0.88mA/T) of the silicon magnetic sensitive triode with the full-medium isolation structure is the largest, the magnetic sensitivity S (0.75mA/T) of the silicon magnetic sensitive triode with the PN junction isolation structure is the second order, and the magnetic sensitivity S (0.74mA/T) of the silicon magnetic sensitive triode without the isolation structure is the smallest, so that the silicon magnetic sensitive triode manufactured based on the full-medium isolation structure has better magnetic sensitivity.
FIGS. 7-1 to 7-3 show the silicon magnetosensitive triode without isolation structure, the silicon magnetosensitive triode with PN junction isolation structure and the silicon magnetosensitive triode with full-medium isolation structure at different temperatures C -V CE The characteristics are that the conditions are set when no external magnetic field exists: collector voltage V CE Is in the range of 0V to 5V, the step length is 0.25V, and the base injection current I B The temperature variation range of the silicon magnetosensitive triodes with the three structures is-40 ℃ to 85 ℃, and the step length is 20 ℃.
As can be seen from fig. 7, the temperature coefficient a (1629 ppm/deg.c) of the silicon magnetosensitive triode with the all-dielectric isolation structure is the smallest, the temperature coefficient a (1669 ppm/deg.c) of the silicon magnetosensitive triode with the PN junction isolation structure is the second largest, and the temperature coefficient a (1676 ppm/deg.c) of the silicon magnetosensitive triode without the isolation structure is the largest, so that the temperature drift of the silicon magnetosensitive triode manufactured based on the all-dielectric isolation structure is the smallest.
In summary, the manufacturing process of the invention, i.e. the silicon magnetosensitive triode with the all-dielectric isolation structure designed and manufactured on the device silicon by fusing the MEMS technology and the SOI technology, can effectively realize isolation between components, simultaneously limit the deflection degree of carriers under the action of a magnetic field, improve the magnetic sensitivity and temperature characteristics of the silicon magnetosensitive triode, realize miniaturization and integration of the silicon magnetosensitive triode, and lay the foundation for batch production of high-performance silicon magnetosensitive triodes.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", and the like indicate orientations or positional relationships based on operational states of the present invention, and are only used for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
The present invention has been described above in connection with preferred embodiments, but these embodiments are merely exemplary and merely illustrative. On the basis of the above, the invention can be subjected to various substitutions and modifications, and the substitutions and the modifications are all within the protection scope of the invention.

Claims (9)

1. An all-dielectric isolation silicon magneto-sensitive triode is characterized by comprising an SOI silicon magneto-sensitive triode and a dielectric isolating ring, wherein the SOI silicon magneto-sensitive triode comprises device silicon (1), substrate silicon (2) and buried layer silicon dioxide (3), the device silicon (1) is provided with the silicon magneto-sensitive triode,
the dielectric isolation ring and the buried layer silicon dioxide (3) form an all-dielectric isolation structure.
2. The all-dielectric isolation silicon magnetic sensitive triode according to claim 1, wherein the dielectric isolation ring comprises a first dielectric isolation ring (51), a second dielectric isolation ring (52) and a third dielectric isolation ring (53), which are all arranged in the device silicon (1).
3. The all-dielectric isolation silicon magnetosensitive triode of claim 2, wherein the depths of the first dielectric isolation ring (51), the second dielectric isolation ring (52) and the third dielectric isolation ring (53) are all consistent with the thickness of the device silicon (1),
preferably, the widths of the isolation grooves of the first dielectric isolation ring (51), the second dielectric isolation ring (52) and the third dielectric isolation ring (53) are all 1-2 μm.
4. The all-dielectric isolation silicon magnetosensitive triode of claim 1, wherein the silicon magnetosensitive triode comprises an emitter region (4), a collector region (6) and a base region (7), which are all arranged inside a first dielectric isolation ring (51).
5. An all-dielectric isolated silicon magnetosensitive triode according to claim 2, characterized in that a base load resistor (R) is further fabricated on the device silicon (1) b ) Collector loadResistance (R) L ) Wherein the base load resistance (R) b ) A collector load resistor (R) arranged inside the dielectric isolation ring II (52) L ) Is arranged inside the medium isolating ring III (53).
6. An all-dielectric isolated silicon magnetosensitive triode according to claim 5, wherein the base load resistance (R) is b ) Collector load resistance (R) L ) Are all n - Doping, wherein the types of the doped ions are phosphorus ions, and the doping concentration is 5E 14-5E 15cm -3 。
7. A process for fabricating an all-dielectric isolated silicon magnetosensitive triode, preferably for fabricating an all-dielectric isolated silicon magnetosensitive triode according to any one of claims 1 to 6, the process comprising the steps of:
step 1, cleaning a first wafer, photoetching the upper surface of the first wafer for one time, and etching a register mark;
step 2, cleaning the second wafer, and growing silicon dioxide layers on two sides;
step 3, bonding the lower surface of the wafer and the upper surface of the wafer II;
step 4, secondary photoetching is carried out, and the register mark on the upper surface of the first wafer is transferred to the lower surface of the second wafer;
step 5, thinning the upper surface of the first wafer, polishing and cleaning to form an SOI wafer;
step 6, carrying out third photoetching, and etching an isolation groove and a base region deep groove of the medium isolation ring on the upper surface of the device silicon (1);
step 7, injecting boron ions into the deep groove of the base region to form p + A heavily doped region;
and 8, growing a silicon dioxide layer on the upper surface of the device silicon (1), and filling the isolation groove and the base region deep groove to form a dielectric isolation ring and a base region.
8. The process of claim 7, further comprising, after step 8, the steps of:
step 9, cleaning the SOI wafer, and growing a layer of thin oxygen on the upper surface of the device silicon (1);
step 10, four times of photoetching is carried out, a collector load resistance window and a base load resistance window are respectively etched on the upper surface of the device silicon (1), and phosphorus ions are injected to form n - Doped region as collector load resistance (R) L ) And base load resistance (R) b )；
Step 11, five times of photoetching, etching a collector region window on the upper surface of the device silicon (1), and injecting phosphorus ions to form n + A heavily doped region as a collector region (6);
step 12, cleaning the SOI wafer, carrying out high-temperature annealing treatment, respectively forming a collector region (6), a base region (7) and a load resistor, and removing a thin oxygen layer;
step 13, cleaning the SOI wafer, and growing a silicon dioxide layer on the upper surface of the device silicon (1);
step 14, six times of photoetching is carried out, and pin holes are etched on the upper surface of the device silicon (1) to form a collector region (6), a base region (7) and pin holes of a load resistor;
step 15, seven times of photoetching is carried out, an emitting area window is etched on the lower surface of the substrate silicon (2) to form an etching pit, and phosphorus ions are injected to form n + A heavily doped region as an emitter region (4);
step 16, cleaning the SOI wafer, and carrying out high-temperature annealing treatment to form an emitting region (4);
step 17, cleaning the SOI wafer, and growing an Al layer on the upper surface of the device silicon (1);
step 18, performing eight times of photoetching, reversely etching the first metal Al layer (91), and forming a metal Al interconnection line and an electrode on the upper surface of the device silicon 1;
step 19, cleaning the SOI wafer, and growing a second metal Al layer (92) on the lower surface of the substrate silicon (2);
and 20, alloying to form ohmic contact.
9. An all-dielectric isolated silicon magnetosensitive triode prepared by the manufacturing process of claim 7 or 8.
CN202110402723.4A 2021-04-14 2021-04-14 Manufacturing process of all-dielectric isolation silicon magnetic sensitive triode Pending CN114823843A (en)

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