CN114823581B - Embedded cooling heat sink for power chip and semiconductor device - Google Patents
Embedded cooling heat sink for power chip and semiconductor device Download PDFInfo
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- CN114823581B CN114823581B CN202210759568.6A CN202210759568A CN114823581B CN 114823581 B CN114823581 B CN 114823581B CN 202210759568 A CN202210759568 A CN 202210759568A CN 114823581 B CN114823581 B CN 114823581B
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- 238000001816 cooling Methods 0.000 title claims abstract description 101
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000003475 lamination Methods 0.000 claims abstract description 118
- 238000003466 welding Methods 0.000 claims abstract description 79
- 238000007789 sealing Methods 0.000 claims abstract description 61
- 238000005192 partition Methods 0.000 claims abstract description 19
- 239000000110 cooling liquid Substances 0.000 claims description 79
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 5
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- MSSNHSVIGIHOJA-UHFFFAOYSA-N pentafluoropropane Chemical compound FC(F)CC(F)(F)F MSSNHSVIGIHOJA-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 6
- 239000002826 coolant Substances 0.000 description 5
- 239000012530 fluid Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000007787 solid Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
- H01S5/0237—Fixing laser chips on mounts by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02375—Positioning of the laser chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02407—Active cooling, e.g. the laser temperature is controlled by a thermo-electric cooler or water cooling
- H01S5/02423—Liquid cooling, e.g. a liquid cools a mount of the laser
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to an embedded cooling heat sink for a power chip and a semiconductor device, and aims to solve the technical problems that the heat between the power chip and the cooling heat sink needs to pass through multiple layers of conducting paths, so that the thermal resistance is increased, the packaging thickness of the heat sink and the power chip is large, and the chip is exposed outside the heat sink and is easy to damage. One end of an upper sealing lamination of the embedded cooling heat sink is provided with a positioning groove, the size of the positioning groove is matched with that of the power chip, and the inner side surface of the positioning groove is used for being welded with the power chip in a sealing mode; k cooling partition plates are arranged at positions, corresponding to the positioning grooves, in the first hollowed-out area on the cooling lamination sheet, so that k +1 cooling grooves are formed; the cooling lamination is provided with a first welding edge, a second welding edge and a third welding edge, and the orthographic projection of the positioning groove of the upper sealing lamination on the cooling lamination covers the first welding edge, the second welding edge and the third welding edge. The semiconductor device includes a power chip and the embedded cooling heat sink for the power chip described above.
Description
Technical Field
The invention relates to a cooling heat sink for a power chip and a semiconductor device, in particular to an embedded cooling heat sink for a power chip and a semiconductor device.
Background
At present, a semiconductor laser chip is connected with a heat sink by welding the semiconductor laser chip on the outside with a microchannel heat sink through a welding material, the vertical thickness from the chip to a fluid is larger, the heat transfer of the chip is conducted to the welding material through a substrate, then the heat is conducted to the heat sink through the welding material, the heat is guided to an internal fluid coolant by the heat sink, heat exchange is generated at a solid-liquid interface, the heat is taken away by the coolant, the main thermal resistance is the thermal resistance of the chip substrate + the thermal resistance of the welding material interface + the thermal resistance of the heat sink and the welding material interface + the convective heat exchange thermal resistance of the fluid and the solid, the thermal resistance is increased through multi-layer heat conduction, the chip is not directly contacted with the cooling liquid, the heat exchange efficiency is reduced, meanwhile, the chip is welded on the surface of the heat sink, and the chip is easy to damage to the chip when a semiconductor device is prepared.
Disclosure of Invention
The invention aims to solve the technical problems that the heat generated by a chip is conducted by multiple layers due to the connection mode of the chip and a cooling heat sink at present, so that the thermal resistance is increased, the packaging thickness of the heat sink and the chip is large, and the chip is exposed outside the heat sink and is easy to damage.
The technical scheme of the invention is as follows:
the invention provides an embedded cooling heat sink for a power chip, which comprises an upper sealing lamination, a cooling lamination, a flow guiding lamination and a lower sealing lamination which are stacked from top to bottom;
a first cooling liquid inlet and a first cooling liquid outlet which are isolated from each other are arranged on the upper sealing lamination;
the cooling lamination is provided with a first hollow area, a second cooling liquid inlet and a second cooling liquid outlet, wherein the first hollow area, the second cooling liquid inlet and the second cooling liquid outlet are isolated from each other;
a third cooling liquid inlet corresponding to the second cooling liquid inlet and a second hollow-out area corresponding to the second cooling liquid outlet which are isolated from each other are arranged on the drainage lamination;
a third hollowed-out area corresponding to a third cooling liquid inlet and a fourth hollowed-out area corresponding to the second hollowed-out area are arranged on the flow guide lamination and are isolated from each other;
the lower sealing lamination is provided with a fourth cooling liquid inlet corresponding to the third hollowed-out area and a third cooling liquid outlet corresponding to the fourth hollowed-out area which are isolated from each other;
it is characterized in that:
one end of the upper sealing lamination is provided with a positioning groove, and the size of the positioning groove is matched with that of the power chip; the inner side surface of the positioning groove is used for being welded with the power chip in a sealing mode;
the first cooling liquid inlet of the upper sealing lamination is used for introducing non-conductive cooling liquid;
k cooling clapboards are arranged at the positions, corresponding to the positioning grooves, in the first hollow-out areas on the cooling laminated sheet to form k +1 cooling grooves; the upper side face of the cooling partition plate is used for being welded with a power chip;
defining: the extending direction of the cooling partition plate is the X direction, the stacking direction of each lamination is the Y direction, and the Z direction is simultaneously vertical to the X direction and the Y direction;
the cooling lamination is provided with a welding edge, and the welding edge comprises a first welding edge, a second welding edge and a third welding edge; the first welding edge and the third welding edge are oppositely arranged and are positioned on two sides of the k cooling clapboards along the Z direction; the second welding edge is connected with the first welding edge and the third welding edge and is far away from the second cooling liquid inlet;
the orthographic projection of the positioning groove of the upper sealing lamination on the cooling lamination covers the first welding edge, the second welding edge and the third welding edge; the welding edge is used for sealing and welding with the power chip;
a plurality of drainage holes are formed in the positions, corresponding to the cooling grooves, on the drainage lamination; the third hollowed-out area of the flow guide lamination is provided with n flow guide plates, the n flow guide plates form n +1 flow guide grooves, and the positions of the flow guide grooves correspond to the positions of the drainage holes.
Furthermore, the depth of the positioning groove in the Y direction is greater than or equal to the thickness of the power chip in the Y direction.
Further, the length of each cooling partition plate in the X direction is equal to or greater than the width of the power chip in the X direction.
Further, the cooling liquid is pure water or pentafluoropropane or freon.
Further, the material of the cooling partition plate is copper or diamond plated with conductive metal or silicon carbide plated with conductive metal.
Further, in the Z direction, the arrangement of the air deflectors located on both sides to the air deflector located in the center is: the length of the baffle in the X direction gradually increases.
Furthermore, the drainage holes are rectangular or circular and are arranged in an array.
Furthermore, after the upper sealing lamination, the cooling lamination, the drainage lamination, the flow guide lamination and the lower sealing lamination are sequentially laminated, all the joint surfaces are connected in a diffusion welding mode;
the external shapes and the sizes of the cooling lamination, the drainage lamination, the flow guide lamination and the lower sealing lamination in the X direction and the Z direction are the same;
the upper sealing lamination and the cooling lamination have the same size in the X direction and the Z direction.
Meanwhile, the invention also provides a semiconductor device which is characterized in that:
the embedded cooling heat sink comprises a power chip and the embedded cooling heat sink for the power chip;
the power chip is clamped in the positioning groove of the upper sealing lamination, the power chip is welded with the inner side surface of the positioning groove in a sealing mode, and the power chip is welded with the cooling partition plate, the first welding edge, the second welding edge and the third welding edge of the cooling lamination in a sealing mode.
The power chip and the embedded heat sink are combined together to form a complete and continuous cooling liquid channel inside the heat sink, and the power chip and the cooling liquid can be in direct contact for heat exchange.
Furthermore, the solder used for the sealing welding is tin or gold tin.
The invention has the beneficial effects that:
1. the invention arranges the locating slot matched with the power chip on the upper sealing lamination, installs the power chip in the locating slot and welds with the cooling clapboard of the cooling lamination, so that the power chip and the embedded cooling heat sink form a whole, the cooling liquid continuously flows in the embedded cooling heat sink, the direct contact of the power chip and the cooling liquid in the cooling slot is realized for heat exchange, the heat resistance of the power chip heat conduction is the power chip substrate heat resistance + the solid and fluid convection heat exchange heat resistance, compared with the existing heat sink, the heat resistance of the power chip heat conduction is the power chip substrate heat resistance + the solder heat resistance + the substrate and solder interface heat resistance + the heat sink and solder interface heat resistance + the convection heat exchange heat resistance of the solid and fluid, the heat resistance in the heat conduction process is greatly reduced, and the temperature rise of the power chip is greatly reduced.
2. According to the semiconductor device, the power chip is embedded into the heat sink, compared with the existing connection mode that the chip is welded on the surface of the heat sink, the whole thickness of the prepared semiconductor device is reduced, the integration of the power chip is facilitated, meanwhile, the power chip is protected due to the embedded power chip arrangement mode, and the damage of the power chip is reduced.
Drawings
FIG. 1 is a schematic diagram of a layered structure embodiment of an embedded cooling heat sink for a power chip in accordance with the present invention;
FIG. 2 is an enlarged view of part A of FIG. 1;
FIG. 3 is a first schematic perspective view of an embodiment of an embedded cooling heat sink for a power chip according to the present invention;
FIG. 4 is a schematic perspective view of an embodiment of an embedded cooling heat sink for a power chip according to the present invention;
FIG. 5 is a side view of the embedded cooling heat sink for a power chip of the present invention;
fig. 6 is a schematic diagram comparing the effect of a semiconductor device using the embedded cooling heat sink of the present invention with that of a semiconductor device using the conventional heat sink structure.
The reference numbers are as follows:
1-upper sealing lamination, 11-first cooling liquid inlet, 12-first cooling liquid outlet, 13-positioning groove, 2-cooling lamination, 21-second cooling liquid inlet, 22-second cooling liquid outlet, 23-cooling partition plate, 24-first hollowed-out area, 25-first welding edge, 26-third welding edge, 27-second welding edge, 3-drainage lamination, 31-third cooling liquid inlet, 32-second hollowed-out area, 33-drainage hole, 4-drainage lamination, 41-third hollowed-out area, 42-fourth hollowed-out area, 43-guide plate, 5-lower sealing lamination, 51-fourth cooling liquid inlet, 52-third cooling liquid outlet, 6-first positioning hole, 7-second positioning hole, 8-third positioning hole and 9-power chip.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as specifically described herein, and it will be appreciated by those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the present invention and that the present invention is not limited by the specific embodiments disclosed below.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in other embodiments" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
The present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially in general scale for convenience of illustration, and the drawings are only exemplary and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Meanwhile, in the description of the present invention, it should be noted that the terms "upper, lower, etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in fig. 3 only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first, second, third, or fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Defining: the extending direction of the cooling separator 23 is the X direction, the stacking direction of the respective lamination sheets is the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction.
Referring to fig. 1-5, the present embodiment provides an embedded cooling heat sink for a power chip, which includes an upper sealing lamination 1, a cooling lamination 2, a flow guiding lamination 3, a flow guiding lamination 4, and a lower sealing lamination 5, which are stacked from top to bottom;
a first cooling liquid inlet 11 and a first cooling liquid outlet 12 which are isolated from each other are arranged on the upper sealing lamination 1, a positioning groove 13 for positioning a chip is arranged at one end of the upper sealing lamination 1, the size of the positioning groove 13 is matched with that of the power chip 9, and the inner side surface of the positioning groove 13 is used for being hermetically welded with the power chip 9; the solder used is tin or gold tin.
The depth of the positioning groove 13 in the Y direction is larger than or equal to the thickness of the power chip 9 in the Y direction, so that packaging is facilitated; a first cooling liquid inlet 11 of the upper sealing lamination 1 is filled with cooling liquid, and the cooling liquid is non-conductive cooling liquid; the coolant may be pure water or pentafluoropropane or freon, with pure water having a high specific heat capacity being preferred.
The cooling lamination 2 is provided with a first hollow-out area 24, a second cooling liquid inlet 21 corresponding to the first cooling liquid inlet 11 and a second cooling liquid outlet 22 corresponding to the first cooling liquid outlet 12 which are mutually isolated; k cooling partition plates 23 with conductivity are arranged in the first hollow-out area 24 of the cooling lamination 2 corresponding to the positioning groove 13 to form k +1 cooling grooves; the upper side of the cooling partition plate 23 is used for welding with the power chip 9; preferably, the length of each cooling partition plate 23 in the X direction is equal to or greater than the width of the power chip 9 in the X direction, so that the cooling liquid is in full contact with the power chip, more heat is taken away, and the cooling efficiency is improved. The cooling partition 23 needs to have conductivity, and copper or diamond plated with conductive metal or silicon carbide plated with conductive metal can be adopted to plate the conductive metal on the diamond or silicon carbide, so that the conductivity of the cooling partition 23 is increased, and the power chip 9 can be conveniently and electrically connected.
The cooling lamination 2 is provided with a welding edge which comprises a first welding edge 25, a second welding edge 27 and a third welding edge 26; the first welding edge 25 and the third welding edge 26 are oppositely arranged and are positioned on two sides of the k cooling partition plates 23 along the Z direction; the second welding edge 27 connects the first welding edge 25 and the third welding edge 26, and the second welding edge 27 is far away from the second cooling liquid inlet 21; the orthographic projection of the positioning groove 13 of the upper sealing lamination 1 on the cooling lamination 2 covers the first welding edge 25, the second welding edge 27 and the third welding edge 26; the welding edge is used for sealing welding with the power chip 9, and the welding flux used for sealing welding is tin or gold tin.
A third cooling liquid inlet 31 corresponding to the second cooling liquid inlet 21 and a second hollow-out area 32 corresponding to the second cooling liquid outlet 22 which are isolated from each other are arranged on the drainage lamination 3; a plurality of drainage holes 33 are formed in the drainage lamination 3 at positions corresponding to the cooling grooves, specifically, the drainage holes 33 are circular holes, the diameter of each circular drainage hole is 0.1-0.5mm, and the circular drainage holes are arranged in an array; it is understood that in other embodiments, the drainage apertures 33 may also be, but are not limited to, square apertures or rectangular apertures, and accordingly, the sides of the square drainage apertures may be 0.1-0.3mm; the length of the rectangular drainage hole is 0.3-0.6mm, and the width is 0.1-0.3mm.
The flow guide lamination 4 is provided with a third hollow-out area 41 corresponding to the third cooling liquid inlet 31 and a fourth hollow-out area 42 corresponding to the second hollow-out area 32 which are isolated from each other; the third hollow-out area 41 of the flow guiding lamination 4 is provided with n flow guiding plates 43, n flow guiding plates 43 form n +1 flow guiding grooves, and the positions of the flow guiding grooves correspond to the positions of the drainage holes 33; preferably, in the Z direction, the arrangement of the baffles 43 on both sides to the baffle 43 in the center is: the length of the deflector 43 in the X direction gradually increases; by the arrangement mode that the middle guide plate 43 is long and the guide plates 43 on the two sides are gradually shortened, the flow of the cooling liquid entering the third hollow-out area 41 is more uniform, the uniformity of the distribution of the cooling liquid in the flow guide holes and the cooling groove is favorably improved, and the heat exchange performance of the power chip 9 is improved.
The lower sealing lamination 5 is provided with a fourth coolant inlet 51 corresponding to the third hollow area 41 and a third coolant outlet 52 corresponding to the fourth hollow area 42, which are isolated from each other.
The external shapes and the sizes of the cooling lamination 2, the drainage lamination 3, the flow guide lamination 4 and the lower sealing lamination 5 in the X direction and the Z direction are the same; the upper sealing lamination 1 has the same dimensions in the X-direction and in the Z-direction as the cooling lamination 2, the upper sealing lamination 1 having positioning grooves 13 and an external shape different from that of the cooling lamination 2.
The upper sealing lamination 1, the cooling lamination 2, the drainage lamination 3, the flow guiding lamination 4 and the lower sealing lamination 5 are respectively and coaxially provided with a first positioning hole 6, a second positioning hole 7 and a third positioning hole 8; the first positioning hole 6 and the second positioning hole 7 are symmetrically arranged at one end far away from the end where the power chip 9 is installed, and the third positioning hole 8 is arranged between the first cooling liquid inlet 11 and the first cooling liquid outlet 12; after the upper sealing lamination 1, the cooling lamination 2, the drainage lamination 3, the flow guiding lamination 4 and the lower sealing lamination 5 are sequentially laminated, the joint surfaces of the layers are fixedly and hermetically connected in a diffusion welding mode, and bolts penetrate through the first positioning hole 6, the second positioning hole 7 and the third positioning hole 8 of the layers, so that the embedded heat sinks can be positioned when being sequentially stacked and installed from bottom to top.
The diameters of the second cooling liquid inlet 21, the third cooling liquid inlet 31 and the fourth cooling liquid inlet 51 are the same, and the diameter of the first cooling liquid inlet 11 is larger than that of the second cooling liquid inlet 21; the diameters of the second cooling liquid outlet 22 and the third cooling liquid outlet 52 are the same, and the diameter of the first cooling liquid outlet 12 is larger than that of the second cooling liquid outlet 22; thus, counter bores are formed at the first cooling liquid inlet 11 and the first cooling liquid outlet 12 after the upper sealing lamination 1, the cooling lamination 2, the flow guiding lamination 3, the flow guiding lamination 4 and the lower sealing lamination 5 are welded, and the counter bores are used for installing sealing rings and connecting cooling liquid pipelines.
Meanwhile, the embodiment also provides a semiconductor device, which comprises a power chip 9 and the embedded cooling heat sink for the power chip; the power chip 9 is clamped in the positioning groove 13 of the upper sealing lamination 1, the power chip 9 is hermetically welded with the position where the inner side surface of the positioning groove 13 is connected, and the power chip 9 is hermetically welded with the cooling partition plate 23, the first welding edge 25, the second welding edge 27 and the third welding edge 26 of the cooling lamination 2; the solder used to fabricate the semiconductor device may be tin or gold tin. Meanwhile, the power chip 9 is embedded into the positioning groove 13 in the semiconductor device provided by the embodiment, so that the power chip 9 is well protected, and the damage to the power chip 9 is reduced.
To further illustrate the effect of the embedded cooling heat sink, the following experiments were conducted.
Test subjects:
the power chip 9 with the diameter of 3mm multiplied by 10mm is welded with the embedded heat sink provided by the embodiment;
the 3mm × 10mm power chip 9 is directly welded to the existing heat sink, that is, no positioning groove 13 is provided on the upper sealing laminate 1, and the power chip 9 is directly welded to the surface of the upper sealing laminate 1.
Referring to fig. 6, tests show that the highest temperature of the power chip 9 adopting the embedded heat sink is within the range of 0.05-0.35L/min of the volume flow of the cooling liquid, and is lower than the highest temperature of the power chip 9 adopting the existing heat sink; for example, when the volume flow rate of the cooling liquid is 0.35L/min, the heat flow density is 100W/cm 2 When the two types of heat sinks are adopted, the difference between the maximum temperature of the power chip 9 and the maximum temperature rise is 2.37 ℃, and the maximum temperature rise is 23.7 percent lower than that of the traditional micro-channel heat sink; at present, under the same volume flow, the temperature control of the power chip 9 reaches the development bottleneck in the field, the development of a semiconductor device is restricted, under the conditions of equal flow and driving pressure, the temperature of 1 ℃ is very difficult to reduce, the embedded heat sink of the embodiment is adopted, so that cooling liquid is in direct contact with the power chip 9, the thermal resistance of intermediate heat exchange is reduced, the heat exchange efficiency is greatly improved, meanwhile, the volume of the semiconductor device adopting the embedded heat sink is reduced by about 20%, and the integrated setting of the semiconductor device is more facilitated.
Claims (10)
1. An embedded cooling heat sink for a power chip comprises an upper sealing lamination (1), a cooling lamination (2), a flow guiding lamination (3), a flow guiding lamination (4) and a lower sealing lamination (5) which are stacked from top to bottom;
a first cooling liquid inlet (11) and a first cooling liquid outlet (12) which are isolated from each other are arranged on the upper sealing lamination (1); the cooling lamination (2) is provided with first hollowed-out areas (24) which are isolated from each other, a second cooling liquid inlet (21) corresponding to the first cooling liquid inlet (11), and a second cooling liquid outlet (22) corresponding to the first cooling liquid outlet (12); a third cooling liquid inlet (31) corresponding to the second cooling liquid inlet (21) and a second hollow-out area (32) corresponding to the second cooling liquid outlet (22) which are isolated from each other are arranged on the drainage lamination (3); a third hollow-out area (41) corresponding to the third cooling liquid inlet (31) and a fourth hollow-out area (42) corresponding to the second hollow-out area (32) which are isolated from each other are arranged on the flow guide lamination (4); the lower sealing lamination (5) is provided with a fourth cooling liquid inlet (51) which is isolated from each other and corresponds to the third hollow-out area (41), and a third cooling liquid outlet (52) which corresponds to the fourth hollow-out area (42); the method is characterized in that:
one end of the upper sealing lamination (1) is provided with a positioning groove (13), and the size of the positioning groove (13) is matched with that of the power chip (9); the inner side surface of the positioning groove (13) is used for being hermetically welded with the power chip (9);
the first cooling liquid inlet (11) of the upper sealing lamination (1) is used for introducing non-conductive cooling liquid;
k cooling clapboards (23) are arranged in the first hollow-out area (24) on the cooling lamination (2) and correspond to the positioning groove (13) to form k +1 cooling grooves; the upper side surface of the cooling partition plate (23) is used for welding with the power chip (9);
defining: the extension direction of the cooling partition plate (23) is an X direction, the stacking direction of each lamination is a Y direction, and the Z direction is vertical to the X direction and the Y direction simultaneously;
the cooling lamination (2) is provided with a welding edge, and the welding edge comprises a first welding edge (25), a second welding edge (27) and a third welding edge (26); the first welding edge (25) and the third welding edge (26) are oppositely arranged and are positioned on two sides of the k cooling clapboards (23) along the Z direction; the second welding edge (27) is connected with the first welding edge (25) and the third welding edge (26), and the second welding edge (27) is far away from the second cooling liquid inlet (21);
the orthographic projection of the positioning groove (13) of the upper sealing lamination (1) on the cooling lamination (2) covers the first welding edge (25), the second welding edge (27) and the third welding edge (26); the welding edge is used for sealing and welding with the power chip (9);
a plurality of drainage holes (33) are formed in the positions, corresponding to the cooling grooves, of the drainage lamination (3); the third hollowed-out area (41) of the flow guide lamination (4) is provided with n flow guide plates (43), the n flow guide plates (43) form n +1 flow guide grooves, and the positions of the flow guide grooves correspond to the positions of the drainage holes (33).
2. The embedded cooling heat sink for a power chip of claim 1, wherein:
the depth of the positioning groove (13) in the Y direction is larger than or equal to the thickness of the power chip (9) in the Y direction.
3. The embedded cooling heat sink for a power chip of claim 2, wherein:
the length of each cooling partition plate (23) in the X direction is equal to or greater than the width of the power chip (9) in the X direction.
4. The embedded cooling heat sink for power chips of claim 3, wherein:
the cooling liquid is pure water or pentafluoropropane or freon.
5. The embedded cooling heat sink for power chips of any of claims 1-4, wherein:
the cooling partition plate (23) is made of copper or diamond plated with conductive metal or silicon carbide plated with conductive metal.
6. The embedded cooling heat sink for power chips of claim 5, wherein:
in the Z direction, the arrangement mode from the guide plates (43) at two sides to the guide plate (43) at the center is as follows: the length of the guide plate (43) in the X direction is gradually increased.
7. The embedded cooling heat sink for power chips of claim 6, wherein:
the drainage holes (33) are rectangular or circular and are arranged in an array.
8. The embedded cooling heat sink for power chips of claim 7, wherein:
after the upper sealing lamination (1), the cooling lamination (2), the drainage lamination (3), the flow guiding lamination (4) and the lower sealing lamination (5) are sequentially laminated, all the joint surfaces are connected in a diffusion welding mode;
the external shapes and the sizes of the cooling lamination (2), the drainage lamination (3), the flow guide lamination (4) and the lower sealing lamination (5) in the X direction and the Z direction are the same;
the dimensions of the upper sealing lamination (1) and the cooling lamination (2) in the X direction and the Z direction are the same.
9. A semiconductor device, characterized by:
comprising a power chip (9) and an embedded cooling heat sink for a power chip (9) according to any of claims 1-8;
the power chip (9) is clamped in the positioning groove (13) of the upper sealing lamination (1), the power chip (9) is welded with the inner side surface of the positioning groove (13) in a sealing mode, and the power chip (9) is welded with the cooling partition plate (23), the first welding edge (25), the second welding edge (27) and the third welding edge (26) of the cooling lamination (2) in a sealing mode.
10. The semiconductor device according to claim 9, wherein:
the solder adopted by the sealing welding is tin or gold tin.
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