CN114823384A - Board-level system-in-package method and package structure - Google Patents

Board-level system-in-package method and package structure Download PDF

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Publication number
CN114823384A
CN114823384A CN202110130714.4A CN202110130714A CN114823384A CN 114823384 A CN114823384 A CN 114823384A CN 202110130714 A CN202110130714 A CN 202110130714A CN 114823384 A CN114823384 A CN 114823384A
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China
Prior art keywords
chip
pad
circuit board
bonding
cavity
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CN202110130714.4A
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Chinese (zh)
Inventor
黄河
向阳辉
刘孟彬
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Ningbo Semiconductor International Corp
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Ningbo Semiconductor International Corp
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Priority to CN202110130714.4A priority Critical patent/CN114823384A/en
Priority to PCT/CN2021/143214 priority patent/WO2022143930A1/en
Publication of CN114823384A publication Critical patent/CN114823384A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00095—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00865—Multistep processes for the separation of wafers into individual elements
    • B81C1/00888—Multistep processes involving only mechanical separation, e.g. grooving followed by cleaving
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/037—Hollow conductors, i.e. conductors partially or completely surrounding a void, e.g. hollow waveguides

Abstract

A board level system level packaging method and a packaging structure comprise: bonding the first device wafer on the first surface of the circuit board through a bonding layer, wherein the bonding layer is arranged to avoid the first bonding pad and the second bonding pad, the first bonding pad and the second bonding pad are opposite to each other to form a first gap, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is located above the second cavity; forming a first conductive bump in the first gap by an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad; and after the first conductive bump is formed, cutting the circuit board from one side of the second surface along the cutting area to form a cutting groove penetrating through the circuit board. The invention improves the packaging efficiency of the board-level system-level packaging process and the compatibility with the chip forming process of the front section.

Description

Board-level system-in-package method and package structure
Technical Field
The embodiment of the invention relates to the field of semiconductor device manufacturing, in particular to a board-level system-in-package method and a package structure.
Background
The system-in-package is formed by integrally assembling a plurality of active elements/devices, passive elements/devices, MEMS devices, discrete KGD (Known Good chips) such as a photo chip, a biochip, etc., having different functions and prepared by different processes, into a single standard package having a multi-layered device structure in three dimensions (X direction, Y direction, and Z direction) in any combination, and can provide a plurality of functions, forming one system or subsystem.
Flip-Chip (FC) bonding is a common system-level packaging method. The system-in-package method comprises the following steps: providing a PCB (printed circuit board), wherein solder balls (formed by a ball-planting process) arranged according to a certain requirement are formed on the PCB; dipping the circuit board with the soldering flux, and then inversely mounting the chip on the circuit board; soldering pads (pad) on the chip and solder balls on the circuit board by using a reflow soldering process and then electrically connecting the pads and the solder balls; and filling glue between the bottom of the chip and the circuit board to increase the mechanical strength of the whole structure.
However, the existing system-in-package process still has a large challenge.
Disclosure of Invention
The embodiment of the invention provides a board-level system-level packaging method and a packaging structure, which are beneficial to simplifying the packaging process flow and improving the packaging efficiency.
In order to solve the above problem, an embodiment of the present invention provides a board-level system-in-package method, including: providing a circuit board, wherein the circuit board comprises a first surface and a second surface which are opposite to each other, the circuit board comprises a chip bonding area and a cutting area, a first cavity is formed in the circuit board in the chip bonding area, a plurality of first welding pads are formed on the first surface of the outer side of the first cavity, and the first welding pads are sunken on the first surface; providing a first device wafer serving as a carrier plate, wherein the first device wafer is provided with a plurality of first chips, a second welding pad is formed on one surface of each first chip, and the second welding pad is sunken on the surface of each first chip; bonding the first surface of the circuit board on the first device wafer through a bonding layer, wherein the bonding layer is arranged to avoid the first bonding pad and the second bonding pad, the first bonding pad and the second bonding pad oppositely enclose a first gap, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is positioned above the second cavity; forming a first conductive bump in the first gap by an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad; and after the first conductive bump is formed, cutting the circuit board from one side of the second surface along the cutting area to form a cutting groove penetrating through the circuit board.
Accordingly, an embodiment of the present invention provides a board-level system-in-package structure, including: the circuit board comprises a chip bonding area and a cutting area, wherein a first cavity is formed in the circuit board in the chip bonding area, a plurality of first welding pads are formed on the first surface of the outer side of the first cavity, and the first welding pads are sunken on the first surface; the first device wafer is used as a carrier plate and bonded on the first surface of the circuit board, a plurality of first chips are arranged in the first device wafer, a second welding pad is formed on one surface of each first chip and is sunken on the surface of each first chip, and a first gap is formed by the second welding pad and the first welding pad in an opposite enclosing mode; the bonding layer is positioned between the first chip of the circuit board and the device wafer and arranged to avoid the first welding pad and the second welding pad, a closed second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is positioned above the second cavity; the first electroplated conductive bump is positioned in the first gap and electrically connected with the first welding pad and the second welding pad; and the cutting groove is positioned in the cutting area and penetrates through the circuit board.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the board-level system-in-package method provided by the embodiment of the invention, a circuit board comprises a first surface and a second surface which are opposite, the circuit board comprises a chip bonding area and a cutting area, a first cavity is formed in the circuit board in the chip bonding area, the first surface 101 of the circuit board is bonded on a first device wafer 50 through a bonding layer, a first gap is defined by a first bonding pad of the circuit board and a second bonding pad of a first chip in an opposite surrounding manner, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, the first chip is positioned above the second cavity, and then a first conductive bump electrically connected with the first bonding pad and the second bonding pad is formed in the first gap through an electroplating process, so that the wafer is electrically connected with the circuit board. Compared with the scheme of realizing the electric connection between the chip and the circuit board by welding, firstly, the embodiment of the invention realizes the electric connection between the device wafer and the circuit board by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, the device wafer is bonded on the circuit board, wafer-level bonding is achieved, and after the device wafer and the circuit board are bonded together, the conductive bump for electrically connecting the device wafer and the circuit board is formed through an electroplating process, so that compared with a scheme that each chip is independently welded to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high compatibility with the process of the packaging front section, and the traditional chip manufacturing process or the wafer level packaging process is convenient to realize the board level system level packaging process; in addition, the device wafer is physically connected with the circuit board through a bonding layer, the bonding layer avoids the arrangement of the first welding pad and the second welding pad, the bonding layer not only realizes the physical connection between the device wafer and the circuit board, but also forms a second cavity in the bonding layer, and the second cavity can provide a part of depth of the functional cavity of the first chip, so that the depth of the first cavity is not too large, and the influence on the design of the circuit board is favorably reduced; and the bonding layer is also used for defining the forming position of the first conductive bump, which is beneficial to preventing the first conductive bump from overflowing transversely in the electroplating process and is convenient for controlling the electroplating process.
In the board-level system-in-package structure provided by the embodiment of the invention, a first cavity is formed in a circuit board, a plurality of first welding pads are formed on a first surface outside the first cavity, and the first welding pads are recessed in the first surface; a device wafer is bonded on a first surface of the chip bonding area, a plurality of first chips are arranged in the device wafer, a second welding pad is formed on one surface of each first chip and is sunken on the surface of each first chip, and a first gap is formed by the second welding pad and the first welding pad in a surrounding mode; the bonding layer is positioned between the first chip of the circuit board and the device wafer and arranged to avoid the first welding pad and the second welding pad, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is positioned above the second cavity; the first electroplated conductive bump is positioned in the first gap and electrically connected with the first welding pad and the second welding pad; the cutting groove is located the cutting zone and runs through the circuit board. Compared with the scheme of realizing the electric connection between the chip and the circuit board by welding, firstly, the embodiment of the invention realizes the electric connection between the device wafer and the circuit board by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, the device wafer is bonded on the circuit board, wafer-level bonding is achieved, and after the device wafer and the circuit board are bonded together, the conductive bump for electrically connecting the device wafer and the circuit board is formed through an electroplating process, so that compared with a scheme that each chip is independently welded to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high compatibility with the process of the packaging front section, and the traditional chip manufacturing process or the wafer level packaging process is convenient to realize the board level system level packaging process; in addition, the device wafer and the circuit board are physically connected through a bonding layer, the bonding layer is arranged to avoid the first bonding pad and the second bonding pad, the bonding layer not only realizes the physical connection between the device wafer and the circuit board, but also is provided with a second cavity, and the second cavity can provide a part of depth of a function cavity of the first chip, so that the depth of the first cavity is not too large, and the influence on the design of the circuit board is favorably reduced; in addition, the bonding layer is also used for defining the forming position of the first conductive bump, which is beneficial to preventing the first conductive bump from overflowing transversely in the electroplating process and is convenient for controlling the electroplating process.
Drawings
Fig. 1 to fig. 6 are schematic structural diagrams corresponding to steps in a first embodiment of a board-level system-in-package method according to the present invention;
fig. 7 to fig. 8 are schematic structural diagrams corresponding to steps in a second embodiment of the board-level system-in-package method of the invention;
fig. 9 is a schematic structural diagram corresponding to each step in the third embodiment of the board-level system-in-package method of the present invention;
fig. 10 is a schematic structural diagram corresponding to each step in the fourth embodiment of the board-level system-in-package method according to the present invention;
fig. 11 is a schematic structural diagram corresponding to each step in the fifth embodiment of the board-level system-in-package method of the invention.
Detailed Description
Existing system-in-package approaches still have major challenges. Specifically, taking a flip chip as an example, the conventional system-in-package method has the following disadvantages: 1. the process is complex, so that the packaging efficiency is low; 2. all chips need to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. the chip and the circuit board need to be electrically connected by using a welding process, and the chip cannot be compatible with the process of the packaging front section; 4. when larger pressure is applied carelessly in the process of dipping the soldering flux, the circuit board is easy to be fractured.
In order to solve the technical problem, an embodiment of the present invention provides a board level system in package method, including: providing a circuit board, wherein the circuit board comprises a first surface and a second surface which are opposite, the circuit board comprises a chip bonding area and a cutting area, a first cavity is formed in the circuit board in the chip bonding area, a plurality of first welding pads are formed on the first surface outside the first cavity, and the first welding pads are sunken in the first surface; providing a first device wafer serving as a carrier plate, wherein the first device wafer is provided with a plurality of first chips, a second welding pad is formed on one surface of each first chip, and the second welding pad is sunken on the surface of each first chip; bonding the first device wafer on the first surface of the circuit board through a bonding layer, wherein the bonding layer is arranged to avoid the first bonding pad and the second bonding pad, the first bonding pad and the second bonding pad are opposite to each other to form a first gap, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is located above the second cavity; forming a first conductive bump in the first gap by an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad; and after the first conductive bump is formed, cutting the circuit board from one side of the second surface along the cutting area to form a cutting groove penetrating through the circuit board. Compared with the scheme of realizing the electric connection between the chip and the circuit board by welding, firstly, the embodiment of the invention realizes the electric connection between the device wafer and the circuit board by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, the device wafer is bonded on the circuit board, wafer-level bonding is achieved, and after the device wafer and the circuit board are bonded together, the conductive bump for electrically connecting the device wafer and the circuit board is formed through an electroplating process, so that compared with a scheme that each chip is independently welded to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high compatibility with the process of the packaging front section, and the traditional chip manufacturing process or the wafer level packaging process is convenient to realize the board level system level packaging process; in addition, the device wafer and the circuit board are physically connected through a bonding layer, the bonding layer is arranged to avoid the first bonding pad and the second bonding pad, the bonding layer not only realizes the physical connection between the device wafer and the circuit board, but also is provided with a second cavity, and the second cavity can provide a part of depth of a function cavity of the first chip, so that the depth of the first cavity is not too large, and the influence on the design of the circuit board is favorably reduced; in addition, the bonding layer is also used for defining the forming position of the first conductive bump, which is beneficial to preventing the first conductive bump from overflowing transversely in the electroplating process and is convenient for controlling the electroplating process.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1 to fig. 6 are schematic structural diagrams corresponding to steps in the first embodiment of the board-level system-in-package method of the present invention.
Referring to fig. 1 in combination, a circuit board 10 is provided and includes a first surface 101 and a second surface 102 which are opposite to each other, the circuit board includes a chip bonding region a and a cutting region b, a first cavity 18 is formed in the circuit board 10 in the chip bonding region a, a plurality of first pads 11 are formed on the first surface 101 outside the first cavity 18, and the first pads 11 are recessed in the first surface 101.
The circuit board 10 serves to support and fix a plurality of different circuit components and also serves to achieve electrical connection between the circuit components. In this embodiment, the circuit board 10 has a first surface 101 and a second surface 102 opposite to each other.
In this embodiment, the circuit board 10 includes a chip bonding region a and a dicing region b, and after a first device wafer having a plurality of first chips is bonded to the circuit board 10, the first chips are located above the chip bonding region a.
In this embodiment, the Circuit Board 10 may be a Printed Circuit Board (PCB). The circuit board 10 is not limited to a PCB board, but may be other types of circuit boards such as a ceramic circuit board.
In the present embodiment, the circuit board 10 includes a multilayer board (Multi layer board) including a non-wiring region 10a for forming the first cavity 18 in the chip bonding area a. The non-wiring region 10a is used to form a first cavity 18.
In this embodiment, each layer includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The interconnect structure 14 may include interconnect lines, and interconnect pads on the interconnect lines. In this embodiment, each laminate further includes: and the interconnection plugs 15 penetrate through the substrate 12, and the interconnection plugs 15 are connected with the interconnection structures 14 on two sides of the substrate 12. The interconnection plug 15 may include a via hole and a conductive layer plated on a surface of the via hole, and the via hole is filled with an insulating resin. Or, the through hole can be filled with conductive resin, so that the process for forming the conductive layer is saved. The number of layers of the circuit board 10 may be determined according to actual requirements. The present embodiment is described by taking the circuit board 10 as a three-layer board as an example. In other embodiments, the circuit board may be a single-layer board, a double-layer board, or a four-layer board.
It should be noted that the first cavity 18 is formed in the non-wiring region 10a of the circuit board 10, and therefore, in the manufacturing process of the circuit board 10, a circuit structure may not be manufactured in a part of the laminated board or the whole laminated board of the non-wiring region 10a, so that in the process of removing the part of the laminated board or the whole laminated board of the non-wiring region 10a, only the insulating material may be removed without removing the conductive material, and accordingly, the difficulty of the process for forming the first cavity 18 is reduced. In other embodiments, when the first cavity is formed in a circuit board with a partial thickness, a circuit structure may also be fabricated in the remaining layer number board at the bottom of the first cavity.
In this embodiment, after the first device wafer is subsequently bonded to the circuit board 10, the first chip in the first device wafer is bonded to the first surface of the chip bonding region a, and the first cavity 18 serves as a part of the functional cavity of the first device wafer to be bonded, so that when the first device wafer is prepared, the preparation processes of all the functional cavities do not need to be completed, which is beneficial to reducing the process complexity for preparing the first device wafer and improving the wafer manufacturing efficiency. Specifically, the step of forming the first cavity 18 in the chip bonding region a of the circuit board 10 includes: the board of a part of the number of layers or the whole number of layers of the non-wiring region 10a is removed to form the first cavity 18
In the present embodiment, the first cavity 18 is located in the circuit board 10 of a partial thickness, and therefore, a part of the number of layers of the board in the non-wiring region 10a is removed to form the first cavity 18. In other embodiments, the first cavity may also extend through the circuit board, removing the entire number of layers of board in the non-routing area, depending on the functional type of the first chip to be bonded. Correspondingly, in order to reduce the difficulty of the process for forming the first cavity, in the manufacturing process of the circuit board, a circuit structure is not formed in all the laminated boards in the non-wiring area. In the present embodiment, the first cavity 18 is formed by removing a part of or the entire number of layers of the non-wiring region 10a by a laser dicing process.
In this embodiment, the first cavity 18 is used as a part of a functional cavity of a device wafer, and the device wafer is subsequently bonded to the first surface 101 of the circuit board 10 through a bonding layer, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first cavity 18 and the second cavity are used together as the functional cavity of the device wafer, so that, in the step of forming the first cavity 18, the bottom area of the first cavity 18 is determined according to the performance of a first chip in the device wafer, and the depth of the first cavity 18 is determined according to the performance of the first chip and the thickness of the subsequent bonding layer (i.e., the depth of the second cavity).
In the process of forming the first cavity 18, the first cavity 18 is located in a partial thickness of the circuit board 10, and the first cavity 18 is correspondingly formed in either one or both of the first surface 101 and the second surface 102. In the present embodiment, the first cavity 18 is formed in the first surface 101 of the circuit board 10.
The first bonding pad 11 is used for corresponding electrical connection with a second bonding pad of a subsequent first chip. Specifically, the first pad 11 is recessed on the surface of the circuit board 10, so that after the first chip is bonded on the circuit board 10 in the following step, the first pad 11 and the second pad of the first chip can enclose a first gap, so that the first gap can provide a space for forming the first conductive bump. In this embodiment, the first pads 11 are located on the top layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14. The first Pad 11 may be a Pad (Pad), but is not limited to a Pad, and may be another conductive block having an electrical connection function. The material of the first pad 11 is a conductive material. In this embodiment, the material of the first pad 11 includes: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium
In this embodiment, the first organic dielectric layer 13 or the first inorganic dielectric layer is formed on the first surface 101, and the first pads 11 are embedded in the first organic dielectric layer 13 or the first inorganic dielectric layer and partially exposed. In this embodiment, since the electrical connection between the first chip and the circuit board 10 is not required to be realized by using a soldering process, and the solder resist and the flux are not required to be formed on the circuit board 10, the first organic dielectric layer 13 or the first inorganic dielectric layer having the photolithographic bonding property can be formed, thereby improving the forming efficiency of the circuit board 10 and saving the process flow. When the top layer of the circuit board 10 is the first organic medium layer 13 with the photoetching bonding characteristic, the first organic medium layer 13 with a certain thickness can be selected according to requirements, so that the first chip can be conveniently bonded to the circuit board 10 in the subsequent process without additionally forming a bonding layer, the process can be saved, and the forming efficiency of the circuit board can be improved; when the top layer of the circuit board 10 is the first inorganic dielectric layer, the electroplating solution can more easily enter the first gap due to the small surface tension of the electroplating solution on the inorganic dielectric layer, thereby being beneficial to improving the formation yield and efficiency of the first conductive bump; in addition, as the welding assisting layer and the solder mask layer are not required to be formed, the process can be saved, and the forming efficiency of the circuit board is improved.
For better subsequent electroplating to form a better first conductive bump, the first pad 11 needs to be disposed to satisfy certain requirements, such as: the area of the first bonding pad 11 exposed is 5 to 200 square micrometers. When the area of the exposed first bonding pad 11 is within the above range, the first bonding pad 11 can be in sufficient contact with the plating solution in the subsequent plating process, so as to avoid the first bonding pad 11 from being in insufficient contact with the plating solution to affect the contact performance of the first conductive bump and the first bonding pad 11, for example, the contact resistance is affected by too small contact area, or the first conductive bump and the first bonding pad cannot be in contact with each other to cause poor electrical contact, and further, the contact area can be ensured not to be too large to reduce the plating efficiency, and meanwhile, the excessive area can not be occupied.
Referring to fig. 2, a first device wafer 50 is provided as a carrier, the first device wafer 50 has a plurality of first chips 30 therein, one surface of each first chip 30 is formed with a second bonding pad 31, and the second bonding pad 31 is recessed in the surface of the first chip 30.
In this embodiment, the first device wafer 100 is used as a carrier for a subsequent packaging process, that is, the whole packaging process needs to be performed in a process environment (e.g., a clean room) suitable for the first device wafer 100, and the whole packaging process needs to use process equipment and a production line suitable for the first device wafer 100
The first device wafer 50 is used to bond with the circuit board 10. In particular, the first chip 30 is intended to be bonded to the circuit board 10, at least part of the first chip 30 being located above the first cavity 18, so that the first cavity 18 can function as a functional cavity.
In this embodiment, the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, and the second pad 31 is located on one side of the third surface 301 and recessed in the third surface 301. As an example, the third surface 301 is a chip front surface of the first chip 30, and the fourth surface 302 is a chip back surface of the first chip 30. Wherein, the chip back side refers to the bottom side of the substrate in the chip. In other embodiments, according to the function type of the first chip, the following may also be: the fourth surface is a front surface of the chip, and the third surface is a back surface of the chip.
In this embodiment, the shapes and the areas of the circuit board 10 and the first device wafer 50 are the same, so that in the step of bonding the first device wafer 50 on the circuit board 10 through the bonding layer, when stress is applied to each of the circuit board 10 and the device wafer 50, it can be ensured that the pressure between each first chip 30 and the circuit board 10 is the same, so that the uniformity of the bonding strength between each first chip 30 and the circuit board 10 meets the requirement. In addition, the shapes and the areas of the circuit board 10 and the device wafer 50 are the same, so that the area of the circuit board 10 can be matched with the area of the first device wafer 50, the areas of the circuit board 10 and the first device wafer 50 can be fully utilized, and more packaging structures can be formed after subsequent cutting.
In this embodiment, the circuit board 10 and the first device wafer 50 are both circular. The circular circuit board 10 can be applied to equipment in the front-end semiconductor process, and is highly compatible with the equipment and the process. In other embodiments, the circuit board may also be a polygon, and the polygon includes: square, pentagonal, hexagonal, octagonal, etc.
In this embodiment, the number of the first chips 30 is plural, and the plural first chips 30 are chips with the same function; alternatively, the plurality of first chips 30 includes at least two chips with different functions, and the chips with different functions are integrated together to realize a certain function. Wherein, the first chip 30 includes: the first chip is at least one of a bare chip, a plastic package layer wrapped on the surface, a shielding layer arranged on the top surface and an interconnection through hole structure penetrating through the chip formed in the first chip. In this embodiment, the surface of the first chip 30 includes an active area d and an interconnection area c surrounding the active area d, and the second pad 31 is located in the interconnection area c.
The first chip 30 includes at least one of a sensor module chip, a MEMS chip, a filter chip, and a biosensor chip. The sensor module chip comprises a module chip which at least senses one of radio frequency signals, infrared radiation signals, visible light signals, sound wave signals and electromagnetic wave signals. The module chip for sensing the radio frequency signal may be a radio frequency module chip applied in a 5G device, but is not limited to a 5G radio frequency sensor module chip, and may also be other types of radio frequency module chips. The module chip for receiving the infrared radiation signal may be an infrared sensor module chip using the infrared radiation signal for temperature measurement or imaging in thermal imagers, forehead temperature guns, other types, and the like. The sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and an optical filter, which can receive visible light for imaging. The sensor module chip can also be a microphone module chip which can receive sound waves for transmitting sound signals. The sensor module chip is not limited to the type listed here, and may be various types of sensor module chips that can perform a certain function in the art. The MEMS chip comprises a thermopile sensor chip, and the thermopile sensor chip and the logic chip are integrated together to realize an infrared sensing function, such as temperature measurement. The MEMS chip can also be a microphone sensor chip, and the microphone sensor chip and the logic chip are integrated together to realize the sound wave sensing function. The filter chip includes: one or both of a Surface Acoustic Wave (SAW) resonator and a bulk acoustic wave (bulk acoustic wave) resonator. For example, the bulk acoustic wave resonator may be a reflection array type bulk acoustic wave resonator (BAW-SMR), a diaphragm bulk acoustic wave (FBAR) resonator, or an air gap type FBAR. The biosensor chip comprises one or two of a fingerprint identification chip and an ultrasonic fingerprint sensor chip.
Depending on the type of function of the first chip 30, the first chip 30 may have a third cavity therein, the third cavity being located on the side of the third surface 301, or the third cavity being located on the side of the fourth surface 302. For example, for a surface acoustic wave resonator, the third cavity is located on the third surface 301 side.
The second bonding pads 31 are recessed in the third surface 301, and after the first chip 30 is bonded to the circuit board 10, the second bonding pads 31 and the first bonding pads 11 enclose a first gap, which is favorable for increasing the height of the first gap. The second pad 31 may be a pad, but is not limited to a pad, and may also be another conductive block having an electrical connection function. The material of the second pad 31 is a conductive material. In this embodiment, the material of the second pad 31 includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc or chromium. In the present embodiment, the area of the exposed second pad 31 is 5 to 200 square micrometers for similar reasons as the first pad 11.
Referring to fig. 3, the first surface 301 of the circuit board is bonded to the first device wafer 50 through a bonding layer 20, the bonding layer 20 is disposed to avoid the first bonding pad 11 and the second bonding pad 31, the first bonding pad 11 and the second bonding pad 31 are opposite to each other to form a first gap 32, a closed second cavity 21 is formed in the bonding layer 20, the second cavity 21 is opposite to and communicated with the first cavity 18, and the first chip is located above the second cavity.
It should be noted that, in this embodiment, the first device wafer 50 is used as a carrier, and the first surface 101 of the circuit board 10 is bonded on the first device wafer 50 in the bonding process.
The first voids 32 are used to provide spatial locations for forming the first conductive bumps. The first gap 32 exposes the first pad 11 and the second pad 31, and the first pad 11 and the second pad 31 are made of conductive materials, so that a first conductive bump is formed only on the exposed first pad 11 and the exposed second pad 31 by electroplating in the subsequent electroplating process.
The bonding layer 20 not only enables physical connection between the device wafer 50 and the circuit board 10, but also the second cavity 21 in the bonding layer 20 provides a part of the depth of the cavity below the first chip 30, so that the depth of the first cavity 18 is not too large, which is beneficial to reducing the influence on the design of the circuit board 10. In this embodiment, the first cavity 18 and the second cavity 21 are used to jointly form a functional cavity of the first chip 30, so as to provide a chip cavity required for the operation of the first chip 30. For example, when the first chip 30 is a thermopile sensor chip, the first chip 30 and the circuit board 10 are thermally insulated by the first cavity 18 and the second cavity 21, so as to reduce the conduction of heat received by the thermopile structure into the circuit board 10 below the first cavity 18 and the second cavity 21, thereby improving the measurement accuracy of the thermopile sensor.
In this embodiment, the second cavity 21 is closed, and the first chip 30 is located above the second cavity 21, such that the first chip seals the second cavity 21. Depending on the type of function of the first chip 30, at least part of the first chip 30 is located above the first cavity 18. In this embodiment, the first chip 30 completely covers the first cavity 18, so as to increase the effective space size of the functional cavity, thereby improving the performance of the first chip 30. In other embodiments, the second cavity 21 may be non-closed.
Specifically, a bonding layer 20 is formed on either or both of the first chip 30 and the circuit board 10, the bonding layer 20 exposing a corresponding pad; a first die 30 in a device wafer 50 is bonded to a circuit board 10 using a bonding layer 20. As an example, the bonding layer 20 is formed on the first chip 30. The first cavity 18 is formed in the circuit board 10, and therefore, the surface flatness of the first chip 30 is higher than that of the circuit board 10, and the bonding layer 20 is more easily formed on the first chip 30.
Specifically, a bonding material (not shown) is formed on a surface of the first device wafer 50; patterning the bonding material to expose the second pad 31, and forming a second cavity 21 in the bonding material, where the second cavity is located in the working area d, and at the same time, since the first device wafer 100 further includes a scribe line, after the bonding material is patterned, the scribe line is also exposed, and then the remaining bonding material is used as the bonding layer 20; the first cavity 18 and the second cavity 21 are oppositely arranged, and the first chip 30 and the circuit board 10 are bonded together through the bonding layer 20. In other embodiments, a bonding material may also be formed on the first surface of the circuit board, and the bonding material may be patterned to expose the first pads and the first cavities, and the remaining bonding material may serve as a bonding layer. By forming the bonding layer on the circuit board, the bonding layer can be formed outside each first cavity in the same step, and the packaging efficiency is improved.
The material of the bonding layer 20 includes one or more of a lithographically bondable material, a Die Attach Film (DAF), glass, a dielectric material, and a polymer material.
In this embodiment, the material of the bonding layer 20 comprises a lithographically bondable material. The bonding layer 20 has high bonding strength, good chemical resistance, acid and alkali resistance, high temperature resistance and the like, and is favorable for realizing bonding in a short process time. In addition, the bonding layer 20 has photoetching performance, and can be patterned by using a photoetching process so as to avoid using an additional etching process, thereby facilitating simplification of the patterning process step, improvement of packaging efficiency and production capacity, and reducing influence on the bonding strength of the bonding layer 20 and damage to the circuit board 10 or the first chip 30.
In this embodiment, the material of the bonding layer 20 includes: film-like dry film or liquid dry film. The dry film material has a relatively low elastic modulus, and is easily deformed to prevent damage when subjected to a thermal stress, thereby facilitating reduction of a bonding stress between the first chip 30 and the circuit board 10. In this embodiment, the bonding layer 20 is annular, and the second cavity 21 is a closed cavity, so that the plastic package material is prevented from being filled into the second cavity 21 and the first cavity 18 (i.e., the functional cavity of the first chip) during a subsequent plastic package process, thereby avoiding affecting the normal performance of the first chip.
In other embodiments, the bonding layer is made of a die bonding film, the die bonding film is a film-shaped material with double-sided adhesiveness, and patterning can be performed by etching or laser ablation to form the second cavity; or, the material of the bonding layer may also be a dielectric material, such as an oxide or a nitride containing silicon, and accordingly, the second cavity may be formed by patterning in an etching manner, and the first chip and the circuit board may be bonded by fusion bonding; or the bonding layer is made of glass, correspondingly, the second cavity can be formed by patterning in an etching mode, and the first chip and the circuit board are bonded in a glass medium bonding mode; or, the bonding layer is made of a polymer material, and may be patterned by etching to form a second cavity, and accordingly, the first chip and the circuit board are bonded by adhesive bonding, where the polymer material refers to a polymer adhesive, such as polymethyl methacrylate (PMMA) Polyimide (PI).
It should be noted that, in this embodiment, the second cavity is formed by patterning as an example. In other embodiments, a sacrificial member may be first disposed at a position where the second cavity is to be formed (for example, the sacrificial member is bonded by means of temporary bonding) to define an area of the second cavity, and after forming a bonding layer exposing the top of the sacrificial member, the sacrificial member is removed to form the second cavity. Wherein a pyrolytic film may be attached to the surface of the sacrificial member to serve as a release layer between the sacrificial member and the bonding layer.
As an example, since the circuit board has the first cavity formed therein, the second cavity may be formed by temporarily bonding a sacrificial member on the first chip and removing the sacrificial member after forming the bonding layer on the first chip.
In this embodiment, the bonding layer 20 covers a remaining area outside the first gap 32 between the first chip 30 and the circuit board 10 outside the first cavity 18, and the bonding layer 20 is used to define a forming position of the first conductive bump, that is, the bonding layer 20 encloses a boundary of the first gap 32, so as to prevent the subsequent first conductive bump from exceeding the boundary, thereby facilitating control of the electroplating process and preventing the first conductive bump from laterally overflowing during the electroplating process. In addition, since the physical connection between the first chip 30 and the circuit board 10 is realized through the bonding layer 20, the bonding layer 20 covers the remaining area outside the first gap 32 between the first chip 30 and the circuit board 10 outside the first cavity 18, and the mechanical strength of the package structure is enhanced.
In this embodiment, after the first device wafer 50 is bonded to the first surface 101 of the circuit board 10 through the bonding layer 20, the sidewalls of the second cavity 21 and the sidewalls of the first cavity 18 are flush. In other embodiments, the projection of the first cavity on the surface of the circuit board is located within the projection of the second cavity on the surface of the circuit board; alternatively, the projection of the second cavity on the surface of the circuit board is located within the projection of the first cavity on the surface of the circuit board.
In the present embodiment, the thickness of the bonding layer 20 is 5 μm to 200 μm, and the bonding layer 20 covers at least 10% of the area of the first chip 30, so as to ensure the bonding strength between the first chip 30 and the circuit board 10. In the present embodiment, the height of the first voids 32 is 5 μm to 200 μm. When the height of the first gap 32 is 5 μm to 200 μm, the electroplating solution can easily enter the first gap 32 to perform the electroplating process in the subsequent electroplating process, and the problem of overlong electroplating time due to too large height of the first gap 32 can be avoided, so that the electroplating efficiency and the electroplating yield can be considered.
In this embodiment, in order to better perform the electroplating process, the first pad 11 and the second pad 31 may be designed to include a facing portion and a staggered portion. The first pad 11 and the second pad 31 include opposite portions to ensure that the first conductive bump formed subsequently can have good contact with both the first pad 11 and the second pad 31, thereby ensuring that the first pad 11 and the second pad 31 can have good electrical connection through the first conductive bump. The first bonding pad 11 and the second bonding pad 31 further include staggered portions, and the staggered portions are more easily contacted with the electroplating solution, so that the electroplating solution is easily flowed into the first gap 32 under the condition that the first gap 32 is smaller, and further, the formation of a relatively good first conductive bump is facilitated. In this embodiment, the area of the facing portion of the first pad 11 and the second pad 31 is larger than one-half of the area of the first pad 11 or the second pad 31. When the area of the facing portion of the first bonding pad 11 and the second bonding pad 31 is greater than one-half of the area of the first bonding pad 11 or the second bonding pad 31, the electroplating process can be better realized, which is beneficial to completely filling the formed first conductive bump in the first gap 32 as much as possible, thereby ensuring that the first conductive bump and the first bonding pad 11 and the second bonding pad 31 have enough contact area, and correspondingly being beneficial to realizing lower contact resistance.
Referring to fig. 4, a first conductive bump 40 is formed in the first void 32 through an electroplating process, and the first conductive bump 40 electrically connects the first pad 11 and the second pad 31.
The first conductive bump 40 is used to electrically connect the first pad 11 and the second pad 31, and accordingly, the first chip 30 and the circuit board 10 are electrically connected. Wherein the bonding layer 20 covers a region of the periphery of the first conductive bump 40 between the first chip 30 and the surface of the circuit board 10 outside the first cavity 18.
Compared with the scheme of electrically connecting the chip and the circuit board by welding, the embodiment realizes the electrical connection between the device wafer 50 and the circuit board 10 by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, in the embodiment, the first device wafer 50 is bonded on the circuit board 10, so that wafer-level bonding is realized, and after the first device wafer 50 and the circuit board 10 are bonded together, a conductive bump for electrically connecting the device wafer and the circuit board is formed through an electroplating process, so that compared with a scheme that each chip is individually welded to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process and the packaging front-stage process have high compatibility, and the traditional chip manufacturing process or the wafer-level packaging process is convenient to realize the board-level system-level packaging process.
In this embodiment, the materials of the first pad 11 and the second pad 31 include: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, and chromium, and the material of the first conductive bump 40 accordingly includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc and chromium. In this embodiment, the material of the first conductive bump 40 is the same as the material of the second pad 11 and the first pad 31, so that the first conductive bump 40 is easier to form in the first gap 32. The material of the first conductive bump 40 may be different from the material of the first pad 11 or the second pad 31, and in order to form the first conductive bump 40 more easily, a material layer having the same material as the material of the conductive bump 40 may be formed on the first pad 11 or the second pad 31.
In this embodiment, the electroplating process includes electroless plating. The plating solution used for the electroless plating is determined according to the material of the conductive bump to be formed and the materials of the first pad 11 and the second pad 31. In this embodiment, the electroless plating includes: electroless palladium plating immersion gold (ENEPIG), wherein the time of chemical nickel is 30 minutes to 50 minutes, the time of chemical gold is 4 minutes to 40 minutes, and the time of chemical palladium is 7 minutes to 32 minutes; or, chemical nickel gold, wherein the chemical nickel time is 30 minutes to 50 minutes, and the chemical gold time is 4 minutes to 40 minutes; or, chemical nickel, wherein the time of chemical nickel is 30 minutes to 50 minutes.
In this embodiment, when the plating process selects electroless palladium gold immersion (ENEPIG) or electroless nickel gold (ENIG), the process parameters may refer to table 1.
TABLE 1
Figure BDA0002925123950000121
In this embodiment, before the chemical plating, in order to better complete the electroplating process, the surfaces of the first pad 11 and the second pad 31 may be cleaned first, so as to remove the natural oxide layer on the surfaces of the first pad 11 and the second pad 31 and improve the surface wettability (wettability) of the first pad 11 and the second pad 31; an activation process may then be performed to promote nucleation growth of the plating metal on the metal to be plated.
In this embodiment, the cross-sectional area of the first conductive bump 40 is greater than 10 square microns, so that the area occupied by the first conductive bump 40 is not too large, the bonding strength between the first conductive bump 40 and the first pad 11 or the second pad 31 is ensured, and the good electrical connection between the first pad 11 and the second pad 31 is ensured.
Referring to fig. 5, after the first conductive bump 40 is formed, the circuit board 10 is cut along the cutting region b from the second surface 102 side, so as to form a cutting groove 70 penetrating through the circuit board 10.
In this embodiment, the circuit board 10 is cut along the cutting area b by using a blade cutting (blade saw) or laser cutting process.
The cutting process by the blade comprises the following steps: attaching the surface of the first device wafer 50, which faces away from the circuit board 10, to a uv (ultraviolet) adhesive film, and cutting the circuit board 10 along the cutting area b to form a cutting groove 70; after the cutting groove 70 is formed, the UV adhesive film is irradiated by ultraviolet light, and the UV adhesive film is removed.
The UV glue film serves as a dicing tape (dicing tape) for providing a process platform and mechanical support during the cutting of the circuit board 10. Moreover, the viscosity of the UV adhesive film before being irradiated by ultraviolet light is high, and the viscosity of the UV adhesive film after being irradiated by ultraviolet light is significantly reduced, so that the first device wafer 50 can be easily taken down from the UV adhesive film after cutting is completed.
It should be noted that, in other embodiments, a package layer may be formed on the first device wafer 50 before the circuit board 10 is cut, or the first device wafer 50 may be temporarily bonded to a carrier substrate, and then the circuit board 10 is cut, so as to improve the strength of the first device wafer 50, reduce the influence of the cutting process on the first device wafer 50, and improve the yield.
In this embodiment, in the process of cutting the circuit board 10 along the cutting area b, the first device wafer 50 is used as a carrier plate, and the cutting process needs to be performed in a dust-free environment and only by using a process machine and a production line for preparing the first device wafer 50, which is beneficial to simplifying the process steps of cutting the circuit board 10 and reducing the production cost.
It should be noted that, according to the functional type of the first chip 30, the first chip 30 may be a chip requiring a cavity at both top and bottom, such as a bulk acoustic wave thin film resonator; the first chip 30 may also be a chip that requires only an upper cavity or a lower cavity, such as a surface acoustic wave resonator.
Referring to fig. 6, for example, the first chip 30 is a chip requiring a cavity on both the top and bottom, the first chip 30 may include a third cavity 331.
The first chip 30 may be an FBAR filter in a bulk acoustic wave filter, which includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes) and a third cavity 331 on one side of the resonant structure 3013. Correspondingly, the second cavity 21 in the bonding layer 20 and the third cavity 331 in the first chip 30 are respectively located on two sides of the resonant structure 3013, and the second cavity 21, the third cavity 331 and the first cavity 18 together serve as a working cavity of the first chip 30.
In other embodiments, the first chip may be other chips containing cavities, such as an infrared thermopile sensor.
Fig. 7 to fig. 8 are schematic structural diagrams corresponding to steps in a second embodiment of the board-level system-in-package method of the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: a second conductive bump 80 is also formed on the second surface 102 of the circuit board 10.
Referring to fig. 7, a circuit board 10 is provided, a first cavity 18 is formed in the circuit board 10, a plurality of first pads 11 are formed on the surface of the circuit board 10 outside the first cavity 18, and the first pads 11 are recessed on the surface of the circuit board 10. The circuit board 10 includes opposing first and second surfaces 101 and 102. In this embodiment, the first surface 101 of the circuit board 10 has a first cavity 18 formed therein.
In this embodiment, the circuit board 10 comprises a plurality of boards, each of which includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The circuit board 10 further includes a third pad 16 located on the second surface 102, and the third pad 16 is located on the bottom layer of the interconnect structure 14 and electrically connected to the corresponding interconnect structure 14.
Specifically, the third pads 16 are formed on the second surface 102 of the circuit board 10. A portion of the surface of the third pad 16 is exposed at the second surface 102 for forming a second conductive bump during the electroplating process. The third bonding pad 16 is recessed in the second surface 102 to facilitate the formation of the second conductive bump. In this embodiment, a part of the surface of the interconnection structure 14 located at the bottom layer is exposed to the second surface 102, and a part of the interconnection structure 14 exposed by the second surface 102 is used as the third pad 16, so that it is not necessary to additionally form a pad on the second surface 102, which is beneficial to simplifying the process; alternatively, the third pad 16 is formed on the underlying interconnect structure 14 and exposed to the second surface 102.
In this embodiment, a second organic dielectric layer 81 or a second inorganic dielectric layer is formed on the second surface 102, and the third pad 16 is embedded in the second organic dielectric layer 81 or the second inorganic dielectric layer and partially exposed. For specific description of the second organic dielectric layer 81 and the second inorganic dielectric layer, reference may be made to the description of the first organic dielectric layer and the first inorganic dielectric layer in the foregoing embodiments, and details are not repeated here.
For better subsequent electroplating to form a second conductive bump, the third pad 16 is also required to satisfy certain requirements, such as: the area of the third bonding pad 16 exposed is 5 to 200 square micrometers. When the exposed area of the third bonding pad 16 is within the above range, the third bonding pad 16 can be in sufficient contact with the plating solution in the subsequent plating process, so as to prevent the third bonding pad 16 from being in insufficient contact with the plating solution and affecting the contact performance between the second conductive bump and the third bonding pad 16, for example, if the contact area is too small, the contact resistance is affected, or the contact cannot be made, the poor electrical contact is caused, and it can be ensured that the contact area is not too large, the plating efficiency is not reduced, and meanwhile, too much area is not occupied.
Continuing to refer to fig. 7, the first device wafer 50 is bonded on the circuit board 10 through the bonding layer 20, the bonding layer 20 is disposed to avoid the first pad 11 and the second pad 31, the first pad 11 and the second pad 31 are opposite to each other to form a first gap 32, a second cavity 21 is formed in the bonding layer 20, the second cavity 21 is opposite to and communicated with the first cavity 18, and the first chip 30 is located above the second cavity 21.
Referring to fig. 8, a first conductive bump 40 is formed in the first void 32 and a second conductive bump 80 is formed on the third pad 16 through an electroplating process. The second conductive bump 80 is used to electrically connect the circuit board 10 with other chips or components.
In the present embodiment, the first conductive bump 40 and the second conductive bump 80 are formed in the same step, which greatly improves the packaging efficiency. In other embodiments, the first conductive bump and the second conductive bump may be formed by separately performing electroplating processes in different steps. In other embodiments, the second conductive bump can be formed by other processes (e.g., ball-mounting process).
For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 9 is a schematic structural diagram of a board-level system-in-package method according to a third embodiment of the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the first cavity 18 is located in the circuit board 10 at a portion of the thickness of the chip bonding area a, and a plurality of air holes 90 are formed in the circuit board 10 at the bottom of the first cavity 18 through the remaining thickness.
The actual device function requirements of the first chip 30 are met by forming a plurality of air holes 90 through the remaining thickness in the circuit board 10 at the bottom of the first cavity 18. For example, the first chip 30 is a sensor module chip, and the sensor module chip is a microphone sensor chip, and the microphone sensor chip can implement an acoustic wave sensing function by forming the air hole 90.
In this embodiment, after the first cavity 18 is formed in the circuit board 10, the circuit board 10 with the remaining thickness at the bottom of the first cavity 18 is etched by using a laser cutting process. Therefore, in the present embodiment, in the manufacturing process of the circuit board 10, no circuit structure is formed in all the layer number boards in the non-wiring region, so that in the process of forming the first cavity 18 and the air hole 90, only the insulating material can be removed without removing the conductive material, and accordingly, the difficulty of the process of forming the first cavity 18 and the air hole 90 is reduced.
For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 10 is a schematic structural diagram corresponding to each step in the fourth embodiment of the board-level system-in-package method of the present invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the packaging method realizes three-dimensional packaging (3D package).
Referring to fig. 10, a first device wafer 50 is provided, the first device wafer 50 has a plurality of first chips 30 therein, each first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, the second pads 31 are located on one side of the third surface 301 and are recessed in the third surface 301, the first chips 30 further include fourth pads 36, the fourth pads 36 are located on one side of the fourth surface 302 and are recessed in the fourth surface 302, and electrical connection is achieved between the fourth pads 36 and the second pads 31.
In this embodiment, the first chip 30 has a via interconnection structure 33 formed therein, an end of the via interconnection structure 33 facing the third surface 301 is connected to the second pad 31, and an end of the via interconnection structure 33 facing the fourth surface 302 is connected to the fourth pad 36. Specifically, the Via interconnection structure 33 is a Through Silicon Via (TSV) interconnection structure.
In this embodiment, a third organic dielectric layer 37 or a third inorganic dielectric layer is formed on the fourth surface 302, and the fourth pad 36 is embedded in the third organic dielectric layer 37 or the third inorganic dielectric layer and partially exposed.
For specific description of the third organic dielectric layer 37 and the third inorganic dielectric layer, reference may be made to the description of the first organic dielectric layer and the second inorganic dielectric layer in the foregoing embodiments, and details are not repeated here.
With continued reference to fig. 10, the packaging method further includes: providing a second device wafer 42, wherein the second device wafer 42 has a second chip 45, a fifth pad 44 is formed on any surface of the second chip 45, and the fifth pad 44 is recessed in the surface of the second chip 45.
The second device wafer 42 is used to bond with the first device wafer 50 to perform a particular function.
The fifth bonding pad 44 is recessed on the surface of the second chip 45, so that the fifth bonding pad 44 and the fourth bonding pad 36 can relatively enclose a third gap after the second device wafer 42 is used for bonding with the first device wafer 50. Accordingly, the fifth pads 44 are used to make electrical connection with the fourth pads 36 of the first device wafer 50.
The second device wafer 42 may or may not be the same type as the first device wafer 50. For a detailed description of the second device wafer 42 and the fifth pads 44, reference may be made to the corresponding description of the first device wafer 50 and the second pads 31 in the foregoing embodiments, and no further description is provided here.
With continued reference to fig. 10, the first device wafer 50 is bonded to the second device wafer 42, and the fourth bonding pads 36 and the fifth bonding pads 44 are oppositely formed to form a third gap (not shown); a first device wafer 50 is bonded to the die bonding area a of the circuit board 10.
The second device wafer 42 and the first device wafer 50 are bonded together, and the first device wafer 50 is bonded to the circuit board 10, so that the second device wafer 42 and the first device wafer 50 are stacked in a direction perpendicular to the surface of the circuit board 10, and accordingly, a three-dimensional package (3D package) is realized. In this embodiment, after the first device wafer 50 is bonded to the circuit board 10, the second device wafer 42 is bonded to the first device wafer 50, so that the circuit board 10 can function as a support carrier in the process of implementing the second device wafer 42 and the first device wafer 50. In other embodiments, the first device wafer 50 may also be bonded to the circuit board 10 after the second device wafer 42 is bonded to the first device wafer 50.
In this embodiment, the second device wafer 42 and the first device wafer 50 are bonded together, and the fourth bonding pads 36 and the fifth bonding pads 44 are relatively surrounded to form a third gap, so that the third conductive bumps 43 are conveniently formed in the third gap through an electroplating process. Regarding the bonding manner between the second device wafer 42 and the first device wafer 50, reference may be made to the corresponding description of the step of bonding the first device wafer 50 to the circuit board 10, and details thereof are not repeated herein.
With continued reference to fig. 10, a first conductive bump 40 is formed in the first void 32 by an electroplating process.
The board-level system-in-package method further comprises the following steps: a third conductive bump 43 is formed in the third gap by an electroplating process, and the third conductive bump 43 electrically connects the fourth pad 36 and the fifth pad 44.
The third conductive bump 43 electrically connects the fourth bonding pad 36 and the fifth bonding pad 44, and realizes electrical connection between the second device wafer 42 and the first device wafer 50. In this embodiment, after the second device wafer 42 is bonded to the first device wafer 50, the first conductive bump 40 and the third conductive bump 43 are formed in the same electroplating process, which simplifies the packaging process and improves the packaging efficiency. The electrical connection between the second device wafer 42 and the first device wafer 50 is not limited to this. In other embodiments, the first device wafer may be bonded to the circuit board and the first conductive bumps are formed by an electroplating process, and then the second device wafer and the first device wafer are electrically connected by the solder balls. Or, according to the process requirement, the second device wafer is electrically connected with the first device wafer in a routing mode.
For a detailed description of the electroplating process, the first conductive bump 40 and the third conductive bump 43, please refer to the corresponding description of the previous embodiments, which is not repeated herein.
For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 11 is a schematic structural diagram corresponding to each step in the fifth embodiment of the board-level system-in-package method of the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that:
referring to fig. 11, in the step of providing the circuit board 10, a plurality of sixth pads 55 are further formed on the surface of the circuit board 10, and the sixth pads 55 are recessed on the surface of the circuit board 10.
The specific description of the sixth pad 55 may be combined with the corresponding description of the first pad, and is not repeated herein.
With continued reference to fig. 11, in the step of providing the first device wafer, the first device wafer 50 further has an interconnect die 300 formed therein and spaced apart from the first die 30, the interconnect die 300 has a conductive structure 305 formed therein, and a surface of the interconnect die 300 exposes a portion of the conductive structure 305.
During the process of bonding the first surface 301 of the circuit board 10 to the third surface 301 of the first device wafer 50, the interconnection chip 300 is located at the bonding region position on the side of the interconnection chip 300, the interconnection chip 300 is bonded to the circuit board 10, and the conductive structure 305 and the sixth pad 55 of the interconnection chip 300 relatively enclose a fourth gap (not labeled);
forming a fourth conductive bump 45 in the fourth void by an electroplating process, the fourth conductive bump 45 electrically connecting the sixth pad 55 and the conductive structure 305 of the interconnect chip 300; wherein the interconnect chip 300 is located on the circuit board 10 at the side of the first chip 30.
One surface of the interconnect chip 300 exposes a portion of the conductive structure 305, so that the interconnect chip 300 is electrically connected to the circuit board 10, or the interconnect chip 300 is electrically connected to the first chip 30 through the circuit board 10.
In this embodiment, the first conductive bump 40 and the fourth conductive bump 45 are formed in the same electroplating process, which is beneficial to improving the packaging efficiency.
In this embodiment, the interconnect chip 300 may be electrically connected to the circuit board 10 by designing a wiring manner in the circuit board 10, or the interconnect chip 300 may be electrically connected to the first chip 30 through the circuit board 10. The interconnection chip 300 may be used to electrically lead out the circuit board 10, so that the circuit board 10 may be subsequently interconnected with an external circuit or other chips through the interconnection chip 300; the interconnection chip 300 may also be used to electrically lead out the first chip 30, so as to lead out the terminals of the first chip 30 into the interconnection chip 300, so as to change the interconnection position of the first chip 30 and redistribute the terminals of the first chip 30.
In this embodiment, the conductive structure 305 penetrates through the interconnect chip 300, and both ends of the conductive structure 305 are exposed, wherein one end is used for electrically connecting with the sixth pad 55, and the other end is used for electrically connecting with other chips or external circuits. As an example, the conductive structure 305 includes an interconnect line 310 and a pad on one surface of the interconnect die 300, and a plug 320 embedded in the interconnect die 300 from the opposite surface, the plug 320 being connected to the interconnect line 310. Wherein, a portion of the interconnect line 310 on the surface of the interconnect die 300 is exposed, and a portion of the interconnect line 310 exposed on the surface of the interconnect die 300 is used as a pad (not labeled). In other embodiments, the interconnect structure may also include only plugs extending through the interconnect die, the plugs being correspondingly exposed portions of the surface of the interconnect die. In other embodiments, the interconnect structure may also include an interconnect line and a pad, where the pad is an exposed portion of a surface of the interconnect die, and electrical properties of the interconnect die may be subsequently extracted by forming a plug embedded in the interconnect die from the opposite surface.
Correspondingly, the invention also provides a board-level system-in-package structure. Fig. 5 is a schematic structural diagram of a board-level system-in-package structure according to an embodiment of the invention.
In this embodiment, the board-level system-in-package structure includes: the circuit board 10 comprises a first surface 101 and a second surface 102 which are opposite to each other, the circuit board 10 comprises a chip bonding area a and a cutting area b, a first cavity 18 is formed in the circuit board 10 in the chip bonding area a, a plurality of first welding pads 11 are formed on the first surface 101 outside the first cavity 18, and the first welding pads 11 are recessed in the first surface 101; a first device wafer 50 bonded on the first surface 101 of the circuit board 10, wherein the first device wafer 50 has a plurality of first chips 30 therein, one surface of each first chip 30 is formed with a second bonding pad 31, the second bonding pad 31 is recessed in the surface of the first chip 30, and a first gap (not shown) is defined by the second bonding pad 31 and the first bonding pad 11; the bonding layer 20 is located between the first chip of the circuit board 10 and the first device wafer 50, and is arranged to avoid the first bonding pad 11 and the second bonding pad 31, a closed second cavity 21 is formed in the bonding layer 20, the second cavity 21 is opposite to and communicated with the first cavity 18, and the first chip 30 is located above the second cavity 21; a first plated conductive bump 40 in the first gap, the first conductive bump 40 electrically connecting the first pad 11 and the second pad 31; and a cutting groove 70 located in the cutting region b and penetrating through the circuit board 10.
The electroplated first conductive bump 40 is correspondingly formed by adopting an electroplating process, and compared with the scheme of electrically connecting the chip and the circuit board by welding, firstly, the embodiment of the invention realizes the electrical connection between the first device wafer 50 and the circuit board 10 by utilizing the electroplating process, the process flow is simple, and the packaging efficiency is high; secondly, in the embodiment of the present invention, the first device wafer 50 is bonded to the circuit board, so that wafer-level bonding is achieved, and after the first device wafer 50 and the circuit board 10 are bonded together, a conductive bump for electrically connecting the first device wafer 50 and the circuit board 10 is formed by an electroplating process, so that compared with a scheme of individually welding each chip and electrically connecting the chip to the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high compatibility with the process of the packaging front section, and the traditional chip manufacturing process or the wafer level packaging process is convenient to realize the board level system level packaging process; in addition, the first device wafer 50 and the circuit board 10 are physically connected through a bonding layer, the bonding layer 20 is disposed to avoid the first bonding pad 11 and the second bonding pad 31, the bonding layer 20 not only realizes the physical connection between the first device wafer 50 and the circuit board 10, but also forms a second cavity 21 in the bonding layer 20, and the second cavity 21 can provide a part of depth of the functional cavity of the first chip 30, so that the depth of the first cavity 30 is not too large, which is beneficial to reducing the influence on the design of the circuit board 10; in addition, the bonding layer 20 is further used to define a forming position of the first conductive bump 40, which is beneficial to preventing the first conductive bump 40 from overflowing laterally in the electroplating process, and is convenient for controlling the electroplating process.
The circuit board 10 is used to support and secure a plurality of different circuit components and also to make electrical connections between the circuit components. In this embodiment, the circuit board 10 has a first surface 101 and a second surface 102 opposite to each other. Either one of the first surface 101 and the second surface 102 is a front surface of the circuit board 10, and the other is a back surface of the circuit board 10.
In this embodiment, the circuit board 10 includes a chip bonding region a and a dicing region b, and after a first device wafer having a plurality of first chips is bonded to the circuit board 10, the first chips are located above the chip bonding region a.
In this embodiment, the circuit board 10 may be a printed circuit board. The circuit board 10 is not limited to a PCB board, but may be other types of circuit boards such as a ceramic circuit board.
In the present embodiment, the circuit board 10 includes a multilayer board. The multilayer board includes a non-wiring region 10a for forming a first cavity 18. The non-wiring region 10a is used to form a first cavity 18. In this embodiment, each layer includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The interconnect structure 14 may include interconnect lines, and interconnect pads on the interconnect lines. In this embodiment, each laminate further includes: and an interconnection plug 15 penetrating the substrate 12, the interconnection plug connecting the interconnection structures 14 on both sides of the substrate 12. The number of layers of the circuit board 10 may be determined according to actual requirements. The present embodiment is described by taking the circuit board 10 as a three-layer board as an example. In other embodiments, the circuit board may be a single-layer board, a double-layer board, a four-layer board, or the like.
In this embodiment, after the first device wafer is subsequently bonded to the circuit board 10, the first chip in the first device wafer is bonded to the first surface of the chip bonding region a, and the first cavity 18 serves as a part of the functional cavity of the first device wafer to be bonded, so that when the first device wafer is prepared, the preparation processes of all the functional cavities do not need to be completed, which is beneficial to reducing the process complexity for preparing the first device wafer and improving the wafer manufacturing efficiency.
In this embodiment, the first cavity 18 is located in a portion of the thickness of the circuit board 10. In other embodiments, the first cavity may also extend through the circuit board depending on the type of function of the first chip.
The first cavity 18 is used as a part of the first device wafer function cavity, and thus, the bottom area of the first cavity 18 is determined according to the performance of the first chip 30, and the depth of the first cavity 18 is determined according to the performance of the first chip 30 and the depth of the second cavity 21. The first cavity 18 is located in a partial thickness of the circuit board 10, the first cavity 18 being located in either or both of the first surface 101 and the second surface 102. In this embodiment, the first cavity 18 is located in the first surface 101 of the circuit board 10.
The first pads 11 are used for corresponding electrical connection with the second pads 31 of the first chip 30. Specifically, the first pad 11 is recessed on the surface of the circuit board 10, so that the first pad 11 and the second pad 31 can enclose a first gap, so that the first gap can provide a space for forming the first conductive bump 40.
In this embodiment, the first pads 11 are located on the top layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14. The first pad 11 may be a pad, but is not limited to a pad, and may also be another conductive block having an electrical connection function. The material of the first pad 11 is a conductive material. In this embodiment, the material of the first pad 11 includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc or chromium.
In this embodiment, a first organic dielectric layer 13 or a first inorganic dielectric layer is formed on the surface (i.e., the first surface 101) of the circuit board 10 on one side of the first pad 11, and the first pad 11 is embedded in the first organic dielectric layer 13 or the first inorganic dielectric layer and partially exposed.
In this embodiment, the first conductive bump 40 is formed by an electroplating process, and since a soldering process is not required to achieve electrical connection between the first chip 30 and the circuit board 10, a solder resist and a flux are not required to be formed on the circuit board 10, and the first organic dielectric layer 13 or the first inorganic dielectric layer having a photolithographic bonding characteristic can be formed, thereby improving the forming efficiency of the circuit board 10 and saving the process flow. When the top layer of the circuit board 10 is the first organic dielectric layer 13 with the photolithography bonding characteristic, the first organic dielectric layer 13 with a certain thickness can be selected as required, so that the first chip 30 can be conveniently bonded to the circuit board 10 without additionally forming a bonding layer, thereby saving the process and improving the forming efficiency of the circuit board; when the top layer of the circuit board 10 is the first inorganic dielectric layer, the electroplating solution can enter the first gap more easily due to the small surface tension of the electroplating solution on the inorganic dielectric layer, thereby improving the formation yield and efficiency of the first conductive bump 40.
The first chip 30 in the first device wafer 50 is bonded to the circuit board 10 such that the first cavity 18 can be part of a functional cavity of the first chip 30. In this embodiment, the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, and the second pad 31 is located on one side of the third surface 301 and recessed in the third surface 301. As an example, the third surface 301 is a chip front surface of the first chip 30, and the fourth surface 302 is a chip back surface of the first chip 30. In other embodiments, according to the function type of the first chip, the following may also be: the fourth surface is a front surface of the chip, and the third surface is a back surface of the chip.
In this embodiment, the shapes and the areas of the circuit board 10 and the first device wafer 50 are the same, so that in the step of bonding the first device wafer 50 on the circuit board 10 through the bonding layer, when stress is applied to each of the circuit board 10 and the device wafer 50, it can be ensured that the pressure between each first chip 30 and the circuit board 10 is the same, so that the uniformity of the bonding strength between each first chip 30 and the circuit board 10 meets the requirement. In addition, the shapes and the areas of the circuit board 10 and the first device wafer 50 are the same, so that the area of the circuit board 10 and the area of the first device wafer 50 can be matched, the areas of the circuit board 10 and the first device wafer 50 can be fully utilized, and after subsequent cutting, more packaging structures can be formed.
In this embodiment, the circuit board 10 and the first device wafer 50 are both circular. The circuit board 10 is circular, which is suitable for a machine in a front-end process of a semiconductor, and has high compatibility with equipment and a process. In other embodiments, the circuit board may also be a polygon, and the polygon includes: square, pentagonal, hexagonal, octagonal, etc.
In this embodiment, the number of the first chips 30 is multiple, and the multiple first chips 30 are chips with the same function; alternatively, the plurality of first chips 30 may include at least two chips with different functions, and the chips with different functions may be integrated together to realize a certain function. Depending on the functional type of the first chip 30, the first chip 30 may comprise a third cavity (not shown), wherein the third cavity is located at the side of the third surface 301, or at the side of the fourth surface 302, or at the side of the third surface 301 and the fourth surface 302, respectively. The first chip 30 may further have a through-silicon via interconnection structure (not shown) formed therein, and one end of the through-silicon via interconnection structure is electrically connected to the second pad 31. For the specific description of the first chip 30, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.
The second pad 31 is recessed in the third surface 301, so that the second pad 31 and the first pad 11 enclose a first gap, and the height of the first gap is increased.
The first voids are used to provide spatial locations for forming the first conductive bumps 40. The first gap exposes the first pad 11 and the second pad 31, and the first pad 11 and the second pad 31 are made of conductive materials, so that the first conductive bump 40 is formed only on the exposed first pad 11 and the exposed second pad 31 by electroplating in the process of the electroplating process for forming the first conductive bump 40.
In this embodiment, the height of the first gap is 5 μm to 200 μm, which is beneficial to making the electroplating solution easily enter the first gap for electroplating process, improving the formation quality of the first conductive bump 40, and preventing the height of the first conductive bump 40 from being too large.
In this embodiment, the first pad 11 and the second pad 31 include a facing portion and a staggered portion. The area of the facing part of the first welding pad 11 and the second welding pad 31 is larger than one half of the area of the first welding pad 11 or the second welding pad 31, so that the electroplating process is better realized, the first conductive bump 40 is favorably and completely filled in the first gap as far as possible, the sufficient contact area is ensured between the first conductive bump 40 and the first welding pad 11 as well as between the first conductive bump 40 and the second welding pad 31, and the lower contact resistance is correspondingly favorably realized.
The bonding layer 20 not only realizes the physical connection between the first device wafer 50 and the circuit board 10, but also forms the second cavity 21 in the bonding layer 20, and the second cavity 21 provides a part of the depth of the cavity below the first chip 30, so that the depth of the first cavity 18 is not too large, which is beneficial to reducing the influence on the design of the circuit board 10. In this embodiment, the first cavity 18 and the second cavity 21 together constitute a functional cavity of the first chip 30. In this embodiment, the second cavity 21 is a closed cavity, and the first chip 30 is located above the second cavity 21, so that the first chip seals the second cavity 21. And depending on the type of function of the first chip 30, at least part of the first chip 30 is located above the first cavity 18. In this embodiment, the first chip 30 completely covers the first cavity 18, so as to increase the effective space of the functional cavity and improve the performance of the first chip 30.
The material of the bonding layer 20 includes one or more of a lithographically bondable material, a Die Attach Film (DAF), glass, a dielectric material, and a polymer material.
In this embodiment, the material of the bonding layer 20 comprises a lithographically bondable material. The material of the bonding layer 20 includes: film-like dry film or liquid dry film. The dry film material has a relatively low elastic modulus, and is easily deformed to prevent damage when subjected to a thermal stress, thereby facilitating reduction of a bonding stress between the first chip 30 and the circuit board 10. In this embodiment, the bonding layer 20 is annular, and the second cavity 21 is a closed cavity, so that the plastic package material is prevented from being filled into the second cavity 21 and the first cavity 18 (i.e., the working cavity of the first chip) during a subsequent plastic package process, thereby avoiding affecting the normal performance of the first chip.
In other embodiments, the material of the bonding layer is a die bonding film, and the die bonding film is a film-shaped material with double-sided adhesiveness; alternatively, the material of the bonding layer is a dielectric material, such as an oxide or nitride containing silicon; or the bonding layer is made of glass; alternatively, the material of the bonding layer is a polymer material, wherein the polymer material refers to a polymer binder, such as PMMA or polyimide.
In this embodiment, the bonding layer 20 covers a remaining area outside the first gap between the first chip 30 and the circuit board 10 outside the first cavity 18, and the bonding layer 20 is used to define a forming position of the first conductive bump 40, that is, the bonding layer 20 defines a boundary of the first gap, so as to prevent the subsequent first conductive bump 40 from exceeding the boundary, facilitate control of an electroplating process, and prevent the first conductive bump from laterally overflowing during the electroplating process. In addition, since the physical connection between the first chip 30 and the circuit board 10 is realized through the bonding layer 20, the bonding layer 20 covers the remaining area outside the first gap between the first chip 30 and the circuit board 10 outside the first cavity 18, and the mechanical strength of the package structure is enhanced.
In this embodiment, the side wall of the second cavity 21 is flush with the side wall of the first cavity 18. In other embodiments, the projection of the first cavity on the surface of the circuit board is located within the projection of the second cavity on the surface of the circuit board; alternatively, the projection of the second cavity on the surface of the circuit board is located within the projection of the first cavity on the surface of the circuit board. The bonding layer 20 has a thickness of 5 μm to 200 μm, and the bonding layer 20 covers at least 10% of the area of the first chip 30 to ensure the bonding strength between the first chip 30 and the circuit board 10.
The first conductive bump 40 is used to electrically connect the first pad 11 and the second pad 31, so that the first chip 30 and the circuit board 10 are electrically connected. Wherein the bonding layer 20 covers a region of the periphery of the first conductive bump 40 between the first chip 30 and the surface of the circuit board 10 outside the first cavity 18.
In this embodiment, the cross-sectional area of the first conductive bump 40 is greater than 10 square microns, so that the area occupied by the first conductive bump 40 is not too large, the bonding strength between the first conductive bump 40 and the first pad 11 or the second pad 31 is ensured, and the good electrical connection between the first pad 11 and the second pad 31 is ensured.
In this embodiment, the cutting groove 70 is located in the cutting region b and penetrates through the circuit board 10.
For a specific description of the board-level system-in-package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 8 is a schematic structural diagram of a board-level system-in-package structure according to a second embodiment of the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the preceding embodiments in that: the circuit board 10 further includes a third pad 16 located on the second surface 102, and the third pad 16 is located on the bottom layer of the interconnect structure 14 and electrically connected to the corresponding interconnect structure 14.
The circuit board 10 includes opposing first and second surfaces 101 and 102. In this embodiment, the first surface 101 of the circuit board 10 has a first cavity 18 formed therein.
In this embodiment, the circuit board 10 comprises a plurality of boards, each of which includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The circuit board 10 further includes third pads 16, and the third pads 16 are located on the bottom layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14.
Specifically, the third pads 16 are formed on the second surface 102 of the circuit board 10. A portion of the surface of the third pad 16 is exposed to the second surface 102. The third bonding pad 16 is embedded in the second surface 102, facilitating the formation of the second conductive bump. In this embodiment, a part of the surface of the interconnection structure 14 located at the bottom layer is exposed to the second surface 102, and the part of the interconnection structure 14 exposed by the second surface 102 is used as the third pad 16, so that it is not necessary to additionally form a pad on the second surface 102, which is beneficial to simplifying the process; alternatively, the third pad 16 is formed on the underlying interconnect structure 14 and exposed to the second surface 102. In this embodiment, a second organic dielectric layer 81 or a second inorganic dielectric layer is formed on the second surface 102, and the third pad 16 is disposed in the second organic dielectric layer 81 or the second inorganic dielectric layer and partially exposed.
In this embodiment, the board-level system-in-package structure further includes: and a second conductive bump 80 plated on the third bonding pad 16. The second conductive bump 80 is used to electrically connect the circuit board 10 with other chips or components. In this embodiment, the second conductive bump 80 and the first conductive bump 40 are formed by an electroplating process in the same step, so that the packaging efficiency is improved.
For a specific description of the board-level system-in-package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 9 is a schematic structural diagram of a board-level system-in-package structure according to a third embodiment of the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the first cavity 18 is located in the circuit board 10 at a portion of the thickness of the chip bonding area a, and a plurality of air holes 90 are formed through the thickness in the circuit board 10 at the bottom of the first cavity 18.
The actual device function requirements of the first chip 30 are met by forming a plurality of air holes 90 through the remaining thickness in the circuit board 10 at the bottom of the first cavity 18. For example, the first chip 30 is a sensor module chip, and the sensor module chip is a microphone sensor chip, and the microphone sensor is enabled to realize an acoustic wave sensing function by forming the air hole 19.
For a specific description of the board-level system-in-package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 10 is a schematic structural diagram of a fourth embodiment of a board-level system-in-package structure according to the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the packaging method is used for realizing three-dimensional packaging (3D package).
The first device wafer 50 has a plurality of first chips 30, the first chips 30 have a third surface 301 and a fourth surface 302 opposite to each other, the second pads 31 are disposed on one side of the third surface 301 and recessed in the third surface 301, the first chips 30 further include fourth pads 36, the fourth pads 36 are disposed on one side of the fourth surface 302 and recessed in the fourth surface 302, and the fourth pads 36 and the second pads 31 are electrically connected. In this embodiment, the first chip 30 has a via interconnection structure 33 formed therein, and an end of the via interconnection structure 33 facing the third surface 301 is connected to the second pad 31. Specifically, the via interconnection structure 33 is a through-silicon via interconnection structure. In this embodiment, an end of the via interconnection structure 33 facing the fourth surface 302 is connected to the fourth pad 36.
In this embodiment, a third organic dielectric layer 37 or a third inorganic dielectric layer is formed on the fourth surface 302, and the fourth pad 36 is embedded in the third organic dielectric layer 37 or the third inorganic dielectric layer and partially exposed. In this embodiment, since the first chip 30, the circuit board 10 and the second chip are not electrically connected by using a soldering process, and a solder resist and a flux are not required to be formed on the fourth surface 302, a third organic dielectric layer 37 or a third inorganic dielectric layer with a photolithographic bonding characteristic can be formed, thereby improving the forming efficiency of the first chip 30 and saving the process flow.
In this embodiment, the board-level system-in-package structure further includes: a second device wafer 42, where the second device wafer 42 has a plurality of second chips 45, a fifth pad 44 is formed on any surface of the second chip 45, the fifth pad 44 is recessed in the surface of the second chip 45, and the fifth pad 44 and the fourth pad 36 enclose a third gap (not shown); and a plated third conductive bump 43 positioned in the third gap, the third conductive bump 43 electrically connecting the fourth pad 36 and the fifth pad 44. The second device wafer 42 is bonded to the first device wafer 50 to perform a particular function. Wherein, the second device wafer 42 and the first device wafer 50 are bonded together, and the first device wafer 50 is bonded on the circuit board 10, so that the second device wafer 42 and the first device wafer 50 are stacked in a direction perpendicular to the surface of the circuit board 10, and accordingly, three-dimensional packaging is realized. The second device wafer 42 may or may not be the same type as the first device wafer 50. For a detailed description of the second device wafer 42 and the fifth pads 44, reference may be made to the corresponding description of the first device wafer 50 and the second pads 31 in the foregoing embodiments, and no further description is provided here.
The fifth pads 44 are recessed on the surface of the second chip 70, so that the fifth pads 44 and the fourth pads 36 can enclose a third gap. The fifth pads 44 are respectively used for making electrical connection with the fourth pads 36 of the first chip 30. The third conductive bump 43 is located in the third gap, and the third conductive bump 43 electrically connects the fourth bonding pad 36 and the fifth bonding pad 34, so that the second device wafer 42 is used for electrical connection with the first device wafer 50.
For a specific description of the board-level system-in-package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 11 is a schematic structural diagram of a fifth embodiment of a board-level system-in-package structure according to the invention.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the preceding embodiments in that:
referring to fig. 11, in the step of providing the circuit board 10, a plurality of sixth pads 55 are further formed on the surface of the circuit board 10, and the sixth pads 55 are recessed on the surface of the circuit board 10.
The specific description of the sixth pad 55 can be combined with the corresponding description of the first pad, and is not repeated herein.
With continued reference to fig. 11, in the step of providing the first device wafer, the first device wafer 50 further has an interconnect die 300 formed therein and spaced apart from the first die 30, the interconnect die 300 has a conductive structure 305 formed therein, and a surface of the interconnect die 300 exposes a portion of the conductive structure 305.
During the process of bonding the first surface 301 of the circuit board 10 to the third surface 301 of the first device wafer 50, the interconnection chip 300 is located at the bonding region position on the side of the interconnection chip 300, the interconnection chip 300 is bonded to the circuit board 10, and the conductive structure 305 and the sixth pad 55 of the interconnection chip 300 relatively enclose a fourth gap (not labeled);
forming a fourth conductive bump 45 in the fourth void by an electroplating process, the fourth conductive bump 45 electrically connecting the sixth pad 55 and the conductive structure 305 of the interconnect chip 300; wherein the interconnect chip 300 is located on the circuit board 10 at a side of the first chip 30.
One surface of the interconnect chip 300 exposes a portion of the conductive structure 305, so that the interconnect chip 300 is electrically connected to the circuit board 10, or the interconnect chip 300 is electrically connected to the first chip 30 through the circuit board 10.
In this embodiment, the first conductive bump 40 and the fourth conductive bump 45 are formed in the same electroplating process, which is beneficial to improving the packaging efficiency.
In this embodiment, the interconnect chip 300 may be electrically connected to the circuit board 10 by designing the wiring manner of the interconnect structure 14 in the circuit board 10, or the interconnect chip 300 may be electrically connected to the first chip 30 through the circuit board 10. The interconnection chip 300 may be used to electrically lead out the circuit board 10, so that the circuit board 10 may be subsequently interconnected with an external circuit or other chips through the interconnection chip 300; the interconnection chip 300 may also be used to electrically lead out the first chip 30, so as to lead out the terminals of the first chip 30 into the interconnection chip 300, so as to change the interconnection position of the first chip 30 and redistribute the terminals of the first chip 30.
In this embodiment, the conductive structure 305 penetrates through the interconnect chip 300, and both ends of the conductive structure 305 are exposed, wherein one end is used for electrically connecting with the sixth pad 55, and the other end is used for electrically connecting with other chips or external circuits. As an example, the conductive structure 305 includes an interconnect line 310 and a pad on one surface of the interconnect die 300, and a plug 320 embedded in the interconnect die 300 from the opposite surface, the plug 320 being connected to the interconnect line 310. Wherein, a portion of the interconnect line 310 on the surface of the interconnect die 300 is exposed, and a portion of the interconnect line 310 exposed on the surface of the interconnect die 300 is used as a pad (not labeled). In other embodiments, the interconnect structure may also include only plugs extending through the interconnect die, the plugs being correspondingly exposed portions of the surface of the interconnect die. In other embodiments, the interconnect structure may also include an interconnect line and a pad, where the pad is an exposed portion of a surface of the interconnect die, and electrical properties of the interconnect die may be subsequently extracted by forming a plug embedded in the interconnect die from the opposite surface.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (27)

1. A board level system-in-package method is characterized by comprising the following steps:
providing a circuit board, wherein the circuit board comprises a first surface and a second surface which are opposite, the circuit board comprises a bonding area and a cutting area which surrounds the bonding area, a first cavity is formed in the circuit board in the bonding area, a plurality of first welding pads are formed on the first surface of the outer side of the first cavity, and the first welding pads are sunken on the first surface;
providing a first device wafer serving as a carrier plate, wherein the first device wafer is provided with a plurality of first chips, a second welding pad is formed on one surface of each first chip, and the second welding pad is sunken on the surface of each first chip;
bonding the first surface of the circuit board on the first device wafer through a bonding layer, wherein the bonding layer is arranged to avoid the first bonding pad and the second bonding pad, the first bonding pad and the second bonding pad are opposite to each other to form a first gap, a second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is located above the second cavity;
forming a first conductive bump in the first gap by an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad;
and after the first conductive bump is formed, cutting the circuit board from one side of the second surface along the cutting area to form a cutting groove penetrating through the circuit board.
2. The board level system-in-package method of claim 1, wherein the material of the bonding layer comprises one or more of a lithographically bondable material, a die attach film, glass, a dielectric material, and a polymer material.
3. The board level system in package method according to claim 1, wherein after forming the bonding layer on the first surface of the first device wafer or the circuit board, the first device wafer is bonded on the first surface of the chip bonding region through the bonding layer; the bonding layer is located at the bonding area.
4. The board level system-in-package method according to claim 1, wherein the bonding layer has a thickness of 5 μm to 200 μm, and the bonding layer covers at least 10% of the area of the first chip.
5. The board level system-in-package method of claim 1, wherein the first pad and the second pad which are opposite comprise a facing portion and a staggered portion, and the area of the facing portion is larger than one-half of the area of the first pad or the area of the second pad.
6. The board-level system-in-package method according to claim 1, wherein the height of the first voids is 5 μm to 200 μm.
7. The board level system-in-package method of claim 1, wherein an exposed area of the first bonding pad or the second bonding pad is 5-200 μm square.
8. The board-level system-in-package method of claim 1, wherein a cross-sectional area of the first conductive bump is greater than 10 square microns.
9. The board level system in package method according to claim 1, wherein the material of the first bonding pad and the second bonding pad comprises any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium; the material of the first conductive bump comprises any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium.
10. The board level system in package method of any one of claims 1-9, wherein said electroplating process comprises electroless plating.
11. The board-level system-in-package method according to claim 10, wherein the electroless plating comprises: electroless palladium plating and immersion gold, wherein the time of chemical nickel is 30 minutes to 50 minutes, the time of chemical gold is 4 minutes to 40 minutes, and the time of chemical palladium is 7 minutes to 32 minutes;
or, chemical nickel gold, wherein the chemical nickel time is 30 minutes to 50 minutes, and the chemical gold time is 4 minutes to 40 minutes;
or, chemical nickel, wherein the time of chemical nickel is 30 minutes to 50 minutes.
12. The board-level system-in-package method according to claim 1, wherein the circuit board is diced along the dicing area by a blade dicing or laser dicing process.
13. The board level system in package method according to claim 1, wherein in the step of providing the circuit board, the circuit board further includes a third pad, the third pad is located at a side of the second surface in the chip bonding region and recessed in the second surface;
the board-level system-in-package method further comprises the following steps: and forming a second conductive bump on the third pad by electroplating process.
14. The board-level system-in-package method according to claim 13, wherein a first organic dielectric layer or a first inorganic dielectric layer is formed on the first surface, and the first pad is embedded in the first organic dielectric layer or the first inorganic dielectric layer;
and a second organic medium layer or a second inorganic medium layer is formed on the second surface, and the third welding pad is embedded in the second organic medium layer or the second inorganic medium layer.
15. The board-level system-in-package method according to claim 1, wherein in the step of providing a circuit board, the first cavity is located in the circuit board at a partial thickness of the chip bonding region;
or the first cavity is positioned in the circuit board of partial thickness of the chip bonding area, and a plurality of air holes penetrating through the residual thickness are formed in the circuit board at the bottom of the first cavity.
16. The board level system in package method according to claim 1, wherein in the step of providing the first device wafer, the first chip has a third surface and a fourth surface opposite to each other, the second pad is located on one side of the third surface and recessed in the third surface, the first chip further includes a fourth pad located on one side of the fourth surface and recessed in the fourth surface, and an electrical connection is implemented between the fourth pad and the second pad;
the board-level system-in-package method further comprises the following steps: providing a second device wafer, wherein the second device wafer is provided with a second chip, a fifth welding pad is formed on any surface of the second chip, and the fifth welding pad is sunken in the surface of the second chip; bonding the first device wafer and the second device wafer, wherein a third gap is defined by the fourth welding pad and the fifth welding pad oppositely; and forming a third conductive bump in the third gap through an electroplating process, wherein the third conductive bump is electrically connected with the fourth welding pad and the fifth welding pad.
17. The board-level system-in-package method according to claim 1, wherein in the step of providing the circuit board, a plurality of sixth pads are further formed on the surface of the circuit board, and the sixth pads are recessed in the surface of the circuit board;
in the step of providing the first device wafer, an interconnection chip spaced apart from the first chip is further formed in the first device wafer, a conductive structure is formed in the interconnection chip, and a surface of the interconnection chip exposes a part of the conductive structure;
in the process of bonding the first surface of the circuit board to the first device wafer, the interconnection chip is located at the bonding region at the side of the interconnection chip, and the conductive structure of the interconnection chip and the sixth bonding pad relatively enclose a fourth gap;
the board-level system-in-package method further comprises the following steps: forming a fourth conductive bump in the fourth gap by an electroplating process, the fourth conductive bump electrically connecting the sixth pad and the conductive structure of the interconnection chip; the interconnection chip is electrically connected with the circuit board, or the interconnection chip is electrically connected with the first chip through the circuit board.
18. The board-level system-in-package method according to claim 1, wherein the plurality of first chips are same-function chips; or, the plurality of first chips at least comprise chips with two different functions; the first chip includes: the surface of the bare chip is wrapped with a plastic package layer, the top surface of the bare chip is provided with a shielding layer, and the first chip is provided with at least one of an interconnection through hole structure penetrating through the chip;
the first chip comprises at least one of a CIS chip, an MEMS chip, a filter chip and a sensor module chip;
the sensor module chip comprises at least one of a biosensor chip, a radio frequency sensing module chip, an infrared radiation sensing module chip, a visible light signal sensing module chip, a sound wave signal sensing module chip and an electromagnetic wave signal sensing module chip.
19. A board level system-in-package structure, comprising:
the circuit board comprises a chip bonding area and a cutting area, wherein a first cavity is formed in the circuit board in the chip bonding area, a plurality of first welding pads are formed on the first surface of the outer side of the first cavity, and the first welding pads are sunken on the first surface;
the first device wafer is used as a carrier plate and bonded on the first surface of the circuit board, a plurality of first chips are arranged in the first device wafer, a second welding pad is formed on one surface of each first chip and is sunken on the surface of each first chip, and a first gap is formed by the second welding pad and the first welding pad in an opposite enclosing mode;
the bonding layer is positioned between the first chip of the circuit board and the device wafer and arranged to avoid the first welding pad and the second welding pad, a closed second cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is positioned above the second cavity;
the first electroplated conductive bump is positioned in the first gap and electrically connected with the first welding pad and the second welding pad;
and the cutting groove is positioned in the cutting area and penetrates through the circuit board.
20. The board level system in package structure of claim 19, wherein the material of the bonding layer comprises one or more of a lithographically bondable material, a die attach film, glass, a dielectric material, and a polymer material.
21. The board level system in package structure of claim 19, wherein the first and second opposing pads comprise opposing portions and staggered portions, the opposing portions having an area greater than one-half of the area of the first pad or the second pad.
22. The board-level system-in-package structure of claim 19, wherein the height of the first voids is 5um to 200 um.
23. The board-level system-in-package structure of claim 19, wherein the circuit board further comprises a third pad, the third pad being located at the second surface in the chip bonding region and recessed in the second surface;
the board-level system-in-package structure further comprises: and the electroplated second conductive bump is positioned on the third bonding pad.
24. The board-level system-in-package structure of claim 23, wherein a first organic dielectric layer or a first inorganic dielectric layer is formed on the first surface, and the first pad is embedded in the first organic dielectric layer or the first inorganic dielectric layer;
and a second organic medium layer or a second inorganic medium layer is formed on the second surface, and the third welding pad is embedded in the second organic medium layer or the second inorganic medium layer.
25. The board-level system-in-package structure of claim 19, wherein the first cavity is located in a device region of the circuit board at a partial thickness of the chip bonding region;
or the first cavity is positioned in the circuit board with partial thickness of the chip bonding area, and a plurality of air holes penetrating through the thickness are formed in the circuit board at the bottom of the first cavity.
26. The board level system in package structure of claim 19, wherein the first chip has a third surface and a fourth surface opposite to each other, the second pad is located on one side of the third surface and recessed in the third surface, the first chip further comprises a fourth pad located on one side of the fourth surface and recessed in the fourth surface, and an electrical connection is formed between the fourth pad and the second pad;
the board-level system-in-package structure further comprises: a second device wafer bonded to the first device wafer, the second device wafer having a plurality of second chips, the second chips being bonded to the first chips, a fifth pad being formed on any surface of the second chips, the fifth pad being recessed in a surface of the second chips, the fifth pad and a fourth pad enclosing a third gap; and the third electroplated conductive bump is positioned in the third gap, and the third conductive bump is electrically connected with the fourth welding pad and the fifth welding pad.
27. The board-level system-in-package structure of claim 19, wherein the circuit board surface is further formed with a plurality of sixth pads, and the sixth pads are recessed in the circuit board surface;
the first device wafer is also provided with an interconnection chip spaced from the first chip, a conductive structure is formed in the interconnection chip, one surface of the interconnection chip is exposed with part of the conductive structure, and the conductive structure of the interconnection chip and the sixth welding pad oppositely enclose a fourth gap;
the board-level system-in-package structure further comprises: a plated fourth conductive bump in the fourth gap, the fourth conductive bump electrically connecting the sixth pad and the conductive structure of the interconnect die;
the interconnection chip is electrically connected with the circuit board, or the interconnection chip is electrically connected with the first chip through the circuit board.
CN202110130714.4A 2020-12-30 2021-01-29 Board-level system-in-package method and package structure Withdrawn CN114823384A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110130714.4A CN114823384A (en) 2021-01-29 2021-01-29 Board-level system-in-package method and package structure
PCT/CN2021/143214 WO2022143930A1 (en) 2020-12-30 2021-12-30 Board-level system-level packaging method and structure, and circuit board and forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110130714.4A CN114823384A (en) 2021-01-29 2021-01-29 Board-level system-in-package method and package structure

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