WO2022143930A1 - Board-level system-level packaging method and structure, and circuit board and forming method - Google Patents

Board-level system-level packaging method and structure, and circuit board and forming method Download PDF

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Publication number
WO2022143930A1
WO2022143930A1 PCT/CN2021/143214 CN2021143214W WO2022143930A1 WO 2022143930 A1 WO2022143930 A1 WO 2022143930A1 CN 2021143214 W CN2021143214 W CN 2021143214W WO 2022143930 A1 WO2022143930 A1 WO 2022143930A1
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WO
WIPO (PCT)
Prior art keywords
chip
circuit board
pad
bonding
board
Prior art date
Application number
PCT/CN2021/143214
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French (fr)
Chinese (zh)
Inventor
黄河
向阳辉
刘孟彬
Original Assignee
中芯集成电路（宁波）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202110129836.1A external-priority patent/CN114684780A/en
Priority claimed from CN202110130721.4A external-priority patent/CN114823386A/en
Priority claimed from CN202110129088.7A external-priority patent/CN114823375A/en
Priority claimed from CN202110130717.8A external-priority patent/CN114823385A/en
Priority claimed from CN202110130714.4A external-priority patent/CN114823384A/en
Priority claimed from CN202110130724.8A external-priority patent/CN114823387A/en
Priority claimed from CN202110129086.8A external-priority patent/CN114823373A/en
Priority claimed from CN202110129853.5A external-priority patent/CN114698259A/en
Priority claimed from CN202110129065.6A external-priority patent/CN114823372A/en
Priority claimed from CN202110129087.2A external-priority patent/CN114823374A/en
Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Publication of WO2022143930A1 publication Critical patent/WO2022143930A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to the field of semiconductor device manufacturing, in particular to a board-level system-level packaging method, structure, circuit board and forming method.
  • System-in-package uses any combination to combine multiple active components/devices, passive components/devices, MEMS devices, discrete KGD (Known Good Die) with different functions and prepared by different processes, such as optoelectronic chips, biochips, etc., It is integrated and assembled in three dimensions (X direction, Y direction and Z direction) into a single standard package with a multi-layer device structure and can provide multiple functions to form a system or subsystem.
  • KGD known Good Die
  • the system-in-package method includes: providing a PCB circuit board, wherein solder balls arranged according to certain requirements are formed on the PCB circuit board (formed by a ball-mounting process); dipping flux on the circuit board, and then flip-chip bonding the chip
  • the chip is placed on the circuit board; the pads on the chip are electrically connected to the solder balls on the circuit board by the reflow process; after that, the bottom of the chip and the circuit board are filled with glue to increase the overall structure mechanical strength.
  • the existing system-level packaging method has the following disadvantages: 1. The process is complicated, resulting in low packaging efficiency; 2. Each chip needs to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. The chip needs to be realized by a welding process The electrical connection with the PCB board is not compatible with the process in the front section of the package; 4. When a large pressure is accidentally applied during the process of dipping the flux, it is easy to cause the circuit board to crack.
  • the problem to be solved by the present invention is that the existing board-level system-level packaging has low packaging efficiency and cannot be compatible with the chip forming process in the previous stage.
  • the present invention provides a board-level system-in-package method, comprising: providing a circuit board, a surface of the circuit board is formed with a plurality of first pads, and the first pads are recessed on the surface;
  • a plurality of first chips are provided, a surface of the first chips is formed with a second pad, and the second pad is recessed on the surface;
  • a first conductive bump is formed in the first void by an electroplating process to electrically connect the first pad and the second pad.
  • the present invention also provides a board-level system-level packaging structure, comprising:
  • circuit board wherein a plurality of first pads are formed on the surface of the circuit board, and the first pads are recessed on the front surface;
  • one surface of the first chips is formed with a second bonding pad, the second bonding pad is recessed on the surface;
  • the first chip and the circuit board are bonded together, and the first bonding pad and the second bonding pad are electrically connected through electroplated first conductive bumps.
  • the present invention also provides a circuit board, comprising:
  • each layer of board at least includes a substrate, an interconnection structure located on the surface of the substrate, and the first pad is located on the interconnection structure on the top layer and is electrically connected to the interconnection structure;
  • a first organic medium layer or a first inorganic medium layer with photolithographic bonding characteristics is formed on the front surface of the circuit board, and a first pad is embedded in the first organic medium layer or the first inorganic medium layer;
  • solder pad is located on the interconnect structure on the bottom layer of the circuit board and is electrically connected to the corresponding interconnect structure, and the back surface is formed with a second organic layer with photolithographic bonding characteristics.
  • the dielectric layer or the second inorganic dielectric layer, and the fourth pad is embedded in the second organic dielectric layer or the second inorganic dielectric layer.
  • the present invention also provides a method for forming a circuit board, comprising:
  • each board at least includes a substrate and an interconnection structure on the surface of the substrate;
  • a first solder pad is formed on the top layer, and the first solder pad is electrically connected to the interconnect structure on the top layer;
  • first organic dielectric layer or a first inorganic dielectric layer with photolithographic bonding properties on the top board, covering the surface of the circuit board and exposing the first pads;
  • a fourth pad is formed on the bottom plate, the fourth pad is electrically connected to the interconnect structure on the bottom plate, and a second organic medium layer or a first inorganic medium layer with photolithographic bonding characteristics is formed on the bottom plate , covering the surface of the circuit board and exposing the fourth solder pad.
  • the present invention completely avoids the traditional packaging process of using welding to realize the electrical connection between the chip and the circuit board, and forms the first conductive bumps through the electroplating process to realize the electrical connection between the first chip and the circuit board.
  • the process flow is simple and the packaging efficiency is high;
  • the electrical connection between each chip and the circuit board can be formed through the electroplating process , compared with the traditional method that each chip is individually soldered and electrically connected to the circuit board, which greatly improves the packaging efficiency.
  • the electroplating process is compatible with the process in the front-end of the packaging, and the board-level system-level packaging process can be realized by using the traditional chip manufacturing process or the wafer-level packaging process.
  • the physical connection between the first chip and the circuit board is realized by the lithographic bonding material, and the lithographic bonding material covers the peripheral area of the first conductive bump, which directly enhances the mechanical strength of the entire structure,
  • the filling and gluing process of the prior art can be omitted.
  • the plastic packaging material does not need to fill the gap between the first chip and the circuit board, thereby saving the time of the plastic packaging process.
  • the photolithographic bonding material of the dry film material due to its relatively small elastic modulus, can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the first chip and the circuit board.
  • the photolithographic bonding material can define the positions of the first conductive bumps to prevent lateral overflow of the first conductive bumps in the electroplating process.
  • the staggered part can be more It is easy to be in contact with the electroplating solution, which can avoid the problem that the electroplating solution is not easy to flow into the first gap due to the small first gap, resulting in the inability to form relatively intact first conductive bumps.
  • the height of the first void is 5-200 microns, it not only satisfies that the electroplating solution can easily enter the first void for electroplating, but also avoids the problem that the height of the first void is too high and leads to a long electroplating time, thus taking into account the electroplating. Efficiency and Plating Yield.
  • solder resist and flux since there is no need to use the soldering process, there is no need to form solder resist and flux on the circuit board. It can be an organic dielectric layer with photolithographic bonding characteristics or an inorganic dielectric layer, thereby improving the formation efficiency of the circuit board. Save on craftsmanship.
  • the top layer is an organic medium layer with photolithographic bonding characteristics, an organic medium layer with a certain thickness can be selected as required, so as to facilitate the subsequent bonding of the first chip to the circuit board without additional bonding layers.
  • the top layer is an inorganic dielectric layer
  • the surface tension of the electroplating solution on the inorganic dielectric layer is smaller, and the electroplating solution is more likely to enter the first voids, thereby improving the formation yield of the first conductive bumps.
  • FIG. 1 to 5 show schematic structural diagrams corresponding to different steps in a board-level system-in-package method according to Embodiment 1 of the present invention
  • FIG. 6-7 are schematic diagrams of the board-level system-level packaging structure in Embodiment 2 of the present invention.
  • FIGS 8-14 are schematic diagrams of the board-level system-level packaging structure in Embodiment 3 of the present invention.
  • FIG. 20 is a schematic diagram of a board-level system-level packaging structure in Embodiment 6 of the present invention.
  • 21 and 21a are schematic diagrams of the board-level system-level package structure in Embodiment 7 of the present invention.
  • 25-27 are schematic diagrams of the board-level system-level packaging structure in Embodiment 9 of the present invention.
  • FIG. 28 is a schematic diagram of a board-level system-level package structure in Embodiment 10 of the present invention.
  • FIG. 29 is a schematic diagram of a board-level system-level package structure in Embodiment 11 of the present invention.
  • FIG. 30 is a schematic diagram of a board-level system-level package structure in Embodiment 12 of the present invention.
  • 31 to 34 are schematic diagrams showing corresponding structures in different steps in a circuit board formation process according to an embodiment of the present invention.
  • the present invention provides a board-level system-level packaging method, comprising:
  • a circuit board is provided, and a plurality of first bonding pads are formed on the surface of the circuit board, and the first bonding pads are recessed on the surface;
  • a plurality of first chips are provided, a surface of the first chips is formed with a second pad, and the second pad is recessed on the surface;
  • a first conductive bump is formed in the first void by an electroplating process to electrically connect the first pad and the second pad.
  • the present invention completely avoids the traditional packaging process of using welding to realize the electrical connection between the chip and the circuit board on the PCB, and forms conductive bumps through the electroplating process to realize the electrical connection between the first chip and the circuit board.
  • the process flow is simple and the packaging efficiency is high;
  • the electrical connection between each chip and the circuit board can be formed through the electroplating process , compared with the traditional method that each chip is individually soldered and electrically connected to the circuit board, which greatly improves the packaging efficiency.
  • the electroplating process is compatible with the process in the front-end of the package, and the board-level system-level packaging process can be realized by using the traditional chip manufacturing process or the wafer-level packaging process.
  • Embodiment 1 of the present invention provides a board-level system-level packaging method. Referring to FIG. 1 to FIG. 5 , the packaging method will be described.
  • a circuit board 10 is provided, the circuit board 10 has a front surface and a back surface, the front surface is formed with a plurality of first solder pads 11 , and the first solder pads 11 are recessed in the front surface.
  • the first pad 11 may be a pad (PAD), but is not limited to a pad, and may also be other conductive blocks with an electrical connection function.
  • the circuit board 10 includes: at least one layer of boards 12, each layer of board 12 at least includes a substrate and an interconnection structure located on the surface of the substrate, and the first pad 11 is located on the top layer and is electrically connected to the interconnection structure .
  • the circuit board 10 is a printed circuit board, that is, a PCB board.
  • the circuit board 10 can be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc. Specifically, the number of layers of the circuit board 10 can be determined according to actual needs.
  • the circuit board 10 is a three-layer board, and each layer of the board 12 includes an interconnection structure 14 located on the surface of the substrate, and an interconnection plug 15 electrically connected to the interconnection structure 14.
  • the interconnection plug 15 includes through holes and The conductive layer is plated on the surface of the through hole, and the through hole is filled with insulating resin. Alternatively, the conductive resin can also be filled in the through hole to save the process of forming the conductive layer. In the present invention, it can also be determined according to actual requirements whether each layer of the board includes interconnection plugs and interconnection structures, and there may be only interconnection structures without interconnection plugs.
  • the circuit board is not limited to a PCB board, but can also be other forms of circuit boards, such as ceramic circuit boards.
  • the top layer of the circuit board is a solder resist layer and a solder flux layer, and the solder resist covers the top surface of the circuit board and exposes the solder pads.
  • the top layer of the circuit board can be the same as the prior art, and a solder resist layer and a solder resist are arranged on the top surface; because in the present invention, the electrical connection between the first chip and the circuit board does not need to be realized by welding, so the top surface can not be A solder mask layer (green oil) is provided, or a solder flux layer is not required.
  • the top layer may be a first organic dielectric layer 13 with photolithographic bonding properties, and the first pads 11 are buried in the first organic dielectric layer 13 and partially exposed.
  • the top layer is the first organic medium layer with photolithographic bonding characteristics
  • the first organic medium layer with a certain thickness can be selected according to the needs, so as to facilitate the subsequent bonding of the first chip to the circuit board without additional bonding layers. In this way, processes can be saved, thereby improving the formation efficiency of the circuit board.
  • the top layer can also be the first inorganic medium layer.
  • the top layer is the inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is smaller, and the electroplating solution is more likely to enter the first gap, which improves the first gap.
  • a plurality of first chips 30 are provided, and a surface of the first chips 30 is formed with a second pad 31 , and the second pad 31 is recessed on the surface;
  • the surface of the bonding pad 31 is the front side of the chip, but it can be the back side of the chip.
  • the first chip 30 may contain a Through Silicon Via (TSV for short), and the second bonding pad 31 is electrically connected to the TSV. .
  • TSV Through Silicon Via
  • the first chip 30 is bonded to the circuit board 10 , and the first bonding pad 11 and the second bonding pad 31 are opposite to form a first gap 32 .
  • the first space 32 is prepared for the subsequent electroplating work, and a first conductive bump will be formed in the first space later to realize the electrical connection between the first bonding pad 11 and the second bonding pad 31 .
  • the first chip 30 and the circuit board 10 are bonded to each other through a bonding layer, and the bonding layer is arranged to avoid bonding pads.
  • the material of the bonding layer includes: one or more of photolithographic bonding material, die bonding film, dielectric material, glass and polymer material, the photolithographic material includes dry film, the medium Materials include silicon oxide or silicon nitride.
  • the material of the bonding layer is a photolithographic bonding material
  • the first chip 30 is bonded to the circuit board 10 through the photolithographic bonding material 20
  • the photolithographic bonding material 20 is used to bond the first chip 30 to the circuit board 10 .
  • the bonding material 20 is arranged to avoid the first pad 11 .
  • the photolithographic bonding material 20 may be formed on the circuit board 10 , or may be formed on the first chip 30 , or the photolithographic bonding material may be formed on both the first chip 30 and the circuit board 10 .
  • a photolithographic bonding material 20 is formed on the circuit board 10 .
  • the specific method includes: forming a photolithographic bonding material on the surface of the circuit board; patterning the photolithographic bonding material to form an opening to expose the first pad 11 ; The bonding material bonds the first chip 30 and the circuit board 10 together.
  • the photolithographic bonding material may be a liquid dry film or a film-like dry film.
  • the liquid dry film can be spin-coated on the surface of the circuit board 10 and then subjected to a patterning process.
  • the film-like dry film can be pasted on the surface of the circuit board 10 and then subjected to a patterning process.
  • the photolithographic bonding material 20 covers the area surrounding the first conductive bumps formed subsequently, that is, defines the formation position of the first conductive bumps, that is to say, the photolithographic bonding material encloses the first conductive bump.
  • the boundary of a gap 40 cannot be exceeded by subsequent conductive bumps, which facilitates the control of the electroplating process. Because the physical connection between the first chip 30 and the circuit board 10 is achieved by the photolithographic bonding material 20, and the photolithographic bonding material covers the peripheral area of the first conductive bump, the mechanical properties of the entire structure are directly enhanced. The strength can save the filling and gluing process of the prior art.
  • the plastic packaging material does not need to fill the gap between the first chip and the circuit board, thereby saving the time of the plastic packaging process.
  • the photolithographic bonding material of the dry film material due to its relatively small elastic modulus, can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the first chip and the circuit board.
  • the bonding layer may also be one or more of a die attach film, a dielectric material, glass and a polymer material, and the dielectric material includes silicon oxide or silicon nitride.
  • the dielectric material includes: silicon oxide.
  • the material of the third surface is silicon oxide
  • the material of the first inorganic medium layer is silicon oxide.
  • the first device wafer and the circuit board are bonded together by a fusion bonding process, and the bonding Silicon oxide-silicon oxide covalent bonds are formed between the layer and the first device wafer, and between the bonding layer and the circuit board, between the bonding layer and the first device wafer, and between the bonding layer and the circuit board There is a high bonding strength between them, thereby improving the packaging yield of board-level system packaging.
  • the material of the bonding layer can also be glass.
  • glass dielectric bonding is used to bond the first device wafer to the circuit board.
  • Glass dielectric bonding refers to printing glass solder on the first device wafer or circuit board. Then put it into a reflow furnace for pre-sintering, and place the pre-sintered first device wafer in alignment with the circuit board so that the first chip is located directly under the bonding layer, and then put it into the bonding machine Sintering is carried out.
  • the glass medium bonding process is simple, the bonding strength is high and the sealing effect is good, especially suitable for mass production.
  • the thickness of the photolithographic bonding material is 5-200 ⁇ m, and the photolithographic bonding material covers at least 10% of the area of the chip, which can ensure the gap between the first chip and the circuit board. bond strength.
  • the first organic medium layer 13 may be a photolithographic bonding material. In this case, there is no need to separately form the photolithographic bonding material 20, which saves the process.
  • the first chip includes at least one of: a bare chip, being wrapped with a plastic sealing layer, having a shielding layer on the top surface, and forming an interconnect via structure penetrating the chip.
  • the multiple first chips on the circuit board 10 may be chips with the same function; it may also be that the multiple first chips include at least two chips with different functions, and the multiple chips with different functions are integrated together to achieve a certain function .
  • the first chip can be a passive device or an active device, and the passive device includes capacitors, inductors, connection chips (electrical connection blocks for electrical connection, such as interconnection chips formed with interconnection structures, and the interconnection structures may include plug or TSV structure), active devices may include sensor module chips, CIS chips, MEMS chips, filter chips, logic chips, and memory chips.
  • the MEMS chip includes a thermopile sensor chip, and the thermopile sensor chip and the logic chip can be integrated together to realize infrared sensing functions, such as realizing temperature measurement.
  • the MEMS chip can also be a microphone sensor, and the microphone sensor and the logic chip can be integrated together to realize the sound wave sensing function.
  • the filter chip includes at least one of a surface acoustic wave resonator and a bulk acoustic wave resonator.
  • the first chip is a chip whose top surface receives infrared radiation, or the top surface of the first chip is a chip that receives visible light, or the top surface of the first chip is a chip that receives radio frequency signals, or the first
  • the chip can also be a flexible circuit board FPC
  • the sensor module chip includes a module chip for sensing at least one of radio frequency signals, infrared radiation signals, visible light signals, acoustic wave signals, and electromagnetic wave signals.
  • the module chip that senses the RF signal can be the RF module chip used in 5G equipment, but is not limited to the 5G RF sensor module chip, and can also be other types of RF module chips.
  • the module chip that receives the infrared radiation signal may be an infrared sensor module chip that utilizes the infrared radiation signal, such as a thermal imager, a forehead temperature gun, and other types of temperature measurement or imaging.
  • the sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and a filter, which can receive visible light for imaging.
  • the sensor module chip can also be a microphone module chip, which can receive sound waves to transmit sound signals.
  • the sensor module chips in the present invention are not limited to the types listed here, and can be various types of sensor module chips that can achieve certain functions in the
  • the first chip includes: an ultrasonic sensor chip and a peripheral chip
  • the peripheral chip includes: a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic chip, and a control chip. at least one;
  • the first chip includes: an image sensor chip and a peripheral chip, the image sensor chip includes at least one of a CMOS sensor chip or a CCD sensor chip; the peripheral chip includes : Integration of at least one or more of a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic circuit chip or a driver chip.
  • the first chip includes: a radio frequency chip, which includes at least one filter chip, and the other radio frequency chips include at least one function of signal amplification, signal reception, and signal tuning.
  • a first conductive bump 40 is formed in the first space by an electroplating process to electrically connect the first pad 11 and the second pad 31 .
  • the electroplating process includes electroless plating.
  • the plating solution used in the electroless plating is determined according to the materials of the conductive bumps and the materials of the first bonding pad and the second bonding pad to be formed in practice.
  • the materials of the first pad 11 and the second pad 31 are selected from any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof.
  • the material of the first conductive bump includes: any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof.
  • the height of the first conductive bump is 5-200 ⁇ m, such as 10 ⁇ m, 50 ⁇ m, and 100 ⁇ m.
  • the height of the first conductive bumps namely the first voids
  • the electroplating solution can easily enter the first voids for electroplating, but also avoids the problem that the height of the first voids is too high and leads to a long electroplating time.
  • the electroplating efficiency and electroplating yield are improved.
  • electroless palladium immersion gold wherein the time of chemical nickel is 30-50 minutes, the time of chemical gold is 4-40 minutes, and the time of chemical palladium is 7-32 minutes; The time is 30-50 minutes, and the time for chemical gold is 4-40 minutes.
  • electroless palladium immersion gold EPIG
  • electroless nickel gold EIG
  • the surface of the pad Before electroless plating, in order to better complete the electroplating process, the surface of the pad can be cleaned first to remove the natural oxide layer on the surface of the pad and improve the surface wettability of the pad; after that, an activation process can be performed to promote Nucleation and growth of the coating metal on the metal to be plated.
  • the settings of the first bonding pad and the second bonding pad also need to meet certain requirements, such as: the first bonding pad or the second bonding pad
  • the exposed area of the pad is 5-200 square microns.
  • the pad can be fully contacted with the plating solution to avoid insufficient contact between the pad and the plating solution and affect the contact between the conductive bump and the pad, such as contact If the area is too small, the resistance will be affected, or the inability to contact will result in poor electrical contact; moreover, it can also ensure that the contact area will not be too large, which will reduce the electroplating efficiency and will not occupy too much surface.
  • the cross-sectional area of the first conductive bumps formed is greater than 10 square micrometers, which can not only ensure that the area occupied by the first conductive bumps is not too large, but also ensure the bonding strength between the first conductive bumps and the bonding pads.
  • the first pad and the second pad can be designed to include a facing portion and a staggered portion, and the area of the facing portion is larger than half of the pad.
  • the electroplating process can be better realized, so that the formed conductive bumps are as complete as possible. Fill the first gap to avoid the formation of conductive bumps and pads with too small contact area to cause resistance to increase; The electroplating solution is not easy to flow into the first voids, resulting in the problem that relatively intact conductive bumps cannot be formed.
  • the material of the conductive bump is the same as that of the second bonding pad and the material of the first bonding pad, so that it is easier to form the conductive bump in the first void.
  • the material of the first pad and the second pad can be different from the material of the conductive bump.
  • a material layer can be first formed on the first pad or the second pad.
  • the material layer The material of the conductive bump is the same as that of the conductive bump, and the method for forming the material layer may be a deposition process.
  • a plastic sealing layer 50 is formed, and the plastic sealing layer 50 covers the circuit board 10 and the first chip 30 bonded thereon.
  • the plastic sealing layer 50 may not be formed. If the plastic sealing layer 50 is formed, an opening needs to be made on the image sensor chip module to expose the filter. In this embodiment, the plastic sealing process is performed, but whether the plastic sealing process is required in the present invention needs to be determined according to the actual situation.
  • the plastic sealing layer 50 may be formed by an injection molding process.
  • the filling performance of the injection molding process is good, and the injection molding agent can be well filled between the plurality of second chips 20 , so that the second chips 200 have a good encapsulation effect.
  • other processes may also be used to form the encapsulation layer.
  • the gap between the first chip and the circuit board is completely filled with the photolithographic bonding material layer, so the plastic sealing layer 50 does not need to be filled between the first chip and the circuit board, so that the plastic sealing process can be saved time.
  • the plastic encapsulation layer will enter the gap to better insulate and seal the first chip. and protection.
  • the first chip bonded on the circuit board includes a connection chip 30b, and the top surface of the connection chip 30b can form conductive bumps 30b1 through an electroplating process, which can be performed simultaneously with the electroplating process for forming the bumps 40 .
  • the conductive bumps 30b1 may also be formed through a ball mounting process.
  • the connection chip 30b can be used as a bridge for connecting other chips with the circuit board, and other chips are stacked on the connection chip or the connection chip is electrically connected with other chips by means of wire bonding.
  • an interconnect structure may be formed on the plastic encapsulation layer to electrically connect the chip 30 b and the other first chips 30 , and then an electroplating process or The ball mounting process forms the conductive bumps 30b1.
  • the difference between the board-level system-in-package method of the third embodiment and the first embodiment is that a cavity is provided under the first chip, and the cavity is used as a working cavity of the first chip.
  • the cavity may be located in the bonding layer or in the circuit board.
  • first chips 30a need to have a working cavity, and a first cavity 21 can be formed in the photolithographic bonding material 20 as a working cavity of the first chip 30a; then the first chip 30a is bonded on the first cavity 21 , the first cavity 21 may be a closed cavity or a non-closed cavity.
  • some of the first chips 30a need to have cavities below, and some of the first chips 30 do not need to have cavities below.
  • the photolithographic bonding material is formed on the circuit board, when the photolithographic bonding material is patterned, not only the first bonding pad is exposed, but also the first cavity is formed. bonded to the first cavity. Others are the same as the embodiment, and are not repeated here.
  • the photolithographic bonding material 20 on the first chip 30 may be patterned to form the first cavity 21 .
  • the first chip may be a chip that needs both upper and lower cavities, such as a bulk acoustic wave thin film resonator; the first chip may also be a chip that only needs an upper cavity or a lower cavity, such as a surface acoustic wave resonator.
  • the first chip 30a may contain a third cavity 3011
  • the first chip 30a may be an FBAR filter of a bulk acoustic wave filter, which includes a resonant structure 3013 (including upper and lower electrodes and a cavity between the upper and lower electrodes). piezoelectric film) and the first cavity 21 and the third cavity 3011 on both sides of the resonant structure.
  • the first chip may also be other chips containing cavities, such as an infrared thermopile sensor.
  • the first chip is a radio frequency chip, which is used to form a radio frequency module, wherein the radio frequency chip includes at least one filter chip 30a, and the other radio frequency chips include at least one of signal amplification, signal reception and signal tuning. Function. After the filter chip is bonded to the circuit board, the cavity serves as the upper cavity of the filter chip. The filtering effect of the radio frequency chip is improved.
  • Each radio frequency chip is electrically connected through the circuit board 10 to form a signal receiving path and a signal sending path inside the radio frequency front-end module.
  • the signal receiving path may include sequentially connected: an antenna, a radio frequency switch, a filter, and a low noise filter;
  • the signal transmitting path may include sequentially connected: a power amplifier, a filter, a radio frequency switch, antenna.
  • the signal receiving path and the signal sending path may also share the antenna and/or the radio frequency switch.
  • the signal receiving path may include sequentially connected: an antenna, a radio frequency switch, a duplexer, and a low noise amplifier;
  • the signal transmitting path may include sequentially connected: a power amplifier, a duplexer, a radio frequency switch; the signal receiving path and the signal sending path share the duplexer.
  • the first chip 30a may not contain the second cavity, for example, referring to FIG. 9 , it may be a surface acoustic wave filter including a resonant structure 3013 (including interdigital electrodes and a piezoelectric film), for example, referring to FIG. 10 , It can be an SMR BAW filter, which includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes), a first cavity 21 on one side of the resonant structure, and a Bragg reflection layer 3014 on the other side.
  • SMR BAW filter which includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes), a first cavity 21 on one side of the resonant structure, and a Bragg reflection layer 3014 on the other side.
  • the first chip 30c containing the cavity 21 may also be a cavity that the cavity 21 needs to communicate with the external environment, such as a microphone sensor, and the cavity above the cavity needs to communicate with the outside world.
  • a through hole 211 may be formed at a preset position in the circuit board 10 by means of laser cutting or mechanical cutting, and the through hole 211 communicates with the cavity 21 .
  • a through hole 211 may be formed at a preset position in the circuit board 10 by means of laser cutting or mechanical cutting, and the through hole 211 communicates with the cavity 21 .
  • the first chip is an ultrasonic sensor chip, which is used to form an ultrasonic sensor.
  • a resonant cavity 3011 and a transducer 3012 are formed inside the ultrasonic sensor chip 301 .
  • the transducer 3012 is used to convert between electrical and mechanical energy.
  • the resonant cavity 3011 can increase the vibration amplitude of the ultrasonic sensor chip 301 and improve the conversion efficiency.
  • the front surface of the ultrasonic sensor chip 301 is the surface where the transducer 3012 is located, and the front and back surfaces of the ultrasonic sensor chip 301 are formed with second pads 31 .
  • the analog-to-digital conversion chip 302 and the digital signal processing chip 303 are used to process the sensing signal output by the ultrasonic sensor chip 301 ; the control chip 304 is used to control the transducer of the ultrasonic sensor chip 301 The 3012 vibrates, producing ultrasonic waves.
  • the ultrasonic sensor chip 301 and other peripheral chips are bonded to the circuit board 10 , and the first bonding pad 11 and the second bonding pad 31 are opposite to form a gap.
  • the first cavity 21 is formed in the dry film, when the first chip 30 is manufactured, it is not necessary to form the first cavity in the first chip 30a, which can save the process flow and thus save the cost , improve process efficiency.
  • the cover plate side the cover plate forms the cavity 21, and in some cases, a circuit structure needs to be formed on the cover plate to realize the interconnection of chips.
  • the circuit board can be used as a cover plate, and the electrical connection structure in the circuit board can also be used to realize the interconnection of the first chip on the side of the cover plate.
  • the interconnection of the first chip is all completed in the chip, and the interconnection between the first chip and other chips is completed by the circuit board without the aid of a circuit board.
  • the bonding layer does not have a cavity
  • the circuit board has a second cavity 18
  • the first chip is located above the second cavity 18
  • the second cavity 18 The cavity 18 serves as a working cavity of the first chip 30a.
  • the circuit board 10 includes a multi-layer board.
  • the multilayer board includes a non-wiring area 10 a for forming the second cavity 18 .
  • the non-wiring area 10 a is used to form the second cavity 18 .
  • the second cavity 18 is formed in the non-wiring area 10a of the circuit board 10. Therefore, in the manufacturing process of the circuit board 10, part or all of the non-wiring area 10a may not be part of the multi-layer board or all the multi-layer boards In the process of fabricating the circuit structure in the non-wiring area 10a, only the insulating material can be etched and the conductive material can be etched in the process of removing part or all of the multilayer board in the non-wiring area 10a, which reduces the difficulty of forming the cavity 18 accordingly. In other embodiments, when the cavity is formed in a circuit board with a partial thickness, the circuit structure can also be fabricated in the remaining layers at the bottom of the cavity.
  • the device wafer 100 is subsequently bonded on the circuit board 10, so that each first chip on the first device wafer 100 is bonded to the circuit board 10.
  • the second space The cavity 18 is used as the functional cavity of the first chip to be bonded. Therefore, when preparing the chip, there is no need to complete the preparation process of all functional cavities, which is beneficial to reduce the process complexity of preparing the chip and improve the chip manufacturing efficiency.
  • the step of forming the second cavity 18 in the circuit board 10 includes: removing part or all of the layers of the non-wiring area 10 a to form the second cavity 18 .
  • the second cavity 18 is taken as an example in the circuit board 10 having a partial thickness. Therefore, the second cavity 18 is formed by removing some layers of the board in the non-wiring area 10a.
  • a laser cutting process is used to remove some or all of the layers of the non-wiring area 10 a, and the second cavity 18 is formed in the circuit board 10 .
  • the second cavity 18 is used as a functional cavity of the first chip.
  • the bottom area of the second cavity 18 is based on the size of the first chip.
  • the depth of the second cavity 18 is determined according to the performance of the first chip.
  • the second cavity 18 is located in the circuit board 10 with a partial thickness, and is correspondingly formed in any one or both of the front and back surfaces the cavity 18.
  • the circuit board has a second cavity 18, the bonding layer has a first cavity 21, the second cavity and the first cavity are opposite and communicate with each other , the first chip is located above the first cavity.
  • the photolithographic bonding material 20 and the circuit board 10 under the first chip 31a have a through cavity.
  • the circuit board can be further etched along the patterned photolithographic bonding material layer 20 to form the circuit board 10 .
  • the second cavity 18, the first cavity 21 and the second cavity 18 as a whole serve as the upper cavity of the d-chip 301a.
  • the second cavity 18 may be formed in the circuit board 10 by patterning, and then the photolithographic bonding material may be formed on the surface of the circuit board 10 . By patterning, a first cavity 21 is formed. The first cavity 21 and the second cavity 18 are located opposite to each other, and pass through each other after bonding.
  • the difference between this embodiment and the first embodiment is that the circuit board 10 includes a groove (not numbered in the figure), and the chip can be accommodated in the groove.
  • a second chip 70 is embedded in the groove, and a surface of the second chip 70 has a third pad 71 , and the third pad 71 corresponds to the second pad 31 of the first chip 30 .
  • the first voids are relatively formed.
  • the formation process of forming the conductive bumps in the first gap is the same as the process of forming the conductive bumps between the first bonding pad and the second bonding pad, and the two are formed at the same time, which will not be repeated here.
  • a groove is formed in the circuit board, a first pad is formed at the bottom of the groove, and the first pad is recessed on the bottom surface of the groove; the first chip is bonded to the bottom surface of the groove.
  • a first chip 30 is embedded in the groove 101 , a first bonding pad 11 is formed at the bottom of the groove 101 , and a second bonding pad 31 of the first chip 30 is formed opposite to the first bonding pad 11 .
  • said gap The formation process of forming the conductive bump in the gap is the same as the process of forming the conductive bump between the first bonding pad and the second bonding pad, and the two are formed at the same time, which will not be repeated here.
  • a first cavity 21 may be formed in the photolithographic bonding material below the first chip 30 as an upper cavity of the first chip 30 .
  • only a single groove is formed on the front surface of the circuit board 10 and the first chip 30 is disposed in the groove 101 as an example.
  • single or multiple grooves may be formed on the front and/or back of the circuit board 10 , and the grooves may be formed by etching the circuit board 10 .
  • One or more radio frequency chips may be arranged in each groove, and the depth of the groove may be greater than, equal to or less than the thickness of the radio frequency chip.
  • the thickness of the entire RF front-end module can be reduced by arranging the RF chip with a larger thickness in the groove.
  • the first chip 30 is bonded to the bottom of the groove and the top surface of the circuit board 10 . This situation is applicable when the thickness of the first chip located in the groove is relatively thick, while the thickness of the chip located on the top of the circuit board is relatively thin, which can be used to reduce the overall thickness of the formed packaged device.
  • the difference between this embodiment and the first embodiment is that the fourth pad is formed on the back of the circuit board; a second conductive pad is formed on the fourth pad on the back of the circuit board through an electroplating process bumps; and/or, bonding at least one first chip to the back of the circuit board.
  • the circuit board 10 includes opposite front and back sides, the first pad 11 is formed on the front side of the circuit board, the back side of the circuit board 10 further includes a fourth pad 16 , and the first pad 16 is formed on the front side of the circuit board.
  • a pad 16 is located on the interconnect structure of the bottom board and is electrically connected to the corresponding interconnect structure.
  • a second conductive bump 80 is formed on the fourth pad 11 .
  • the exposed area of the fourth pad is 5-200 square microns. Within this range, the pad can be in sufficient contact with the electroplating solution to avoid insufficient contact between the pad and the electroplating solution and affect the conductive bumps and pads. For example, the contact area is too small to affect the resistance, or the inability to contact causes poor electrical contact.
  • the second organic medium layer 17 can be a photolithographic bonding material, in which case it is not necessary to separately form a photolithographic bonding material between the pasted chip and the circuit board. Engraved bonding material to save process.
  • the second conductive bumps are formed on the bottom layer of the circuit board, that is, the backside, it is usually necessary to form a solder resist layer on the backside. There is no soldering phenomenon in the solder mask area around the bump.
  • the first chip is bonded only on one side of the circuit board, that is, the top surface.
  • the first chip may be bonded on the front side of the circuit board.
  • the first chip is also bonded on the back side, and the second pad on the back side of the first chip and the fourth pad on the back side of the circuit board are electrically connected through the second conductive bumps 80 .
  • the electroplating process formed by the first conductive bumps 40 and the second conductive bumps 80 may be performed simultaneously or separately; the first chip bonding process on the front side of the circuit board may also be performed first, followed by the electroplating process, followed by the The first die bonding process on the back of the circuit board, followed by the electroplating process.
  • the bottom layer of the circuit board can be the same as the prior art, and a solder resist layer and a solder resist are provided on the bottom surface; since in the present invention, the electrical connection between the first chip and the circuit board does not need to be realized by welding, so the bottom surface may not be provided with Solder mask layer (green oil), or no solder flux layer.
  • the bottom layer may be a second organic dielectric layer 17 (refer to FIG. 16 ) with photolithographic bonding properties, and the first pads 11 are buried in the second organic dielectric layer 17 and partially exposed.
  • the second organic medium layer with a certain thickness can be selected according to the needs, so as to facilitate the subsequent bonding of the first chip to the circuit board without additional bonding layers. In this way, processes can be saved, thereby improving the formation efficiency of the circuit board.
  • the bottom layer can also be a second inorganic medium layer.
  • the bottom layer is an inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is smaller, and the electroplating solution is more likely to enter the first gap and improve the conductivity.
  • a groove may also be formed on the back of the circuit board 10 , the first chip on the back of the circuit board 10 may be fully or partially disposed in the groove, and the second pad of the first chip may be disposed in the groove.
  • a gap is formed opposite to the first pad at the bottom of the groove, and a first conductive bump is formed in the gap while electroplating.
  • a plurality of first chips may be bonded on the circuit board 10 at the same time, and subsequently, the respective first package structures may be divided by cutting the circuit board. In this way, packaging efficiency can be improved.
  • the difference between the present embodiment and the previous embodiments is that a third chip is stacked on the first chip, and the first chip and the third chip are electrically connected by plated third conductive bumps.
  • a fifth bonding pad 32 is formed on the other side of the first chip 30, and the fifth bonding pad and the second bonding pad are respectively located on the opposite surfaces of the first chip.
  • a third chip 33 can be bonded on the second chip 30, and the bonding can be made of a photolithographic bonding material 20, such as a dry film; the third chip 33 contains a sixth pad 34, so A second space is formed between the fifth bonding pad and the sixth bonding pad; and a third conductive bump 35 is formed in the second space through an electroplating process.
  • the process of forming the third conductive bumps 35 may be the same as the forming process of forming the first conductive bumps 40 .
  • the first chip is first bonded to the circuit board, and then the third chip is bonded to the first chip, and then an electroplating process is performed to form the first conductive bumps 40 and the third conductive bumps 34; in other implementations
  • the first chip and the third chip that are bonded together can be bonded together on the circuit board; and then the electroplating process is performed.
  • the conductive bumps can also be formed multiple times, for example, the first conductive bumps between the first chip and the first chip and the third conductive bumps between the chips and the circuit board are divided into two parts secondary formation.
  • the second bonding pad 31 and the fifth bonding pad 32 are interconnected by TSV, but in this embodiment, it is not limited to this situation, and the second bonding pad 31 and the fifth bonding pad 32 may be connected
  • the electrical connection is achieved by other interconnection methods, for example, the electrical connection between the second pad 31 and the corresponding fifth pad 32 is achieved by interconnecting wires and plugs.
  • only part of the first chips are stacked; or, there are stacked first chips on both the front and the back of the circuit board.
  • Embodiments 1 to 6 of the present invention describe various specific situations, wherein various situations described in Embodiments 1 to 6 can be combined to form new embodiments as required.
  • the present invention will not describe them one by one, and those skilled in the art can obtain specific embodiments that are different from the situations listed in Embodiments 1 to 6 according to the teachings of the present invention.
  • the first chip is an image sensor chip, which is used to form a camera module, and the first chip includes an image sensor chip and a peripheral chip.
  • the image sensor chip may include at least one of a CCS image sensor chip and an SSD image sensor chip, and an optical sensor array 3011 is formed on the front side.
  • the image processing chip may include: a reading circuit chip, an analog signal processing chip, an analog-to-digital conversion chip, and an integration of at least one or several of various functional chips, such as a digital logic chip, for processing the image.
  • the optical sensing signal output by the sensing chip 301 is processed to form an image signal.
  • multiple functional chip circuits are integrated into one image sensor chip 301 .
  • multiple image processing chips 301 may be included, and each image processing chip includes one or more functional circuits, such as an analog-to-digital conversion chip, an analog signal processing chip, and the like.
  • some circuits may also be integrated in the image sensor chip 301, such as a reading circuit and the like.
  • the camera may further include more than two image sensor chips 301 and multiple image processing chips 302 .
  • the camera may further include more than two image sensor chips 301 and multiple image processing chips 302 .
  • only a single image sensor chip 301 and a single image processing chip 302 are shown as examples.
  • a memory chip 303 and a driving chip 304 are also provided, which are used as data buffers for the light sensing signals of the image sensing chip 301, and the speed of data processing.
  • the memory chip 303 may be a DRAM memory chip, which has high data transmission bandwidth and efficiency.
  • the driving chip is used to drive the lens of the camera to move, so as to adjust the focal length of the camera.
  • the image sensor chip 301 , the image processing chip 302 , the memory chip 303 and the driving chip 304 are bonded to the circuit board 10 , and the first pad 11 and the second pad 31 are opposite to form a gap.
  • An optical lens 50 is provided, and the optical lens 50 includes a lens 51 and a motor 52 connected to the lens; the optical lens 50 is bonded to the circuit board 10 through a support 53, and the support 53 surrounds the
  • the image sensor chip 301 is disposed, and the front surface of the image sensor chip 301 faces the lens 51 .
  • a filter 54 is fixed on the inner side of the support member 51 , and the filter 54 is located between the lens 51 and the image sensor chip 301 .
  • the support member 53 may be cylindrical, and is bonded to the periphery of the image sensor chip 301 by adhesive or photolithographic bonding material, forming a cavity between the support member 53 and the circuit board 10 .
  • the sensor chip 301 is located in the cavity.
  • the motor 52 is fixed between the support and the lens 51, and is used to drive the lens 51 to move and adjust the focal length of the camera.
  • the motor 52 may be a driving motor such as a voice coil motor, a stepping motor, or the like.
  • the motor 52 is connected to the driving chip 304 through the circuit board 10 , and the motor 52 is driven by the driving chip 304 .
  • the various chips and components in the camera are electrically connected through the circuit board 10, the image sensor chip 301 is connected to the memory chip 303, the graphics processing chip 302 is connected to the memory chip 303, the driver Chip 304 is connected to the motor 52 .
  • the connection relationship in the circuit board 10 in FIG. 21 is only for illustration, and does not represent the actual connection relationship between chips.
  • the filter 54 is directly bonded to the surface of the image sensor chip 301 .
  • the filter 54 is first bonded to the image sensor chip 301 , and then the image sensor chip 301 is bonded to the surface of the circuit board 10 .
  • a bonding layer can be formed on the front side of the image sensor chip 301, for example, the bonding material 20 can be photoetched; then the bonding layer is patterned to form a cavity 21, and then the filter is bonded on the cavity 21, so that A sealed cavity is formed between the image sensor chip 301 , the filter 54 and the photolithographic bonding material 20 , and the sealed cavity can protect the sensing surface of the image sensor chip 301 from being affected by the external environment.
  • the bonding layer such as the photolithographic bonding material 20
  • the photolithographic bonding material 20 on the chip can be patterned to form the cavity 21, and then the filter The sheet 54 is bonded to the image sensor chip 301 .
  • the image sensor chip 301 , the image processing chip 302 , the storage chip 303 and the driver chip 304 can be located on the front and back of the circuit board 10 and are reasonably arranged according to their functions.
  • a groove may also be formed in the circuit board 10, the image sensor chip 301 is located in the groove, the filter is bonded on the surface of the circuit board 10, and the optical lens 50 is disposed above the filter.
  • a flexible circuit board 1000 is soldered on the back of the circuit board 10 .
  • the peripheral chips are bonded to the front side of the circuit board 10
  • the flexible circuit board 1000 is bonded to the back side of the circuit board 100 .
  • the surface of the flexible circuit board 1000 has solder pads 1001, and the flexible circuit board 1000 is bonded to the back of the circuit board 10 through a photolithographic bonding material 20.
  • the solder pads 1001 on the surface of the flexible circuit board 1000 are connected to the circuit A space is formed between the first pads on the backside of the board 10, and then first conductive bumps 40 are formed in the space by electroplating.
  • the circuit board 10 has opposite fronts and backs, a first groove 102 is formed on the front of the circuit board 10 , a second groove 103 is formed on the back, and a first groove 102 is formed inside. and the light-transmitting hole 104 of the second groove 103; the front surface of the image sensor chip 301 faces the bottom of the second groove 103, and is bonded to the bottom of the second groove 103; the filter 54 Bonded to the bottom surface of the first groove 102 , the light-transmitting hole 104 is located on the light-transmitting path between the filter 54 and the front surface of the image sensor chip 301 .
  • the optical lens 50 is fixed on the surface of the circuit board 10 by a support member 53 , and the filter 54 is located under the lens 51 .
  • the optical filter 54 can also be bonded to the circuit board 10 on the top edge of the first groove 102 .
  • the front side of the circuit board 10 is the light entrance side, so the front side of the image sensor chip 301 faces the second groove
  • the bottom of 103 can directly use the front surface of the image sensor chip 301 as a bonding surface, and the first conductive bumps formed by electroplating between the second pads on the front and the pads at the bottom of the second groove 103
  • it is not necessary to form bonding pads on the backside of the image sensor chip 301 so that the structure of the image sensor chip 301 can be simplified.
  • the first conductive bumps 40 and the second conductive bumps 80 at each position can be simultaneously formed by electroplating. In other embodiments, bonding and electroplating processes may also be performed on the chip and the flexible circuit board, respectively.
  • the flexible circuit board 1000 may also be bonded to the front surface of the circuit board 10 .
  • the difference between this embodiment and the first embodiment is that the state of the first chip bonding is different.
  • the plurality of first chips are located in the first device wafer, and are bonded to the circuit board in the state of wafers.
  • the step of providing a plurality of first chips 30 includes: providing a first device wafer 100 , a plurality of first chips 30 are formed in the first device wafer 100 , and one surface of the first chips 30 is A second bonding pad 31 is formed, and the second bonding pad 31 is recessed on the surface of the first chip 30 .
  • This embodiment provides a board-level system-in-package method, including: providing a circuit board as a carrier board, a plurality of first bonding pads are formed on the surface of the circuit board, and the first bonding pads are recessed on the surface of the circuit board A first device wafer is provided, a plurality of first chips are formed in the first device wafer, a second pad is formed on one surface of the first chip, and the second pad is recessed in the The surface of the first chip; the first device wafer is bonded to the circuit board, and the first pad and the second pad are opposite to form a first gap; through the electroplating process, on the first A first conductive bump is formed in the gap, and the first conductive bump is electrically connected to the first pad and the second pad; after the first conductive bump is formed, the first device wafer is crystallized Circular cutting to separate the first chips from each other.
  • a circuit board 10 is provided; a first device wafer 100 is provided, and a plurality of first chips 30 are formed in the first device wafer 100 , and a second pad 31 is formed on one surface of the first chips 30 , the second pad 31 is recessed on the surface of the first chip 30 .
  • the circuit board 10 is used for supporting and fixing a plurality of different circuit elements, and also for realizing the electrical connection between the circuit elements.
  • the circuit board 10 is used as a carrier for the subsequent packaging process, that is to say, the subsequent packaging process needs to be completed in a process environment suitable for the circuit board 10, and the subsequent packaging process needs to be used for the circuit board. 10 process equipment and production lines.
  • the encapsulation reduces the requirements on the production environment, for example, the subsequent encapsulation process may not be performed in a clean room, and the encapsulation process may be performed in the environment of a common workshop.
  • the first device wafer 100 is used for bonding with the circuit board 10 .
  • the circuit board 10 and the first device wafer 100 are both circular.
  • the circular circuit board 10 can be applied to the equipment in the semiconductor front-end process, and has strong compatibility with the equipment and the process.
  • the circuit board may also be a polygon, and the polygon includes a square, a pentagon, a hexagon, an octagon, and the like.
  • the first device wafer 100 is bonded to the circuit board 10 , and the first bonding pads 11 and the second bonding pads 31 are opposite to form a first gap 32 .
  • the first device wafer 100 is bonded to the circuit board 10 through a bonding layer, and the bonding layer is disposed away from the first pad 11 and the second pad 31 .
  • first conductive bumps 40 are formed in the first voids 32 , and the first conductive bumps 40 are electrically connected to the first pads 11 and the second pads 31 .
  • wafer dicing is performed on the first device wafer 100 to separate the first chips 30 from each other.
  • the circuit board 10 is used as a carrier board. Therefore, the circuit board 10 provides a process platform for wafer cutting. Specifically, the cutting area 100a of the first device wafer 100 is cut to form a plurality of structures to be packaged.
  • blade saw or laser cutting is used to cut the cutting area of the first device wafer 100 along the cutting line.
  • the circuit board 10 is used as a carrier board, and the cutting process needs to use the process machine and production line for preparing the circuit board 10, and no need It is performed in a clean room, and the environment of an ordinary production workshop is sufficient, which is beneficial to simplify the process steps of cutting the first device wafer 100 and reduce the production cost.
  • the first device wafer 100 is integrally bonded to the circuit board, and finally the first device wafer 100 is cut to achieve the effect of dividing the chips from each other.
  • the scheme of bonding the chips on the circuit board step by step achieves the effect of wafer-level packaging, further simplifies the process flow, and improves packaging efficiency.
  • the board-level system-in-package method further includes: after wafer dicing the first device wafer 100 , forming a plastic sealing layer 50 to cover the first chip 30 and the circuit board 10 .
  • the plastic sealing layer 50 is used to realize the packaging integration of the first chip 30 and the circuit board 10 .
  • the difference between the board-level system-in-package method of the ninth embodiment and the eighth embodiment is that a cavity is provided under the first chip, and the cavity is used as a working cavity of the first chip.
  • the settings of the cavity are all applicable to those described in the fourth embodiment.
  • some of the first chips 30a need to have a working cavity, and a first cavity 21 may be formed in the photolithographic bonding material 20 as a working cavity of the first chip 30a.
  • the first chip 30a may contain a third cavity 3011, and the first chip 30a may be an FBAR filter of a bulk acoustic wave filter.
  • the first device wafer and the circuit board are bonded through a bonding layer, the bonding layer does not have a cavity, the circuit board has a second cavity 18, and the second cavity 18 is formed in the circuit board.
  • a chip is located above the second cavity, and the second cavity 18 serves as the working cavity of the first chip 30a.
  • the first device wafer and the circuit board are bonded through a bonding layer, the circuit board has a second cavity 18 therein, and the bonding layer has a first cavity 21 therein , the second cavity is opposite to and communicated with the first cavity, and the first chip is located above the first cavity.
  • the difference between this embodiment and the foregoing eighth embodiment is that the first device wafer 100 is bonded on two opposite surfaces of the circuit board 10 .
  • the double-sided arrangement of the first chip in the fifth embodiment is applicable to this embodiment.
  • the circuit board 10 includes opposite front and back surfaces, and the first pads 11 are formed on both the front and the back;
  • the first conductive bumps 40 are formed by an electroplating process;
  • the second conductive bumps 80 are formed on the first pads on the back of the circuit board 10 by an electroplating process;
  • the first device wafer 100 containing at least one first chip 30 is bonded on the back of the circuit board.
  • the second conductive bumps 80 are also formed on the second surface of the circuit board 10 .
  • the first conductive bumps may be formed in the first voids on the side of the first surface of the circuit board, and the first conductive bumps may be formed in the first voids on the first surface of the circuit board, and the first conductive bumps may be formed on the first surface of the circuit board through two electroplating processes in different steps.
  • a first conductive bump is formed in the first void on one side of the two surfaces.
  • a plastic encapsulation layer or protective layer covering the circuit board, the first chip and the first conductive bumps can be formed on the side where the first conductive bumps have been formed, Covering the formed first conductive bumps prevents the first conductive bumps on the surface from being affected during the electroplating process performed on the other surface of the circuit board.
  • the wafer 100 is diced on the first device wafer to separate the first chips 30 from each other.
  • the second conductive bumps 80 may be formed only on the second surface of the circuit board 10 . After the first conductive bumps 40 and the second conductive bumps 80 are formed, the wafer 100 is diced on the first device wafer to separate the first chips 30 from each other.
  • the packaging method realizes three-dimensional packaging (3D package), that is, a second device wafer is bonded on the first device wafer, and the second device wafer is inside the second device wafer.
  • 3D package three-dimensional packaging
  • the stacking arrangements of the first chips in the sixth embodiment are all applicable to this embodiment.
  • the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, and the second pad 31 is located on one side of the third surface 301 and is recessed in The third surface 301 , the first chip 30 further includes a fifth bonding pad 36 , the fifth bonding pad 36 is located on one side of the fourth surface 302 and is recessed in the fourth surface 302 , between the fifth bonding pad 36 and the second bonding pad 31 Make electrical connections.
  • a via interconnect structure 33 is formed in the first chip 30 , and an end of the via interconnect structure 34 facing the third surface 301 is connected to the second pad 31 , and the via interconnect structure 34 is connected to the second pad 31 .
  • One end of the via interconnect structure 33 facing the fourth surface 302 is connected to the fifth pad 36 .
  • the through hole interconnection structure 33 is a Through Silicon Via (TSV) interconnection structure.
  • the fourth surface 302 is formed with a third organic medium layer 37 or a third inorganic medium layer
  • the fifth pad 36 is buried in the third organic medium layer 37 or the third inorganic medium layer and partially exposed.
  • the third organic medium layer 37 and the third inorganic medium layer reference may be made to the descriptions of the first organic medium layer and the second inorganic medium layer in the foregoing embodiments, which are not repeated here.
  • the packaging method further includes: providing a second device wafer 200 , a plurality of third chips 72 are formed in the second device wafer 200 , and sixth bonding pads are formed on any surface of the third chips 72 34 , the sixth bonding pad 34 is recessed on the surface of the second chip 70 .
  • the second device wafer 200 is used for bonding with the first device wafer 100 to achieve a specific function.
  • the third chip 72 includes a dicing road (not marked), the area where the dicing road is located is the dicing area 30a, the dicing road of the second device wafer 200 and the first device wafer 100 are aligned up and down, and the dicing road is the first device wafer 100. The position where the two device wafers 200 and the first device wafer 100 are diced together.
  • the third chip 72 and the first chip 30 are bonded together, and the first chip 30 is bonded on the circuit board 10 , so that the third chip 72 and the first chip 30 are perpendicular to the surface of the circuit board 10 . Stacked in the direction of the corresponding three-dimensional packaging (3D package).
  • the second device wafer 200 is bonded to the first device wafer 100 , so as to realize the third chip 72 In the process of bonding with the first chip 30, the circuit board 10 can play the role of supporting the carrier board.
  • the first device wafer may also be bonded to the circuit board after the second device wafer is bonded to the first device wafer.
  • the third chip 72 and the first chip 30 are bonded together, and the fifth bonding pad 36 and the sixth bonding pad 34 are opposite to form a third gap, and the third gap 35 is in the third gap 35 .
  • Third conductive bumps 75 are formed.
  • the method further includes: after the first device wafer 100, the second device wafer 200 and the circuit board 10 are bonded to each other, wafer cutting is performed on the second device wafer 200 and the first device wafer 100, The first chips 30 are separated from each other, and the third chips 72 are also separated from each other.
  • the dicing lanes of the second device wafer 200 and the first device wafer 100 are aligned up and down, and the third chips 72 are separated from each other by one dicing, and the first chips 30 are also separated from each other at the same time.
  • the process flow is simplified and the packaging efficiency is improved.
  • circuit board is cut from the side of the circuit board facing away from the first chip to form a cutting groove penetrating the circuit board.
  • An embodiment of the present invention provides a board-level system-in-package method, including: providing a circuit board, the circuit board having a first surface and a second surface, the circuit board including a bonding area and a cut surrounding the bonding area In the bonding area, a plurality of first pads are formed on the surface of the circuit board, and the first pads are recessed on the first surface of the circuit board; a first device wafer is provided, and the A plurality of first chips are formed in the first device wafer, a second pad is formed on one surface of the first chip, and the second pad is recessed on the surface of the first chip; The first device wafer is bonded on the first surface of the circuit board, the first chip is located above the bonding area, and the first bonding pad and the second bonding pad are opposite to form a first gap; electroplating process, forming a first conductive bump in the first gap, the first conductive bump electrically connecting the first pad and the second pad; after forming the first conductive bump, from the On the side of the second
  • Cutting the circuit board to form the cutting groove in this embodiment is also applicable to the structures before cutting in the eighth, ninth, and tenth embodiments.
  • the first device wafer 100 is used as a carrier to cut the circuit board 10. Since the first device wafer 100 needs to be processed in a clean room, the cutting process of the circuit board 10 also needs to be performed in a clean room. workshop, and is completed using equipment and production lines suitable for the first device wafer 100 .
  • the cutting area 10b of the circuit board 10 is cut by blade saw or laser cutting.
  • the blade cutting process includes: attaching the side of the first device wafer 100 away from the circuit board on the adhesive film layer, cutting the circuit board 10 along the cutting area 10b, and degrading the circuit board 10 after cutting.
  • the adhesion between the adhesive film layer and the first device wafer 100 is improved, thereby removing the adhesive film layer.
  • ultraviolet light is used to irradiate the adhesive film layer to reduce the viscosity between the adhesive film layer and the first device wafer 100 and remove the adhesive film layer.
  • an encapsulation layer may be formed on the first device wafer 100 shown, or the first device wafer 100 shown may be temporarily bonded to the carrier substrate, and then The circuit board 10 is cut to improve the strength of the first device wafer 100, reduce the influence of the cutting process on the first device wafer 100, and improve the yield.
  • the cutting area 10b of the circuit board 10 is cut, so as to realize the effect of dividing the bonding areas 10a of the circuit board 10 from each other. Compared with the solution of bonding on the chips one by one, the effect of wafer-level packaging is achieved, the process flow is simplified, and the packaging efficiency is improved.
  • Embodiments 8 to 11 of the present invention describe various specific situations, wherein various situations described in Embodiments 7 to 11 can be combined to form new embodiments as required. In the present invention, one by one is not described, and those skilled in the art can obtain specific embodiments different from the situations listed in Embodiment 7 to Embodiment 11 according to the teachings of the present invention.
  • the thirteenth embodiment provides a board-level system-level packaging structure, including:
  • the circuit board 10 has a surface, the surface is formed with a plurality of first pads 11, the first pads 11 are recessed on the surface of the circuit board; the surface can be the front or the back, or It includes the back and front;
  • first chips 30 one surface of the first chips 30 is formed with a second bonding pad 31, the second bonding pad 31 is recessed on the surface of the first chip;
  • the first chip 30 and the circuit board 10 are bonded together, the first pad and the second pad are opposite to form a first gap, and a first conductive electroplating is formed in the first gap.
  • the bumps 40 are used to electrically connect the first pads 11 and the second pads 31 .
  • the first chip 30 and the circuit board 10 are bonded together by a photolithographic bonding material 20, and the photolithographic bonding material 20 is arranged to avoid the bonding pads (the first bonding pad, the second bonding pad) , covering the peripheral area of the first conductive bump 40 .
  • the first bonding pad and the second bonding pad include a facing portion and a staggered portion, the area of the facing portion is at least half of the area of the first bonding pad or the second bonding pad, and the first gap is Height is 5-200 microns.
  • the circuit board 10 includes: at least one layer of boards, each layer of board at least includes a substrate, an interconnection structure on the surface of the substrate, and the first pads on the interconnection structure on the top layer are electrically connected to the interconnection structure. connect.
  • the circuit board 10 is a three-layer board.
  • the first chip bonded on the circuit board includes a connection chip 30b, and the top surface of the connection chip 30b can be formed with conductive bumps 30b1 through an electroplating process.
  • the cavity may be located in the bonding layer, may also be located in the circuit board, and may also penetrate through the bonding layer and part of the circuit board.
  • the bonding layer of the package structure is formed with a first cavity, and at least part of the first chip 30 is bonded on the first cavity 21 .
  • some of the first chips 30 need to have cavities below, and some of the first chips 30 do not need cavities below.
  • a first cavity may also be provided under the first chip 30 on the entire PCB.
  • the first chip may or may not contain the second cavity, that is, the first chip may be a chip that requires cavities on both the upper and lower sides, such as a bulk acoustic wave thin film resonator.
  • the packaging structure is a radio frequency module, and the first chip includes: a radio frequency chip, which includes at least one filter chip, and the other radio frequency chips include at least one function of signal amplification, signal reception, and signal tuning.
  • the first chip may also be a chip that only needs to have an upper cavity or a lower cavity, such as a surface acoustic wave resonator.
  • the first chip 30a may not contain the second cavity, for example, referring to FIG. 9, it may be a surface acoustic wave filter including a resonant structure 3013 (including interdigital electrodes and a piezoelectric film), for example, referring to FIG.
  • the resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes), a first cavity 21 on one side of the resonant structure, and a Bragg reflection layer 3014 on the other side.
  • the first chip 30c includes a cavity 21 .
  • the cavity 21 needs a cavity that communicates with the external environment, such as a microphone sensor, and the cavity above the cavity needs to communicate with the outside world.
  • the circuit board has a through hole 211 , and the through hole 211 communicates with the cavity 21 .
  • the package structure is an ultrasonic sensor
  • the first chip includes an ultrasonic sensor chip and a peripheral chip
  • the peripheral chip includes a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, and a digital logic chip. At least one of a chip and a control chip.
  • the bonding layer does not have a cavity
  • the circuit board has a second cavity 18
  • the first chip is located above the second cavity
  • the second cavity 18 serves as the first chip 30 a working chamber.
  • the circuit board has a second cavity 18
  • the bonding layer has a first cavity 21, the second cavity and the first cavity are opposite and communicate with each other, and the first chip is located in above the first cavity.
  • the circuit board 10 is formed with a groove (not numbered in the figure), a second chip 70 is embedded in the groove, and a surface of the second chip 70 has a third pad 71 , and the third welding Conductive bumps 80 are formed between the pads and the second pads 31 of the corresponding first chips 30 .
  • a groove is formed in the circuit board 10 , a first pad 13 is formed at the bottom of the groove, and the first pad 13 is recessed on the bottom surface of the groove; the first chip 30 is keyed fit the bottom surface of the groove.
  • the first chip 30 may be bonded to the bottom surface of the groove and the surface of the circuit board.
  • the package structure may further include fourth solder pads 16 .
  • the fourth solder pads 16 are located on the underlying interconnect structures and are electrically connected to the corresponding interconnect structures. During the electroplating process, the fourth solder pads 16 are A second conductive bump 80 is formed on the fourth pad.
  • the chips on the backside can be soldered on the second conductive bumps 80 through a soldering process.
  • the circuit board has a first chip 30 on both the back and front sides, and also has a first conductive bump 40 and a second conductive bump 80 formed by an electroplating process between the first chip 30 and the circuit board.
  • the third chips 32 are stacked on the first chips 30 , and the third chips 32 may be stacked on all the first chips 30 , or the third chips 32 may be stacked on some of the first chips 30 .
  • the third chip and the first chip are connected by bonding, for example, a photolithographic bonding material, a dry film.
  • the stacked first chips 30 and the third chips 32 are electrically connected through third conductive bumps 35 .
  • the package structure is a camera module
  • the first chip includes: an image sensor chip and a peripheral chip
  • the image sensor chip includes: at least one of a CMOS sensor chip or a CCD sensor chip
  • the peripheral chip includes: a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic circuit chip or an integration of at least one or several of the driver chips.
  • a first organic dielectric layer 13 having photolithographic bonding characteristics is formed on the front side of the circuit board 10 , and the first pads 11 are embedded in the first organic dielectric layer 13 ; and/or, the back side is formed with
  • the first organic medium layer 13 may be replaced by a first inorganic medium layer; the second organic medium layer 17 may be replaced by a second inorganic medium layer.
  • the plurality of first chips are located in the first device wafer 100, and the first device wafer is bonded to the circuit board, thereby realizing the bonding of the first chips and the circuit board.
  • the first device wafer 100 has a dicing groove to separate the first chips 30 from each other.
  • the first device wafer 100 and the circuit board are bonded through a bonding layer, and the bonding layer has a first cavity 21 therein, and the first chip 30 is located on the first cavity.
  • the bottom of the first chip in the first device wafer 100 has a working cavity
  • the circuit board has a second cavity 18 as the working cavity of the first chip.
  • the bottom of the first chip located in the first device wafer 100 has a working cavity
  • the second cavity 18 in the circuit board communicates with the first cavity 21 in the bonding layer, which together serve as the first cavity of the first chip. working cavity.
  • the first conductive bumps 40 are formed on the first solder pads 11 on the front side of the circuit board 10 by an electroplating process; the second conductive bumps 80 are formed on the first solder pads on the backside of the circuit board 10 by an electroplating process.
  • the backside of the circuit board 10 may also have only the second conductive bumps.
  • a second device wafer is bonded on the first device wafer, and the second device wafer also has a plurality of first chips; after the first device wafer and the second device wafer are bonded, the The first chips in the two device wafers are stacked above the first chips in the first device wafer to realize stacking of the chips.
  • the plurality of first chips are located in the first device wafer 100, and the circuit board is formed with cutting grooves penetrating the circuit board.
  • the circuit board 10 includes a bonding area 10a and a cutting area 10b surrounding the bonding area 10a.
  • a plurality of first solder pads 11 are formed on the surface of the circuit board 10, and the first solder pads 11 are recessed. the surface of the circuit board 10 .
  • the cutting groove is located in the cutting area 10b, and the projection of the first chip on the circuit board is located in the bonding area 10a.
  • the fourteenth embodiment provides a circuit board 10 , including: at least one layer of boards 12 , each layer of board 12 at least includes a substrate, an interconnection structure located on the surface of the substrate, and the first pads are located on the top layer.
  • the interconnection structure is electrically connected to the interconnection structure; a first organic dielectric layer with photolithographic bonding characteristics is formed on the front surface of the circuit board, and the first pad 11 is buried in the first organic dielectric layer 13.
  • the first organic medium layer may be a first inorganic medium layer, and for specific advantages, please refer to the relevant description in the first embodiment.
  • the circuit board 10 is a printed circuit board, that is, a PCB board.
  • the circuit board 10 can be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc. Specifically, the number of layers of the circuit board 10 can be determined according to actual needs.
  • the circuit board 10 is a three-layer board, and each layer of the board includes: an interconnection structure located on the surface of the substrate, and an interconnection plug electrically connected to the interconnection structure; the interconnection plug includes through holes and through-hole surface plating There is a conductive layer and is filled with insulating resin; the interconnection structure may include interconnection lines and interconnection pads.
  • a conductive resin can also be filled in the interconnect plug to save the process of forming the conductive layer.
  • it can also be determined according to actual requirements whether each layer of the board includes interconnection plugs and interconnection structures, and there may be only interconnection structures without interconnection plugs.
  • a fourth solder pad 16 is formed on the backside of the PCB board (referring to FIG. 7 and FIG. 8 and Embodiment 5 in conjunction), the fourth solder pad is located on the interconnect structure on the bottom layer of the circuit board and is connected to the corresponding interconnection
  • the structure is electrically connected, a second organic medium layer 17 with photolithographic bonding characteristics is formed on the back surface, and a fourth pad is buried in the second organic medium layer.
  • the second organic medium layer 17 may be replaced with a second inorganic medium layer.
  • this embodiment further provides a method for forming a circuit board, including:
  • each layer of board 12 at least includes a substrate and an interconnection structure 14 located on the surface of the substrate; in this embodiment, a three-layer board is formed, and the formation method of each layer of board includes providing a substrate, Interconnection plugs 15 are formed in the substrate, and interconnection structures 14 are formed on the upper and lower sides of the substrate.
  • the interconnection structures may include interconnection lines and interconnection pads on the interconnection plugs.
  • the interconnect plug includes a through hole and a conductive structure located in the through hole, the conductive structure may be a conductive layer located on the surface of the through hole, and the through hole may be filled with a resin material; in other embodiments, the interconnect plug It may include a through hole and a conductive resin in the through hole, and the conductive resin plays the role of conducting electricity and filling the through hole at the same time, saving process.
  • first pads 11 are formed on the top board 12, and the first pads are electrically connected to the interconnect structure on the top board; after the bottom board is formed, on the bottom board
  • the fourth solder pad 16 is formed; if the backside of the circuit board does not need to be electrically connected, the fourth solder pad need not be formed.
  • a first organic medium layer 13 having photolithographic bonding properties is formed on the top plate, and a second organic medium layer 17 having photolithographic bonding properties is formed on the bottom plate.
  • the organic medium layer can be selected as a dry film, and its formation method can refer to the relevant description in the first embodiment.
  • first organic medium layer and the second organic medium layer reference may be made to the relevant descriptions in the above embodiments.
  • the first organic medium layer can be replaced with a first inorganic medium layer
  • the second organic medium layer needs to be replaced with a second inorganic medium layer
  • the materials of the first inorganic medium layer and the second inorganic medium layer can be selected from silicon oxide, nitride Inorganic dielectric materials such as silicon and silicon oxynitride.
  • the inorganic dielectric layer is formed by means of deposition.
  • openings are formed in the first organic dielectric layer 13 and the second organic dielectric layer 17 to expose the first pads 11 and the fourth pads 16 .
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

Abstract

A board-level system-level packaging method and structure, and a circuit board forming method and structure. The packaging method comprises: providing a circuit board, which has a front face and a back face, a plurality of first pads being formed on the front face, and the first pads being recessed in the front face; providing a plurality of first chips, second pads being formed on one surface of the first chips, and the second pads being recessed in the surface; bonding the first chips to the circuit board, and the first pads and the second pads oppositely enclosing a first gap; and forming a first conductive bump in the first gap by means of an electroplating process, so as to electrically connect the first pads and the second pads. Compared with a traditional packaging process, the process flow is simple, and the packaging efficiency is high. The electrical connection between each chip and the circuit board is formed by means of the electroplating process, and compared with a traditional way of separately welding each chip to electrically connect same to a circuit board, the packaging efficiency is greatly improved. The electroplating process is compatible with a process of early-stage packaging, and a traditional chip manufacturing process or a wafer-level packaging process can be used to implement a board-level system-level packaging process.

Description

一种板级系统级封装方法、结构、电路板及形成方法A board-level system-level packaging method, structure, circuit board and forming method 技术领域technical field
本发明涉及半导体器件制造领域，尤其涉及板级的系统级封装方法、结构、电路板及形成方法。The invention relates to the field of semiconductor device manufacturing, in particular to a board-level system-level packaging method, structure, circuit board and forming method.
背景技术Background technique
系统级封装采用任何组合，将多个具有不同功能和采用不同工艺制备的有源元/器件、无源元/器件、MEMS器件、分立的KGD(Known Good Die)诸如光电芯片、生物芯片等，在三维(X方向、Y方向和Z方向)集成组装成为具有多层器件结构，并且可以提供多种功能的单个标准封装件，形成一个系统或者子系统。System-in-package uses any combination to combine multiple active components/devices, passive components/devices, MEMS devices, discrete KGD (Known Good Die) with different functions and prepared by different processes, such as optoelectronic chips, biochips, etc., It is integrated and assembled in three dimensions (X direction, Y direction and Z direction) into a single standard package with a multi-layer device structure and can provide multiple functions to form a system or subsystem.
倒装芯片(FC，Flip-Chip)焊接为目前比较常用的一种系统级封装方法。该系统级封装的方法包括：提供PCB电路板，其中PCB电路板上形成有按一定要求排列的焊球(利用植球工艺形成)；在电路板上浸蘸助焊剂，然后将芯片倒装贴片在电路板上；利用回流焊工艺将芯片上的焊垫(pad)与电路板上的焊球进行焊接后电连接；之后，在芯片底部和电路板之间充填灌胶，以增加整个结构的机械强度。Flip-chip (FC, Flip-Chip) soldering is a commonly used system-in-package method at present. The system-in-package method includes: providing a PCB circuit board, wherein solder balls arranged according to certain requirements are formed on the PCB circuit board (formed by a ball-mounting process); dipping flux on the circuit board, and then flip-chip bonding the chip The chip is placed on the circuit board; the pads on the chip are electrically connected to the solder balls on the circuit board by the reflow process; after that, the bottom of the chip and the circuit board are filled with glue to increase the overall structure mechanical strength.
但是，现有的系统级封装的方法，存在以下缺点：1、工艺复杂，造成封装效率低；2、需要将各个芯片依次焊接在焊球上，封装效率低；3、需要利用焊接工艺实现芯片与PCB板的电连接，无法与封装前段的工艺兼容；4、浸蘸助焊剂过程中稍有不慎施以较大压力时容易造成电路板压裂。However, the existing system-level packaging method has the following disadvantages: 1. The process is complicated, resulting in low packaging efficiency; 2. Each chip needs to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. The chip needs to be realized by a welding process The electrical connection with the PCB board is not compatible with the process in the front section of the package; 4. When a large pressure is accidentally applied during the process of dipping the flux, it is easy to cause the circuit board to crack.
发明内容SUMMARY OF THE INVENTION
本发明要解决的问题是现有的板级系统级封装封装效率低、无法与前段的芯片形成工艺兼容等。The problem to be solved by the present invention is that the existing board-level system-level packaging has low packaging efficiency and cannot be compatible with the chip forming process in the previous stage.
为了实现上述目的，本发明提供一种板级系统级封装方法，包括：提供电路板，所述电路板表面形成有多个第一焊垫，所述第一焊垫凹陷于所述表面；In order to achieve the above object, the present invention provides a board-level system-in-package method, comprising: providing a circuit board, a surface of the circuit board is formed with a plurality of first pads, and the first pads are recessed on the surface;
提供多个第一芯片，所述第一芯片其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述表面；a plurality of first chips are provided, a surface of the first chips is formed with a second pad, and the second pad is recessed on the surface;
将所述第一芯片与所述电路板键合，所述第一焊垫与所述第二焊垫相对围成第一空隙；bonding the first chip and the circuit board, the first pad and the second pad are opposite to form a first gap;
通过电镀工艺在所述第一空隙形成第一导电凸块以电连接所述第一焊垫、第二焊垫。A first conductive bump is formed in the first void by an electroplating process to electrically connect the first pad and the second pad.
本发明还提供一种板级系统级封装结构，包括：The present invention also provides a board-level system-level packaging structure, comprising:
电路板，所述电路板表面形成有多个第一焊垫，所述第一焊垫凹陷于所述正面；a circuit board, wherein a plurality of first pads are formed on the surface of the circuit board, and the first pads are recessed on the front surface;
多个第一芯片，所述第一芯片其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述表面；a plurality of first chips, one surface of the first chips is formed with a second bonding pad, the second bonding pad is recessed on the surface;
所述第一芯片与所述电路板键合在一起，所述第一焊垫与所述第二焊垫通过电镀的第一导电凸块电连接。The first chip and the circuit board are bonded together, and the first bonding pad and the second bonding pad are electrically connected through electroplated first conductive bumps.
本发明还提供一种电路板，包括：The present invention also provides a circuit board, comprising:
至少一层板，每层板至少包括基板、位于所述基板表面互连结构，所述第一焊垫位于顶层的所述互连结构上与所述互连结构电连接；at least one layer of boards, each layer of board at least includes a substrate, an interconnection structure located on the surface of the substrate, and the first pad is located on the interconnection structure on the top layer and is electrically connected to the interconnection structure;
所述电路板的正面形成有具有光刻键合特性的第一有机介质层或第一无机介质层，第一焊垫埋设于所述第一有机介质层或第一无机介质层；A first organic medium layer or a first inorganic medium layer with photolithographic bonding characteristics is formed on the front surface of the circuit board, and a first pad is embedded in the first organic medium layer or the first inorganic medium layer;
和/或，and / or,
还包括第四焊垫，所述第四焊垫位于所述电路板底层的所述互连结构上与相应所述互连结构电连接，所述背面形成有光刻键合特性的第二有机介质层或第二无机介质层，第四焊垫埋设于所述第二有机介质层或所述第二无机介质层。It also includes a fourth solder pad, the fourth solder pad is located on the interconnect structure on the bottom layer of the circuit board and is electrically connected to the corresponding interconnect structure, and the back surface is formed with a second organic layer with photolithographic bonding characteristics. The dielectric layer or the second inorganic dielectric layer, and the fourth pad is embedded in the second organic dielectric layer or the second inorganic dielectric layer.
本发明还提供一种电路板的形成方法，包括：The present invention also provides a method for forming a circuit board, comprising:
至少形成一层板，每层板至少包括基板、位于所述基板表面的互连结构；at least one layer of boards is formed, and each board at least includes a substrate and an interconnection structure on the surface of the substrate;
形成位于顶层的板后，在顶层板上形成第一焊垫、第一焊垫与位于顶层板的所述互连结构电连接；After the board on the top layer is formed, a first solder pad is formed on the top layer, and the first solder pad is electrically connected to the interconnect structure on the top layer;
在所述顶层板上形成具有光刻键合特性的第一有机介质层或第一无机介质层，覆盖所述电路板表面、暴露出所述第一焊垫；forming a first organic dielectric layer or a first inorganic dielectric layer with photolithographic bonding properties on the top board, covering the surface of the circuit board and exposing the first pads;
和/或，and / or,
在底层板上形成第四焊垫、第四焊垫与位于底层板的互连结构电连接，在所述底层板上形成具有光刻键合特性的第二有机介质层或第一无机介质层，覆盖所述电路板表面、暴露出所述第四焊垫。A fourth pad is formed on the bottom plate, the fourth pad is electrically connected to the interconnect structure on the bottom plate, and a second organic medium layer or a first inorganic medium layer with photolithographic bonding characteristics is formed on the bottom plate , covering the surface of the circuit board and exposing the fourth solder pad.
本发明的有益效果在于：The beneficial effects of the present invention are:
本发明完全避开了传统的PCB板上的利用焊接实现芯片与电路板电连接的封装工艺，通过电镀工艺形成第一导电凸块，以实现第一芯片与电路板电连接。第一、相对于传统的封装工艺，工艺流程简单，封装效率高；第二、可以将所有的芯片均键合在电路板上之后，通过电镀工艺形成每一芯片与所述电路板的电连接，相较于传统的每个芯片单独焊接与电路板实现电连接，极大的提高了封装效率。第三、电镀工艺与封装前段的工艺兼 容，可以利用传统的芯片制造工艺或晶圆级封装工艺实现板级的系统级封装工艺。The present invention completely avoids the traditional packaging process of using welding to realize the electrical connection between the chip and the circuit board, and forms the first conductive bumps through the electroplating process to realize the electrical connection between the first chip and the circuit board. First, compared with the traditional packaging process, the process flow is simple and the packaging efficiency is high; second, after all the chips are bonded on the circuit board, the electrical connection between each chip and the circuit board can be formed through the electroplating process , compared with the traditional method that each chip is individually soldered and electrically connected to the circuit board, which greatly improves the packaging efficiency. Third, the electroplating process is compatible with the process in the front-end of the packaging, and the board-level system-level packaging process can be realized by using the traditional chip manufacturing process or the wafer-level packaging process.
进一步地，第一芯片与电路板之间通过可光刻键合材料实现物理连接，而且可光刻键合材料覆盖所述第一导电凸块外围的区域，直接增强了整个结构的机械强度，可以省去现有技术的充填灌胶工艺。在后续进行塑封工艺时，塑封材料无需填充第一芯片与电路板之间的间隙，从而节省了塑封工艺的时间。另外，干膜材料的可光刻键合材料，由于弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，从而减小第一芯片与电路板的结合应力。进一步的，可光刻键合材料可以定义第一导电凸块的位置，防止电镀工艺中第一导电凸块横向外溢。Further, the physical connection between the first chip and the circuit board is realized by the lithographic bonding material, and the lithographic bonding material covers the peripheral area of the first conductive bump, which directly enhances the mechanical strength of the entire structure, The filling and gluing process of the prior art can be omitted. In the subsequent plastic packaging process, the plastic packaging material does not need to fill the gap between the first chip and the circuit board, thereby saving the time of the plastic packaging process. In addition, the photolithographic bonding material of the dry film material, due to its relatively small elastic modulus, can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the first chip and the circuit board. Further, the photolithographic bonding material can define the positions of the first conductive bumps to prevent lateral overflow of the first conductive bumps in the electroplating process.
进一步地，当所述第一焊垫和所述第二焊垫的正对部分、错开部分的面积大于第一焊垫或第二焊垫面积的二分之一时，可以更好的实现电镀工艺，使形成的第一导电凸块尽可能完整的填充第一空隙内，避免形成的第一导电凸块与焊垫接触面积过小而导致电阻增大；另一方面，错开的部分可以更容易与电镀液接触，这样可以避免由于第一空隙小而导致电镀液不容易流入第一空隙而导致无法形成比较完好的第一导电凸块的问题。Further, when the area of the facing portion and the staggered portion of the first pad and the second pad is greater than half of the area of the first pad or the second pad, electroplating can be better achieved. process, so that the formed first conductive bumps fill the first voids as completely as possible, so as to avoid that the contact area between the formed first conductive bumps and the pads is too small and the resistance increases; on the other hand, the staggered part can be more It is easy to be in contact with the electroplating solution, which can avoid the problem that the electroplating solution is not easy to flow into the first gap due to the small first gap, resulting in the inability to form relatively intact first conductive bumps.
进一步地，当第一空隙的高度为5-200微米时，既满足了电镀液容易进入第一空隙进行电镀，也避免了第一空隙高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。Further, when the height of the first void is 5-200 microns, it not only satisfies that the electroplating solution can easily enter the first void for electroplating, but also avoids the problem that the height of the first void is too high and leads to a long electroplating time, thus taking into account the electroplating. Efficiency and Plating Yield.
进一步的，由于无需利用焊接工艺，电路板上的无需再形成阻焊剂和助焊剂，可以是具有光刻键合特性的有机介质层或者也可以是无机介质层，从而提升电路板的形成效率，节省工艺。当顶层是具有光刻键合特性的有机介质层时，可以根据需要选择一定厚度的有机介质层，方便后续将第一芯片键合至电路板上，无需额外形成键合层。当顶层是无机介质层时，相比有机介质层而言，电镀液在无机介质层上的表面张力小，电镀液更容易进入第一空隙中，提高第一导电凸块的形成良率。Further, since there is no need to use the soldering process, there is no need to form solder resist and flux on the circuit board. It can be an organic dielectric layer with photolithographic bonding characteristics or an inorganic dielectric layer, thereby improving the formation efficiency of the circuit board. Save on craftsmanship. When the top layer is an organic medium layer with photolithographic bonding characteristics, an organic medium layer with a certain thickness can be selected as required, so as to facilitate the subsequent bonding of the first chip to the circuit board without additional bonding layers. When the top layer is an inorganic dielectric layer, compared with the organic dielectric layer, the surface tension of the electroplating solution on the inorganic dielectric layer is smaller, and the electroplating solution is more likely to enter the first voids, thereby improving the formation yield of the first conductive bumps.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.
图1至图5示出了根据本发明实施例一中板级系统级封装方法中不同步骤中对应的结构示意图；1 to 5 show schematic structural diagrams corresponding to different steps in a board-level system-in-package method according to Embodiment 1 of the present invention;
图6-图7为本发明实施例二中板级系统级封装结构示意图；6-7 are schematic diagrams of the board-level system-level packaging structure in Embodiment 2 of the present invention;
图8-图14为本发明实施例三中板级系统级封装结构示意图；8-14 are schematic diagrams of the board-level system-level packaging structure in Embodiment 3 of the present invention;
图15-图17为本发明实施例四中板级系统级封装结构示意图；15-17 are schematic diagrams of the board-level system-level package structure in Embodiment 4 of the present invention;
图18-图19为本发明实施例五中板级系统级封装结构示意图；18-19 are schematic diagrams of the board-level system-level packaging structure in Embodiment 5 of the present invention;
图20为本发明实施例六中板级系统级封装结构示意图；20 is a schematic diagram of a board-level system-level packaging structure in Embodiment 6 of the present invention;
图21、21a为本发明实施例七中板级系统级封装结构示意图；21 and 21a are schematic diagrams of the board-level system-level package structure in Embodiment 7 of the present invention;
图22-图24示出了根据本发明实施例八中板级系统级封装方法中不同步骤中对应的结构示意图；22-24 show schematic structural diagrams corresponding to different steps in the board-level system-in-package method according to Embodiment 8 of the present invention;
图25-图27为本发明实施例九中板级系统级封装结构示意图；25-27 are schematic diagrams of the board-level system-level packaging structure in Embodiment 9 of the present invention;
图28为本发明实施例十中板级系统级封装结构示意图；28 is a schematic diagram of a board-level system-level package structure in Embodiment 10 of the present invention;
图29为本发明实施例十一中板级系统级封装结构示意图；29 is a schematic diagram of a board-level system-level package structure in Embodiment 11 of the present invention;
图30为本发明实施例十二中板级系统级封装结构示意图；30 is a schematic diagram of a board-level system-level package structure in Embodiment 12 of the present invention;
图31至图34示出了根据本发明实施例的电路板形成过程中不同步骤中对应的结构示意图。31 to 34 are schematic diagrams showing corresponding structures in different steps in a circuit board formation process according to an embodiment of the present invention.
具体实施方式Detailed ways
以下结合附图和具体实施例对本发明进一步详细说明。根据下面的说明和附图，本发明的优点和特征将更清楚，然而，需说明的是，本发明技术方案的构思可按照多种不同的形式实施，并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and accompanying drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in various forms, and is not limited to the specific implementation described here. example. The accompanying drawings are all in a very simplified form and in an inaccurate scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.
本发明提供一种板级系统级封装方法，包括：The present invention provides a board-level system-level packaging method, comprising:
提供电路板，所述电路板表面形成有多个第一焊垫，所述第一焊垫凹陷于所述表面；A circuit board is provided, and a plurality of first bonding pads are formed on the surface of the circuit board, and the first bonding pads are recessed on the surface;
提供多个第一芯片，所述第一芯片其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述表面；a plurality of first chips are provided, a surface of the first chips is formed with a second pad, and the second pad is recessed on the surface;
将所述第一芯片与所述电路板键合，所述第一焊垫与所述第二焊垫相对围成第一空隙；bonding the first chip and the circuit board, the first pad and the second pad are opposite to form a first gap;
通过电镀工艺在所述第一空隙形成第一导电凸块以电连接所述第一焊垫、第二焊垫。A first conductive bump is formed in the first void by an electroplating process to electrically connect the first pad and the second pad.
本发明完全避开了传统的PCB板上的利用焊接实现芯片与电路板电连接的封装工艺，通过电镀工艺形成导电凸块，以实现第一芯片与电路板电连接。第一、相对于传统的封装工艺，工艺流程简单，封装效率高；第二、可以将所有的芯片均键合在电路板上之后，通过电镀工艺形成每一芯片与所述电路板的电连接，相较于传统的每个芯片单独焊接与电路板实现电连接，极大的提高了封装效率。第三、电镀工艺与封装前段的工艺兼容，可 以利用传统的芯片制造工艺或晶圆级封装工艺实现板级的系统级封装工艺。The present invention completely avoids the traditional packaging process of using welding to realize the electrical connection between the chip and the circuit board on the PCB, and forms conductive bumps through the electroplating process to realize the electrical connection between the first chip and the circuit board. First, compared with the traditional packaging process, the process flow is simple and the packaging efficiency is high; second, after all the chips are bonded on the circuit board, the electrical connection between each chip and the circuit board can be formed through the electroplating process , compared with the traditional method that each chip is individually soldered and electrically connected to the circuit board, which greatly improves the packaging efficiency. Third, the electroplating process is compatible with the process in the front-end of the package, and the board-level system-level packaging process can be realized by using the traditional chip manufacturing process or the wafer-level packaging process.
下面将结合附图对本发明的具体实施例进行详细的说明。The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
实施例一Example 1
本发明实施例1提供一种板级系统级封装的方法，参考图1-图5，对该封装方法进行说明。Embodiment 1 of the present invention provides a board-level system-level packaging method. Referring to FIG. 1 to FIG. 5 , the packaging method will be described.
参考图1，提供电路板10，所述电路板10具有正面和背面，所述正面形成有多个第一焊垫11，所述第一焊垫11凹陷于所述正面。该第一焊垫11可以是焊盘(PAD)，但不限于焊盘，也可以是其他具有电连接功能的导电块。Referring to FIG. 1 , a circuit board 10 is provided, the circuit board 10 has a front surface and a back surface, the front surface is formed with a plurality of first solder pads 11 , and the first solder pads 11 are recessed in the front surface. The first pad 11 may be a pad (PAD), but is not limited to a pad, and may also be other conductive blocks with an electrical connection function.
所述电路板10包括：至少一层板12，每层板12至少包括基板、位于所述基板表面的互连结构，所述第一焊垫11位于顶层板上与所述互连结构电连接。电路板10为印刷线路板即PCB板，电路板10可以是单层板，双层板，三层板，四层板等，具体的，电路板10的层数可以根据实际需求确定。本实施例中，电路板10为三层板，每层板12包括位于基板表面的互连结构14、与互连结构14电连接的互连插塞15，互连插塞15包括通孔及通孔表面镀有的导电层，且通孔内填充绝缘树脂。或者，也可以在通孔内填充导电树脂，节省形成导电层的工艺。本发明中，也可以根据实际需求，确定每层板是否包含互连插塞、互连结构，可以只有互连结构，没有互连插塞。本发明中，电路板不限于PCB板，还可以为其他形式的电路板，比如陶瓷电路板。The circuit board 10 includes: at least one layer of boards 12, each layer of board 12 at least includes a substrate and an interconnection structure located on the surface of the substrate, and the first pad 11 is located on the top layer and is electrically connected to the interconnection structure . The circuit board 10 is a printed circuit board, that is, a PCB board. The circuit board 10 can be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc. Specifically, the number of layers of the circuit board 10 can be determined according to actual needs. In this embodiment, the circuit board 10 is a three-layer board, and each layer of the board 12 includes an interconnection structure 14 located on the surface of the substrate, and an interconnection plug 15 electrically connected to the interconnection structure 14. The interconnection plug 15 includes through holes and The conductive layer is plated on the surface of the through hole, and the through hole is filled with insulating resin. Alternatively, the conductive resin can also be filled in the through hole to save the process of forming the conductive layer. In the present invention, it can also be determined according to actual requirements whether each layer of the board includes interconnection plugs and interconnection structures, and there may be only interconnection structures without interconnection plugs. In the present invention, the circuit board is not limited to a PCB board, but can also be other forms of circuit boards, such as ceramic circuit boards.
现有技术中，电路板顶层为阻焊层、助焊层，阻焊剂覆盖电路板顶面且暴露出焊垫。本发明中，电路板的顶层可以同现有技术相同，在顶面设置阻焊层、阻焊；由于本发明中，第一芯片与电路板的电连接无需通过焊接实现，因此顶面可以不设置阻焊层(绿油)，也可以不设置助焊层。顶层可以是具有光刻键合特性的第一有机介质层13，第一焊垫11埋设于所述第一有机介质层13且部分暴露在外。当顶层是具有光刻键合特性的第一有机介质层时，可以根据需要选择一定厚度的第一有机介质层，方便后续将第一芯片键合至电路板上，无需额外形成键合层，这样可以节省工艺，从而提升电路板的形成效率。顶层也可以是第一无机介质层，当顶层是无机介质层时，相比有机介质层而言，电镀液在无机介质层上的表面张力小，电镀液更容易进入第一空隙中，提高第一导电凸块的形成良率；而且，由于无需形成助焊层、阻焊层，这样可以节省工艺，从而提升电路板的形成效率。In the prior art, the top layer of the circuit board is a solder resist layer and a solder flux layer, and the solder resist covers the top surface of the circuit board and exposes the solder pads. In the present invention, the top layer of the circuit board can be the same as the prior art, and a solder resist layer and a solder resist are arranged on the top surface; because in the present invention, the electrical connection between the first chip and the circuit board does not need to be realized by welding, so the top surface can not be A solder mask layer (green oil) is provided, or a solder flux layer is not required. The top layer may be a first organic dielectric layer 13 with photolithographic bonding properties, and the first pads 11 are buried in the first organic dielectric layer 13 and partially exposed. When the top layer is the first organic medium layer with photolithographic bonding characteristics, the first organic medium layer with a certain thickness can be selected according to the needs, so as to facilitate the subsequent bonding of the first chip to the circuit board without additional bonding layers. In this way, processes can be saved, thereby improving the formation efficiency of the circuit board. The top layer can also be the first inorganic medium layer. When the top layer is the inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is smaller, and the electroplating solution is more likely to enter the first gap, which improves the first gap. The formation yield of a conductive bump; and, since there is no need to form a solder flux layer and a solder resist layer, the process can be saved, thereby improving the formation efficiency of the circuit board.
参考图2和图3，提供多个第一芯片30，所述第一芯片30其中一表面形成有第二焊垫31，所述第二焊垫31凹陷于所述表面；通常，含有第二 焊垫31的面为芯片的正面，但可以是芯片的背面，第一芯片30中可以含有穿硅通孔(Through Silicon Via，简称TSV)，第二焊垫31与该穿硅通孔电连接。Referring to FIGS. 2 and 3 , a plurality of first chips 30 are provided, and a surface of the first chips 30 is formed with a second pad 31 , and the second pad 31 is recessed on the surface; The surface of the bonding pad 31 is the front side of the chip, but it can be the back side of the chip. The first chip 30 may contain a Through Silicon Via (TSV for short), and the second bonding pad 31 is electrically connected to the TSV. .
将所述第一芯片30与所述电路板10键合，所述第一焊垫11与所述第二焊垫31相对围成第一空隙32。该第一空隙32为后续的电镀工作做准备，后续会在该第一空隙中形成第一导电凸块，以实现第一焊垫11和第二焊垫31的电连接。The first chip 30 is bonded to the circuit board 10 , and the first bonding pad 11 and the second bonding pad 31 are opposite to form a first gap 32 . The first space 32 is prepared for the subsequent electroplating work, and a first conductive bump will be formed in the first space later to realize the electrical connection between the first bonding pad 11 and the second bonding pad 31 .
继续参考图2和图3，通过键合层实现所述第一芯片30与所述电路板10键合，所述键合层避开焊垫设置。Continuing to refer to FIG. 2 and FIG. 3 , the first chip 30 and the circuit board 10 are bonded to each other through a bonding layer, and the bonding layer is arranged to avoid bonding pads.
所述键合层的材料包括：可光刻键合材料、芯片粘结膜、介质材料、玻璃和聚合物材料中的一种或多种，所述可光刻材料包括干膜，所述介质材料包括氧化硅或者氮化硅。The material of the bonding layer includes: one or more of photolithographic bonding material, die bonding film, dielectric material, glass and polymer material, the photolithographic material includes dry film, the medium Materials include silicon oxide or silicon nitride.
本实施例中，所述键合层的材料为可光刻键合材料，通过可光刻键合材料20将所述第一芯片30键合于所述电路板10，所述可光刻键合材料20避开第一焊垫11设置。其中，可光刻键合材料20可以形成在电路板10上，也可以形成在第一芯片30上，还可以是在第一芯片30以及电路板10上均形成可光刻键合材料。In this embodiment, the material of the bonding layer is a photolithographic bonding material, the first chip 30 is bonded to the circuit board 10 through the photolithographic bonding material 20 , and the photolithographic bonding material 20 is used to bond the first chip 30 to the circuit board 10 . The bonding material 20 is arranged to avoid the first pad 11 . The photolithographic bonding material 20 may be formed on the circuit board 10 , or may be formed on the first chip 30 , or the photolithographic bonding material may be formed on both the first chip 30 and the circuit board 10 .
本实施例中，在电路板10上形成可光刻键合材料20。具体方法包括：在所述电路板表面上形成可光刻的键合材料；对所述可光刻键合材料进行图形化形成开口以露出所述第一焊垫11；通过所述可光刻键合材料将所述第一芯片30与所述电路板10键合在一起。其中，可光刻键合材料可以是液体干膜，也可以是膜状干膜。液态干膜可以旋涂在电路板10的表面上，然后进行图形化工艺。膜状干膜可以贴覆在电路板10的表面上，然后进行图形化工艺。In this embodiment, a photolithographic bonding material 20 is formed on the circuit board 10 . The specific method includes: forming a photolithographic bonding material on the surface of the circuit board; patterning the photolithographic bonding material to form an opening to expose the first pad 11 ; The bonding material bonds the first chip 30 and the circuit board 10 together. The photolithographic bonding material may be a liquid dry film or a film-like dry film. The liquid dry film can be spin-coated on the surface of the circuit board 10 and then subjected to a patterning process. The film-like dry film can be pasted on the surface of the circuit board 10 and then subjected to a patterning process.
其中，所述可光刻键合材料20覆盖后续形成的所述第一导电凸块外围的区域，即定义第一导电凸块的形成位置，也就是说可光刻键合材料围成了第一空隙40的边界，后续导电凸块不能超越该边界，方便进行电镀工艺的控制。由于，第一芯片30与电路板10之间通过可光刻键合材料20实现物理连接，而且可光刻键合材料覆盖所述第一导电凸块外围的区域，直接增强了整个结构的机械强度，可以省去现有技术的充填灌胶工艺。在后续进行塑封工艺时，塑封材料无需填充第一芯片与电路板之间的间隙，从而节省了塑封工艺的时间。另外，干膜材料的可光刻键合材料，由于弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，从而减小第一芯片与电路板的结合应力。Wherein, the photolithographic bonding material 20 covers the area surrounding the first conductive bumps formed subsequently, that is, defines the formation position of the first conductive bumps, that is to say, the photolithographic bonding material encloses the first conductive bump. The boundary of a gap 40 cannot be exceeded by subsequent conductive bumps, which facilitates the control of the electroplating process. Because the physical connection between the first chip 30 and the circuit board 10 is achieved by the photolithographic bonding material 20, and the photolithographic bonding material covers the peripheral area of the first conductive bump, the mechanical properties of the entire structure are directly enhanced. The strength can save the filling and gluing process of the prior art. In the subsequent plastic packaging process, the plastic packaging material does not need to fill the gap between the first chip and the circuit board, thereby saving the time of the plastic packaging process. In addition, the photolithographic bonding material of the dry film material, due to its relatively small elastic modulus, can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the first chip and the circuit board.
其他实施例中，键合层也可以是芯片粘结膜、介质材料、玻璃和聚合 物材料中的一种或多种，介质材料包括：氧化硅或氮化硅。In other embodiments, the bonding layer may also be one or more of a die attach film, a dielectric material, glass and a polymer material, and the dielectric material includes silicon oxide or silicon nitride.
其他实施例中，介质材料包括：氧化硅。所述第三表面的材料为氧化硅，所述第一无机介质层的材料为氧化硅，相应的，通过熔融键合工艺将第一器件晶圆和电路板键合在一起，所述键合层和第一器件晶圆之间，以及键合层和电路板之间均构成氧化硅-氧化硅的共价键，键合层和第一器件晶圆之间，以及键合层和电路板之间具有较高的键合强度，进而提高板级系统封装的封装成品率。In other embodiments, the dielectric material includes: silicon oxide. The material of the third surface is silicon oxide, and the material of the first inorganic medium layer is silicon oxide. Correspondingly, the first device wafer and the circuit board are bonded together by a fusion bonding process, and the bonding Silicon oxide-silicon oxide covalent bonds are formed between the layer and the first device wafer, and between the bonding layer and the circuit board, between the bonding layer and the first device wafer, and between the bonding layer and the circuit board There is a high bonding strength between them, thereby improving the packaging yield of board-level system packaging.
键合层的材料还可以为玻璃，相应的采用玻璃介质键合使得第一器件晶圆和电路板键合，玻璃介质键合指的是，将玻璃焊料印刷在第一器件晶圆或电路板上，然后放入回流炉中进行预烧结，将预烧结完成后的第一器件晶圆与电路板对准放置，使第一芯片位于所述键合层正下方，之后放入键合机中进行烧结。玻璃介质键合工艺简单、键合强度高且密封效果好，尤其适合大批量生产。The material of the bonding layer can also be glass. Correspondingly, glass dielectric bonding is used to bond the first device wafer to the circuit board. Glass dielectric bonding refers to printing glass solder on the first device wafer or circuit board. Then put it into a reflow furnace for pre-sintering, and place the pre-sintered first device wafer in alignment with the circuit board so that the first chip is located directly under the bonding layer, and then put it into the bonding machine Sintering is carried out. The glass medium bonding process is simple, the bonding strength is high and the sealing effect is good, especially suitable for mass production.
本发明实施例中，所述可光刻的键合材料的厚度为5-200μm，所述可光刻键合材料至少覆盖所述芯片面积的10％，可以保证第一芯片与电路板之间的粘结强度。In the embodiment of the present invention, the thickness of the photolithographic bonding material is 5-200 μm, and the photolithographic bonding material covers at least 10% of the area of the chip, which can ensure the gap between the first chip and the circuit board. bond strength.
本发明实施例中，第一有机介质层13可以是可光刻键合材料，在此情形下无需单独形成可光刻键合材料20，节省工艺。In the embodiment of the present invention, the first organic medium layer 13 may be a photolithographic bonding material. In this case, there is no need to separately form the photolithographic bonding material 20, which saves the process.
其中，所述第一芯片包括：裸芯片、包裹有塑封层、顶面具有屏蔽层、形成有贯穿芯片的互连通孔结构中的至少一种情形。Wherein, the first chip includes at least one of: a bare chip, being wrapped with a plastic sealing layer, having a shielding layer on the top surface, and forming an interconnect via structure penetrating the chip.
电路板10上的多个第一芯片可以为具有同功能的芯片；也可以是所述多个第一芯片至少包括两种不同功能的芯片，多种不同功能的芯片集成在一起实现一定的功能。第一芯片可以是无源器件或者有源器件，无源器件包括电容、电感、连接芯片(起电连接作用的电连接块，比如形成有互连结构的互连芯片，互连结构可以包括插塞或者TSV结构)，有源器件可以包括传感器模组芯片、CIS芯片、MEMS芯片、滤波器芯片、逻辑芯片、存储芯片。其中，所述MEMS芯片包括热堆传感器芯片，热堆传感器芯片与逻辑芯片集成在一起可以实现红外传感功能，比如实现测温。所述MEMS芯片也可以是麦克风传感器，麦克风传感器与逻辑芯片集成在一起可以实现声波传感功能。所述滤波器芯片包括：表面声波谐振器、体声波谐振器至少其中之一。或者所述第一芯片为顶面接收红外辐射的芯片，或者所述第一芯片顶面为接收可见光的芯片，或者所述第一芯片顶面为接收射频信号的芯片，或者，所述第一芯片也可以是柔性电路板FPCThe multiple first chips on the circuit board 10 may be chips with the same function; it may also be that the multiple first chips include at least two chips with different functions, and the multiple chips with different functions are integrated together to achieve a certain function . The first chip can be a passive device or an active device, and the passive device includes capacitors, inductors, connection chips (electrical connection blocks for electrical connection, such as interconnection chips formed with interconnection structures, and the interconnection structures may include plug or TSV structure), active devices may include sensor module chips, CIS chips, MEMS chips, filter chips, logic chips, and memory chips. Wherein, the MEMS chip includes a thermopile sensor chip, and the thermopile sensor chip and the logic chip can be integrated together to realize infrared sensing functions, such as realizing temperature measurement. The MEMS chip can also be a microphone sensor, and the microphone sensor and the logic chip can be integrated together to realize the sound wave sensing function. The filter chip includes at least one of a surface acoustic wave resonator and a bulk acoustic wave resonator. Or the first chip is a chip whose top surface receives infrared radiation, or the top surface of the first chip is a chip that receives visible light, or the top surface of the first chip is a chip that receives radio frequency signals, or the first The chip can also be a flexible circuit board FPC
所述传感器模组芯片包括至少传感射频信号、红外辐射信号、可见光信号、声波信号、电磁波信号其中之一的模组芯片。传感射频信号的模组 芯片可以是应用在5G设备中的射频模组芯片，但不限于5G射频传感器模组芯片，还可以是其他类型的射频模组芯片。接收红外辐射信号的模组芯片可以是热像仪、额温枪、其他类型中的测温或成像等利用红外辐射信号的红外传感器模组芯片。传感器模组芯片还可以是摄像头模组芯片，比如包括感光芯片以及滤光片的模组芯片，可以接收可见光用来成像。传感器模组芯片还可以是麦克风模组芯片，可以接收声波用来传递声音信号。本发明中的传感器模组芯片不限于在此列举的类型，可以为本领域可以实现一定功能的各种类型的传感器模组芯片。The sensor module chip includes a module chip for sensing at least one of radio frequency signals, infrared radiation signals, visible light signals, acoustic wave signals, and electromagnetic wave signals. The module chip that senses the RF signal can be the RF module chip used in 5G equipment, but is not limited to the 5G RF sensor module chip, and can also be other types of RF module chips. The module chip that receives the infrared radiation signal may be an infrared sensor module chip that utilizes the infrared radiation signal, such as a thermal imager, a forehead temperature gun, and other types of temperature measurement or imaging. The sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and a filter, which can receive visible light for imaging. The sensor module chip can also be a microphone module chip, which can receive sound waves to transmit sound signals. The sensor module chips in the present invention are not limited to the types listed here, and can be various types of sensor module chips that can achieve certain functions in the art.
在一实施例中，所述第一芯片包括：超声波传感芯片以及外围芯片，所述外围芯片包括：信号读取芯片、模拟信号处理芯片、模数转换芯片、数字逻辑芯片以及控制芯片中的至少一种；In one embodiment, the first chip includes: an ultrasonic sensor chip and a peripheral chip, and the peripheral chip includes: a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic chip, and a control chip. at least one;
在又一实施例中，所述第一芯片包括：图像传感芯片以及外围芯片，所述图像传感芯片包括：CMOS传感芯片或CCD传感芯片中的至少一种；所述外围芯片包括：信号读取芯片、模拟信号处理芯片、模数转换芯片、数字逻辑电路芯片或驱动芯片中的至少一种或几种的集成。In yet another embodiment, the first chip includes: an image sensor chip and a peripheral chip, the image sensor chip includes at least one of a CMOS sensor chip or a CCD sensor chip; the peripheral chip includes : Integration of at least one or more of a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic circuit chip or a driver chip.
在又一实施例中，所述第一芯片包括：射频芯片，其中包括至少一个滤波器芯片，其他射频芯片包括信号放大、信号接收以及信号调谐中的至少一个功能。In yet another embodiment, the first chip includes: a radio frequency chip, which includes at least one filter chip, and the other radio frequency chips include at least one function of signal amplification, signal reception, and signal tuning.
参考图4，通过电镀工艺在所述第一空隙形成第一导电凸块40以电连接所述第一焊垫11、第二焊垫31。Referring to FIG. 4 , a first conductive bump 40 is formed in the first space by an electroplating process to electrically connect the first pad 11 and the second pad 31 .
本发明中，所述电镀工艺包括化学镀。其中，化学镀采用的镀液根据实际中需要形成的导电凸块的材料以及第一焊垫、第二焊垫的材料确定。第一焊垫11、第二焊垫31的材料选自铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或它们的任意组合。第一导电凸块的材料包括：铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或它们的任意组合。可选实施例中，第一导电凸块的高度为5-200μm，如10μm、50μm、100μm。当第一导电凸块即第一空隙的高度为5-200μm时，既满足了电镀液容易进入第一空隙进行电镀，也避免了第一空隙高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。In the present invention, the electroplating process includes electroless plating. Wherein, the plating solution used in the electroless plating is determined according to the materials of the conductive bumps and the materials of the first bonding pad and the second bonding pad to be formed in practice. The materials of the first pad 11 and the second pad 31 are selected from any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof. The material of the first conductive bump includes: any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof. In an optional embodiment, the height of the first conductive bump is 5-200 μm, such as 10 μm, 50 μm, and 100 μm. When the height of the first conductive bumps, namely the first voids, is 5-200 μm, it not only satisfies that the electroplating solution can easily enter the first voids for electroplating, but also avoids the problem that the height of the first voids is too high and leads to a long electroplating time. The electroplating efficiency and electroplating yield are improved.
可以选择，化学镀钯浸金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟，化学钯的时间为7-32分钟；或，化学镍金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟。Optionally, electroless palladium immersion gold, wherein the time of chemical nickel is 30-50 minutes, the time of chemical gold is 4-40 minutes, and the time of chemical palladium is 7-32 minutes; The time is 30-50 minutes, and the time for chemical gold is 4-40 minutes.
电镀工艺选择化学镀钯浸金(ENEPIG)或化学镍金(ENIG)时，工艺参数可以参照下表1。When the electroplating process selects electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), the process parameters can refer to Table 1 below.
表1Table 1
Figure PCTCN2021143214-appb-000001
Figure PCTCN2021143214-appb-000001
在进行化学镀之前，为了更好的完成电镀工艺，可以先对焊垫的表面进行清洁，以去除焊垫表面的自然氧化层、提高焊垫的表面湿润度；之后，可以进行活化工艺，促进镀层金属在待镀金属上的形核生长。Before electroless plating, in order to better complete the electroplating process, the surface of the pad can be cleaned first to remove the natural oxide layer on the surface of the pad and improve the surface wettability of the pad; after that, an activation process can be performed to promote Nucleation and growth of the coating metal on the metal to be plated.
为了更好的实现电镀，形成比较完善的第一导电凸块40，第一焊垫、第二焊垫的设置也需要满足一定的要求，比如：所述第一焊垫或所述第二焊垫的暴露出面积为5-200平方微米，在该范围内，焊垫可以与电镀液较充分的接触，避免焊垫与镀液不充分接触而影响导电凸块与焊垫的接触，比如接触面积过小影响电阻，或者，无法接触造成电接触不良；而且，也可以保证接触面积不会过大而降低电镀效率及不会占用过多的面。In order to better realize electroplating and form relatively complete first conductive bumps 40, the settings of the first bonding pad and the second bonding pad also need to meet certain requirements, such as: the first bonding pad or the second bonding pad The exposed area of the pad is 5-200 square microns. Within this range, the pad can be fully contacted with the plating solution to avoid insufficient contact between the pad and the plating solution and affect the contact between the conductive bump and the pad, such as contact If the area is too small, the resistance will be affected, or the inability to contact will result in poor electrical contact; moreover, it can also ensure that the contact area will not be too large, which will reduce the electroplating efficiency and will not occupy too much surface.
形成的第一导电凸块的横截面积大于10平方微米，既可以保证第一导电凸块占用的面积不会太大，也可以保证第一导电凸块与焊垫之间的结合强度。The cross-sectional area of the first conductive bumps formed is greater than 10 square micrometers, which can not only ensure that the area occupied by the first conductive bumps is not too large, but also ensure the bonding strength between the first conductive bumps and the bonding pads.
为了可以更好进行电镀工艺，可以设计所述第一焊垫和所述第二焊垫包括正对部分、错开部分，所述正对部分的面积为大于pad的二分之一。当所述第一焊垫和所述第二焊垫的正对部分、错开部分的面积大于pad的二分之一时，可以更好的实现电镀工艺，使形成的导电凸块尽可能完整的填充第一空隙内，避免形成的导电凸块与焊垫接触面积过小而导致电阻增大；另一方面，错开的部分可以更容易与电镀液接触，这样可以避免由于第一空隙小而导致电镀液不容易流入第一空隙而导致无法形成比较完好的导电凸块的问题。In order to better perform the electroplating process, the first pad and the second pad can be designed to include a facing portion and a staggered portion, and the area of the facing portion is larger than half of the pad. When the area of the facing part and the offset part of the first bonding pad and the second bonding pad is larger than half of the pad, the electroplating process can be better realized, so that the formed conductive bumps are as complete as possible. Fill the first gap to avoid the formation of conductive bumps and pads with too small contact area to cause resistance to increase; The electroplating solution is not easy to flow into the first voids, resulting in the problem that relatively intact conductive bumps cannot be formed.
可选方案中，导电凸块的材料与第二焊垫、第一焊垫的材料相同，这样更容易在第一空隙中形成导电凸块。当然，第一焊垫、第二焊垫的材料可以与导电凸块的材料不同，为了后续更容易形成导电凸块，可以在第一焊垫或第二焊垫上先形成材料层，该材料层的材料与导电凸块的材料相同，形成材料层的方法可以为沉积工艺。In an alternative solution, the material of the conductive bump is the same as that of the second bonding pad and the material of the first bonding pad, so that it is easier to form the conductive bump in the first void. Of course, the material of the first pad and the second pad can be different from the material of the conductive bump. In order to form the conductive bump more easily, a material layer can be first formed on the first pad or the second pad. The material layer The material of the conductive bump is the same as that of the conductive bump, and the method for forming the material layer may be a deposition process.
参考图5，形成塑封层50，该塑封层50覆盖电路板10及其上键合的第一芯片30。当然，本发明中也可以无需形成塑封层50。比如，键合的芯片为图像传感器芯片模组，可以不形成塑封层50，如果形成塑封层50，则需要在图像传感器芯片模组上进行开口，以暴露出滤光片。本实施例中，进行了塑封工艺，但本发明中是否需要进行塑封工艺需要根据实际情况确定，比如第一芯片为进行了塑封的芯片，则无需再进行本步骤的塑封工艺。Referring to FIG. 5 , a plastic sealing layer 50 is formed, and the plastic sealing layer 50 covers the circuit board 10 and the first chip 30 bonded thereon. Of course, in the present invention, it is also not necessary to form the plastic sealing layer 50 . For example, if the bonded chip is an image sensor chip module, the plastic sealing layer 50 may not be formed. If the plastic sealing layer 50 is formed, an opening needs to be made on the image sensor chip module to expose the filter. In this embodiment, the plastic sealing process is performed, but whether the plastic sealing process is required in the present invention needs to be determined according to the actual situation.
具体地，可以通过注塑工艺形成所述塑封层50。注塑工艺的填充性能较好，可以使注塑剂较好地填充在多个第二芯片20之间，从而使第二芯片200具有良好的封装效果。在其他实施例中，还可以采用其他工艺形成所述封装层。Specifically, the plastic sealing layer 50 may be formed by an injection molding process. The filling performance of the injection molding process is good, and the injection molding agent can be well filled between the plurality of second chips 20 , so that the second chips 200 have a good encapsulation effect. In other embodiments, other processes may also be used to form the encapsulation layer.
其中，在本实施例中，第一芯片与电路板之间的间隙被可光刻键合材料层完全填充，因此塑封层50无需填充在第一芯片和电路板之间，从而可以节省塑封工艺的时间。当然，本发明中，如果第一芯片和电路板之间如果并没有完全被可光刻键合材料占据、存在间隙，则塑封层会进入该间隙，对第一芯片进行更好的绝缘、密封以及保护作用。Wherein, in this embodiment, the gap between the first chip and the circuit board is completely filled with the photolithographic bonding material layer, so the plastic sealing layer 50 does not need to be filled between the first chip and the circuit board, so that the plastic sealing process can be saved time. Of course, in the present invention, if there is a gap between the first chip and the circuit board that is not completely occupied by the lithographic bonding material, the plastic encapsulation layer will enter the gap to better insulate and seal the first chip. and protection.
实施例二Embodiment 2
参考图6，键合在电路板上的第一芯片包括连接芯片30b，该连接芯片30b的顶面可以通过电镀工艺形成导电凸块30b1，该电镀工艺可以与形成凸块40的电镀工艺同时进行。导电凸块30b1也可以通过植球工艺形成。该连接芯片30b可以作为其他芯片与电路板连接的桥梁，在该连接芯片上堆叠其他芯片或者通过打线的方式将连接芯片与其他芯片电连接。Referring to FIG. 6 , the first chip bonded on the circuit board includes a connection chip 30b, and the top surface of the connection chip 30b can form conductive bumps 30b1 through an electroplating process, which can be performed simultaneously with the electroplating process for forming the bumps 40 . The conductive bumps 30b1 may also be formed through a ball mounting process. The connection chip 30b can be used as a bridge for connecting other chips with the circuit board, and other chips are stacked on the connection chip or the connection chip is electrically connected with other chips by means of wire bonding.
参考图7，与图6显示的实施例不同，该例子中，在进行了塑封工艺后，可以在塑封层上形成互连结构以电连接芯片30b与其他第一芯片30，之后利用电镀工艺或者植球工艺形成导电凸块30b1。Referring to FIG. 7 , different from the embodiment shown in FIG. 6 , in this example, after the plastic encapsulation process is performed, an interconnect structure may be formed on the plastic encapsulation layer to electrically connect the chip 30 b and the other first chips 30 , and then an electroplating process or The ball mounting process forms the conductive bumps 30b1.
实施例三Embodiment 3
参考图8至图14，实施例三的板级系统级封装的方法与实施例一的差异在于：第一芯片下方具有空腔，所述空腔作为第一芯片的工作腔。所述空腔可以位于键合层中，也可以位于电路板中。Referring to FIGS. 8 to 14 , the difference between the board-level system-in-package method of the third embodiment and the first embodiment is that a cavity is provided under the first chip, and the cavity is used as a working cavity of the first chip. The cavity may be located in the bonding layer or in the circuit board.
部分第一芯片30a需要有工作腔，可以在可光刻键合材料20中形成第一空腔21，作为第一芯片30a的工作腔；之后第一芯片30a键合在第一空腔21上，第一空腔21可以为封闭的空腔，可以为非封闭空腔。其中，本实施例中，部分第一芯片30a的下方需要具有空腔，部分第一芯片30的下方不需要空腔。在其他实施例中，也可以是整个电路板上的第一芯片30下方均具有第一空腔，此种情况，需要对每一个第一芯片30对应的可光刻键合材料部分均形成第一空腔。Some of the first chips 30a need to have a working cavity, and a first cavity 21 can be formed in the photolithographic bonding material 20 as a working cavity of the first chip 30a; then the first chip 30a is bonded on the first cavity 21 , the first cavity 21 may be a closed cavity or a non-closed cavity. Wherein, in this embodiment, some of the first chips 30a need to have cavities below, and some of the first chips 30 do not need to have cavities below. In other embodiments, there may be a first cavity under the first chip 30 on the entire circuit board. In this case, it is necessary to form a first cavity for the part of the photolithographic bonding material corresponding to each first chip 30 . a cavity.
在一实施例中，形成在电路板上形成可光刻键合材料后，图形化可光刻键合材料时，不仅暴露出第一焊垫，也形成第一空腔，所述第一芯片键合于所述第一空腔上。其他与实施例相同，在此不做赘述。In one embodiment, after the photolithographic bonding material is formed on the circuit board, when the photolithographic bonding material is patterned, not only the first bonding pad is exposed, but also the first cavity is formed. bonded to the first cavity. Others are the same as the embodiment, and are not repeated here.
当可光刻键合材料形成在第一芯片30上时，可以对第一芯片30上的可光刻键合材料20进行图形化形成第一空腔21。When the photolithographic bonding material is formed on the first chip 30 , the photolithographic bonding material 20 on the first chip 30 may be patterned to form the first cavity 21 .
第一芯片可以是上下均需要空腔的芯片，比如体声波薄膜谐振器；第一芯片也可以是仅需要具有上空腔或下空腔的芯片，比如表面声波谐振器。The first chip may be a chip that needs both upper and lower cavities, such as a bulk acoustic wave thin film resonator; the first chip may also be a chip that only needs an upper cavity or a lower cavity, such as a surface acoustic wave resonator.
参考图8，所述第一芯片30a可以含有第三空腔3011，该第一芯片30a可以为体声波滤波器的FBAR滤波器，其包括谐振结构3013(包括上下电极以及位于上下电极之间的压电膜)以及位于谐振结构两侧的第一空腔21以及第三空腔3011。第一芯片也可以是其他含有空腔的芯片，比如红外热堆传感器。8, the first chip 30a may contain a third cavity 3011, the first chip 30a may be an FBAR filter of a bulk acoustic wave filter, which includes a resonant structure 3013 (including upper and lower electrodes and a cavity between the upper and lower electrodes). piezoelectric film) and the first cavity 21 and the third cavity 3011 on both sides of the resonant structure. The first chip may also be other chips containing cavities, such as an infrared thermopile sensor.
在一实施例中所述第一芯片为射频芯片，用于形成射频模组，其中所述射频芯片包括至少一个滤波器芯片30a，其他射频芯片包括信号放大、信号接收以及信号调谐中的至少一个功能。所述滤波芯片键合于所述电路板后，所述空腔作为滤波器芯片的上空腔。提高所述射频芯片的滤波效果。In an embodiment, the first chip is a radio frequency chip, which is used to form a radio frequency module, wherein the radio frequency chip includes at least one filter chip 30a, and the other radio frequency chips include at least one of signal amplification, signal reception and signal tuning. Function. After the filter chip is bonded to the circuit board, the cavity serves as the upper cavity of the filter chip. The filtering effect of the radio frequency chip is improved.
各个射频芯片之间通过所述电路板10实现电连接，形成射频前端模块内部的信号接收通路和信号发送通路。在一个实施例中，所述信号接收通路可以包括顺次连接的：天线、射频开关、滤波器、低噪声滤波器；所述信号发送通路可以包括顺次连接的：功率放大器、滤波器、射频开关、天线。所述信号接收通路和所述信号发送通路还可以共用所述天线和/或射频开关。Each radio frequency chip is electrically connected through the circuit board 10 to form a signal receiving path and a signal sending path inside the radio frequency front-end module. In one embodiment, the signal receiving path may include sequentially connected: an antenna, a radio frequency switch, a filter, and a low noise filter; the signal transmitting path may include sequentially connected: a power amplifier, a filter, a radio frequency switch, antenna. The signal receiving path and the signal sending path may also share the antenna and/or the radio frequency switch.
在其他实施例中，所述信号接收通路可以包括顺次连接的：天线、射频开关、双工器、低噪声放大器；所述信号发送通路可以包括顺次连接的：功率放大器、双工器、射频开关；所述信号接收通路和信号发送通路共用所述双工器。In other embodiments, the signal receiving path may include sequentially connected: an antenna, a radio frequency switch, a duplexer, and a low noise amplifier; the signal transmitting path may include sequentially connected: a power amplifier, a duplexer, a radio frequency switch; the signal receiving path and the signal sending path share the duplexer.
参考图9、图10，第一芯片30a可以未含第二空腔，比如参考图9可以为表声波滤波器其包括谐振结构3013(包括叉指电极以及压电膜)，比如参考图10，可以为SMR体声波滤波器其包括谐振结构3013(包括上下电极以及位于上下电极之间的压电膜)以及位于谐振结构一侧的第一空腔21以及另一侧的布拉格反射层3014。Referring to FIG. 9 and FIG. 10 , the first chip 30a may not contain the second cavity, for example, referring to FIG. 9 , it may be a surface acoustic wave filter including a resonant structure 3013 (including interdigital electrodes and a piezoelectric film), for example, referring to FIG. 10 , It can be an SMR BAW filter, which includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes), a first cavity 21 on one side of the resonant structure, and a Bragg reflection layer 3014 on the other side.
参考图11，含有空腔21的第一芯片30c，也可以是该空腔21需要与外界环境连通的空腔，比如麦克风传感器，其上空腔需要与外界连通。该实施例中，可以在键合第一芯片之前，在电路板10中的预设位置利用激光切割或机械切割的方式形成通孔211，该通孔211与空腔21连通。该实施 例中，也可以在键合第一芯片之后，在电路板10中的预设位置利用激光切割或机械切割的方式形成通孔211，该通孔211与空腔21连通。Referring to FIG. 11 , the first chip 30c containing the cavity 21 may also be a cavity that the cavity 21 needs to communicate with the external environment, such as a microphone sensor, and the cavity above the cavity needs to communicate with the outside world. In this embodiment, before bonding the first chip, a through hole 211 may be formed at a preset position in the circuit board 10 by means of laser cutting or mechanical cutting, and the through hole 211 communicates with the cavity 21 . In this embodiment, after bonding the first chip, a through hole 211 may be formed at a preset position in the circuit board 10 by means of laser cutting or mechanical cutting, and the through hole 211 communicates with the cavity 21 .
参考图12，该实施例中，所述第一芯片为超声波传感器芯片，用于形成超声波传感器。Referring to FIG. 12 , in this embodiment, the first chip is an ultrasonic sensor chip, which is used to form an ultrasonic sensor.
所述超声波传感芯片301内部形成有谐振腔3011和换能器3012。所述换能器3012用于再电能与机械能量之间进行转换。所述谐振腔3011可以提高超声波传感芯片301的振动幅度，提高转换效率。该实施例中，所述超声波传感芯片301的正面为换能器3012所在表面，所述超声波传感芯片301的正面和背面均形成有第二焊垫31。A resonant cavity 3011 and a transducer 3012 are formed inside the ultrasonic sensor chip 301 . The transducer 3012 is used to convert between electrical and mechanical energy. The resonant cavity 3011 can increase the vibration amplitude of the ultrasonic sensor chip 301 and improve the conversion efficiency. In this embodiment, the front surface of the ultrasonic sensor chip 301 is the surface where the transducer 3012 is located, and the front and back surfaces of the ultrasonic sensor chip 301 are formed with second pads 31 .
所述模数转换芯片302、数字信号处理芯片303用于对所述超声波传感芯片301输出的传感信号进行处理；所述控制芯片304用于控制所述超声波传感芯片301的换能器3012进行振动，产生超声波。The analog-to-digital conversion chip 302 and the digital signal processing chip 303 are used to process the sensing signal output by the ultrasonic sensor chip 301 ; the control chip 304 is used to control the transducer of the ultrasonic sensor chip 301 The 3012 vibrates, producing ultrasonic waves.
将所述超声波传感芯片301以及其他外围芯片与所述电路板10键合，所述第一焊垫11与所述第二焊垫31相对围成空隙。The ultrasonic sensor chip 301 and other peripheral chips are bonded to the circuit board 10 , and the first bonding pad 11 and the second bonding pad 31 are opposite to form a gap.
上述实施例中，由于通过在干膜中形成第一空腔21，则在制造第一芯片30时，则可以无需在第一芯片30a中形成第一空腔，可以节省工艺流程，从而节约成本，提升工艺效率。相对于现有技术而言，通常是盖板侧，盖板形成该空腔21，在有些情形盖板上需要形成电路结构以实现芯片的互连。在该实施例的各种情形中，电路板可以作为盖板，而且，也可以利用电路板中的电连接结构实现第一芯片在盖板一侧的互连，当然，也可以根据实际情况，将第一芯片的互连均在芯片内完成，无需借助电路板，由电路板完成第一芯片与其他芯片之间的互连。In the above embodiment, since the first cavity 21 is formed in the dry film, when the first chip 30 is manufactured, it is not necessary to form the first cavity in the first chip 30a, which can save the process flow and thus save the cost , improve process efficiency. Compared with the prior art, it is usually the cover plate side, the cover plate forms the cavity 21, and in some cases, a circuit structure needs to be formed on the cover plate to realize the interconnection of chips. In various situations of this embodiment, the circuit board can be used as a cover plate, and the electrical connection structure in the circuit board can also be used to realize the interconnection of the first chip on the side of the cover plate. Of course, according to the actual situation, The interconnection of the first chip is all completed in the chip, and the interconnection between the first chip and other chips is completed by the circuit board without the aid of a circuit board.
参考图13，在又一实施例中，键合层内不具有空腔，所述电路板中具有第二空腔18，所述第一芯片位于第二空腔18上方，所述第二空腔18作为第一芯片30a的工作腔。Referring to FIG. 13 , in yet another embodiment, the bonding layer does not have a cavity, the circuit board has a second cavity 18 , the first chip is located above the second cavity 18 , and the second cavity 18 The cavity 18 serves as a working cavity of the first chip 30a.
所述电路板10包括多层板(Multi layer board)。所述多层板包括用于形成第二空腔18的非布线区域10a。所述非布线区域10a用于形成第二空腔18。The circuit board 10 includes a multi-layer board. The multilayer board includes a non-wiring area 10 a for forming the second cavity 18 . The non-wiring area 10 a is used to form the second cavity 18 .
所述第二空腔18形成于电路板10的非布线区域10a中，因此，在所述电路板10的制作过程中，可以不在所述非布线区域10a的部分层数板或全部层数板中制作电路结构，以便于去除非布线区域10a的部分层数板或全部层数板的过程中，能够仅刻蚀绝缘材料而不刻蚀导电材料，相应降低形成空腔18的工艺难度。在其他实施例中，当所述空腔形成于部分厚度的电路板中时，所述空腔底部的剩余层数板中也可以制作电路结构。The second cavity 18 is formed in the non-wiring area 10a of the circuit board 10. Therefore, in the manufacturing process of the circuit board 10, part or all of the non-wiring area 10a may not be part of the multi-layer board or all the multi-layer boards In the process of fabricating the circuit structure in the non-wiring area 10a, only the insulating material can be etched and the conductive material can be etched in the process of removing part or all of the multilayer board in the non-wiring area 10a, which reduces the difficulty of forming the cavity 18 accordingly. In other embodiments, when the cavity is formed in a circuit board with a partial thickness, the circuit structure can also be fabricated in the remaining layers at the bottom of the cavity.
本实施例中，后续将器件晶圆100键合在电路板10上，使得第一器件 晶圆100上的各第一芯片与电路板10相键合，本实施例中，所述第二空腔18作为待键合的第一芯片的功能腔，因此，在制备芯片时，无需完成所有功能腔的制备工艺，有利于降低制备芯片的工艺复杂度，提高芯片制造效率。In this embodiment, the device wafer 100 is subsequently bonded on the circuit board 10, so that each first chip on the first device wafer 100 is bonded to the circuit board 10. In this embodiment, the second space The cavity 18 is used as the functional cavity of the first chip to be bonded. Therefore, when preparing the chip, there is no need to complete the preparation process of all functional cavities, which is beneficial to reduce the process complexity of preparing the chip and improve the chip manufacturing efficiency.
具体地，在所述电路板10中形成第二空腔18的步骤包括：去除所述非布线区域10a的部分层数或全部层数的板，形成第二空腔18。Specifically, the step of forming the second cavity 18 in the circuit board 10 includes: removing part or all of the layers of the non-wiring area 10 a to form the second cavity 18 .
本实施例中，以所述第二空腔18位于部分厚度的所述电路板10中为例，因此，去除所述非布线区域10a的部分层数的板，形成第二空腔18。In this embodiment, the second cavity 18 is taken as an example in the circuit board 10 having a partial thickness. Therefore, the second cavity 18 is formed by removing some layers of the board in the non-wiring area 10a.
本实施例中，采用激光切割工艺，去除所述非布线区域10a的部分层数或全部层数的板，在所述电路板10中形成第二空腔18。In this embodiment, a laser cutting process is used to remove some or all of the layers of the non-wiring area 10 a, and the second cavity 18 is formed in the circuit board 10 .
本实施例中，所述第二空腔18用于作为第一芯片的功能腔，在形成所述第二空腔18的步骤中，所述第二空腔18的底部面积根据第一芯片的性能而定，所述第二空腔18的深度根据第一芯片的性能而定。In this embodiment, the second cavity 18 is used as a functional cavity of the first chip. In the step of forming the second cavity 18, the bottom area of the second cavity 18 is based on the size of the first chip. Depending on the performance, the depth of the second cavity 18 is determined according to the performance of the first chip.
在所述电路板10中形成第二空腔18的过程中，所述第二空腔18位于部分厚度的电路板10中，且在所述正面和背面中的任意一个或两个中对应形成所述空腔18。In the process of forming the second cavity 18 in the circuit board 10, the second cavity 18 is located in the circuit board 10 with a partial thickness, and is correspondingly formed in any one or both of the front and back surfaces the cavity 18.
参考图14，在又一实施例中，所述电路板中具有第二空腔18，所述键合层中具有第一空腔21，所述第二空腔和第一空腔相对并连通，所述第一芯片位于所述第一空腔上方。14, in yet another embodiment, the circuit board has a second cavity 18, the bonding layer has a first cavity 21, the second cavity and the first cavity are opposite and communicate with each other , the first chip is located above the first cavity.
所述第一芯片31a下方的可光刻键合材料20以及电路板10内具有贯通的空腔。可以在对可光刻键合材料层20进行图形化，形成第一空腔21后，沿图形化后的可光刻键合材料层20进一步刻蚀所述电路板，在电路板10内形成第二空腔18，所述第一空腔21和第二空腔18整体作为所述d芯片301a的上腔体。The photolithographic bonding material 20 and the circuit board 10 under the first chip 31a have a through cavity. After patterning the photolithographic bonding material layer 20 to form the first cavity 21 , the circuit board can be further etched along the patterned photolithographic bonding material layer 20 to form the circuit board 10 . The second cavity 18, the first cavity 21 and the second cavity 18 as a whole serve as the upper cavity of the d-chip 301a.
在其他实施例中，也可以先通过图形化在电路板10内形成第二空腔18之后，再在所述电路板10表面形成可光刻键合材料之后，对可光刻键合材料进行图形化，形成第一空腔21，所述第一空腔21和第二空腔18的位置相对，键合后相互贯通。In other embodiments, the second cavity 18 may be formed in the circuit board 10 by patterning, and then the photolithographic bonding material may be formed on the surface of the circuit board 10 . By patterning, a first cavity 21 is formed. The first cavity 21 and the second cavity 18 are located opposite to each other, and pass through each other after bonding.
实施例四Embodiment 4
参考图15至图17，本实施例与实施例一不同之处在于：所述电路板10包括凹槽(图中未标号)，所述凹槽内可以容纳芯片。Referring to FIG. 15 to FIG. 17 , the difference between this embodiment and the first embodiment is that the circuit board 10 includes a groove (not numbered in the figure), and the chip can be accommodated in the groove.
参考图15，所述凹槽内嵌设有第二芯片70，所述第二芯片70表面具有第三焊垫71，所述第三焊垫71与相应第一芯片30的第二焊垫31相对形成所述第一空隙。在该第一空隙内形成导电凸块的形成工艺与第一焊垫和第二焊垫之间的导电凸块工艺相同，而且二者同时形成，在此不做赘述。Referring to FIG. 15 , a second chip 70 is embedded in the groove, and a surface of the second chip 70 has a third pad 71 , and the third pad 71 corresponds to the second pad 31 of the first chip 30 . The first voids are relatively formed. The formation process of forming the conductive bumps in the first gap is the same as the process of forming the conductive bumps between the first bonding pad and the second bonding pad, and the two are formed at the same time, which will not be repeated here.
参考图16，所述电路板中形成有凹槽，所述凹槽的底部形成有第一焊垫，所述第一焊垫凹陷于所述凹槽的底面；所述第一芯片键合于所述凹槽的底面。Referring to FIG. 16 , a groove is formed in the circuit board, a first pad is formed at the bottom of the groove, and the first pad is recessed on the bottom surface of the groove; the first chip is bonded to the bottom surface of the groove.
所述凹槽101内嵌设有第一芯片30，所述凹槽101的底部形成有第一焊垫11，所述第一芯片30的第二焊垫31与第一焊垫11相对形成所述空隙。在该空隙内形成导电凸块的形成工艺与第一焊垫和第二焊垫之间的导电凸块工艺相同，而且二者同时形成，在此不做赘述。且还可以在所述第一芯片30下方的可光刻键合材料内具有第一空腔21，作为所述第一芯片30的上空腔。A first chip 30 is embedded in the groove 101 , a first bonding pad 11 is formed at the bottom of the groove 101 , and a second bonding pad 31 of the first chip 30 is formed opposite to the first bonding pad 11 . said gap. The formation process of forming the conductive bump in the gap is the same as the process of forming the conductive bump between the first bonding pad and the second bonding pad, and the two are formed at the same time, which will not be repeated here. Furthermore, a first cavity 21 may be formed in the photolithographic bonding material below the first chip 30 as an upper cavity of the first chip 30 .
该实施例中，仅以在电路板10正面形成单个凹槽，且第一芯片30设置于所述凹槽101内作为示例。在其他实施例中，所述电路板10的正面和/或背面均可以形成单个或多个凹槽，所述凹槽可以通过刻蚀所述电路板10形成。每个凹槽内可以设置一个或多个射频芯片，所述凹槽的深度可以大于、等于或小于所述射频芯片的厚度。优选的，将厚度较大的射频芯片设置于凹槽内，可以降低整个射频前端模组的厚度。In this embodiment, only a single groove is formed on the front surface of the circuit board 10 and the first chip 30 is disposed in the groove 101 as an example. In other embodiments, single or multiple grooves may be formed on the front and/or back of the circuit board 10 , and the grooves may be formed by etching the circuit board 10 . One or more radio frequency chips may be arranged in each groove, and the depth of the groove may be greater than, equal to or less than the thickness of the radio frequency chip. Preferably, the thickness of the entire RF front-end module can be reduced by arranging the RF chip with a larger thickness in the groove.
参考图17，在又一实施例中，所述第一芯片30键合于凹槽底部和所述电路板10顶面。该种情况适用于位于凹槽中的第一芯片的厚度较厚，而位于电路板顶部的芯片厚度较薄，可以用于降低所形成的封装器件的整体厚度。Referring to FIG. 17 , in yet another embodiment, the first chip 30 is bonded to the bottom of the groove and the top surface of the circuit board 10 . This situation is applicable when the thickness of the first chip located in the groove is relatively thick, while the thickness of the chip located on the top of the circuit board is relatively thin, which can be used to reduce the overall thickness of the formed packaged device.
实施例五Embodiment 5
参考图18、图19，本实施例与实施例一不同的是：所述电路板背面形成有所述第四焊垫；在所述电路板背面的第四焊垫上通过电镀工艺形成第二导电凸块；和/或，将至少一个第一芯片键合于所述电路板背面。Referring to FIG. 18 and FIG. 19 , the difference between this embodiment and the first embodiment is that the fourth pad is formed on the back of the circuit board; a second conductive pad is formed on the fourth pad on the back of the circuit board through an electroplating process bumps; and/or, bonding at least one first chip to the back of the circuit board.
具体为，参考图17，所述电路板10包括相对的正面和背面，所述电路板正面形成有所述第一焊垫11，电路板10的背面还包括第四焊垫16，所述第一焊垫16位于底层板的所述互连结构上与相应所述互连结构电连接，进行所述电镀工艺时，在所述第四焊垫11上形成第二导电凸块80。Specifically, referring to FIG. 17 , the circuit board 10 includes opposite front and back sides, the first pad 11 is formed on the front side of the circuit board, the back side of the circuit board 10 further includes a fourth pad 16 , and the first pad 16 is formed on the front side of the circuit board. A pad 16 is located on the interconnect structure of the bottom board and is electrically connected to the corresponding interconnect structure. During the electroplating process, a second conductive bump 80 is formed on the fourth pad 11 .
所述第四焊垫的暴露出面积为5-200平方微米，在该范围内，焊垫可以与电镀液较充分的接触，避免焊垫与镀液不充分接触而影响导电凸块与焊垫的接触，比如接触面积过小影响电阻，或者，无法接触造成电接触不良。The exposed area of the fourth pad is 5-200 square microns. Within this range, the pad can be in sufficient contact with the electroplating solution to avoid insufficient contact between the pad and the electroplating solution and affect the conductive bumps and pads. For example, the contact area is too small to affect the resistance, or the inability to contact causes poor electrical contact.
另外，如果电路板的背面也粘贴至少一个第一芯片，则第二有机介质层17可以是可光刻键合材料，在此情形下无需单独在粘贴的芯片和电路板之间再形成可光刻键合材料，以节省工艺。In addition, if at least one first chip is also attached to the back of the circuit board, the second organic medium layer 17 can be a photolithographic bonding material, in which case it is not necessary to separately form a photolithographic bonding material between the pasted chip and the circuit board. Engraved bonding material to save process.
当电路板底层即背面形成第二导电凸块时，通常需要在背面形成阻焊 层，阻焊层覆盖电路板底面即背面且暴露出第二导电凸块，确保焊接过程中，在第二导电凸块外周的阻焊层区域不会出现焊接的现象。When the second conductive bumps are formed on the bottom layer of the circuit board, that is, the backside, it is usually necessary to form a solder resist layer on the backside. There is no soldering phenomenon in the solder mask area around the bump.
参考图19，在本发明的以上各个实施例中，仅在电路板的其中一面即顶面上键合了第一芯片，在本实施例中，可以是在电路板的正面键合第一芯片、背面也键合第一芯片，背面第一芯片上的第二焊垫与电路板背面的第四焊垫之间通过第二导电凸块80电连接。所述第一导电凸块40和第二导电凸块80形成的电镀工艺可以同时进行，也可以分别进行；也可以先进行电路板正面的第一芯片键合工艺，之后进行电镀工艺，接着进行电路板背面的第一芯片键合工艺，之后进行电镀工艺。Referring to FIG. 19 , in the above embodiments of the present invention, the first chip is bonded only on one side of the circuit board, that is, the top surface. In this embodiment, the first chip may be bonded on the front side of the circuit board. . The first chip is also bonded on the back side, and the second pad on the back side of the first chip and the fourth pad on the back side of the circuit board are electrically connected through the second conductive bumps 80 . The electroplating process formed by the first conductive bumps 40 and the second conductive bumps 80 may be performed simultaneously or separately; the first chip bonding process on the front side of the circuit board may also be performed first, followed by the electroplating process, followed by the The first die bonding process on the back of the circuit board, followed by the electroplating process.
实施例一中，相关的内容可以援引于此，在此不做赘述。In the first embodiment, the relevant content can be cited here, and details are not repeated here.
该实施例中，电路板的底层可以同现有技术相同，在底面设置阻焊层、阻焊；由于本发明中，第一芯片与电路板的电连接无需通过焊接实现，因此底面可以不设置阻焊层(绿油)，也可以不设置助焊层。底层可以是具有光刻键合特性的第二有机介质层17(参考图16)，第一焊垫11埋设于所述第二有机介质层17且部分暴露在外。当底层是具有光刻键合特性的第二有机介质层时，可以根据需要选择一定厚度的第二有机介质层，方便后续将第一芯片键合至电路板上，无需额外形成键合层，这样可以节省工艺，从而提升电路板的形成效率。底层也可以是第二无机介质层，当底层是无机介质层时，相比有机介质层而言，电镀液在无机介质层上的表面张力小，电镀液更容易进入第一空隙中，提高导电凸块的形成良率；而且，由于无需形成助焊层、阻焊层，这样可以节省工艺，从而提升电路板的形成效率。In this embodiment, the bottom layer of the circuit board can be the same as the prior art, and a solder resist layer and a solder resist are provided on the bottom surface; since in the present invention, the electrical connection between the first chip and the circuit board does not need to be realized by welding, so the bottom surface may not be provided with Solder mask layer (green oil), or no solder flux layer. The bottom layer may be a second organic dielectric layer 17 (refer to FIG. 16 ) with photolithographic bonding properties, and the first pads 11 are buried in the second organic dielectric layer 17 and partially exposed. When the bottom layer is the second organic medium layer with photolithographic bonding characteristics, the second organic medium layer with a certain thickness can be selected according to the needs, so as to facilitate the subsequent bonding of the first chip to the circuit board without additional bonding layers. In this way, processes can be saved, thereby improving the formation efficiency of the circuit board. The bottom layer can also be a second inorganic medium layer. When the bottom layer is an inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is smaller, and the electroplating solution is more likely to enter the first gap and improve the conductivity. The formation yield of bumps; and, since there is no need to form a solder flux layer and a solder resist layer, processes can be saved, thereby improving the formation efficiency of the circuit board.
在其他实施例中，所述电路板10的背面也可以形成有凹槽，所述电路板10背面的第一芯片可以全部或部分设置于所述凹槽内，第一芯片的第二焊垫与凹槽底部的第一焊垫相对形成间隙，在电镀的同时，在所述间隙内形成第一导电凸块。In other embodiments, a groove may also be formed on the back of the circuit board 10 , the first chip on the back of the circuit board 10 may be fully or partially disposed in the groove, and the second pad of the first chip may be disposed in the groove. A gap is formed opposite to the first pad at the bottom of the groove, and a first conductive bump is formed in the gap while electroplating.
在电路板10上可以同时键合多个第一芯片芯片，后续可以通过将电路板进行切割，将各个第一封装结构进行分割。如此，可以提高封装效率。A plurality of first chips may be bonded on the circuit board 10 at the same time, and subsequently, the respective first package structures may be divided by cutting the circuit board. In this way, packaging efficiency can be improved.
实施例六Embodiment 6
参考图20，本实施例与前述实施例的不同之处在于：在第一芯片上堆叠有第三芯片，所述第一芯片与第三芯片之间通过电镀的第三导电凸块电连接。Referring to FIG. 20 , the difference between the present embodiment and the previous embodiments is that a third chip is stacked on the first chip, and the first chip and the third chip are electrically connected by plated third conductive bumps.
实施例六中，所述第一芯片30的另一面形成有第五焊垫32，所述第五焊垫与第二焊垫分别位于第一芯片相对的表面，在将第一芯片30键合在电路板上之后，可以在第二芯片30上键合第三芯片33，键合可以采用可光刻键合材料20，比如干膜；所述第三芯片33含有第六焊垫34，所述第 五焊垫与所述第六焊垫之间形成第二空隙；通过电镀工艺在所述第二空隙形成第三导电凸块35。In the sixth embodiment, a fifth bonding pad 32 is formed on the other side of the first chip 30, and the fifth bonding pad and the second bonding pad are respectively located on the opposite surfaces of the first chip. After the circuit board, a third chip 33 can be bonded on the second chip 30, and the bonding can be made of a photolithographic bonding material 20, such as a dry film; the third chip 33 contains a sixth pad 34, so A second space is formed between the fifth bonding pad and the sixth bonding pad; and a third conductive bump 35 is formed in the second space through an electroplating process.
形成第三导电凸块35的工艺可以同形成第一导电凸块40的形成工艺。The process of forming the third conductive bumps 35 may be the same as the forming process of forming the first conductive bumps 40 .
本实施例中，先将第一芯片键合于电路板，之后将第三芯片键合于第一芯片，之后进行电镀工艺形成第一导电凸块40和第三导电凸块34；在其他实施例中，可以先将第一芯片与第三芯片键合在一起之后，再将键合再一起的第一芯片与第三芯片一起键合在电路板上；然后进行电镀工艺。在其他实施例中，所述导电凸块也可以通过多次形成，例如将第一芯片与第一芯片之间的第一导电凸块和芯片与电路板之间的第三导电凸块分两次形成。In this embodiment, the first chip is first bonded to the circuit board, and then the third chip is bonded to the first chip, and then an electroplating process is performed to form the first conductive bumps 40 and the third conductive bumps 34; in other implementations In an example, after the first chip and the third chip are bonded together, the first chip and the third chip that are bonded together can be bonded together on the circuit board; and then the electroplating process is performed. In other embodiments, the conductive bumps can also be formed multiple times, for example, the first conductive bumps between the first chip and the first chip and the third conductive bumps between the chips and the circuit board are divided into two parts secondary formation.
第三芯片与第一芯片之间的键合方式以及工艺可以参考第一芯片与电路板之间的键合方式以及工艺，在此不做赘述。关于第二空隙的大小、高度等的设置可以参考第一实施例；关于第五焊垫与第六焊垫的大小、面积、相互位置关系等可以参考第一焊垫与第二焊垫的设置。For the bonding method and process between the third chip and the first chip, reference may be made to the bonding method and process between the first chip and the circuit board, and details are not described here. For the setting of the size, height, etc. of the second gap, reference may be made to the first embodiment; for the size, area, mutual positional relationship, etc. of the fifth pad and the sixth pad, reference may be made to the setting of the first pad and the second pad .
其中，图20中示意第二焊垫31与第五焊垫32之间通过TSV互连，但本实施例中，不限于此种情形，第二焊垫31与第五焊垫32之间可以通过其他的互连方式实现电连接，比如第二焊垫31与相应的第五焊垫32之间通过互连线和插塞实现电连接。20 shows that the second bonding pad 31 and the fifth bonding pad 32 are interconnected by TSV, but in this embodiment, it is not limited to this situation, and the second bonding pad 31 and the fifth bonding pad 32 may be connected The electrical connection is achieved by other interconnection methods, for example, the electrical connection between the second pad 31 and the corresponding fifth pad 32 is achieved by interconnecting wires and plugs.
在其他实施例中，仅部分第一芯片堆叠设置；或者，在电路板正面和背面均有堆叠设置的第一芯片。In other embodiments, only part of the first chips are stacked; or, there are stacked first chips on both the front and the back of the circuit board.
本发明的实施例一至实施例六阐述了各种具体的情形，其中实施例一至实施例六阐述的各种情形可以根据需要进行相应的组合形成新的实施例。在本发明中不做一一阐述，本领域技术人员根据本发明的教导可以得出不同于实施例一至实施例六所列情形的具体实施例。Embodiments 1 to 6 of the present invention describe various specific situations, wherein various situations described in Embodiments 1 to 6 can be combined to form new embodiments as required. The present invention will not describe them one by one, and those skilled in the art can obtain specific embodiments that are different from the situations listed in Embodiments 1 to 6 according to the teachings of the present invention.
实施例七Embodiment 7
参考图21，本实施例中，所述第一芯片为图像传感芯片，用于形成摄像头模组，所述第一芯片包括图像传感芯片以及外围芯片。Referring to FIG. 21 , in this embodiment, the first chip is an image sensor chip, which is used to form a camera module, and the first chip includes an image sensor chip and a peripheral chip.
所述图像传感芯片可以包括：CCS图像传感芯片、SSD图像传感芯片中的至少一种，正面形成有光学传感阵列3011。The image sensor chip may include at least one of a CCS image sensor chip and an SSD image sensor chip, and an optical sensor array 3011 is formed on the front side.
所述图像处理芯片可以包括：读取电路芯片、模拟信号处理芯片、模数转换芯片、以及数字逻辑芯片等各种功能芯片中的至少一种或几种芯片的集成，用于对所述图像传感芯片301输出的光学传感信号进行处理，形成图像信号。该实施例中，将多个功能芯片电路集成于一个图像传感芯片301内。在其他实施例中，可以包括多个图像处理芯片301，每个图像处理芯片包括一个或多个功能电路，例如包括模数转换芯片、模拟信号处理芯 片等。在一些实施例中，部分电路还可以集成于所述图像传感芯片301内，例如读取电路等。The image processing chip may include: a reading circuit chip, an analog signal processing chip, an analog-to-digital conversion chip, and an integration of at least one or several of various functional chips, such as a digital logic chip, for processing the image. The optical sensing signal output by the sensing chip 301 is processed to form an image signal. In this embodiment, multiple functional chip circuits are integrated into one image sensor chip 301 . In other embodiments, multiple image processing chips 301 may be included, and each image processing chip includes one or more functional circuits, such as an analog-to-digital conversion chip, an analog signal processing chip, and the like. In some embodiments, some circuits may also be integrated in the image sensor chip 301, such as a reading circuit and the like.
在其他实施例中，所述摄像头还可以包括两个以上的图像传感芯片301和多个图像处理芯片302。本实施例中，仅示出单个图像传感芯片301以及单个图像处理芯片302作为示例。In other embodiments, the camera may further include more than two image sensor chips 301 and multiple image processing chips 302 . In this embodiment, only a single image sensor chip 301 and a single image processing chip 302 are shown as examples.
该实施例中，还提供存储芯片303和驱动芯片304，用于作为所述图像传感芯片301的光传感信号的数据缓存，数据处理的速度。所述存储芯片303可以为DRAM存储芯片，具有较高的数据传输带宽和效率。所述驱动芯片用于驱动摄像头的镜头透镜移动，以调整摄像头的焦距。In this embodiment, a memory chip 303 and a driving chip 304 are also provided, which are used as data buffers for the light sensing signals of the image sensing chip 301, and the speed of data processing. The memory chip 303 may be a DRAM memory chip, which has high data transmission bandwidth and efficiency. The driving chip is used to drive the lens of the camera to move, so as to adjust the focal length of the camera.
将所述图像传感芯片301、图像处理芯片302、存储芯片303和驱动芯片304与所述电路板10键合，所述第一焊垫11与所述第二焊垫31相对围成空隙。The image sensor chip 301 , the image processing chip 302 , the memory chip 303 and the driving chip 304 are bonded to the circuit board 10 , and the first pad 11 and the second pad 31 are opposite to form a gap.
提供光学镜头50，所述光学镜头50包括透镜51以及连接所述透镜的电机52；将所述光学镜头50通过支撑件53键合于所述电路板10上，所述支撑件53围绕所述图像传感芯片301设置，所述图像传感芯片301的正面朝向所述透镜51。所述支撑件51内侧固定有滤光片54，所述滤光片54位于所述透镜51与所述图像传感芯片301之间。An optical lens 50 is provided, and the optical lens 50 includes a lens 51 and a motor 52 connected to the lens; the optical lens 50 is bonded to the circuit board 10 through a support 53, and the support 53 surrounds the The image sensor chip 301 is disposed, and the front surface of the image sensor chip 301 faces the lens 51 . A filter 54 is fixed on the inner side of the support member 51 , and the filter 54 is located between the lens 51 and the image sensor chip 301 .
所述支撑件53可以为圆筒状，通过粘胶或可光刻键合材料键合于所述图像传感芯片301的外围，与所述电路板10之间形成腔体，所述图像传感芯片301位于所述腔体内。The support member 53 may be cylindrical, and is bonded to the periphery of the image sensor chip 301 by adhesive or photolithographic bonding material, forming a cavity between the support member 53 and the circuit board 10 . The sensor chip 301 is located in the cavity.
所述电机52固定于所述支撑件与所述透镜51之间，用于驱动所述透镜51移动，调整摄像头的焦距。所述电机52可以为音圈马达、步进马达等驱动马达。所述电机52通过所述电路板10连接至所述驱动芯片304，由所述驱动芯片304驱动所述电机52。The motor 52 is fixed between the support and the lens 51, and is used to drive the lens 51 to move and adjust the focal length of the camera. The motor 52 may be a driving motor such as a voice coil motor, a stepping motor, or the like. The motor 52 is connected to the driving chip 304 through the circuit board 10 , and the motor 52 is driven by the driving chip 304 .
摄像头内各个芯片及部件之间通过所述电路板10实现电连接，所述图像传感芯片301连接至所述存储芯片303，所述图形处理芯片302连接至所述存储芯片303，所述驱动芯片304连接至所述电机52。图21中电路板10内的连接关系仅作为示意，并不代表芯片之间的真实的连接关系。The various chips and components in the camera are electrically connected through the circuit board 10, the image sensor chip 301 is connected to the memory chip 303, the graphics processing chip 302 is connected to the memory chip 303, the driver Chip 304 is connected to the motor 52 . The connection relationship in the circuit board 10 in FIG. 21 is only for illustration, and does not represent the actual connection relationship between chips.
将滤光片54直接键合于所述图像传感芯片301表面。具体的，首先将滤光片54键合于所述图像传感芯片301上后，再将所述图像传感芯片301键合于所述电路板10表面。可以在图像传感芯片301正面形成键合层，例如可光刻键合材料20；再对所述键合层图形化形成空腔21，之后将滤光片键合在空腔21上，使得图像传感芯片301、滤光片54以及可光刻键合材料20之间围成密闭腔体，所述密闭腔体可以保护所述图像传感芯片301的传感面不受外接环境影响。The filter 54 is directly bonded to the surface of the image sensor chip 301 . Specifically, the filter 54 is first bonded to the image sensor chip 301 , and then the image sensor chip 301 is bonded to the surface of the circuit board 10 . A bonding layer can be formed on the front side of the image sensor chip 301, for example, the bonding material 20 can be photoetched; then the bonding layer is patterned to form a cavity 21, and then the filter is bonded on the cavity 21, so that A sealed cavity is formed between the image sensor chip 301 , the filter 54 and the photolithographic bonding material 20 , and the sealed cavity can protect the sensing surface of the image sensor chip 301 from being affected by the external environment.
当键合层，例如可光刻键合材料20，形成在滤光片54上时，可以对芯片上的可光刻键合材料20进行图形化形成空腔21，后再将所述滤光片54键合于所述图像传感芯片301上。When the bonding layer, such as the photolithographic bonding material 20, is formed on the filter 54, the photolithographic bonding material 20 on the chip can be patterned to form the cavity 21, and then the filter The sheet 54 is bonded to the image sensor chip 301 .
所述图像传感芯片301、图像处理芯片302、存储芯片303和驱动芯片304可以位于电路板10的正面和背面，按照功能合理设置。也可以在电路板10内形成凹槽，图像传感芯片301位于凹槽内，滤波片键合在电路板10表面，光学镜头50设置在滤光片上方。The image sensor chip 301 , the image processing chip 302 , the storage chip 303 and the driver chip 304 can be located on the front and back of the circuit board 10 and are reasonably arranged according to their functions. A groove may also be formed in the circuit board 10, the image sensor chip 301 is located in the groove, the filter is bonded on the surface of the circuit board 10, and the optical lens 50 is disposed above the filter.
请参考图21a，该实施例中，在所述电路板10背面上焊接柔性电路板1000。具体的，该实施例中，将外围芯片均键合与电路板10的正面，将柔性电路板1000键合于所述电路板100的背面。所述柔性电路板1000表面具有焊垫1001，通过可光刻键合材料20将所述柔性电路板1000键合于所述电路板10背面，所述柔性电路板1000表面的焊垫1001与电路板10背面的第一焊垫之间形成空隙，再通过电镀，在所述空隙内形成第一导电凸块40。Referring to FIG. 21 a , in this embodiment, a flexible circuit board 1000 is soldered on the back of the circuit board 10 . Specifically, in this embodiment, the peripheral chips are bonded to the front side of the circuit board 10 , and the flexible circuit board 1000 is bonded to the back side of the circuit board 100 . The surface of the flexible circuit board 1000 has solder pads 1001, and the flexible circuit board 1000 is bonded to the back of the circuit board 10 through a photolithographic bonding material 20. The solder pads 1001 on the surface of the flexible circuit board 1000 are connected to the circuit A space is formed between the first pads on the backside of the board 10, and then first conductive bumps 40 are formed in the space by electroplating.
该实施例中，所述电路板10具有相对的正面和背面，在所述电路板10的正面形成第一凹槽102，背面形成第二凹槽103，内部形成贯穿所述第一凹槽102和第二凹槽103的透光孔104；将所述图像传感芯片301的正面朝向所述第二凹槽103的底部，键合于所述第二凹槽103底部；将滤光片54键合于所述第一凹槽102底部表面，所述透光孔104位于所述滤光片54和所述图像传感芯片301正面之间的透光通路上。In this embodiment, the circuit board 10 has opposite fronts and backs, a first groove 102 is formed on the front of the circuit board 10 , a second groove 103 is formed on the back, and a first groove 102 is formed inside. and the light-transmitting hole 104 of the second groove 103; the front surface of the image sensor chip 301 faces the bottom of the second groove 103, and is bonded to the bottom of the second groove 103; the filter 54 Bonded to the bottom surface of the first groove 102 , the light-transmitting hole 104 is located on the light-transmitting path between the filter 54 and the front surface of the image sensor chip 301 .
所述光学镜头50通过支撑件53固定于所述电路板10表面，所述滤光片54位于所述透镜51下方。The optical lens 50 is fixed on the surface of the circuit board 10 by a support member 53 , and the filter 54 is located under the lens 51 .
在其他实施例中，还可以将所述滤光片54键合于所述第一凹槽102顶部边缘的电路板10上。In other embodiments, the optical filter 54 can also be bonded to the circuit board 10 on the top edge of the first groove 102 .
由于将图像传感芯片301键合于电路板10背面的第二凹槽103内，电路板10的正面所在侧为进光侧，因此，图像传感芯片301的正面朝向所述第二凹槽103的底部，可以直接通过所述图像传感芯片301正面作为键合面，在正面的第二焊垫与所述第二凹槽103底部的焊垫之间通过电镀形成的第一导电凸块形成电连接，无需在所述图像传感芯片301的背面形成焊垫，从而可以简化所述图像传感芯片301的结构。Since the image sensor chip 301 is bonded in the second groove 103 on the back of the circuit board 10 , the front side of the circuit board 10 is the light entrance side, so the front side of the image sensor chip 301 faces the second groove The bottom of 103 can directly use the front surface of the image sensor chip 301 as a bonding surface, and the first conductive bumps formed by electroplating between the second pads on the front and the pads at the bottom of the second groove 103 To form electrical connections, it is not necessary to form bonding pads on the backside of the image sensor chip 301 , so that the structure of the image sensor chip 301 can be simplified.
可以在将各芯片、柔性电路板1000均键合与所述电路板10上后，再通过电镀同时形成各个位置处的第一导电凸块40和第二导电凸块80。在其他实施例中，还可以对所述芯片和所述柔性电路板分别进行键合和电镀工艺。所述柔性电路板1000还可以键合于所述电路板10的正面。After each chip and the flexible circuit board 1000 are bonded to the circuit board 10 , the first conductive bumps 40 and the second conductive bumps 80 at each position can be simultaneously formed by electroplating. In other embodiments, bonding and electroplating processes may also be performed on the chip and the flexible circuit board, respectively. The flexible circuit board 1000 may also be bonded to the front surface of the circuit board 10 .
实施例一至实施例六中的各项特征及其组合，均可以通过合理设置应 用于实施例七中，以形成符合需求的摄像头模组，在本发明中不做一一阐述。The features and combinations thereof in the first embodiment to the sixth embodiment can all be applied in the seventh embodiment through reasonable setting, so as to form a camera module that meets the requirements, and will not be elaborated one by one in the present invention.
实施例八Embodiment 8
参考图22图至图24，本实施例与实施例一的不同之处在于：第一芯片键合时的状态不同。本实施例中，所述多个第一芯片位于第一器件晶圆内，以晶圆的状态键合于所述电路板上。Referring to FIG. 22 to FIG. 24 , the difference between this embodiment and the first embodiment is that the state of the first chip bonding is different. In this embodiment, the plurality of first chips are located in the first device wafer, and are bonded to the circuit board in the state of wafers.
本实施例中，提供多个第一芯片30的步骤包括：提供第一器件晶圆100，第一器件晶圆100中形成有多个第一芯片30，所述第一芯片30的其中一表面形成有第二焊垫31，所述第二焊垫31凹陷于所述第一芯片30的表面。In this embodiment, the step of providing a plurality of first chips 30 includes: providing a first device wafer 100 , a plurality of first chips 30 are formed in the first device wafer 100 , and one surface of the first chips 30 is A second bonding pad 31 is formed, and the second bonding pad 31 is recessed on the surface of the first chip 30 .
本实施例提供一种板级系统级封装方法，包括：提供电路板，作为载板，所述电路板表面形成有多个第一焊垫，所述第一焊垫凹陷于所述电路板表面；提供第一器件晶圆，所述第一器件晶圆中形成有多个第一芯片，所述第一芯片的其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述第一芯片的表面；将所述第一器件晶圆键合于所述电路板上，所述第一焊垫与第二焊垫相对围成第一空隙；通过电镀工艺，在所述第一空隙中形成第一导电凸块，所述第一导电凸块电连接所述第一焊垫和第二焊垫；形成所述第一导电凸块后，对所述第一器件晶圆进行晶圆切割，将所述第一芯片相互分割开。This embodiment provides a board-level system-in-package method, including: providing a circuit board as a carrier board, a plurality of first bonding pads are formed on the surface of the circuit board, and the first bonding pads are recessed on the surface of the circuit board A first device wafer is provided, a plurality of first chips are formed in the first device wafer, a second pad is formed on one surface of the first chip, and the second pad is recessed in the The surface of the first chip; the first device wafer is bonded to the circuit board, and the first pad and the second pad are opposite to form a first gap; through the electroplating process, on the first A first conductive bump is formed in the gap, and the first conductive bump is electrically connected to the first pad and the second pad; after the first conductive bump is formed, the first device wafer is crystallized Circular cutting to separate the first chips from each other.
参考图22，提供电路板10；提供第一器件晶圆100，第一器件晶圆100中形成有多个第一芯片30，所述第一芯片30的其中一表面形成有第二焊垫31，所述第二焊垫31凹陷于所述第一芯片30的表面。Referring to FIG. 22 , a circuit board 10 is provided; a first device wafer 100 is provided, and a plurality of first chips 30 are formed in the first device wafer 100 , and a second pad 31 is formed on one surface of the first chips 30 , the second pad 31 is recessed on the surface of the first chip 30 .
所述电路板10用于支撑和固定多个不同的电路元件，还用于实现电路元件之间的电连接。本实施例中，所述电路板10作为后续封装工艺的载板，也就是说，后续的封装工艺需要在适用于电路板10的工艺环境中完成，且后续的封装工艺需要使用适用于电路板10的工艺设备和产线。相应的，所述封装降低了对生产环境的要求，例如，可以不在无尘间进行后续的封装工艺，封装工艺可以在普通车间的环境下进行。The circuit board 10 is used for supporting and fixing a plurality of different circuit elements, and also for realizing the electrical connection between the circuit elements. In this embodiment, the circuit board 10 is used as a carrier for the subsequent packaging process, that is to say, the subsequent packaging process needs to be completed in a process environment suitable for the circuit board 10, and the subsequent packaging process needs to be used for the circuit board. 10 process equipment and production lines. Correspondingly, the encapsulation reduces the requirements on the production environment, for example, the subsequent encapsulation process may not be performed in a clean room, and the encapsulation process may be performed in the environment of a common workshop.
第一器件晶圆100用于与电路板10键合在一起。其中，第一芯片30之间的还包括切割道(未标示)，切割道所在的区域为切割区30a，切割道为后续进行晶圆切割的位置。本实施例中，电路板10与第一器件晶圆100均为圆形。圆形的电路板10能够适用于半导体前道工艺中的设备，与设备和工艺兼容性强。在其他实施例中，电路板也可以为多边形，多边形包括：方形、五边形、六边形、八边形等。The first device wafer 100 is used for bonding with the circuit board 10 . Wherein, between the first chips 30 further includes a dicing lane (not marked), the area where the dicing lane is located is the dicing area 30a, and the dicing lane is the position where the wafer is subsequently cut. In this embodiment, the circuit board 10 and the first device wafer 100 are both circular. The circular circuit board 10 can be applied to the equipment in the semiconductor front-end process, and has strong compatibility with the equipment and the process. In other embodiments, the circuit board may also be a polygon, and the polygon includes a square, a pentagon, a hexagon, an octagon, and the like.
继续参考图22，将第一器件晶圆100键合于所述电路板10上，所述 第一焊垫11与第二焊垫31相对围成第一空隙32。Continuing to refer to FIG. 22 , the first device wafer 100 is bonded to the circuit board 10 , and the first bonding pads 11 and the second bonding pads 31 are opposite to form a first gap 32 .
具体为，通过键合层将第一器件晶圆100键合于电路板10上，键合层避开第一焊垫11和第二焊垫31设置。Specifically, the first device wafer 100 is bonded to the circuit board 10 through a bonding layer, and the bonding layer is disposed away from the first pad 11 and the second pad 31 .
参考图23，通过电镀工艺，在所述第一空隙32中形成第一导电凸块40，所述第一导电凸块40电连接所述第一焊垫11和第二焊垫31。Referring to FIG. 23 , through an electroplating process, first conductive bumps 40 are formed in the first voids 32 , and the first conductive bumps 40 are electrically connected to the first pads 11 and the second pads 31 .
所述电镀工艺的相关参数参考前述实施例所述。The relevant parameters of the electroplating process are described with reference to the foregoing embodiments.
参考图24，本实施例中，形成所述第一导电凸块40后，对所述第一器件晶圆100进行晶圆切割，将所述第一芯片30相互分割开。Referring to FIG. 24 , in this embodiment, after the first conductive bumps 40 are formed, wafer dicing is performed on the first device wafer 100 to separate the first chips 30 from each other.
本实施例中，所述电路板10作为载板，因此，电路板10为进行晶圆切割提供了工艺平台。具体的，对所述第一器件晶圆100的切割区100a进行切割，形成多个待封装的结构。In this embodiment, the circuit board 10 is used as a carrier board. Therefore, the circuit board 10 provides a process platform for wafer cutting. Specifically, the cutting area 100a of the first device wafer 100 is cut to form a plurality of structures to be packaged.
本实施例中，采用刀片切割(blade saw)或激光切割沿切割道对所述第一器件晶圆100的切割区处进行切割。需要说明的是，对所述第一器件晶圆100的切割区100a进行切割的过程中，电路板10作为载板，切割工艺过程需要使用制备电路板10的工艺机器和产线即可，无需在无尘间中进行，普通生产车间的环境即可，有利于简化对第一器件晶圆100进行切割的工艺步骤，降低生产成本。In this embodiment, blade saw or laser cutting is used to cut the cutting area of the first device wafer 100 along the cutting line. It should be noted that, in the process of cutting the cutting area 100a of the first device wafer 100, the circuit board 10 is used as a carrier board, and the cutting process needs to use the process machine and production line for preparing the circuit board 10, and no need It is performed in a clean room, and the environment of an ordinary production workshop is sufficient, which is beneficial to simplify the process steps of cutting the first device wafer 100 and reduce the production cost.
先将第一器件晶圆100整体键合在电路板上，最后对第一器件晶圆100进行切割，实现各芯片相互分割的效果，与将各芯片逐步键合在电路板上的方案相比，实现了晶圆级封装的效果，进一步简化了工艺流程，提高了封装效率。First, the first device wafer 100 is integrally bonded to the circuit board, and finally the first device wafer 100 is cut to achieve the effect of dividing the chips from each other. Compared with the scheme of bonding the chips on the circuit board step by step , achieves the effect of wafer-level packaging, further simplifies the process flow, and improves packaging efficiency.
本实施例中，所述板级系统级封装方法还包括：在对第一器件晶圆100进行晶圆切割之后，形成塑封层50，覆盖第一芯片30和电路板10。所述塑封层50用于实现第一芯片30与电路板10的封装集成。In this embodiment, the board-level system-in-package method further includes: after wafer dicing the first device wafer 100 , forming a plastic sealing layer 50 to cover the first chip 30 and the circuit board 10 . The plastic sealing layer 50 is used to realize the packaging integration of the first chip 30 and the circuit board 10 .
上述实施例一至七中的各项技术特征及其组合，本领域技术人员，可以根据上述实施例中的描述，进行合理的方案组合，应用于本实施例中以形成其他结构的封装器件，均在本发明的保护范围内。The technical features and their combinations in the above-mentioned embodiments 1 to 7, those skilled in the art can make a reasonable combination of solutions according to the descriptions in the above-mentioned embodiments, and apply them to this embodiment to form packaged devices of other structures. within the protection scope of the present invention.
实施例九Embodiment 9
参考图25至图27，实施例九的板级系统级封装的方法与实施例八的差异在于：第一芯片下方具有空腔，所述空腔作为第一芯片的工作腔。本实施例中，关于空腔的设置均适用于实施例四中所述。Referring to FIG. 25 to FIG. 27 , the difference between the board-level system-in-package method of the ninth embodiment and the eighth embodiment is that a cavity is provided under the first chip, and the cavity is used as a working cavity of the first chip. In this embodiment, the settings of the cavity are all applicable to those described in the fourth embodiment.
在实施例九中，参考图25，部分第一芯片30a需要有工作腔，可以在可光刻键合材料20中形成第一空腔21，作为第一芯片30a的工作腔。所述第一芯片30a可以含有第三空腔3011，该第一芯片30a可以为体声波滤波器的FBAR滤波器。In the ninth embodiment, referring to FIG. 25 , some of the first chips 30a need to have a working cavity, and a first cavity 21 may be formed in the photolithographic bonding material 20 as a working cavity of the first chip 30a. The first chip 30a may contain a third cavity 3011, and the first chip 30a may be an FBAR filter of a bulk acoustic wave filter.
参考图26，在又一实施例中，第一器件晶圆与电路板通过键合层键合，键合层内不具有空腔，所述电路板中具有第二空腔18，所述第一芯片位于第二空腔上方，所述第二空腔18作为第一芯片30a的工作腔。Referring to FIG. 26, in yet another embodiment, the first device wafer and the circuit board are bonded through a bonding layer, the bonding layer does not have a cavity, the circuit board has a second cavity 18, and the second cavity 18 is formed in the circuit board. A chip is located above the second cavity, and the second cavity 18 serves as the working cavity of the first chip 30a.
参考图27，在又一实施例中，第一器件晶圆与电路板通过键合层键合，所述电路板中具有第二空腔18，所述键合层中具有第一空腔21，所述第二空腔和第一空腔相对并连通，所述第一芯片位于所述第一空腔上方。Referring to FIG. 27 , in yet another embodiment, the first device wafer and the circuit board are bonded through a bonding layer, the circuit board has a second cavity 18 therein, and the bonding layer has a first cavity 21 therein , the second cavity is opposite to and communicated with the first cavity, and the first chip is located above the first cavity.
实施例十Embodiment ten
本实施例与前述实施例八的不同之处在于：在所述电路板10相对的两个面上均键合第一器件晶圆100。The difference between this embodiment and the foregoing eighth embodiment is that the first device wafer 100 is bonded on two opposite surfaces of the circuit board 10 .
实施例五中的第一芯片的双面设置均适用于本实施例中。The double-sided arrangement of the first chip in the fifth embodiment is applicable to this embodiment.
进一步，参考图28，所述电路板10包括相对的正面和背面，所述正面和背面均形成有所述第一焊垫11；在所述电路板10的正面的第一焊垫11上通过电镀工艺形成第一导电凸块40；在所述电路板10背面的第一焊垫上通过电镀工艺形成第二导电凸块80；将含有至少一个第一芯片30的第一器件晶圆100键合于所述电路板背面。Further, referring to FIG. 28 , the circuit board 10 includes opposite front and back surfaces, and the first pads 11 are formed on both the front and the back; The first conductive bumps 40 are formed by an electroplating process; the second conductive bumps 80 are formed on the first pads on the back of the circuit board 10 by an electroplating process; the first device wafer 100 containing at least one first chip 30 is bonded on the back of the circuit board.
在第一空隙中形成第一导电凸块40的过程中，还在电路板10的第二表面形成第二导电凸块80。During the process of forming the first conductive bumps 40 in the first voids, the second conductive bumps 80 are also formed on the second surface of the circuit board 10 .
在其他实施例中，还可以在不同步骤中，分别通过两次进行的电镀工艺，在位于电路板第一表面一侧的第一空隙中形成第一导电凸块、以及在位于电路板的第二表面一侧的第一空隙中形成第一导电凸块。其中，在形成位于电路板的其中一面的第一导电凸块后，可以在已形成第一导电凸块的一面形成覆盖电路板、第一芯片和第一导电凸块的塑封层或保护层，覆盖已形成的第一导电凸块，防止该面的第一导电凸块在电路板另一表面进行的电镀工艺中受到影响。In other embodiments, the first conductive bumps may be formed in the first voids on the side of the first surface of the circuit board, and the first conductive bumps may be formed in the first voids on the first surface of the circuit board, and the first conductive bumps may be formed on the first surface of the circuit board through two electroplating processes in different steps. A first conductive bump is formed in the first void on one side of the two surfaces. Wherein, after the first conductive bumps on one side of the circuit board are formed, a plastic encapsulation layer or protective layer covering the circuit board, the first chip and the first conductive bumps can be formed on the side where the first conductive bumps have been formed, Covering the formed first conductive bumps prevents the first conductive bumps on the surface from being affected during the electroplating process performed on the other surface of the circuit board.
形成所述第一导电凸块40和第二导电凸块80后，对所述第一器件晶圆进行晶圆100切割，将所述第一芯片30相互分割开。After the first conductive bumps 40 and the second conductive bumps 80 are formed, the wafer 100 is diced on the first device wafer to separate the first chips 30 from each other.
其他实施例中，也可以仅在电路板10的第二表面形成第二导电凸块80。形成第一导电凸块40和第二导电凸块80后，对第一器件晶圆进行晶圆100切割，将第一芯片30相互分割开。In other embodiments, the second conductive bumps 80 may be formed only on the second surface of the circuit board 10 . After the first conductive bumps 40 and the second conductive bumps 80 are formed, the wafer 100 is diced on the first device wafer to separate the first chips 30 from each other.
实施例十一 Embodiment 11
本实施例与前述实施例八的不同之处在于：所述封装方法实现三维封装(3D package)，即在第一器件晶圆上键合第二器件晶圆，所述第二器件晶圆内具有多个第三芯片；第一器件晶圆和第二器件晶圆键合后，第二器件晶圆内的第三芯片堆叠在第一器件晶圆内的第一芯片上方，实现芯片的堆叠。实施例六中的第一芯片的堆叠设置均适用于本实施例中。The difference between this embodiment and the previous eighth embodiment is that the packaging method realizes three-dimensional packaging (3D package), that is, a second device wafer is bonded on the first device wafer, and the second device wafer is inside the second device wafer. There are a plurality of third chips; after the first device wafer and the second device wafer are bonded, the third chip in the second device wafer is stacked above the first chip in the first device wafer to realize the stacking of chips . The stacking arrangements of the first chips in the sixth embodiment are all applicable to this embodiment.
参考图29，所述提供第一器件晶圆100的步骤中，第一芯片30具有相背的第三表面301和第四表面302，第二焊垫31位于第三表面301一侧且凹陷于第三表面301，第一芯片30还包括第五焊垫36，第五焊垫36位于第四表面302一侧且凹陷于第四表面302，第五焊垫36和第二焊垫31之间实现电连接。Referring to FIG. 29, in the step of providing the first device wafer 100, the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, and the second pad 31 is located on one side of the third surface 301 and is recessed in The third surface 301 , the first chip 30 further includes a fifth bonding pad 36 , the fifth bonding pad 36 is located on one side of the fourth surface 302 and is recessed in the fourth surface 302 , between the fifth bonding pad 36 and the second bonding pad 31 Make electrical connections.
本实施例中，所述第一芯片30中形成有通孔互连结构33，所述通孔互连结构34朝向所述第三表面301的一端与所述第二焊垫31连接，所述通孔互连结构33朝向所述第四表面302的一端与第五焊垫36连接。具体地，通孔互连结构33为硅通孔(Through Silicon Via，TSV)互连结构。In this embodiment, a via interconnect structure 33 is formed in the first chip 30 , and an end of the via interconnect structure 34 facing the third surface 301 is connected to the second pad 31 , and the via interconnect structure 34 is connected to the second pad 31 . One end of the via interconnect structure 33 facing the fourth surface 302 is connected to the fifth pad 36 . Specifically, the through hole interconnection structure 33 is a Through Silicon Via (TSV) interconnection structure.
本实施例中，第四表面302形成有第三有机介质层37或第三无机介质层，第五焊垫36埋设于第三有机介质层37或第三无机介质层中且部分暴露在外。对第三有机介质层37和第三无机介质层的具体描述，可分别参考前述实施例中对第一有机介质层和第二无机介质层的描述，在此不再赘述。In this embodiment, the fourth surface 302 is formed with a third organic medium layer 37 or a third inorganic medium layer, and the fifth pad 36 is buried in the third organic medium layer 37 or the third inorganic medium layer and partially exposed. For the specific description of the third organic medium layer 37 and the third inorganic medium layer, reference may be made to the descriptions of the first organic medium layer and the second inorganic medium layer in the foregoing embodiments, which are not repeated here.
继续参考图29，所述封装方法还包括：提供第二器件晶圆200，第二器件晶圆200中形成有多个第三芯片72，第三芯片72的任一表面形成有第六焊垫34，第六焊垫34凹陷于第二芯片70的表面。Continuing to refer to FIG. 29 , the packaging method further includes: providing a second device wafer 200 , a plurality of third chips 72 are formed in the second device wafer 200 , and sixth bonding pads are formed on any surface of the third chips 72 34 , the sixth bonding pad 34 is recessed on the surface of the second chip 70 .
第二器件晶圆200用于与第一器件晶圆100键合在一起，以实现特定的功能。其中，第三芯片72之间包括切割道(未标示)，切割道所在的区域为切割区30a，第二器件晶圆200与第一器件晶圆100的切割道上下对准，切割道为第二器件晶圆200与第一器件晶圆100一同进行晶圆切割的位置。The second device wafer 200 is used for bonding with the first device wafer 100 to achieve a specific function. Wherein, the third chip 72 includes a dicing road (not marked), the area where the dicing road is located is the dicing area 30a, the dicing road of the second device wafer 200 and the first device wafer 100 are aligned up and down, and the dicing road is the first device wafer 100. The position where the two device wafers 200 and the first device wafer 100 are diced together.
将第三芯片72与第一芯片30键合在一起，且将第一芯片30键合于所述电路板10上，从而将第三芯片72和第一芯片30在沿垂直于电路板10表面的方向上堆叠，相应实现了三维封装(3D package)。The third chip 72 and the first chip 30 are bonded together, and the first chip 30 is bonded on the circuit board 10 , so that the third chip 72 and the first chip 30 are perpendicular to the surface of the circuit board 10 . Stacked in the direction of the corresponding three-dimensional packaging (3D package).
本实施例中，将所述第一器件晶圆100键合于所述电路板10上之后，将第二器件晶圆200键合于第一器件晶圆100上，从而在实现第三芯片72与第一芯片30相键合的过程中，使电路板10能够起到支撑载板的作用。在其他实施例中，也可以在将第二器件晶圆键合于第一器件晶圆上之后，将所述第一器件晶圆键合于所述电路板上。In this embodiment, after the first device wafer 100 is bonded to the circuit board 10 , the second device wafer 200 is bonded to the first device wafer 100 , so as to realize the third chip 72 In the process of bonding with the first chip 30, the circuit board 10 can play the role of supporting the carrier board. In other embodiments, the first device wafer may also be bonded to the circuit board after the second device wafer is bonded to the first device wafer.
本实施例中，将所述第三芯片72与所述第一芯片30键合在一起，所述第五焊垫36与第六焊垫34相对围成第三空隙，在第三空隙35中形成第三导电凸块75。In this embodiment, the third chip 72 and the first chip 30 are bonded together, and the fifth bonding pad 36 and the sixth bonding pad 34 are opposite to form a third gap, and the third gap 35 is in the third gap 35 . Third conductive bumps 75 are formed.
本实施例中，还包括：将第一器件晶圆100、第二器件晶圆200与电路板10相互键合之后，对第二器件晶圆200和第一器件晶圆100进行晶圆 切割，将第一芯片30相互分割开，同时将第三芯片72也相互分割开。In this embodiment, the method further includes: after the first device wafer 100, the second device wafer 200 and the circuit board 10 are bonded to each other, wafer cutting is performed on the second device wafer 200 and the first device wafer 100, The first chips 30 are separated from each other, and the third chips 72 are also separated from each other.
本实施例中，第二器件晶圆200与第一器件晶圆100的切割道上下对准，通过一次切割，将第三芯片72相互分割开，同时将第一芯片30相也互分割开，简化了工艺流程，提高了封装效率。In this embodiment, the dicing lanes of the second device wafer 200 and the first device wafer 100 are aligned up and down, and the third chips 72 are separated from each other by one dicing, and the first chips 30 are also separated from each other at the same time. The process flow is simplified and the packaging efficiency is improved.
实施例十二 Embodiment 12
本实施例与前述实施例八的不同之处在于：从所述电路板背向第一芯片的一侧，对所述电路板进行切割，形成贯穿所述电路板的切割槽。The difference between this embodiment and the previous eighth embodiment is that the circuit board is cut from the side of the circuit board facing away from the first chip to form a cutting groove penetrating the circuit board.
本发明实施例提供一种板级系统级封装方法，包括：提供电路板，所述电路板具有第一表面和第二表面，所述电路板包括键合区和包围所述键合区的切割区，在所述键合区中，所述电路板表面上形成有多个第一焊垫，所述第一焊垫凹陷于所述电路板的第一表面；提供第一器件晶圆，所述第一器件晶圆中形成有多个第一芯片，所述第一芯片的其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述第一芯片的表面；将所述第一器件晶圆键合于所述电路板的第一表面上，所述第一芯片位于所述键合区上方，所述第一焊垫与第二焊垫相对围成第一空隙；通过电镀工艺，在所述第一空隙中形成第一导电凸块，所述第一导电凸块电连接所述第一焊垫和第二焊垫；形成所述第一导电凸块后，从所述第二表面一侧，对所述电路板中的切割区进行切割，形成贯穿所述电路板的切割槽。An embodiment of the present invention provides a board-level system-in-package method, including: providing a circuit board, the circuit board having a first surface and a second surface, the circuit board including a bonding area and a cut surrounding the bonding area In the bonding area, a plurality of first pads are formed on the surface of the circuit board, and the first pads are recessed on the first surface of the circuit board; a first device wafer is provided, and the A plurality of first chips are formed in the first device wafer, a second pad is formed on one surface of the first chip, and the second pad is recessed on the surface of the first chip; The first device wafer is bonded on the first surface of the circuit board, the first chip is located above the bonding area, and the first bonding pad and the second bonding pad are opposite to form a first gap; electroplating process, forming a first conductive bump in the first gap, the first conductive bump electrically connecting the first pad and the second pad; after forming the first conductive bump, from the On the side of the second surface, the cutting area in the circuit board is cut to form a cutting groove penetrating the circuit board.
本实施例中的对电路板进行切割形成切割槽，也适用于实施例八、实施例九和实施例十中进行切割前的结构。Cutting the circuit board to form the cutting groove in this embodiment is also applicable to the structures before cutting in the eighth, ninth, and tenth embodiments.
本实施例中，以第一器件晶圆100作为载板对电路板10进行切割，由于第一器件晶圆100需要在无尘车间完成制程，则对电路板10的切割工艺也需要在无尘车间，并采用适用于第一器件晶圆100的设备和产线完成。In this embodiment, the first device wafer 100 is used as a carrier to cut the circuit board 10. Since the first device wafer 100 needs to be processed in a clean room, the cutting process of the circuit board 10 also needs to be performed in a clean room. workshop, and is completed using equipment and production lines suitable for the first device wafer 100 .
本实施例中，采用刀片切割(blade saw)或激光切割对电路板10的切割区10b处进行切割。In this embodiment, the cutting area 10b of the circuit board 10 is cut by blade saw or laser cutting.
所述采用刀片切割工艺包括：将所述第一器件晶圆100远离电路板的一面贴附于胶膜层上，沿所述切割区10b对所述电路板10进行切割，切割后，降解所述胶膜层和第一器件晶圆100之间的粘性，从而去除所述胶膜层。The blade cutting process includes: attaching the side of the first device wafer 100 away from the circuit board on the adhesive film layer, cutting the circuit board 10 along the cutting area 10b, and degrading the circuit board 10 after cutting. The adhesion between the adhesive film layer and the first device wafer 100 is improved, thereby removing the adhesive film layer.
当所述胶膜层的材料为UV膜时，采用紫外光照射所述胶膜层，以降低胶膜层和第一器件晶圆100之间的粘性，去除所述胶膜层。When the material of the adhesive film layer is a UV film, ultraviolet light is used to irradiate the adhesive film layer to reduce the viscosity between the adhesive film layer and the first device wafer 100 and remove the adhesive film layer.
需要说明的是，在切割所述电路板10之前，可以在所示第一器件晶圆100上形成封装层，也可以将所示第一器件晶圆100临时键合到承载衬底上，再对所述电路板10进行切割，以提高第一器件晶圆100的强度，减 少切割工艺过程对第一器件晶圆100的影响，提高良率。It should be noted that, before the circuit board 10 is cut, an encapsulation layer may be formed on the first device wafer 100 shown, or the first device wafer 100 shown may be temporarily bonded to the carrier substrate, and then The circuit board 10 is cut to improve the strength of the first device wafer 100, reduce the influence of the cutting process on the first device wafer 100, and improve the yield.
将第一器件晶圆100键合在电路板10上之后，对电路板10的切割区10b进行切割，实现电路板10各键合区10a相互分割的效果，与将各个需要键合的电路板逐个键合在芯片上的方案相比，实现了晶圆级封装的效果的同时简化了工艺流程，提高了封装效率。After the first device wafer 100 is bonded on the circuit board 10, the cutting area 10b of the circuit board 10 is cut, so as to realize the effect of dividing the bonding areas 10a of the circuit board 10 from each other. Compared with the solution of bonding on the chips one by one, the effect of wafer-level packaging is achieved, the process flow is simplified, and the packaging efficiency is improved.
本发明的实施例八至实施例十一阐述了各种具体的情形，其中实施例七至实施例十一阐述的各种情形可以根据需要进行相应的组合形成新的实施例。在本发明中不做一一阐述，本领域技术人员根据本发明的教导可以得出不同于实施例七至实施例十一所列情形的具体实施例。Embodiments 8 to 11 of the present invention describe various specific situations, wherein various situations described in Embodiments 7 to 11 can be combined to form new embodiments as required. In the present invention, one by one is not described, and those skilled in the art can obtain specific embodiments different from the situations listed in Embodiment 7 to Embodiment 11 according to the teachings of the present invention.
实施例十三Embodiment thirteen
本实施例十三提供一种板级系统级封装结构，包括：The thirteenth embodiment provides a board-level system-level packaging structure, including:
电路板10，所述电路板10具有表面，所述表面形成有多个第一焊垫11，所述第一焊垫11凹陷于所述电路板表面；该表面可以是正面或背面、也可以是包括了背面和正面； Circuit board 10, the circuit board 10 has a surface, the surface is formed with a plurality of first pads 11, the first pads 11 are recessed on the surface of the circuit board; the surface can be the front or the back, or It includes the back and front;
多个第一芯片30，所述第一芯片30其中一表面形成有第二焊垫31，所述第二焊垫31凹陷于所述第一芯片表面；a plurality of first chips 30, one surface of the first chips 30 is formed with a second bonding pad 31, the second bonding pad 31 is recessed on the surface of the first chip;
所述第一芯片30与所述电路板10键合在一起，所述第一焊垫与所述第二焊垫相对围成第一空隙，所述第一空隙内形成有电镀的第一导电凸块40以电连接所述第一焊垫11、第二焊垫31。The first chip 30 and the circuit board 10 are bonded together, the first pad and the second pad are opposite to form a first gap, and a first conductive electroplating is formed in the first gap. The bumps 40 are used to electrically connect the first pads 11 and the second pads 31 .
所述第一芯片30与所述电路板10通过可光刻键合材料20键合在一起，所述可光刻键合材料20避开焊垫(第一焊垫、第二焊垫)设置、覆盖所述第一导电凸块40外围的区域。所述第一焊垫和所述第二焊垫包括正对部分、错开部分，所述正对部分的面积为第一焊垫或第二焊垫面积的至少二分之一，第一空隙的高度为5-200微米。The first chip 30 and the circuit board 10 are bonded together by a photolithographic bonding material 20, and the photolithographic bonding material 20 is arranged to avoid the bonding pads (the first bonding pad, the second bonding pad) , covering the peripheral area of the first conductive bump 40 . The first bonding pad and the second bonding pad include a facing portion and a staggered portion, the area of the facing portion is at least half of the area of the first bonding pad or the second bonding pad, and the first gap is Height is 5-200 microns.
所述电路板10包括：至少一层板，每层板至少包括基板、位于所述基板表面互连结构，所述第一焊垫位于顶层的所述互连结构上与所述互连结构电连接。该实施例中，电路板10为三层板。The circuit board 10 includes: at least one layer of boards, each layer of board at least includes a substrate, an interconnection structure on the surface of the substrate, and the first pads on the interconnection structure on the top layer are electrically connected to the interconnection structure. connect. In this embodiment, the circuit board 10 is a three-layer board.
参考图6-图7，键合在电路板上的第一芯片包括连接芯片30b，该连接芯片30b的顶面可以通过电镀工艺形成导电凸块30b1。Referring to FIGS. 6-7 , the first chip bonded on the circuit board includes a connection chip 30b, and the top surface of the connection chip 30b can be formed with conductive bumps 30b1 through an electroplating process.
参考图8-图14，第一芯片下方具有空腔，所述空腔作为第一芯片的工作腔。所述空腔可以位于键合层中，也可以位于电路板中，还可以贯穿键合层和部分电路板中。Referring to FIGS. 8-14 , there is a cavity below the first chip, and the cavity is used as a working cavity of the first chip. The cavity may be located in the bonding layer, may also be located in the circuit board, and may also penetrate through the bonding layer and part of the circuit board.
参考图8，封装结构的键合层形成有第一空腔，至少部分第一芯片30键合在第一空腔21上。本实施例中，部分第一芯片30的下方需要具有空 腔，部分第一芯片30的下方不需要空腔。在其他实施例中，也可以时整个PCB板上的第一芯片30下方均具有第一空腔。所述第一芯片可以含有第二空腔或未含第二空腔，也就是说，第一芯片可以是上下均需要空腔的芯片，比如体声波薄膜谐振器。所述封装结构为射频模组，所述第一芯片包括：射频芯片，其中包括至少一个滤波器芯片，其他射频芯片包括信号放大、信号接收以及信号调谐中的至少一个功能。Referring to FIG. 8 , the bonding layer of the package structure is formed with a first cavity, and at least part of the first chip 30 is bonded on the first cavity 21 . In this embodiment, some of the first chips 30 need to have cavities below, and some of the first chips 30 do not need cavities below. In other embodiments, a first cavity may also be provided under the first chip 30 on the entire PCB. The first chip may or may not contain the second cavity, that is, the first chip may be a chip that requires cavities on both the upper and lower sides, such as a bulk acoustic wave thin film resonator. The packaging structure is a radio frequency module, and the first chip includes: a radio frequency chip, which includes at least one filter chip, and the other radio frequency chips include at least one function of signal amplification, signal reception, and signal tuning.
参考图9、图10，第一芯片也可以是仅需要具有上空腔或下空腔的芯片，比如表面声波谐振器。第一芯片30a可以未含第二空腔，比如参考图9可以为表声波滤波器其包括谐振结构3013(包括叉指电极以及压电膜)，比如参考图10，可以为SMR体声波滤波器其包括谐振结构3013(包括上下电极以及位于上下电极之间的压电膜)以及位于谐振结构一侧的第一空腔21以及另一侧的布拉格反射层3014。Referring to FIGS. 9 and 10 , the first chip may also be a chip that only needs to have an upper cavity or a lower cavity, such as a surface acoustic wave resonator. The first chip 30a may not contain the second cavity, for example, referring to FIG. 9, it may be a surface acoustic wave filter including a resonant structure 3013 (including interdigital electrodes and a piezoelectric film), for example, referring to FIG. 10, it may be an SMR bulk acoustic wave filter It includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes), a first cavity 21 on one side of the resonant structure, and a Bragg reflection layer 3014 on the other side.
参考图11，含有空腔21的第一芯片30c，该空腔21需要与外界环境连通的空腔，比如麦克风传感器，其上空腔需要与外界连通。电路板中具有通孔211，该通孔211与空腔21连通。Referring to FIG. 11 , the first chip 30c includes a cavity 21 . The cavity 21 needs a cavity that communicates with the external environment, such as a microphone sensor, and the cavity above the cavity needs to communicate with the outside world. The circuit board has a through hole 211 , and the through hole 211 communicates with the cavity 21 .
参考图12，所述封装结构为超声波传感器，所述第一芯片包括：超声波传感芯片以及外围芯片，所述外围芯片包括：信号读取芯片、模拟信号处理芯片、模数转换芯片、数字逻辑芯片以及控制芯片中的至少一种。Referring to FIG. 12 , the package structure is an ultrasonic sensor, and the first chip includes an ultrasonic sensor chip and a peripheral chip, and the peripheral chip includes a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, and a digital logic chip. At least one of a chip and a control chip.
参考图13，键合层内不具有空腔，所述电路板中具有第二空腔18，所述第一芯片位于第二空腔上方，所述第二空腔18作为第一芯片30a的工作腔。参考图14，所述电路板中具有第二空腔18，所述键合层中具有第一空腔21，所述第二空腔和第一空腔相对并连通，所述第一芯片位于所述第一空腔上方。Referring to FIG. 13 , the bonding layer does not have a cavity, the circuit board has a second cavity 18 , the first chip is located above the second cavity, and the second cavity 18 serves as the first chip 30 a working chamber. Referring to FIG. 14, the circuit board has a second cavity 18, the bonding layer has a first cavity 21, the second cavity and the first cavity are opposite and communicate with each other, and the first chip is located in above the first cavity.
参考图15，电路板10形成有凹槽(图中未标号)，所述凹槽内嵌设有第二芯片70，所述第二芯片70表面具有第三焊垫71，所述第三焊垫与相应第一芯片30的第二焊垫31之间形成有导电凸块80。Referring to FIG. 15 , the circuit board 10 is formed with a groove (not numbered in the figure), a second chip 70 is embedded in the groove, and a surface of the second chip 70 has a third pad 71 , and the third welding Conductive bumps 80 are formed between the pads and the second pads 31 of the corresponding first chips 30 .
参考图16，电路板10中形成有凹槽，所述凹槽的底部形成有第一焊垫13，所述第一焊垫13凹陷于所述凹槽的底面；所述第一芯片30键合于所述凹槽的底面。参考图17，所述第一芯片30可以键合于所述凹槽的底面和电路板表面。Referring to FIG. 16 , a groove is formed in the circuit board 10 , a first pad 13 is formed at the bottom of the groove, and the first pad 13 is recessed on the bottom surface of the groove; the first chip 30 is keyed fit the bottom surface of the groove. Referring to FIG. 17 , the first chip 30 may be bonded to the bottom surface of the groove and the surface of the circuit board.
参考图18，封装结构还可以包括第四焊垫16，所述第四焊垫16位于底层的所述互连结构上与相应所述互连结构电连接，进行所述电镀工艺时，在所述第四焊垫上形成第二导电凸块80。背面的芯片可以通过焊接工艺焊接在第二导电凸块80上。参考图19，在电路板的背面和正面均具有第一芯片30，第一芯片30与电路板之间也具有电镀工艺形成的第一导电凸块 40和第二导电凸块80。Referring to FIG. 18 , the package structure may further include fourth solder pads 16 . The fourth solder pads 16 are located on the underlying interconnect structures and are electrically connected to the corresponding interconnect structures. During the electroplating process, the fourth solder pads 16 are A second conductive bump 80 is formed on the fourth pad. The chips on the backside can be soldered on the second conductive bumps 80 through a soldering process. Referring to FIG. 19 , the circuit board has a first chip 30 on both the back and front sides, and also has a first conductive bump 40 and a second conductive bump 80 formed by an electroplating process between the first chip 30 and the circuit board.
参考图20，在第一芯片30上堆叠有第三芯片32，可以是全部第一芯片30上堆叠有第三芯片32，也可以是部分第一芯片30上堆叠第三芯片32。第三芯片和第一芯片之间通过键合的方式连接，比如可以是可光刻键合材料，干膜。堆叠的第一芯片30第三芯片32之间通过第三导电凸块35电连接。Referring to FIG. 20 , the third chips 32 are stacked on the first chips 30 , and the third chips 32 may be stacked on all the first chips 30 , or the third chips 32 may be stacked on some of the first chips 30 . The third chip and the first chip are connected by bonding, for example, a photolithographic bonding material, a dry film. The stacked first chips 30 and the third chips 32 are electrically connected through third conductive bumps 35 .
参考图21，所述封装结构为摄像头模组，所述第一芯片包括：图像传感芯片以及外围芯片，所述图像传感芯片包括：CMOS传感芯片或CCD传感芯片中的至少一种；所述外围芯片包括：信号读取芯片、模拟信号处理芯片、模数转换芯片、数字逻辑电路芯片或驱动芯片中的至少一种或几种的集成。21, the package structure is a camera module, the first chip includes: an image sensor chip and a peripheral chip, the image sensor chip includes: at least one of a CMOS sensor chip or a CCD sensor chip ; The peripheral chip includes: a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic circuit chip or an integration of at least one or several of the driver chips.
参考图5，电路板10的正面形成有具有光刻键合特性的第一有机介质层13，第一焊垫11埋设于所述第一有机介质层13；和/或，所述背面形成有具有光刻键合特性的第二有机介质层17(参考图16)，替代阻焊剂，第四焊垫16埋设于所述第二有机介质层17。其他实施例中，第一有机介质层13可以用第一无机介质层代替；第二有机介质层17可以用第二无机介质层代替。Referring to FIG. 5 , a first organic dielectric layer 13 having photolithographic bonding characteristics is formed on the front side of the circuit board 10 , and the first pads 11 are embedded in the first organic dielectric layer 13 ; and/or, the back side is formed with The second organic dielectric layer 17 (refer to FIG. 16 ) having photolithographic bonding properties, instead of the solder resist, the fourth pad 16 is buried in the second organic dielectric layer 17 . In other embodiments, the first organic medium layer 13 may be replaced by a first inorganic medium layer; the second organic medium layer 17 may be replaced by a second inorganic medium layer.
参考图24，所述多个第一芯片位于第一器件晶圆100内，所述第一器件晶圆与电路板键合，从而实现第一芯片和电路板的键合。所述第一器件晶圆100具有切割槽，将所述第一芯片30相互分割开。Referring to FIG. 24, the plurality of first chips are located in the first device wafer 100, and the first device wafer is bonded to the circuit board, thereby realizing the bonding of the first chips and the circuit board. The first device wafer 100 has a dicing groove to separate the first chips 30 from each other.
参考图25，第一器件晶圆100和电路板通过键合层键合，所述键合层内具有第一空腔21，第一芯片30位于第一空腔上。参考图26，位于第一器件晶圆100内的第一芯片底部具有工作空腔，所述电路板中具有第二空腔18，作为第一芯片的工作空腔。参考图27，位于第一器件晶圆100内的第一芯片底部具有工作空腔，电路板中的第二空腔18与键合层中的第一空腔21贯通，共同作为第一芯片的工作空腔。Referring to FIG. 25 , the first device wafer 100 and the circuit board are bonded through a bonding layer, and the bonding layer has a first cavity 21 therein, and the first chip 30 is located on the first cavity. Referring to FIG. 26 , the bottom of the first chip in the first device wafer 100 has a working cavity, and the circuit board has a second cavity 18 as the working cavity of the first chip. Referring to FIG. 27 , the bottom of the first chip located in the first device wafer 100 has a working cavity, and the second cavity 18 in the circuit board communicates with the first cavity 21 in the bonding layer, which together serve as the first cavity of the first chip. working cavity.
参考图28，所述电路板10相对的两个面上均键合第一器件晶圆100。在所述电路板10的正面的第一焊垫11上通过电镀工艺形成第一导电凸块40；在所述电路板10背面的第一焊垫上通过电镀工艺形成第二导电凸块80。所述电路板10的背面也可以仅具有第二导电凸块。Referring to FIG. 28 , two opposite surfaces of the circuit board 10 are bonded to the first device wafer 100 . The first conductive bumps 40 are formed on the first solder pads 11 on the front side of the circuit board 10 by an electroplating process; the second conductive bumps 80 are formed on the first solder pads on the backside of the circuit board 10 by an electroplating process. The backside of the circuit board 10 may also have only the second conductive bumps.
参考图29，第一器件晶圆上键合第二器件晶圆，所述第二器件晶圆内也具有多个第一芯片；第一器件晶圆和第二器件晶圆键合后，第二器件晶圆内的第一芯片堆叠在第一器件晶圆内的第一芯片上方，实现芯片的堆叠。Referring to FIG. 29, a second device wafer is bonded on the first device wafer, and the second device wafer also has a plurality of first chips; after the first device wafer and the second device wafer are bonded, the The first chips in the two device wafers are stacked above the first chips in the first device wafer to realize stacking of the chips.
参考图30，所述多个第一芯片位于第一器件晶圆100内，所述电路板 中形成有贯穿电路板的切割槽。电路板10包括键合区10a和包围所述键合区10a的切割区10b，在键合区10a中，电路板10表面上形成有多个第一焊垫11，第一焊垫11凹陷于电路板10的表面。所述切割槽位于切割区10b，所述第一芯片在电路板上的投影位于键合区10a。Referring to FIG. 30, the plurality of first chips are located in the first device wafer 100, and the circuit board is formed with cutting grooves penetrating the circuit board. The circuit board 10 includes a bonding area 10a and a cutting area 10b surrounding the bonding area 10a. In the bonding area 10a, a plurality of first solder pads 11 are formed on the surface of the circuit board 10, and the first solder pads 11 are recessed. the surface of the circuit board 10 . The cutting groove is located in the cutting area 10b, and the projection of the first chip on the circuit board is located in the bonding area 10a.
本发明实施例一至十三中相关的结构、材料、效果等相关的内容可以援引于此，在此不做赘述。The related contents of the structures, materials, effects, etc. in the first to thirteenth embodiments of the present invention can be cited here, and will not be repeated here.
实施例十四 Embodiment 14
参考图34，实施例十四提供一种电路板10，包括：至少一层板12，每层板12至少包括基板、位于所述基板表面的互连结构，所述第一焊垫位于顶层的所述互连结构上与所述互连结构电连接；所述电路板的正面形成有具有光刻键合特性的第一有机介质层，第一焊垫11埋设于所述第一有机介质层13。第一有机介质层可以是第一无机介质层，具体优点可以参照实施例一中的相关描述。Referring to FIG. 34 , the fourteenth embodiment provides a circuit board 10 , including: at least one layer of boards 12 , each layer of board 12 at least includes a substrate, an interconnection structure located on the surface of the substrate, and the first pads are located on the top layer. The interconnection structure is electrically connected to the interconnection structure; a first organic dielectric layer with photolithographic bonding characteristics is formed on the front surface of the circuit board, and the first pad 11 is buried in the first organic dielectric layer 13. The first organic medium layer may be a first inorganic medium layer, and for specific advantages, please refer to the relevant description in the first embodiment.
电路板10为印刷线路板即PCB板，电路板10可以是单层板，双层板，三层板，四层板等，具体的，电路板10的层数可以根据实际需求确定。本实施例中，电路板10为三层板，每层板包括：位于基板表面的互连结构、与互连结构电连接的互连插塞；互连插塞包括通孔及通孔表面镀有导电层，且填充绝缘树脂；互连结构可以包括互连线及互连垫。或者，也可以在互连插塞内填充导电树脂，节省形成导电层的工艺。本发明中，也可以根据实际需求，确定每层板是否包含互连插塞、互连结构，可以只有互连结构，没有互连插塞。The circuit board 10 is a printed circuit board, that is, a PCB board. The circuit board 10 can be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc. Specifically, the number of layers of the circuit board 10 can be determined according to actual needs. In this embodiment, the circuit board 10 is a three-layer board, and each layer of the board includes: an interconnection structure located on the surface of the substrate, and an interconnection plug electrically connected to the interconnection structure; the interconnection plug includes through holes and through-hole surface plating There is a conductive layer and is filled with insulating resin; the interconnection structure may include interconnection lines and interconnection pads. Alternatively, a conductive resin can also be filled in the interconnect plug to save the process of forming the conductive layer. In the present invention, it can also be determined according to actual requirements whether each layer of the board includes interconnection plugs and interconnection structures, and there may be only interconnection structures without interconnection plugs.
如果PCB板的背面形成第四焊垫16(结合参考图7和图8以及实施例5)，所述第四焊垫位于所述电路板底层的所述互连结构上与相应所述互连结构电连接，所述背面形成有具有光刻键合特性的第二有机介质层17，第四焊垫埋设于所述第二有机介质层。第二有机介质层17可以用第二无机介质层替换。优点可以参考实施例5中相关的描述。If a fourth solder pad 16 is formed on the backside of the PCB board (referring to FIG. 7 and FIG. 8 and Embodiment 5 in conjunction), the fourth solder pad is located on the interconnect structure on the bottom layer of the circuit board and is connected to the corresponding interconnection The structure is electrically connected, a second organic medium layer 17 with photolithographic bonding characteristics is formed on the back surface, and a fourth pad is buried in the second organic medium layer. The second organic medium layer 17 may be replaced with a second inorganic medium layer. The advantages can be referred to the related description in Embodiment 5.
参考图31-图34，本实施例还提供一种电路板的形成方法，包括：Referring to FIGS. 31-34 , this embodiment further provides a method for forming a circuit board, including:
参考图31，至少形成一层板12，每层板12至少包括基板、位于所述基板表面互连结构14；本实施例中，形成了三层板，每层板的形成方法包括提供基板、在基板中形成互连插塞15，在基板的上下两面形成互连结构14，该互连结构可以包括互连线、及位于互连插塞上的互连垫。其中，互连插塞包括通孔及位于通孔内的导电结构，该导电结构可以是位于通孔表面的导电层，通孔内可以填充有树脂材料；在其他实施例中，互连插塞可以包括通孔及位于通孔内的导电树脂，导电树脂同时起到导电及填充通孔的作用，节省工艺。Referring to FIG. 31 , at least one layer of board 12 is formed, and each layer of board 12 at least includes a substrate and an interconnection structure 14 located on the surface of the substrate; in this embodiment, a three-layer board is formed, and the formation method of each layer of board includes providing a substrate, Interconnection plugs 15 are formed in the substrate, and interconnection structures 14 are formed on the upper and lower sides of the substrate. The interconnection structures may include interconnection lines and interconnection pads on the interconnection plugs. Wherein, the interconnect plug includes a through hole and a conductive structure located in the through hole, the conductive structure may be a conductive layer located on the surface of the through hole, and the through hole may be filled with a resin material; in other embodiments, the interconnect plug It may include a through hole and a conductive resin in the through hole, and the conductive resin plays the role of conducting electricity and filling the through hole at the same time, saving process.
参考图32，形成位于顶层的板后，在顶层板12上形成第一焊垫11、第一焊垫与位于顶层板的所述互连结构电连接；在形成底层板后，在底层板上形成第四焊垫16；如果电路板背面无需进行电连接，则无需形成第四焊垫。Referring to FIG. 32, after the board on the top layer is formed, first pads 11 are formed on the top board 12, and the first pads are electrically connected to the interconnect structure on the top board; after the bottom board is formed, on the bottom board The fourth solder pad 16 is formed; if the backside of the circuit board does not need to be electrically connected, the fourth solder pad need not be formed.
参考图33，在顶层板上形成具有光刻键合特性的第一有机介质层13，在底层板上形成具有光刻键合特性的第二有机介质层17。有机介质层可以选择干膜，其形成方法可以参考实施例一中的相关描述。形成第一有机介质层、第二有机介质层的优点可以参考以上实施例中的相关描述。其中，第一有机介质层可以用第一无机介质层替换，第二有机介质层需要用第二无机介质层替换，第一无机介质层、第二无机介质层的材料可以选择氧化硅、氮化硅、氮氧化硅等无机介质材料。利用沉积的方式形成无机介质层。Referring to FIG. 33 , a first organic medium layer 13 having photolithographic bonding properties is formed on the top plate, and a second organic medium layer 17 having photolithographic bonding properties is formed on the bottom plate. The organic medium layer can be selected as a dry film, and its formation method can refer to the relevant description in the first embodiment. For the advantages of forming the first organic medium layer and the second organic medium layer, reference may be made to the relevant descriptions in the above embodiments. The first organic medium layer can be replaced with a first inorganic medium layer, the second organic medium layer needs to be replaced with a second inorganic medium layer, and the materials of the first inorganic medium layer and the second inorganic medium layer can be selected from silicon oxide, nitride Inorganic dielectric materials such as silicon and silicon oxynitride. The inorganic dielectric layer is formed by means of deposition.
参考图34，在第一有机介质层13、第二有机介质层17中形成开口暴露出第一焊垫11、第四焊垫16。Referring to FIG. 34 , openings are formed in the first organic dielectric layer 13 and the second organic dielectric layer 17 to expose the first pads 11 and the fourth pads 16 .
需要说明的是，本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于结构实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。It should be noted that each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. . In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and reference may be made to the partial descriptions of the method embodiments for related parts.
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度 或其它取向)并且在此使用的空间描述语相应地被解释。Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (30)

  1. 一种板级系统级封装方法，其特征在于，包括：A board-level system-level packaging method, comprising:
    提供电路板，所述电路板表面形成有多个第一焊垫，所述第一焊垫凹陷于所述表面；A circuit board is provided, and a plurality of first bonding pads are formed on the surface of the circuit board, and the first bonding pads are recessed on the surface;
    提供多个第一芯片，所述第一芯片其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述表面；a plurality of first chips are provided, a surface of the first chips is formed with a second pad, and the second pad is recessed on the surface;
    将所述第一芯片与所述电路板键合，所述第一焊垫与所述第二焊垫相对围成第一空隙；bonding the first chip and the circuit board, the first pad and the second pad are opposite to form a first gap;
    通过电镀工艺在所述第一空隙形成第一导电凸块以电连接所述第一焊垫、第二焊垫。A first conductive bump is formed in the first void by an electroplating process to electrically connect the first pad and the second pad.
  2. 根据权利要求1所述的板级系统级封装方法，其特征在于，The board-level system-in-package method according to claim 1, wherein,
    通过键合层实现所述键合，所述键合层避开焊垫设置；The bonding is realized by a bonding layer, the bonding layer is arranged to avoid the pads;
    所述键合层的材料包括：可光刻键合材料、芯片粘结膜、介质材料、玻璃和聚合物材料中的一种或多种，所述可光刻材料包括干膜，所述介质材料包括氧化硅或者氮化硅。The material of the bonding layer includes: one or more of photolithographic bonding material, die bonding film, dielectric material, glass and polymer material, the photolithographic material includes dry film, the medium Materials include silicon oxide or silicon nitride.
  3. 根据权利要求2所述的板级系统级封装方法，其特征在于，The board-level system-in-package method according to claim 2, wherein,
    在所述键合层中形成有第一空腔，至少部分所述第一芯片键合于所述第一空腔上方，所述第一空腔作为所述第一芯片的工作腔。A first cavity is formed in the bonding layer, at least part of the first chip is bonded above the first cavity, and the first cavity serves as a working cavity of the first chip.
  4. 根据权利要求2所述的板级系统级封装方法，其特征在于，The board-level system-in-package method according to claim 2, wherein,
    在所述电路板中形成第二空腔，所述第一芯片位于第二空腔上方；forming a second cavity in the circuit board, and the first chip is located above the second cavity;
    或者，在所述电路板中形成第二空腔，在所述键合层中形成第一空腔，所述第二空腔和第一空腔相对并连通，所述第一芯片位于所述第一空腔上方。Alternatively, a second cavity is formed in the circuit board, a first cavity is formed in the bonding layer, the second cavity is opposite to and communicated with the first cavity, and the first chip is located in the above the first cavity.
  5. 根据权利要求2或3所述的板级系统级封装方法，其特征在于，The board-level system-in-package method according to claim 2 or 3, wherein,
    所述电路板中形成有凹槽，所述凹槽的底部形成有第一焊垫，所述第一焊垫凹陷于所述凹槽的底面；A groove is formed in the circuit board, a first pad is formed at the bottom of the groove, and the first pad is recessed on the bottom surface of the groove;
    所述第一芯片键合于所述凹槽的底面。The first chip is bonded to the bottom surface of the groove.
  6. 根据权利要求1至4所述的板级系统级封装方法，其特征在于，提供多个第一芯片的步骤包括：The board-level system-in-package method according to claims 1 to 4, wherein the step of providing a plurality of first chips comprises:
    提供第一器件晶圆，所述第一器件晶圆中形成有多个第一芯片，所述第一芯片的其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述第一芯片的表面；A first device wafer is provided, a plurality of first chips are formed in the first device wafer, a second pad is formed on one surface of the first chip, and the second pad is recessed in the first chip. the surface of a chip;
    将所述第一器件晶圆键合于所述电路板上，所述第一焊垫与第二焊垫相对围成第一空隙。The first device wafer is bonded to the circuit board, and the first bonding pad and the second bonding pad are opposite to form a first gap.
  7. 根据权利要求6所述的板级系统级封装方法，其特征在于，形成所述第一导电凸块后，还包括：The board-level system-in-package method according to claim 6, wherein after forming the first conductive bumps, the method further comprises:
    对所述第一器件晶圆进行晶圆切割，将所述第一芯片相互分割开；Wafer cutting is performed on the first device wafer, and the first chips are separated from each other;
    或者，or,
    从所述电路板背向第一芯片的一侧，对所述电路板进行切割，形成贯穿所述电路板的切割槽。From the side of the circuit board facing away from the first chip, the circuit board is cut to form a cutting groove penetrating the circuit board.
  8. 根据权利要求1所述的板级系统级封装方法，其特征在于，The board-level system-in-package method according to claim 1, wherein,
    所述电路板包括相对的正面和背面，所述电路板正面形成有所述第一焊垫，所述电路板背面形成有第四焊垫；在所述电路板背面的第四焊垫上通过电镀工艺形成第二导电凸块；和/或，将至少一个第一芯片键合于所述电路板背面。The circuit board includes opposite front and back, the first pad is formed on the front of the circuit board, and the fourth pad is formed on the back of the circuit board; electroplating is performed on the fourth pad on the back of the circuit board forming a second conductive bump; and/or bonding at least one first chip to the backside of the circuit board.
  9. 根据权利要求1所述的板级系统级封装方法，其特征在于，所述电路板包括凹槽，所述凹槽内嵌设有第二芯片，所述第二芯片表面具有第三焊垫，所述第三焊垫与相应第一芯片的第二焊垫相对形成所述第一空隙。The board-level system-in-package method according to claim 1, wherein the circuit board comprises a groove, a second chip is embedded in the groove, and a surface of the second chip has a third solder pad, The third pad is opposite to the second pad of the corresponding first chip to form the first void.
  10. 根据权利要求1所述的板级系统级封装方法，其特征在于，所述第一芯片的另一面形成有第五焊垫，在所述第一芯片上键合有第三芯片，所述第三芯片含有第六焊垫，所述第五焊垫与所述第六焊垫之间通过电镀的第三导电凸块电连接。The board-level system-in-package method according to claim 1, wherein a fifth bonding pad is formed on the other side of the first chip, a third chip is bonded on the first chip, and the first chip is The three-chip includes a sixth bonding pad, and the fifth bonding pad and the sixth bonding pad are electrically connected with a third conductive bump by electroplating.
  11. 根据权利要求1所述的板级系统级封装方法，其特征在于，The board-level system-in-package method according to claim 1, wherein,
    所述第一芯片包括：裸芯片、包裹有塑封层、顶面具有屏蔽层、形成有贯穿芯片的互连通孔结构中的至少一种情形；The first chip includes at least one of: a bare chip, being wrapped with a plastic sealing layer, having a shielding layer on the top surface, and forming an interconnect via structure penetrating the chip;
    所述多个第一芯片为同功能芯片；或者，所述多个第一芯片至少包括两种不同功能的芯片；或者，所述第一芯片为无源器件或者有源器件；或者，所述第一芯片包括传感器模组芯片、MEMS芯片、滤波器芯片、逻辑芯片、CIS芯片、存储芯片、电容、电感、连接芯片中的至少一种；The plurality of first chips are chips with the same function; or, the plurality of first chips include at least two chips with different functions; or, the first chips are passive devices or active devices; or, the The first chip includes at least one of a sensor module chip, a MEMS chip, a filter chip, a logic chip, a CIS chip, a memory chip, a capacitor, an inductor, and a connection chip;
    或者，所述第一芯片为顶面接收红外辐射的芯片，或者所述第一芯片顶面为接收可见光的芯片，或者所述第一芯片顶面为接收射频信号的芯片，或者，包括柔性电路板；Alternatively, the first chip is a chip whose top surface receives infrared radiation, or the top surface of the first chip is a chip that receives visible light, or the top surface of the first chip is a chip that receives radio frequency signals, or includes a flexible circuit plate;
    或者，所述第一芯片包括：超声波传感芯片以及外围芯片，所述外围芯片包括：信号读取芯片、模拟信号处理芯片、模数转换芯片、数字逻辑芯片以及控制芯片中的至少一种；Alternatively, the first chip includes: an ultrasonic sensor chip and a peripheral chip, and the peripheral chip includes at least one of a signal reading chip, an analog signal processing chip, an analog-to-digital conversion chip, a digital logic chip, and a control chip;
    或者，所述第一芯片包括：图像传感芯片以及外围芯片，所述图像传感芯片包括：CMOS传感芯片或CCD传感芯片中的至少一种；所述外围芯片包括：信号读取芯片、模拟信号处理芯片、模数转换芯片、数字逻辑电路芯片或驱动芯片中的至少一种或几种的集成；Alternatively, the first chip includes: an image sensor chip and a peripheral chip, the image sensor chip includes at least one of a CMOS sensor chip or a CCD sensor chip; the peripheral chip includes: a signal reading chip , Integration of at least one or more of analog signal processing chips, analog-to-digital conversion chips, digital logic circuit chips or driver chips;
    或者，所述第一芯片包括：射频芯片，其中包括至少一个滤波器芯片，其他射频芯片包括信号放大、信号接收以及信号调谐中的至少一个功能。Alternatively, the first chip includes: a radio frequency chip, which includes at least one filter chip, and the other radio frequency chips include at least one function of signal amplification, signal reception, and signal tuning.
  12. 根据权利要求2所述的板级系统级封装方法，其特征在于，所述可光刻键合材料的厚度为5-200μm，所述可光刻键合材料至少覆盖所述第一芯片面积的10％。The board-level system-level packaging method according to claim 2, wherein the thickness of the photolithographic bonding material is 5-200 μm, and the photolithographic bonding material covers at least the first chip area 10%.
  13. 根据权利要求1所述的板级系统级封装方法，其特征在于，所述第一焊垫和所述第二焊垫包括正对部分、错开部分，所述正对部分的面积为面积大小大于所述第一焊垫或所述第二焊垫面积的二分之一。The board-level system-in-package method according to claim 1, wherein the first solder pad and the second solder pad comprise a facing portion and a staggered portion, and the facing portion has an area larger than Half of the area of the first pad or the second pad.
  14. 根据权利要求1所述的板级系统级封装方法，其特征在于，所述第一空隙的高度为5um-200um。The board level system level packaging method according to claim 1, wherein the height of the first void is 5um-200um.
  15. 根据权利要求1所述的板级系统级封装方法，其特征在于，所述第一焊垫或所述第二焊垫的暴露出面积为5-200平方微米；和/或，所述第一导电凸块的横截面积大于10平方微米。The board-level system-in-package method according to claim 1, wherein the exposed area of the first solder pad or the second solder pad is 5-200 square micrometers; and/or the first solder pad The cross-sectional area of the conductive bumps is greater than 10 square microns.
  16. 根据权利要求1所述的板级系统级封装方法，其特征在于，所述电镀工艺包括化学镀；所述化学镀包括：化学镀钯浸金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟，化学钯的时间为7-32分钟；The board-level system-level packaging method according to claim 1, wherein the electroplating process comprises electroless plating; the electroless plating comprises: electroless palladium immersion gold, wherein the time for electroless nickel is 30-50 minutes, and the chemical The time for gold is 4-40 minutes, and the time for chemical palladium is 7-32 minutes;
    或，化学镍金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟；Or, chemical nickel gold, wherein the time of chemical nickel is 30-50 minutes, and the time of chemical gold is 4-40 minutes;
    或，化学镍，其中化学镍的时间为30-50分钟。Or, electroless nickel, where the time for electroless nickel is 30-50 minutes.
  17. 一种板级系统级封装结构，其特征在于，包括：A board-level system-level packaging structure, characterized in that it includes:
    电路板，所述电路板表面形成有多个第一焊垫，所述第一焊垫凹陷于所述表面；a circuit board, a plurality of first pads are formed on the surface of the circuit board, and the first pads are recessed on the surface;
    多个第一芯片，所述第一芯片其中一表面形成有第二焊垫，所述第二焊垫凹陷于所述表面；a plurality of first chips, one surface of the first chips is formed with a second bonding pad, the second bonding pad is recessed on the surface;
    所述第一芯片与所述电路板键合在一起，所述第一焊垫与所述第二焊垫通过电镀的第一导电凸块电连接。The first chip and the circuit board are bonded together, and the first bonding pad and the second bonding pad are electrically connected through electroplated first conductive bumps.
  18. 根据权利要求17所述的板级系统级封装结构，其特征在于，所述第一芯片与所述电路板通过键合层键合在一起，所述键合层避开焊垫设置、覆盖所述第一导电凸块外围的区域，所述键合层的材料包括：可光刻键合材料、芯片粘结膜、介质材料、玻璃和聚合物材料中的一种或多种，所述可光刻材料包括干膜，所述介质材料包括氧化硅或者氮化硅。The board-level system-in-package structure according to claim 17, wherein the first chip and the circuit board are bonded together by a bonding layer, and the bonding layer is disposed away from the pads and covers all the In the peripheral area of the first conductive bump, the material of the bonding layer includes: one or more of photolithographic bonding materials, die bonding films, dielectric materials, glass and polymer materials. The photoresist material includes a dry film, and the dielectric material includes silicon oxide or silicon nitride.
  19. 根据权利要求18所述的板级系统级封装结构，其特征在于，所述键合层具有第一空腔，至少部分所述第一芯片键合于所述第一空腔上，所述第一空腔作为所述第一芯片的工作腔。The board-level system-in-package structure according to claim 18, wherein the bonding layer has a first cavity, and at least part of the first chip is bonded on the first cavity, and the first cavity is bonded to the first cavity. A cavity is used as the working cavity of the first chip.
  20. 根据权利要求18所述的板级系统级封装结构，其特征在于，在所述电路板中具有第二空腔，所述第一芯片位于第二空腔上方；The board-level system-in-package structure according to claim 18, wherein the circuit board has a second cavity, and the first chip is located above the second cavity;
    或者，所述电路板中具有第二空腔，所述键合层中具有第一空腔，所述第二空腔和第一空腔相对并连通，所述第一芯片位于所述第一空腔上方。Alternatively, the circuit board has a second cavity, the bonding layer has a first cavity, the second cavity and the first cavity are opposite and communicate with each other, and the first chip is located in the first cavity above the cavity.
  21. 根据权利要求17所述的板级系统级封装结构，其特征在于,所述电路板中形成有凹槽，所述凹槽的底部形成有第一焊垫，所述第一焊垫凹陷于所述凹槽的底面；The board-level system-in-package structure according to claim 17, wherein a groove is formed in the circuit board, a first solder pad is formed at the bottom of the groove, and the first solder pad is recessed in the the bottom surface of the groove;
    所述第一芯片键合于所述凹槽的底面。The first chip is bonded to the bottom surface of the groove.
  22. 根据权利要求17所述的板级系统级封装结构，其特征在于,所述多个第一芯片位于第一器件晶圆内；通过第一芯片和电路板的键合实现所述第一器件晶圆与电路板的键合。The board-level system-in-package structure according to claim 17, wherein the plurality of first chips are located in a first device wafer; and the first device wafer is realized by bonding the first chips and the circuit board. Bond of circle to circuit board.
  23. 根据权利要求22所述的板级系统级封装结构，其特征在于,所述第一器件晶圆中具有切割道，所述切割道将各个第一芯片分离；The board-level system-level packaging structure according to claim 22, wherein the first device wafer has a dicing lane, and the dicing lane separates each first chip;
    或者，所述电路板中具有贯穿的切割槽。Alternatively, the circuit board has a penetrating cutting groove therein.
  24. 根据权利要求17所述的板级系统级封装结构，其特征在于，所述第一焊垫和所述第二焊垫包括正对部分、错开部分，所述正对部分的面积为大于所述第一或第二焊垫面积的二分之一。The board-level system-in-package structure according to claim 17, wherein the first solder pad and the second solder pad comprise a facing portion and a staggered portion, and an area of the facing portion is larger than that of the One-half of the first or second pad area.
  25. 根据权利要求17所述的板级系统级封装结构，其特征在于，所述电路板包括凹槽，所述凹槽内嵌设有第二芯片，所述第二芯片表面具有第三焊垫，所述第三焊垫与相应第一芯片的第二焊垫之间形成有所述的第一导电凸块。The board-level system-in-package structure according to claim 17, wherein the circuit board comprises a groove, a second chip is embedded in the groove, and a surface of the second chip has a third solder pad, The first conductive bump is formed between the third bonding pad and the second bonding pad of the corresponding first chip.
  26. 根据权利要求17所述的板级系统级封装结构，其特征在于，所述电路板包括相对的正面和背面，所述电路板正面形成有所述第一焊垫，所述电路板背面形成有第四焊垫；所述电路板背面的第四焊垫上形成有第二导电凸块；和/或，至少一个第一芯片键合于所述电路板背面。The board-level system-in-package structure according to claim 17, wherein the circuit board comprises opposite front and back sides, the first solder pad is formed on the front side of the circuit board, and the back side of the circuit board is formed with a fourth bonding pad; a second conductive bump is formed on the fourth bonding pad on the backside of the circuit board; and/or, at least one first chip is bonded to the backside of the circuit board.
  27. 根据权利要求17所述的板级系统级封装结构，其特征在于，所述第一芯片的另一面形成有第五焊垫，所述第一芯片上键合有第三芯片，所述第三芯片含有第六焊垫，所述第五焊垫与所述第六焊垫之间通过电镀的第三导电凸块电连接。The board-level system-in-package structure according to claim 17, wherein a fifth pad is formed on the other side of the first chip, a third chip is bonded on the first chip, and the third The chip includes a sixth bonding pad, and the fifth bonding pad and the sixth bonding pad are electrically connected through a third conductive bump by electroplating.
  28. 一种电路板，其特征在于，包括：A circuit board, characterized in that it includes:
    至少一层板，每层板至少包括基板、位于所述基板表面互连结构，第一焊垫位于顶层的所述互连结构上与所述互连结构电连接；at least one layer of boards, each board at least includes a substrate, an interconnection structure located on the surface of the substrate, and a first pad located on the interconnection structure on the top layer is electrically connected to the interconnection structure;
    所述电路板的正面形成有具有光刻键合特性的第一有机介质层或第一无机介质层，第一焊垫埋设于所述第一有机介质层或第一无机介质层；和/或，A first organic medium layer or a first inorganic medium layer with photolithographic bonding characteristics is formed on the front surface of the circuit board, and a first pad is buried in the first organic medium layer or the first inorganic medium layer; and/or ,
    还包括第四焊垫，所述第四焊垫位于所述电路板底层的所述互连结构上与相应所述互连结构电连接，背面形成有光刻键合特性的第二有机介质层或第二无机介质层，第四焊垫埋设于所述第二有机介质层或所述第二无机介质层。It also includes a fourth solder pad, the fourth solder pad is located on the interconnect structure on the bottom layer of the circuit board and is electrically connected to the corresponding interconnect structure, and a second organic medium layer with photolithographic bonding characteristics is formed on the backside or the second inorganic medium layer, and the fourth pad is embedded in the second organic medium layer or the second inorganic medium layer.
  29. 根据权利要求28所述的电路板，其特征在于，所述第一有机介质层为干膜；和/或，所述第二有机介质层为干膜。The circuit board according to claim 28, wherein the first organic medium layer is a dry film; and/or the second organic medium layer is a dry film.
  30. 一种电路板的形成方法，其特征在于，包括：A method for forming a circuit board, comprising:
    至少形成一层板，每层板至少包括基板、位于所述基板表面的互连结构；形成位于顶层的板后，在顶层板上形成第一焊垫、第一焊垫与位于顶层 板的所述互连结构电连接；At least one layer of boards is formed, and each layer of boards at least includes a substrate and an interconnection structure located on the surface of the substrate; after the board on the top layer is formed, a first pad, a first pad and all the layers on the top layer are formed on the top layer. the interconnection structure is electrically connected;
    在所述顶层板上形成具有光刻键合特性的第一有机介质层或第一无机介质层，覆盖所述电路板表面、暴露出所述第一焊垫；forming a first organic dielectric layer or a first inorganic dielectric layer with photolithographic bonding properties on the top board, covering the surface of the circuit board and exposing the first pads;
    和/或，and / or,
    在底层板上形成第四焊垫、第四焊垫与位于底层板的互连结构电连接，在所述底层板上形成具有光刻键合特性的第二有机介质层或第一无机介质层，覆盖所述电路板表面、暴露出所述第四焊垫。A fourth pad is formed on the bottom plate, the fourth pad is electrically connected to the interconnect structure on the bottom plate, and a second organic medium layer or a first inorganic medium layer with photolithographic bonding characteristics is formed on the bottom plate , covering the surface of the circuit board and exposing the fourth solder pad.
PCT/CN2021/143214 2020-12-30 2021-12-30 Board-level system-level packaging method and structure, and circuit board and forming method WO2022143930A1 (en)

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CN109860064A (en) * 2018-12-21 2019-06-07 中芯集成电路（宁波）有限公司 A kind of wafer scale system packaging method and encapsulating structure
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CN113540066A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 System-level packaging structure and packaging method
CN113539849A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 System-level packaging method and packaging structure thereof
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CN113539852A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 System-level packaging method and packaging structure
CN113539857A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 System-level packaging method and packaging structure
CN113539855A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 System-level packaging method and packaging structure
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CN113555291A (en) * 2021-07-16 2021-10-26 芯知微(上海)电子科技有限公司 System-level packaging method and packaging structure
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CN115542478A (en) * 2022-11-25 2022-12-30 之江实验室 Three-dimensional packaging structure and packaging method based on photoelectric chip double-sided process
CN115542478B (en) * 2022-11-25 2023-04-07 之江实验室 Three-dimensional packaging structure and packaging method based on photoelectric chip double-sided process

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