CN114786367A - High-density interconnection circuit board and preparation method thereof - Google Patents
High-density interconnection circuit board and preparation method thereof Download PDFInfo
- Publication number
- CN114786367A CN114786367A CN202110093848.3A CN202110093848A CN114786367A CN 114786367 A CN114786367 A CN 114786367A CN 202110093848 A CN202110093848 A CN 202110093848A CN 114786367 A CN114786367 A CN 114786367A
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- Prior art keywords
- circuit board
- layer
- conductive
- circuit
- inlayer
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- 238000002360 preparation method Methods 0.000 title abstract description 4
- 230000005611 electricity Effects 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims 2
- 229920005989 resin Polymers 0.000 abstract description 14
- 239000011347 resin Substances 0.000 abstract description 14
- 239000000463 material Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application provides a high density interconnect circuit board, including the inlayer circuit board, range upon range of set up in the first circuit board of multilayer on inlayer circuit board one surface and range upon range of set up in the multilayer second circuit board of another relative surface of inlayer circuit board, each first circuit board and each second circuit board all include the via hole, are located the inlayer circuit board the first circuit board of multilayer and a plurality of via holes on the multilayer second circuit board are coaxial and overlap the setting, just a plurality of via holes electricity in proper order is connected. The maximum diameter of the plurality of via holes is gradually reduced from the inner layer circuit board to the direction far away from the inner layer circuit board, so that when resin expansion generates stress, the via holes with larger diameters in the inner layer can provide larger stress area and higher tensile tension, and the via holes arranged in an overlapped mode can be prevented from being broken. The application also provides a preparation method of the high-density interconnection circuit board.
Description
Technical Field
The present disclosure relates to circuit boards, and particularly to a high-density interconnection circuit board and a method for manufacturing the same.
Background
With the development of miniaturization and light weight of electronic products, High Density Interconnect (HDI) circuit boards are increasingly widely used. The high-density interconnection circuit board comprises insulating layers and conducting circuit layers which are arranged alternately, and the conducting circuit layers are electrically connected through blind holes penetrating through the insulating layers. In order to obtain higher density, blind holes of each layer are stacked. The material of the blind via is generally copper, and the material of the insulating layer is generally resin. However, the thermal expansion coefficients of the resin and copper are not uniform, and an inside-out stress is generated due to a difference in thermal expansion coefficient between the insulating layer and the blind via when heated, which easily causes the blind via to be broken.
Disclosure of Invention
In view of the above, it is desirable to provide a high-density interconnection circuit board and a method for manufacturing the same.
The application provides a high density interconnect circuit board, including the inlayer circuit board, range upon range of set up in the first circuit board of multilayer on inlayer circuit board one surface and range upon range of set up in the multilayer second circuit board of another relative surface of inlayer circuit board, each first circuit board and each second circuit board all include the via hole, are located the inlayer circuit board the first circuit board of multilayer and a plurality of via holes on the multilayer second circuit board are coaxial and overlap the setting, just a plurality of via holes are electric connection in proper order, the maximum diameter of a plurality of via holes certainly the inlayer circuit board is to keeping away from the direction of inlayer circuit board reduces gradually.
The application also provides a preparation method of the high-density interconnection circuit board, which comprises the following steps: providing an inner layer circuit board, wherein the inner layer circuit board comprises a substrate layer, two conductive circuit layers arranged on two opposite surfaces of the substrate layer and a through hole which penetrates through the substrate layer and is electrically connected with the two conductive circuit layers; forming a multilayer first circuit board which is stacked on one surface of the inner circuit board, wherein the first circuit board comprises a first insulating layer, a first circuit layer arranged on one surface of the first insulating layer and a through hole which penetrates through the first insulating layer and is electrically connected with the first circuit layer; forming a multilayer second circuit board in a laminated manner on the other opposite surface of the inner circuit board, wherein the second circuit board comprises a second insulating layer, a second circuit layer arranged on one surface of the second insulating layer and a via hole which penetrates through the second insulating layer and is electrically connected with the second circuit layer; the inner layer circuit board, the first multilayer circuit board and the plurality of via holes on the second multilayer circuit board are coaxial and are arranged in an overlapping mode, the plurality of via holes are sequentially and electrically connected, and the maximum diameters of the plurality of via holes are gradually reduced from the inner layer circuit board to the direction far away from the inner layer circuit board.
The application provides a high density interconnection circuit board, the maximum diameter from inside to outside of a plurality of via holes reduces gradually on the multilayer circuit board for when resin inflation produced stress, it has great diameter via hole and can provide bigger atress area and higher tensile tension to be located the inlayer, can avoid overlapping the via hole production fracture that sets up.
Drawings
Fig. 1 is a schematic cross-sectional view of a high-density interconnect circuit board provided in an embodiment of the present application.
Description of the main elements
High density interconnect circuit board 100
Inner layer wiring board 10
First insulating layer 31
Second insulating layer 51
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any inventive step are within the scope of protection of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, an embodiment of the present invention provides a high-density interconnection circuit board 100, which includes an inner layer circuit board 10, a plurality of first circuit boards 30 stacked on one surface of the inner layer circuit board 10, and a plurality of second circuit boards 50 stacked on the other opposite surface of the inner layer circuit board 10.
The inner layer circuit board 10 includes a substrate layer 11, two conductive circuit layers 13 disposed on two opposite surfaces of the substrate layer 11, and a via 15. The via hole 15 penetrates through two surfaces of the base layer 11, on which the conductive circuit layers 13 are disposed, and is electrically connected to the two conductive circuit layers 13.
In this embodiment, the material of the base layer 11 is glass fiber reinforced resin to increase the mechanical strength. The material of the base layer 11 may also be a flexible resin, such as polyimide, polyethylene terephthalate, polyethylene naphthalate, or the like. In this embodiment, the conductive trace layer 13 and the via hole 15 are made of copper. The material of the conductive circuit layer 13 and the via 15 may also be other conductive materials, such as gold, silver, etc.
The via 15 includes a conductive hole 151 and a pad 153 surrounding the conductive hole 151. The conductive via 151 penetrates through both opposite surfaces of the base layer 11, and is in contact with one conductive trace layer 13 to be electrically connected to the conductive trace layer 13. The conductive hole 151 is filled with a conductive material.
The pad 153 is formed on a surface of the substrate layer 11 to extend outward from an edge of the opening of the conductive hole 151. The pad 153 has a substantially circular ring shape, and the center of the pad 153 overlaps the center of the conductive via 151. The conductive via 151 is electrically connected to another conductive trace layer 13 that is not in contact with the conductive via 151 through the pad 153.
The first circuit board 30 includes a first insulating layer 31, a first circuit layer 33 disposed on a surface of the first insulating layer 31, and a via 35. The via hole 35 penetrates the first insulating layer 31 and is electrically connected to the first circuit layer 33.
The first insulating layer 31 is a resin layer, and the material thereof includes at least one of thermosetting resin, photosensitive resin, and thermoplastic resin. The material of the first circuit layer 33 may be copper, gold, silver, or other conductive materials.
The via 35 includes a conductive hole 351 and a pad 353 surrounding the conductive hole 351. The conductive holes 351 penetrate through the two opposite surfaces of the first insulating layer 31 and are electrically connected to the first circuit layer 33. The conductive hole 151 is filled with a conductive material.
The pad 353 is formed on one surface of the first insulating layer 31 extending outward from the edge of the opening of the conductive hole 351. The pad 353 has a substantially circular ring shape, and a center of the pad 353 overlaps a center of the conductive hole 351.
The second circuit board 50 includes a second insulating layer 51, a second circuit layer 53 disposed on a surface of the second insulating layer 51, and a via hole 55. The via hole 55 penetrates the second insulating layer 51 and is electrically connected to the second circuit layer 53.
The second insulating layer 51 is a resin layer, and the material thereof includes at least one of a thermosetting resin, a photosensitive resin, and a thermal plastic resin. The material of the second circuit layer 53 may be copper, gold, silver, or other conductive materials.
The via 55 includes a conductive via 551 and a pad 553 surrounding the conductive via 551. The conductive via 551 penetrates the two opposite surfaces of the second insulating layer 51 and is electrically connected to the second circuit layer 53. The conductive holes 551 are filled with a conductive material.
The pad 553 extends outward from an edge of the opening of the conductive via 551 and is formed on a surface of the second insulating layer 51. The pad 553 has a substantially circular ring shape, and a center of the pad 553 overlaps a center of the conductive hole 551.
The plurality of via holes 15, 35, 55 on the inner layer circuit board 10, the plurality of first circuit boards 30, and the plurality of second circuit boards 50 are coaxial and overlap, and the plurality of via holes 15, 35, 55 are electrically connected in sequence to electrically connect the two conductive circuit layers 13, the plurality of first circuit layers 33, and the plurality of second circuit layers 53.
The diameter of the conductive hole 151 gradually increases from the side adjacent to the second wiring board 50 toward the side adjacent to the first wiring board 30. The diameters of the conductive holes 351 on the first circuit board 30 and the conductive holes 551 on the second circuit board 50 are gradually increased from the side adjacent to the inner layer circuit board 10 to the direction away from the inner layer circuit board 10. Alternatively, the diameter of the conductive hole 151 may be uniform in the central axial direction thereof, the diameter of the conductive hole 351 may be uniform in the central axial direction thereof, and the diameter of the conductive hole 551 may be uniform in the central axial direction thereof.
The maximum diameter of the plurality of conductive holes 151, 351, 551 gradually decreases from the inner layer wiring board 10 toward a direction away from the inner layer wiring board 10. The pad 153 is formed extending from an opening edge of one side of the conductive hole 151 having the largest diameter. The pad 353 is formed extending from an opening edge of one side of the conductive hole 351 having the largest diameter. The pad 553 is formed extending from an opening edge of a side of the conductive via 551 having the largest diameter. The diameter of the plurality of pads 153, 353, 553 gradually decreases from the inner layer wiring board 10 to a direction away from the inner layer wiring board 10. Therefore, the maximum diameter of the plurality of via holes 15, 35 and 55 is gradually reduced from the inner layer circuit board 10 to the direction far away from the inner layer circuit board 10, and the design enables the via holes with larger diameters in the inner layer to provide larger stress area and higher tensile tension when the resin expands to generate stress, so that the via holes arranged in an overlapped mode can be prevented from being broken.
In this embodiment, the diameter of each conductive hole is controlled within a tolerance range of the diameter of the predetermined conductive hole, and the diameter of each pad is controlled within a tolerance range of the diameter of the predetermined pad.
In the present embodiment, the size of the via hole 55 located on each layer of the second wiring board 50 is equal to the size of the via hole 35 located on the corresponding layer of the first wiring board 30. Alternatively, the size of the via 55 on each layer of the second wiring board 50 and the size of the via 35 on the corresponding layer of the first wiring board 30 may not be equal.
In this embodiment, the conductive hole has a circular shape. Optionally, the shape of the conductive hole may also be an ellipse, a rectangle, or the like.
An embodiment of the present application further provides a method for manufacturing the high-density interconnection circuit board, which includes the following steps:
s1: providing an inner layer circuit board, wherein the inner layer circuit board comprises two conducting circuit layers and a through hole, the base layers are arranged on two opposite surfaces of the base layers, and the through hole penetrates through the base layers and is electrically connected with the two conducting circuit layers;
s2: forming a multilayer first circuit board which is stacked on one surface of the inner circuit board, wherein the first circuit board comprises a first insulating layer, a first circuit layer arranged on one surface of the first insulating layer and a through hole which penetrates through the first insulating layer and is electrically connected with the first circuit layer;
s3: forming a multilayer second circuit board in a laminated manner on the other opposite surface of the inner circuit board, wherein the second circuit board comprises a second insulating layer, a second circuit layer arranged on one surface of the second insulating layer and a via hole which penetrates through the second insulating layer and is electrically connected with the second circuit layer; the inner layer circuit board, the first multilayer circuit board and the plurality of via holes on the second multilayer circuit board are coaxial and are arranged in an overlapping mode, the plurality of via holes are sequentially and electrically connected, and the maximum diameters of the plurality of via holes are gradually reduced from the inner layer circuit board to the direction far away from the inner layer circuit board.
In an alternative embodiment, providing the inner layer wiring board comprises the steps of: providing a double-sided copper-clad plate; forming a through hole on the double-sided copper-clad plate; metallizing the through holes to form via holes; and carrying out circuit manufacturing on the copper layer of the double-sided copper-clad plate to form a conductive circuit layer.
In an alternative embodiment, forming a first multilayer circuit board on a surface of the inner layer circuit board in a stacked arrangement includes: providing a single-sided copper-clad plate and laminating the single-sided copper-clad plate on one surface of the inner-layer circuit board; perforating, metalizing and manufacturing a circuit on the single-sided copper-clad plate to form a first circuit layer and a via hole, so as to form a first circuit board on one surface of the inner-layer circuit board; and repeating the steps to form a plurality of layers of first circuit boards which are arranged in a stacked mode on one surface of the inner layer circuit board.
In an alternative embodiment, forming a second plurality of circuit boards in a stacked arrangement on the other opposing surface of the inner circuit board includes the steps of: providing another single-sided copper-clad plate and pressing the single-sided copper-clad plate on the other opposite surface of the inner layer circuit board; perforating, metalizing and manufacturing a circuit on the single-sided copper-clad plate to form a first circuit layer and a via hole, so as to form a second circuit board on the other surface of the inner-layer circuit board; and repeating the steps to form a plurality of layers of second circuit boards which are stacked on one another on the other surface of the inner layer circuit board.
The application provides a high density interconnect circuit board 100, the maximum diameter of a plurality of via holes reduces from inside to outside gradually on the multilayer circuit board for when resin inflation produced stress, it has great diameter via hole and can provide bigger atress area and higher tensile tension to be located the inlayer, can avoid overlapping the via hole production fracture that sets up.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention.
Claims (10)
1. The utility model provides a high density interconnect circuit board, includes the inlayer circuit board, range upon range of set up in the first circuit board of multilayer on inlayer circuit board one surface and range upon range of set up in the multilayer second circuit board of another relative surface of inlayer circuit board, its characterized in that, inlayer circuit board, each first circuit board and each second circuit board all include the via hole, are located the inlayer circuit board the first circuit board of multilayer and a plurality of via holes on the multilayer second circuit board are coaxial and overlap the setting, just a plurality of via holes are electric connection in proper order, the maximum diameter of a plurality of via holes certainly the inlayer circuit board is to keeping away from the direction of inlayer circuit board reduces gradually.
2. The high-density interconnection circuit board of claim 1, wherein each via hole comprises a conductive hole and a pad formed by extending an edge of an opening of the conductive hole, the conductive hole is filled with a conductive material, and a maximum diameter of the plurality of conductive holes and a diameter of the plurality of pads are gradually decreased from the inner circuit board to a direction away from the inner circuit board.
3. The high-density interconnect circuit board of claim 2, wherein a center of said pad and a center of said conductive via overlap.
4. The high-density interconnection circuit board according to claim 2, wherein the diameters of the conductive holes on the first wiring board and the second wiring board each increase gradually from a side adjacent to the inner-layer wiring board toward a direction away from the inner-layer wiring board, and the diameters of the conductive holes on the inner-layer wiring board increase gradually from a side adjacent to the second wiring board toward a side adjacent to the first wiring board.
5. The high-density interconnect circuit board of claim 1, wherein the size of the vias located on each layer of the second circuit board is equal to the size of the vias located on the corresponding layer of the first circuit board.
6. The high-density interconnect circuit board of claim 1, wherein said inner wiring board includes a base layer and two conductive trace layers disposed on opposite surfaces of said base layer, and a via on said first wiring board passes through said base layer and electrically connects said two conductive trace layers.
7. The high-density interconnection circuit board according to claim 1, wherein the first wiring board includes a first insulating layer and a first wiring layer provided on a surface of the first insulating layer, and the via hole on the second wiring board penetrates the first insulating layer and is electrically connected to the first wiring layer.
8. The high-density interconnect circuit board of claim 1, wherein said second circuit board includes a second insulating layer and a second circuit layer disposed on a surface of said second insulating layer, and a via on said second circuit board penetrates said second insulating layer and is electrically connected to said second circuit layer.
9. A method for preparing a high-density interconnection circuit board is characterized by comprising the following steps:
providing an inner layer circuit board, wherein the inner layer circuit board comprises a substrate layer, two conductive circuit layers arranged on two opposite surfaces of the substrate layer and a through hole which penetrates through the substrate layer and is electrically connected with the two conductive circuit layers;
forming a multilayer first circuit board in a stacked arrangement on one surface of the inner circuit board, wherein the first circuit board comprises a first insulating layer, a first circuit layer arranged on one surface of the first insulating layer and a via hole which penetrates through the first insulating layer and is electrically connected with the first circuit layer;
forming a multilayer second circuit board which is stacked on the other opposite surface of the inner circuit board, wherein the second circuit board comprises a second insulating layer, a second circuit layer arranged on one surface of the second insulating layer and a through hole which penetrates through the second insulating layer and is electrically connected with the second circuit layer;
wherein, be located the inlayer circuit board the first circuit board of multilayer and a plurality of via holes on the multilayer second circuit board are coaxial and overlap the setting, just a plurality of via holes electricity in proper order are connected, the maximum diameter of a plurality of via holes certainly the inlayer circuit board is to keeping away from the direction of inlayer circuit board reduces gradually.
10. The method according to claim 9, wherein each via hole comprises a conductive hole and a pad formed by extending outward from an opening of the conductive hole, the conductive hole is filled with a conductive material, a center of the pad overlaps a center of the conductive hole, and a maximum diameter of the plurality of conductive holes and a diameter of the plurality of pads are gradually decreased from the inner-layer circuit board to a direction away from the inner-layer circuit board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110093848.3A CN114786367A (en) | 2021-01-22 | 2021-01-22 | High-density interconnection circuit board and preparation method thereof |
| TW110103594A TWI763288B (en) | 2021-01-22 | 2021-01-29 | High-density interconnection circuit board and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110093848.3A CN114786367A (en) | 2021-01-22 | 2021-01-22 | High-density interconnection circuit board and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114786367A true CN114786367A (en) | 2022-07-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110093848.3A Pending CN114786367A (en) | 2021-01-22 | 2021-01-22 | High-density interconnection circuit board and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114786367A (en) |
| TW (1) | TWI763288B (en) |
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| TWI416673B (en) * | 2007-03-30 | 2013-11-21 | Sumitomo Bakelite Co | Connection structure for flip-chip semiconductor package, build-up layer material, sealing resin composition, and circuit substrate |
| US10276486B2 (en) * | 2010-03-02 | 2019-04-30 | General Electric Company | Stress resistant micro-via structure for flexible circuits |
| CN104254202B (en) * | 2013-06-28 | 2017-08-22 | 鹏鼎控股(深圳)股份有限公司 | Circuit board with interior embedded electronic component and preparation method thereof |
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2021
- 2021-01-22 CN CN202110093848.3A patent/CN114786367A/en active Pending
- 2021-01-29 TW TW110103594A patent/TWI763288B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200601925A (en) * | 2004-06-30 | 2006-01-01 | Unitech Printed Circuit Board Corp | Manufacturing method of modulization circuit board |
| US20080121422A1 (en) * | 2006-11-29 | 2008-05-29 | Kabushiki Kaisha Toshiba | Multilayered printed-wiring board and inter-layer connecting method thereof |
| CN201216042Y (en) * | 2008-06-04 | 2009-04-01 | 瀚宇博德股份有限公司 | Second order hole overlapping construction constructed by reverse suspension type blind hole |
| CN103379750A (en) * | 2012-04-27 | 2013-10-30 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board and manufacturing method thereof |
| CN104135822A (en) * | 2014-06-10 | 2014-11-05 | 上海美维电子有限公司 | Preparation technology of high-density interconnecting printed circuit board |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW202231143A (en) | 2022-08-01 |
| TWI763288B (en) | 2022-05-01 |
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