CN114784619B - Method for packaging VCSEL laser chip - Google Patents
Method for packaging VCSEL laser chip Download PDFInfo
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- CN114784619B CN114784619B CN202210694000.0A CN202210694000A CN114784619B CN 114784619 B CN114784619 B CN 114784619B CN 202210694000 A CN202210694000 A CN 202210694000A CN 114784619 B CN114784619 B CN 114784619B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
- H01S5/0237—Fixing laser chips on mounts by soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02315—Support members, e.g. bases or carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Wire Bonding (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention relates to a packaging method of a VCSEL laser chip, which comprises the following steps: step A, respectively arranging a chip welding layer on an electrode pad of each laser chip, step B, manufacturing a plurality of butt welding pads on the circuit board, arranging a butt welding layer on each butt welding pad, step C, butt-jointing and overlapping the chip welding layer on each laser chip on the butt welding layer of the circuit board, step D, integrally heating up, melting and hot-melting the chip welding layer and the butt welding layer together, step E, integrally cooling, cooling the chip welding layer and the butt welding layer to be connected into a whole, step C, carrying out chip packaging, and step four, cutting the circuit board to obtain a plurality of independent laser chip finished products.
Description
Technical Field
The present invention relates to a packaging method, and more particularly, to a packaging method for a VCSEL laser chip.
Background
In the field of optical communication, a Vertical Cavity Surface Emitting Laser (VCSEL) is generally packaged in an optoelectronic module of the optoelectronic module, and since a VCSEL laser chip belongs to a micron-sized component, the VCSEL laser chip needs to be assembled, welded and packaged by means of high-precision automation equipment. Generally, the automation equipment needs to perform multiple imaging and positioning through a plurality of high-definition cameras, and can finish the assembly welding of the laser chip by assisting a high-end optical positioning device, particularly, the mechanical transmission part of the automation equipment needs high structural precision, so that the purchase cost of the equipment is expensive, and in order to meet the requirement of mass production, a manufacturer needs to purchase a plurality of equipment to meet the requirement of the yield, so that the production cost of the product is greatly increased. Which is a major disadvantage of the prior art.
Disclosure of Invention
The technical scheme adopted by the invention is as follows: a packaging method of a VCSEL laser chip is characterized by comprising the following steps.
The first step is to prepare a laser chip.
The laser chip comprises a first topological structure, a second topological structure and a substrate, wherein the first topological structure and the second topological structure are arranged on the substrate at the same time, the first topological structure comprises a first active region, a first electrode pad and a first lead, the first lead is connected between the first active region and the first electrode pad, the second topological structure comprises a second active region, a second electrode pad and a second lead, and the second lead is connected between the second active region and the second electrode pad.
And a second step of simultaneously welding a plurality of laser chips on the circuit board, which specifically comprises the following steps.
And step A, respectively arranging chip welding layers on the first electrode bonding pad and the second electrode bonding pad of each laser chip.
And step B, manufacturing a plurality of pad units on the circuit board, wherein each pad unit comprises two butt-joint pads, and each butt-joint pad is provided with a butt-joint welding layer.
The pad units correspond to the laser chips one to one, and the two butt-joint pads in each pad unit correspond to the first electrode pad and the second electrode pad on one laser chip respectively.
And step C, simultaneously placing a plurality of laser chips on the circuit board, so that the chip welding layer on each laser chip is butted and superposed on the butting welding layer of the circuit board.
And D, integrally heating the circuit board and the plurality of laser chips in the step C to melt the chip welding layer and the butt welding layer and fuse the chip welding layer and the butt welding layer together.
And E, integrally cooling the circuit board and the laser chips in the step D to enable the chip welding layer and the butt welding layer to be cooled and connected into a whole.
And thirdly, packaging the laser chips welded in the second step.
And fourthly, cutting the circuit board to obtain a plurality of independent laser chip finished products.
The invention has the beneficial effects that: the invention provides a packaging method of VCSEL laser chips, which can support welding and packaging of laser chips in large batch.
Drawings
Fig. 1 is a schematic diagram of a laser chip according to the present invention.
Fig. 2 is a front view of a laser chip of the present invention.
FIG. 3 is a schematic diagram of step C of the present invention.
Fig. 4 is a schematic top view of a plurality of laser chips packaged on a circuit board according to the present invention.
FIG. 5 is a schematic view of a die solder layer stacked on a solder layer according to the present invention.
FIG. 6 is a schematic process diagram of step D and step E of the present invention.
FIG. 7 is a schematic diagram of a plurality of edge cells arranged on a wafer according to the present invention.
FIG. 8 is a schematic diagram of a border cell of the present invention.
FIG. 9 is a schematic diagram of the arrangement of a plurality of boundary cells according to the present invention.
Detailed Description
As shown in fig. 1 to 6, a method for packaging a VCSEL laser chip includes the following steps.
First, a laser chip 10 is prepared.
As shown in fig. 1 to 2, the laser chip 10 includes a first topology 100, a second topology 200 and a substrate 300, and the first topology 100 and the second topology 200 are simultaneously disposed on the substrate 300.
The first topology 100 includes a first active region 110, a first electrode pad 120, and a first conductive line 130, the first conductive line 130 being connected between the first active region 110 and the first electrode pad 120.
The second topology 200 includes a second active region 210, a second electrode pad 220, and a second conductive line 230, the second conductive line 230 being connected between the second active region 210 and the second electrode pad 220.
And a second step of simultaneously soldering a plurality of the laser chips 10 on a circuit board B, which specifically comprises the following steps.
As shown in fig. 3 and 5, in step a, a die pad layer 510 is respectively disposed on the first electrode pad 120 and the second electrode pad 220 of each laser chip 10.
And step B, manufacturing a plurality of pad units 400 on the circuit board B, wherein each pad unit 400 comprises two butt-joint pads 610, and a butt-joint solder layer 520 is arranged on each butt-joint pad 610.
The pad units 400 correspond to the laser chips 10 one to one, and the two docking pads 610 in each of the pad units 400 correspond to the first electrode pad 120 and the second electrode pad 220 on one of the laser chips 10, respectively.
As shown in fig. 3, in step C, a plurality of the laser chips 10 are simultaneously placed on the circuit board B, such that the chip solder layer 510 of each of the laser chips 10 is stacked on the docking solder layer 520 of the circuit board B.
And D, integrally heating the circuit board B and the plurality of laser chips 10 in the step C to melt and fuse the chip solder layer 510 and the butt solder layer 520 together.
In the process of step D, the die solder layer 510 and the butt solder layer 520 are first melted, and self-aligned and aligned by the surface tension of the liquid, and then are melted together, so that the physical dimensions of the die solder layer 510 and the butt solder layer 520 support the self-aligned and aligned actions of the two due to the micron-sized structures.
And E, integrally cooling the circuit board B and the plurality of laser chips 10 in the step D, and cooling and connecting the chip solder layer 510 and the butt solder layer 520 into a whole.
As shown in fig. 4, in a third step, a plurality of the laser chips 10 subjected to the second bonding step are packaged.
And packaging a plurality of laser chips 10 on the circuit board B by packaging adhesive.
And fourthly, cutting the circuit board B to obtain a plurality of independent laser chip finished products.
As shown in fig. 3 and 5, in step a, the first electrode pad 120 and the second electrode pad 220 have pad contact surfaces 511.
The die solder layer 510 has a solder layer top surface 512 and a solder layer bottom surface 513, wherein the solder layer top surface 512 is connected to the pad contact surface 511.
The area of the solder layer top surface 512 is equal to the area of the pad contact surface 511, and the area of the solder layer bottom surface 513 is smaller than the area of the solder layer top surface 512.
The die solder layer 510 includes an overflow area 514, and the overflow area 514 is disposed around the periphery of the die solder layer 510.
In step B, the landing pad 610 has a contact surface 521, and the landing solder layer 520 has a top surface 522 and a bottom surface 523, wherein the top surface 522 abuts against the solder layer bottom surface 513 of the chip solder layer 510, and the bottom surface 523 is connected to the contact surface 521 of the landing pad 610.
The contact surface 521, the top surface 522 and the bottom surface 523 are smaller in area than the bottom surface 513 of the solder layer.
The landing pad 610 includes a post 611 and a bottom plate 612, wherein the bottom plate 612 corresponds to the overflow area 514 of the die solder layer 510, and the bottom plate 612 surrounds the post 611.
As shown in fig. 6, in step D, the melting point of the butt solder layer 520 is higher than that of the die solder layer 510, and the process of melting and fusing the die solder layer 510 and the butt solder layer 520 is performed as follows.
After the temperature of the circuit board B and the laser chip 10 is raised, the chip solder layer 510 is first melted, and the laser chip 10 moves downward by the gravity of the laser chip 10.
The solder mask 520 enters the melted solder mask layer 510 and the overflow areas 514 of the solder mask layer 510 melt down the disc column 611 and form a support above the base plate 612.
Step two, the overall temperature is continuously raised, the butt solder layer 520 is melted, and the chip solder layer 510 and the butt solder layer 520 are fused together.
In step two, the melting of the butt weld layer 520 can be accelerated by the wrapping of the butt weld layer 520 formed after the overflow area 514 is melted.
As shown in fig. 6, after the chip solder layer 510 and the docking solder layer 520 are cooled and integrated in step E, the overflow area 514 is wrapped around the tray column 611, and the overflow area 514 is mounted above the bottom tray 612.
The welding point position can be made to be extremely firm through the structure, and the welding structure is greatly superior to that of the prior art.
In practical implementation, the top surface area of the substrate 300 of the laser chip 10 is S1, the area of the pad contact surface 511 of the first electrode pad 120 and the second electrode pad 220 is S2, and the relationship between S1 and S2 is as follows: 1/16 × S1< S2<1/10 × S1, the area correspondence between S1 and S2 can be determined by the above relation, so that the laser chip 10 is placed more stably and the melting and hot melting process is more smooth.
In practice, the materials and melting points of the die solder layer 510 and the solder interface layer 520 are selected according to the prior art, and the materials may be selected from gold, silver, tin, etc., or their mixture with other additives, which will not be described again.
When the method of the invention is used for batch production, the method of conveying the laser chips 10 and the circuit board B to the heating furnace and the cooling furnace by the conveyor belt can be adopted to improve the production efficiency and reduce the production cost, for example, the laser chips 10 and the circuit board B can be conveyed to the heating furnace by the conveyor belt to complete the manufacturing of the step D, and meanwhile, the laser chips 10 and the circuit board B can be conveyed to the cooling furnace by the conveyor belt to complete the manufacturing of the step E.
As shown in fig. 7 to 9, it is worth emphasizing that in practice the preparation of the laser chip 10 in the first step may be accomplished by the following steps, which include the following steps.
Step 1, arranging a chip boundary array on a wafer.
The chip boundary array includes a plurality of boundary units 20, and a plurality of boundary units 20 are arranged on the wafer to form the chip boundary array.
Each of the border cells 20 includes a transverse side having a length L and a vertical side having a length W.
The horizontal side includes a top side 11 and a bottom side 12, the vertical side includes a left side 13 and a right side 14, and a unit plane 15 is surrounded by the top side 11, the bottom side 12, the left side 13 and the right side 14.
In step 2, the first topology 100 and the second topology 200 are arranged on the cell surface 15 of each of the boundary cells 20 in the first step.
The boundary cell 20 and the first topology 100 and the second topology 200 satisfy the following plane geometry relationship.
A connection line between the first active region 110 and the center point of the first electrode pad 120 in one of the boundary cells 20 is a first inclined line 131, and the first inclined line 131 intersects the lateral edge to form a first included angle a 1.
A connection line between the second active region 210 and the center point of the second electrode pad 220 in one of the boundary cells 20 is a second inclined line 231, and the second inclined line 231 intersects the lateral side to form a second included angle a 2.
The first active region 110 in one of the boundary cells 20 is spaced apart from the center point of the second active region 210 by a distance D1.
Any two border cells 20 adjacent to each other on the left and right sides of the chip border array, wherein the distance between the first active region 110 of one border cell 20 and the center point of the second active region 210 of the other border cell 20 is D2.
Any two border cells 20 adjacent to each other up and down in the chip border array, wherein the distance between the first active region 110 of one border cell 20 and the center point of the first active region 110 of another border cell 20 is distance D3.
The distance between the first electrode pad 120 and the center point of the second electrode pad 220 in one of the boundary cells 20 is a distance D4.
The diameters of the first electrode pad 120 and the second electrode pad 220 are the diameter D5.
The center point of the first active region 110 and the second active region 210 in one of the boundary cells 20 is vertically distant from the nearest lateral side by a distance D6.
The center point of the first electrode pad 120 and the second electrode pad 220 in one of the boundary cells 20 is vertically distant from the nearest lateral side by a distance D7.
The distance between the first electrode pad 120 and the edge of the second electrode pad 220 in one of the boundary cells 20 is the distance D8.
As described above, the plane geometry calculation relations among a1, a2, W, L, D1, D2, D3, D4, D5, D6, D7, and D8 are as follows.
D1 is a fixed value, L = D1+ D2, W = D3, D4= D5+ D8.
W=D6+D7+[（D1-D4）/2] ×tanA1。
Wherein, when a1= a2, a1 takes the value of a1 or a 2.
When a1 ≠ a2, a1 takes the value of the angle between a1 and a2, which is large in absolute value.
And step 3, cutting a plurality of boundary units 20 from the wafer to obtain a plurality of independent laser chips 10.
The specific calculation of the calculation relation in step 2 is exemplified as follows.
The preferred value of D1 is 250 μm and is constant.
The size of D2 is variable, but D2 is not a function of A1 and A2, and from the aspects of production and cost (efficient utilization of wafer area), the range of D2 is controlled to be between 100 μm and 200 μm, when the value of D2 is too small, the wafer cannot be cut, when the value of D2 is too large, the area is increased, and the cost is increased, and the preferable value of D2 is 130 μm.
The size of L is variable, L = D1+ D2, consistent with the above principle, the range of L is controlled between 350 μm and 450 μm, and the preferable value of L is 380 μm.
W is variable in size, W = D3, W is a variable parameter of A1 and A2, W = D6+ D7+ [ (D1-D4)/2 ] × tanA1, and W is preferably 180 μm.
The size of D5 is variable, the range of D5 is controlled between 50 μm and 90 μm, when D5 is too small, gold wires are not easy to process, when D5 is too large, the area of a bonding pad is increased, cost control is not facilitated, and the preferable value of D5 is 70 μm.
The size of D8 is variable, the range of D8 is controlled between 20 μm and 40 μm, if D8 is too small, the production equipment and process cannot be processed (PAD space is too small to produce), if D8 is too large, the cost is affected, and the preferable value of D8 is 30 μm.
D4= D5+ D8, the value of D4 is determined according to D8, the value of D4 is controlled to be between 70 and 130 μm, and the preferred value of D4 is 100 μm.
The size of D6 is variable, the range of D6 is controlled between 50 μm and 80 μm, if D6 is too small, the wafer cannot be cut, if D6 is too large, the cost is affected, and the preferable value of D6 is 65 μm.
The size of D7 is variable, the range of D7 is controlled between 50 μm and 90 μm, if D7 is too small, the wafer cannot be cut, if D7 is too large, the cost is affected, and the preferable value of D7 is 72 μm.
The value ranges of A1 and A2 are limitedAt (-90) o , +90 o ) I.e. more than minus 90 degrees and less than plus 90 degrees, a1= a 2.
The preferable values of A1 and A2 are more than 20 degrees and less than 40 degrees, or less than minus 20 degrees and more than minus 40 degrees, the over-small values of A1 and A2 can cause that D8 is too small to produce, the over-large values can cause that W, D3 is too large to influence the cost, and the preferable values of A1 and A2 are plus or minus 30 degrees.
Preferred values for D6, D7, D1, D4, a1 are substituted into the equation for W.
D1 is a fixed value, L = D1+ D2, W = D3, D4= D5+ D8.
W=D6+D7+[（D1-D4）/2] ×tanA1。
D6=65μm，D7=72μm，D1=250μm，D4=100μm，D5=70μm，D8=30μm，A1=A2=30 o 。
The calculation result shows that W = D3=65+72+ [ (250-100)/2] ×tan30 o =180 μm, which is a preferred value for W.
And substituting the value ranges of D6, D7, D1, D4 and A1 into the equation of W.
50 μm < D6<80 μm，50 μm < D7<90 μm，D1=250μm。
70 μm < D4<130 μm，20 o < A1<40 o 。
The value range of W = D3 is found to be between 140 μm and 320 μm, which is a preferred value range of W.
Note that when a1 ≠ a2, a1 assumes an angle value with a large absolute value between a1 and a2, and substitutes the angle value into the above equation of W = D3, and the equation still holds.
The preparation of the laser chip 10 in the first step can be completed by the above method, so that the area of the wafer can be fully utilized, and the manufacturing cost of the laser chip 10 is greatly reduced.
Claims (5)
1. A packaging method of a VCSEL laser chip is characterized by comprising the following steps:
the first step is to prepare a laser chip,
the laser chip comprises a first topological structure, a second topological structure and a substrate, wherein the first topological structure and the second topological structure are arranged on the substrate at the same time, the first topological structure comprises a first active region, a first electrode pad and a first lead, the first lead is connected between the first active region and the first electrode pad, the second topological structure comprises a second active region, a second electrode pad and a second lead, the second lead is connected between the second active region and the second electrode pad,
and secondly, welding a plurality of laser chips on the circuit board simultaneously, wherein the method specifically comprises the following steps:
step A, respectively arranging chip solder layers on the first electrode pad and the second electrode pad of each laser chip,
step B, manufacturing a plurality of pad units on the circuit board, wherein each pad unit comprises two butt-joint pads, each butt-joint pad is provided with a butt-joint welding layer,
the pad units correspond to the laser chips one to one, two butt-joint pads in each pad unit respectively correspond to the first electrode pad and the second electrode pad on one laser chip,
step C, simultaneously placing a plurality of laser chips on the circuit board, enabling the chip welding layer on each laser chip to be butted and superposed on the butting welding layer of the circuit board,
step D, integrally heating the circuit board and the plurality of laser chips in the step C to melt and fuse the chip welding layer and the butt welding layer together,
step E, integrally cooling the circuit board and the plurality of laser chips in the step D to enable the chip welding layer and the butt welding layer to be cooled and connected into a whole,
thirdly, packaging a plurality of laser chips welded in the second step,
fourthly, cutting the circuit board to obtain a plurality of independent laser chip finished products,
in step A, the first electrode pad and the second electrode pad are both provided with pad contact surfaces, the chip solder layer is provided with a solder layer top surface and a solder layer bottom surface, wherein the solder layer top surface is connected to the pad contact surfaces, the area of the solder layer top surface is equal to the area of the pad contact surfaces, the area of the solder layer bottom surface is smaller than the area of the solder layer top surface, the chip solder layer comprises an overflow area, the overflow area is annularly arranged at the peripheral edge of the chip solder layer,
in step B, the docking pad has a contact surface, the docking solder layer has a top surface and a bottom surface, wherein the top surface is docked on the bottom surface of the solder layer of the die solder layer, the bottom surface is connected to the contact surface of the docking pad, the areas of the contact surface, the top surface and the bottom surface are all smaller than the area of the bottom surface of the solder layer, the docking pad includes a disc column and a base disc, wherein the base disc corresponds to the overflow area of the die solder layer, and the base disc is annularly arranged around the disc column.
2. A method of packaging a VCSEL laser chip in accordance with claim 1, wherein: in the step D, the melting point of the butt welding layer is higher than that of the chip welding layer, and the process that the chip welding layer and the butt welding layer are melted and fused together is carried out according to the following steps:
step one, after the temperature of the circuit board and the laser chip is raised integrally, the chip welding layer is firstly melted, the laser chip integrally moves downwards under the action of the gravity of the laser chip, the butt welding layer enters the melted chip welding layer, the overflow area of the chip welding layer is melted and flows downwards along the disc column, and a support is formed above the chassis,
step two, the whole temperature is continuously raised, the butt welding layer is melted, the chip welding layer and the butt welding layer are fused together,
in step E, after the chip solder layer and the butt solder layer are cooled and connected into a whole, the overflow area wraps around the disc column, and the overflow area is erected above the chassis.
3. A method of packaging a VCSEL laser chip in accordance with claim 1, wherein: in the first step, the top surface area of the substrate of the laser chip is S1, the pad contact surfaces of the first electrode pad and the second electrode pad have an area of S2, and the relationship between S1 and S2 is: 1/16 × S1< S2<1/10 × S1.
4. A method of packaging a VCSEL laser chip in accordance with claim 1, wherein: the chip solder layer and the butt solder layer are made of tin metal.
5. A method of packaging a VCSEL laser chip in accordance with claim 1, wherein: the chip solder layer and the butt solder layer are made of silver.
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