CN114744869B - Three-level step-down direct current converter - Google Patents

Three-level step-down direct current converter Download PDF

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CN114744869B
CN114744869B CN202210390810.7A CN202210390810A CN114744869B CN 114744869 B CN114744869 B CN 114744869B CN 202210390810 A CN202210390810 A CN 202210390810A CN 114744869 B CN114744869 B CN 114744869B
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CN114744869A (en
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陈林峰
刘腾帝
伍荣翔
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A three-level step-down DC converter belongs to the field of power electronics. The direct current converter comprises a power stage circuit and a feedback control stage circuit, wherein the power stage circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a flying capacitor, an inductor and an output capacitor C; the feedback control stage circuit comprises a sampling amplification and compensation circuit, a duty ratio generation circuit, a first driving circuit and a second driving circuit, wherein the duty ratio generation circuit comprises a comparator, an SR latch, a conduction time control circuit, a duty ratio separation circuit and a clock signal generation circuit. The three-level buck direct-current converter provided by the invention adopts a new duty ratio generation circuit, realizes a new adaptive triangular wave technology, optimizes a feedback loop, reduces the use of an operational amplifier, effectively reduces the circuit complexity and simultaneously improves the circuit response speed.

Description

Three-level step-down direct current converter
Technical Field
The invention belongs to the field of power electronics, and particularly relates to a three-level buck direct current converter.
Background
The Buck DC converter has been widely used in various modern electronic products, and the Buck circuit is the most basic Buck DC converter and one of the most widely used DC/DC topologies. However, as the requirement of products on power supplies is higher and higher, the output ripple of a common Buck-type dc converter is difficult to meet, and the output ripple of the Buck-circuit-based three-level Buck-type dc converter can be reduced to a greater extent, so that the three-level Buck-type dc converter is more and more emphasized by academia and industry. On the basis of a common Buck Buck direct-current converter, the three-level Buck direct-current converter based on the Buck circuit is additionally provided with two switches and a flying capacitor, so that ripples of output voltage can be reduced under the condition that the output voltage is not influenced.
The three-level buck direct-current converter adopts two PWM signals (D1 and D2) with the same duty ratio and 180-degree phase difference to respectively control the on-off of four switching tubes. The first PMOS tube P1 and the first NMOS tube N1 are controlled by PWM signals with duty ratio D1, and the second PMOS tube P2 and the second NMOS tube N2 are controlled by PWM signals with duty ratio D2. Ideally, the dc voltage of the flying capacitor is maintained at half of the input voltage, and the output ripple can be greatly suppressed. However, due to the parasitic effect of the circuit or the change of the input voltage, the flying capacitor voltage always deviates from half of the input voltage, which may cause an increase in output ripple and an increase in risk of power tube breakdown, so that compensation needs to be added in the control loop to maintain the flying capacitor dc voltage at half of the input voltage.
Fig. 1 is a schematic diagram of a conventional three-level buck dc converter, in which a duty cycle generating circuit is shown in fig. 2. The sampling amplification and compensation circuit feeds back the output voltage, compares the output voltage with a reference voltage Vref and compensates the output voltage, and outputs an error signal V EA The error signal is split in an error compensation circuit into two signals V with opposite trend EA_cali1 And V EA_cali2 Corresponding to the control duty ratios D1 and D2, respectively. The error compensation circuit includes a signal generation circuit and differential and common mode negative feedback circuits, and for the error signal V EA Based on the input voltage V input by the signal generating circuit g Half V of the input voltage g /2, voltage V between two ends of flying capacitor A And V B Treatment to produce V NP 、V NN 、V PP And V PN Four signals. The four signals are input into the differential and common mode negative feedback circuit, so that the error signal V can be obtained EA Is divided into V EA_cali1 And V EA_cali2 . It can be seen that the control loop of the conventional three-level buck dc-to-dc converter is complicated, uses more resistive elements, and requires additional circuitry to generate, for example, half V of the input voltage g A/2 signal, and two clock signals and a triangular wave signal which are 180 DEG out of phase; when the input voltage changes, the generated signal needs to pass through the signal generation circuit and the differential and common mode negative feedback circuit to influence the duty ratio, and further influence the voltage of the flying capacitor, so that the flying capacitor does not respond to the change of the input voltage quickly, and the flying capacitor cannot respond quickly when the input voltage changesStabilizing to half the input voltage, resulting in a large ripple of the output voltage over a long period of time.
Disclosure of Invention
The invention aims to provide a three-level buck direct current converter aiming at the defects in the prior art.
In order to realize the purpose, the technical scheme adopted by the invention is as follows:
a three-level step-down DC converter comprises a power stage circuit 101 and a feedback control stage circuit 102;
the power stage circuit 101 comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2, a flying capacitor C F An inductor L and an output capacitor C;
the source electrode of the first PMOS pipe P1 is coupled to an input voltage V g The drain electrode is coupled to the source electrode of the second PMOS pipe P2 and the flying capacitor C F The grid electrode of the first NMOS tube N1 is coupled to the first drive circuit and the grid electrode of the first NMOS tube N1; the drain electrode of the second PMOS tube P2 is coupled to the drain electrode of the second NMOS tube N2 and the first electrode of the inductor L, the source electrode is coupled to the drain electrode of the first PMOS tube P1, and the grid electrode is coupled to the second drive circuit and the grid electrode of the second NMOS tube N2; the source electrode of the first NMOS transistor N1 is coupled to the ground voltage, the drain electrode is coupled to the source electrode of the second NMOS transistor N2 and the flying capacitor C F A gate coupled to the first driving circuit; the source electrode of the second NMOS transistor N2 is coupled to the drain electrode of the first NMOS transistor N1 and the flying capacitor C F The drain of the second electrode is coupled to the drain of the second PMOS transistor P2, and the gate of the second electrode is coupled to the second driving circuit; the second electrode of the inductor L is coupled to the second electrode of the output capacitor C and the sampling amplification and compensation circuit and is used as the output power voltage of the three-level buck direct-current converter, and the first electrode of the output capacitor C is coupled to the ground voltage;
the feedback control stage circuit 102 comprises a sampling amplification and compensation circuit 103, a duty ratio generation circuit 104, a first drive circuit 105 and a second drive circuit 106;
an input port of the sampling amplification and compensation circuit 103 is coupled to the second electrode of the inductor L, and an output port is coupled to an input port of the duty cycle generation circuit 104; a first output port of the duty cycle generation circuit 104 is coupled to an input port of the first drive circuit 105, and a second output port of the duty cycle generation circuit 104 is coupled to an input port of the second drive circuit 106; an output port of the first driving circuit 105 is coupled to the gates of a first PMOS transistor P1 and a first NMOS transistor N1, and an output port of the second driving circuit 106 is coupled to the gates of a second PMOS transistor P2 and a second NMOS transistor N2;
the duty ratio generation circuit 104 comprises a comparator OP1, an SR latch 201, an on-time control circuit 202, a duty ratio separation circuit 203 and a clock signal generation circuit 204;
a first input port of the comparator OP1 is coupled to the input port of the duty cycle generation circuit 104, a second input port of the comparator OP1 is coupled to the output port of the on-time control circuit 202, and an output port of the comparator OP1 is coupled to the reset input port (R port) of the SR latch; a set input port (S port) of the SR latch is coupled to an output port of the clock signal generation circuit 204, a non-inverting output port (Q port) of the SR latch is coupled to an input port of the duty separation circuit 203, an output port of the duty separation circuit 203 is coupled to an output port of the duty generation circuit 104, and an inverting output port of the SR latch: (
Figure BDA0003595433100000035
Port) is coupled to an input port of the on-time control circuit 202.
Further, the on-time control circuit 202 includes a voltage-current conversion circuit 301, a third PMOS transistor P3, a third NMOS transistor N3, and a timing capacitor Cr;
the gates of the third PMOS transistor P3 and the third NMOS transistor N3 are coupled to the input port of the on-time control circuit 202, the drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, and the first electrode of the timing capacitor Cr are coupled to the output port of the on-time control circuit 202, the source of the third PMOS transistor P3 is coupled to the output port of the voltage-current conversion circuit 301, the source of the third NMOS transistor N3 is coupled to the ground voltage, and the voltage-current conversion circuit301 is coupled to an input voltage V g And the second input port is coupled to the drain electrode of the second PMOS tube, and the second electrode of the timing capacitor Cr is coupled to the ground voltage.
The invention provides a three-level step-down direct current converter, which has the working principle that:
the sampling amplification and compensation circuit collects the output voltage Vout of the power stage circuit, outputs a control signal (Vcon) and compares the control signal with the triangular wave generated by the conduction time control circuit in a comparator (OP 1), the signal output by the comparator is used as an input signal of a reset port (R port) of the SR latch, and a set port (S port) of the SR latch inputs a clock signal of the clock signal generating circuit, so that the SR latch is set once every half switching period, and the SR latch is enabled to be connected with the clock signal generating circuit in series, and the output signal of the SR latch is used as an input signal of a reset port (R port) of the SR latch
Figure BDA0003595433100000031
The port outputs a low level to actuate and->
Figure BDA0003595433100000032
The on-time control circuit connected with the port generates a triangular wave signal from a low level until the on-time control circuit is connected with the port>
Figure BDA0003595433100000033
The port is high, i.e., the level of the triangle wave increases to the magnitude of the Vcon signal when it is asserted>
Figure BDA0003595433100000034
The port is at a high level, so that the triangular wave level of the conduction time control circuit returns to a low level; the Q port output signal of the SR latch is used as the input signal of the duty ratio separation circuit; the duty ratio separation circuit separates an input signal into two PWM signals with duty ratios of D1 and D2 and a phase difference of 180 degrees; therefore, the on-off time of the power level switch tube can be controlled by the output voltage, and the stable output voltage is realized.
The working process of the conduction time control circuit is as follows:
input voltage V g And a secondAfter the drain voltage Vsw of the PMOS tube is input into the voltage-current conversion circuit, obtaining a current I with the size of alpha Vg-beta Vsw, wherein alpha and beta are transconductance of the voltage-current conversion circuit; when the temperature is higher than the set temperature
Figure BDA0003595433100000041
When the port is at a low level, P3 is switched on, N3 is switched off, at the moment, the current I charges the timing capacitor Cr, and the switching-on time control circuit outputs a linearly increased voltage in direct proportion to the charging current; when/is>
Figure BDA0003595433100000042
When the port is at a high level, P3 is turned off, N3 is turned on, the timing capacitor Cr discharges through N3, and the output voltage of the on-time control circuit rapidly drops to the ground voltage; the rising and falling processes described above form a triangular wave signal related to Vg and Vsw, which is similar to the adaptive triangular wave technique except that the dc converter of the present invention reflects the magnitude of the power supply voltage and flying capacitor voltage onto the slope of the generated triangular wave.
The on-time control circuit generates a triangular wave signal compared with the Vcon signal so as to achieve the purpose of stabilizing the output voltage, and meanwhile, the effect that the voltage of the flying capacitor is stabilized to 0.5Vg and output ripples are restrained can be achieved.
The specific principle is as follows:
there are four operating states for the power stage circuit: when P1 and N2 are conducted, namely a state 1 (S1), the flying capacitor is connected with the inductor and the power supply in series, and the drain voltage Vsw of the second PMOS tube is = Vg-Vcf; when P1 and P2 are turned on, referred to as state 2 (S2), one end of the flying capacitor is floating, and the inductor is connected to ground, where Vsw =0; when P2 and N1 are on, referred to as state 3 (S3), the flying capacitor and inductor are coupled to ground, vsw = Vcf; when P1 and P2 are on, referred to as state 4 (S4), vsw = Vg. When the output voltage Vout is less than 0.5Vg, the power stage circuit cyclically changes in the order of S1, S2, S3, S2 in a switching period, and therefore Vsw cyclically changes in the order of Vg-Vcf, 0, vcf, 0 in a switching period; similarly, when Vout >0.5Vg, in a switching period, the power stage circuit will cyclically change in the order of S4, S1, S4, S3, and Vsw will cyclically change in the order of Vg, vg-Vcf, vg, vcf in a period.
At Vout<0.5Vg as an example, when a clock cycle starts, the clock signal generation circuit outputs a narrow pulse, so that the input port of the SR latch S becomes high, the SR latch is set,
Figure BDA0003595433100000043
the output port becomes low potential, so the on-time control circuit inputs low potential, P3 is on, N3 is off, the timing capacitor starts to charge, and simultaneously the power stage circuit enters state 1 (S1), vsw = Vg-Vcf, the charging current of the timing capacitor is α Vg- β (Vg-Vcf), the output voltage of the on-time control circuit linearly increases in proportion to the charging current until the output voltage of the on-time control circuit is equal to the first port input signal Vcon of the comparator OP1, which is called as £ or>
Figure BDA0003595433100000051
A stage; when the output voltage of the on-time control circuit is equal to the Vcon signal input by the first port of the comparator OP1, the comparator OP1 outputs high level, the SR latch is reset, namely->
Figure BDA0003595433100000052
The port outputs high level, so that the conduction time control circuit inputs high potential, P3 is disconnected, N3 is conducted, the timing capacitor Cr discharges through N3, the output voltage of the conduction time control circuit quickly drops to the ground potential and is kept until the conduction time control circuit is charged again, and the voltage is called as ^ or ^>
Figure BDA0003595433100000053
A phase when the power stage circuit enters state 2 (S2), vsw =0; so far the power stage circuit changes from state 1 (S1) to state 2 (S2) in the last half cycle, and the on-time control circuit has generated a triangular wave signal ω 1 in the half cycle. When the next half cycle starts, the clock signal generation circuit outputs a narrow pulse, so that the on-time control circuit starts to charge the timing capacitor Cr again, and the same procedure is followedThe time power stage circuit enters state 3 (S3), vsw = Vcf, so that the charging current of the timing capacitor is α Vg- β Vcf, and the output voltage of the on-time control circuit linearly increases again until the output voltage of the on-time control circuit is equal to the first port input signal Vcon of the comparator OP1, which is called ÷ Vcf>
Figure BDA0003595433100000054
A stage; when the output voltage of the on-time control circuit is equal to the Vcon signal input from the first port of the comparator OP1, the output voltage of the on-time control circuit quickly drops to the ground potential again and is kept until the on-time control circuit is charged again, which is called as ^ or ^>
Figure BDA0003595433100000055
A phase, while the power stage circuit enters state 2 (S2), vsw =0; the power stage circuit changes from state 3 (S3) to state 2 (S2) during the next half-cycle, and the on-time control circuit generates a triangle wave signal ω 2 during the half-cycle that is greater than or equal to the ω 1 triangle wave signal generated during the last half-cycle>
Figure BDA0003595433100000056
Stage sum>
Figure BDA0003595433100000057
The current on which the voltage rise slope of the phases depends is different; when the circuit is in a stable state, i.e., vcf =0.5Vsw, both Vsw = Vg-Vcf for state 1 (S1) and Vsw = Vcf for state 3 (S3) are equal to 0.5Vg, so ω 1 ∑ vs>
Figure BDA0003595433100000058
Stage and ω 2->
Figure BDA0003595433100000059
In the stage, the charging currents are the same, so the voltage rising slopes are the same; when the circuit is unstable, e.g. Vcf<0.5Vg, where Vsw for state 1 (S1) is greater than Vsw for state 3 (S3), such that ω 1 @>
Figure BDA00035954331000000510
A phase charging current (alpha Vg-beta (Vg-Vcf)) is less than #2 #>
Figure BDA00035954331000000511
The phase charging current (α Vg- β Vcf) is thus reached the same Vcon, greater or lesser than>
Figure BDA00035954331000000512
Longer stage time, ->
Figure BDA00035954331000000513
The phase time is shorter, resulting in a duty cycle D1 of the final output>D2, namely the charging time of the flying capacitor is longer than the discharging time, and Vcf rises; similarly, when Vcf >0.5Vg, D1 < D2, such that Vcf is reduced; the flying capacitor voltage can be stabilized to 0.5Vg, so that the capability of the three-level buck converter for inhibiting the output ripple is exerted to the maximum extent.
Compared with the prior art, the invention has the beneficial effects that:
the three-level buck direct current converter provided by the invention adopts a new duty ratio generation circuit, realizes a new self-adaptive triangular wave technology, optimizes a feedback loop, reduces the use of an operational amplifier, effectively reduces the circuit complexity and simultaneously improves the circuit response speed.
Drawings
Fig. 1 is a schematic diagram of a conventional three-level buck dc converter;
fig. 2 is a schematic structural diagram of a duty cycle generation circuit in a conventional three-level buck dc converter;
fig. 3 is a schematic structural diagram of a duty cycle generating circuit in a three-level buck dc converter according to the present invention;
fig. 4 is a schematic structural diagram of a turn-on time control circuit in a three-level buck dc converter according to an embodiment of the present invention;
fig. 5 is a waveform diagram of Vcf <0.5Vg and Vcf >0.5Vg in a three-level buck dc-to-dc converter according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is detailed below by combining the accompanying drawings and the embodiment.
A three-level step-down DC converter, as shown in FIG. 1, includes a power stage circuit 101 and a feedback control stage circuit 102;
the power stage circuit 101 comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2, and a flying capacitor C F An inductor L and an output capacitor C;
the source electrode of the first PMOS pipe P1 is coupled to an input voltage V g The drain electrode of the first PMOS tube P2 is coupled to the source electrode of the first NMOS tube N1, the first electrode of the flying capacitor CF is coupled to the drain electrode of the first PMOS tube P2, and the first drive circuit is coupled to the first drive circuit; the drain electrode of the second PMOS pipe P2 is coupled to the drain electrode of the second NMOS pipe N2 and the first electrode of the inductor L, the source electrode is coupled to the drain electrode of the first PMOS pipe P1, and the grid electrode is coupled to the second drive circuit and the grid electrode of the second NMOS pipe N2; the source electrode of the first NMOS tube N1 is coupled to the ground voltage, the drain electrode of the first NMOS tube N1 is coupled to the source electrode of the second NMOS tube N2 and the second electrode of the flying capacitor CF, and the grid electrode of the first NMOS tube N is coupled to the first driving circuit; the source electrode of the second NMOS transistor N2 is coupled to the drain electrode of the first NMOS transistor N1 and the second electrode of the flying capacitor CF, the drain electrode is coupled to the drain electrode of the second PMOS transistor P2, and the grid electrode is coupled to the second drive circuit; the second electrode of the inductor L is coupled to the second electrode of the output capacitor C and the sampling amplification and compensation circuit and is used as the output power voltage of the three-level buck direct-current converter, and the first electrode of the output capacitor C is coupled to the ground voltage;
the feedback control stage circuit 102 comprises a sampling amplification and compensation circuit 103, a duty ratio generation circuit 104, a first drive circuit 105 and a second drive circuit 106;
an input port of the sampling amplification and compensation circuit 103 is coupled to the second electrode of the inductor L, and an output port is coupled to an input port of the duty cycle generation circuit 104; a first output port of the duty cycle generation circuit 104 is coupled to an input port of the first drive circuit 105, and a second output port of the duty cycle generation circuit 104 is coupled to an input port of the second drive circuit 106; an output port of the first driving circuit 105 is coupled to the gates of a first PMOS transistor P1 and a first NMOS transistor N1, and an output port of the second driving circuit 106 is coupled to the gates of a second PMOS transistor P2 and a second NMOS transistor N2;
the duty ratio generation circuit 104 includes a comparator OP1, an SR latch 201, an on-time control circuit 202, a duty ratio separation circuit 203, and a clock signal generation circuit 204, as shown in fig. 3;
a first input port of the comparator OP1 is coupled to the input port of the duty cycle generation circuit 104, a second input port of the comparator OP1 is coupled to the output port of the on-time control circuit 202, and an output port of the comparator OP1 is coupled to the reset input port (R port) of the SR latch; a set input port (S port) of the SR latch is coupled to an output port of the clock signal generation circuit 204, a non-inverting output port (Q port) of the SR latch is coupled to an input port of the duty separation circuit 203, an output port of the duty separation circuit 203 is coupled to an output port of the duty generation circuit 104, and an inverting output port of the SR latch (S) ((
Figure BDA0003595433100000071
Port) is coupled to an input port of on-time control circuit 202;
the on-time control circuit 202 includes a voltage-current conversion circuit 301, a third PMOS transistor P3, a third NMOS transistor N3, and a timing capacitor Cr, as shown in fig. 4;
the gates of the third PMOS transistor P3 and the third NMOS transistor N3 are coupled to the input port of the on-time control circuit 202, the drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, and the first electrode of the timing capacitor Cr are coupled to the output port of the on-time control circuit 202, the source of the third PMOS transistor P3 is coupled to the output port of the voltage-current converting circuit 301, the source of the third NMOS transistor N3 is coupled to the ground voltage, and the first input port of the voltage-current converting circuit 301 is coupled to the input voltage V g And the second input port is coupled to the drain electrode of the second PMOS tube, and the second electrode of the timing capacitor Cr is coupled to the ground voltage.
Sampling amplifying and compensating circuitCollecting the output voltage Vout of the power stage circuit, outputting a control signal (Vcon) and comparing the output signal with the triangular wave generated by the conduction time control circuit in a comparator (OP 1), wherein the signal output by the comparator is used as the input signal of a reset port (R port) of the SR latch, and a set port (S port) of the SR latch inputs the clock signal of the clock signal generating circuit, so that the SR latch is set once every half switching period, and the clock signal is generated by the clock signal generating circuit
Figure BDA0003595433100000081
The port outputs a low level to actuate and->
Figure BDA0003595433100000082
The on-time control circuit connected with the port generates a triangular wave signal from a low level until the on-time control circuit is connected with the port>
Figure BDA0003595433100000083
The port is high, i.e., the level of the triangle wave increases to the magnitude of the Vcon signal when it is asserted>
Figure BDA0003595433100000084
The port is at a high level, so that the triangular wave level of the conduction time control circuit returns to a low level; the Q port output signal of the SR latch is used as the input signal of the duty ratio separation circuit; the duty ratio separation circuit separates an input signal into two PWM signals with duty ratios of D1 and D2 and a phase difference of 180 degrees; therefore, the on-off time of the power level switch tube can be controlled by the output voltage, and the stable output voltage is realized.
In order to maintain the optimal output ripple suppression effect, the flying capacitor voltage should be maintained at 0.5Vg, but due to factors such as parasitic parameters of the circuit, the flying capacitor voltage may deviate from 0.5Vg in an ideal state, so that the ripple suppression effect is reduced, and the output ripple increases, so that maintaining the flying capacitor voltage Vcf =0.5Vg is important for the three-level buck converter.
FIG. 5 shows a three-level buck DC converter according to an embodiment of the present invention, when Vcf is less than 0.5Vg and Vcf>0.5Vg timeThe feedback circuit is used to stabilize the flying capacitor voltage to a 0.5Vg waveform. As can be seen from fig. 5, the state of the power stage circuit cyclically changes from S1, S2, S3, and S4 in this order within one cycle, corresponding to V ramp Phase phi 1, phase phi 2, phase phi 3 and phase phi 4 of the signal. When Vcf =0.5Vg, the circuit enters a steady state, where Vsw = Vg-Vcf in the phase Φ 1 and Vsw = Vcf in the phase Φ 3 are equal, so that the charging current I = α Vg- β Vsw to the timing capacitor Cr is equal in the two phases, and V = α Vg- β Vsw is equal in the two phases ramp Linear rising voltage exhibiting the same slope, the time to reach Vcon is the same, so D1= D2, as V of fig. 5 ramp The solid line portion. If Vcf<0.5Vg, vsw = Vg-Vcf will be larger than the steady state value during the phase Φ 1, and the current charging the timing capacitor Cr during the phase Φ 1 will be smaller than the steady state current, so that V is ramp The slope in the phase phi 1 is smaller than the slope in the steady state, i.e. the time reaching Vcon is longer, so that the duty ratio D1 is increased, and similarly, the value of Vsw = Vcf in the phase phi 3 is smaller than that in the steady state, the charging current is increased, and V ramp The slope becomes larger, the time to reach Vcon decreases, D2 decreases, so the charging time of the flying capacitor increases, the discharging time decreases, and Vcf increases, as shown by the dashed line in the first cycle of fig. 5. Otherwise if Vcf>0.5Vg, as shown in the dotted line part of the second period of fig. 5, the circuit can decrease D1 by increasing the charging current of the phi 1 phase timing capacitor Cr and decrease D2 by decreasing the charging current of the phi 3 phase, so that the charging time of the flying capacitor CF is decreased, the discharging time is increased, vcf is decreased, and finally Vcf is stabilized to 0.5Vg.
In conclusion, the three-level buck direct-current converter provided by the invention can effectively simplify a feedback control loop and improve the response speed of the flying capacitor voltage to the input voltage change.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention, and all of them should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (1)

1. A three-level step-down DC converter is characterized by comprising a power level circuit and a feedback control level circuit;
the power stage circuit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a flying capacitor, an inductor and an output capacitor;
the source electrode of the first PMOS tube is coupled to an input voltage, the drain electrode of the first PMOS tube is coupled to the source electrode of the second PMOS tube and the first electrode of the flying capacitor, and the grid electrode of the first PMOS tube is coupled to the first drive circuit and the grid electrode of the first NMOS tube; the drain electrode of the second PMOS tube is coupled to the drain electrode of the second NMOS tube and a first electrode of the inductor, the source electrode of the second PMOS tube is coupled to the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is coupled to the second drive circuit and the grid electrode of the second NMOS tube; the source electrode of the first NMOS tube is coupled to the ground voltage, the drain electrode of the first NMOS tube is coupled to the source electrode of the second NMOS tube and the second electrode of the flying capacitor, and the grid electrode of the first NMOS tube is coupled to the first driving circuit; the source electrode of the second NMOS tube is coupled to the drain electrode of the first NMOS tube and the second electrode of the flying capacitor, the drain electrode of the second NMOS tube is coupled to the drain electrode of the second PMOS tube, and the grid electrode of the second NMOS tube is coupled to the second driving circuit; the second electrode of the inductor is coupled to the second electrode of the output capacitor and the sampling amplification and compensation circuit and serves as an output voltage end of the three-level buck direct current converter, and the first electrode of the output capacitor is coupled to the ground voltage;
the feedback control stage circuit comprises a sampling amplification and compensation circuit, a duty ratio generation circuit, a first drive circuit and a second drive circuit;
the input port of the sampling amplification and compensation circuit is coupled to the second electrode of the inductor, and the output port of the sampling amplification and compensation circuit is coupled to the input port of the duty cycle generation circuit; a first output port of the duty cycle generation circuit is coupled to an input port of the first drive circuit, and a second output port of the duty cycle generation circuit is coupled to an input port of the second drive circuit; the output port of the first driving circuit is coupled to the grids of a first PMOS tube and a first NMOS tube, and the output port of the second driving circuit is coupled to the grids of a second PMOS tube and a second NMOS tube;
the duty ratio generating circuit comprises a comparator, an SR latch, a conduction time control circuit, a duty ratio separation circuit and a clock signal generating circuit;
a first input port of the comparator is coupled to an input port of the duty cycle generation circuit, a second input port of the comparator is coupled to an output port of the on-time control circuit, and an output port of the comparator is coupled to a reset input port of the SR latch; a set input port of the SR latch is coupled to an output port of the clock signal generating circuit, a normal-phase output port of the SR latch is coupled to an input port of the duty cycle separation circuit, an output port of the duty cycle separation circuit is coupled to an output port of the duty cycle generating circuit, and an inverted-phase output port of the SR latch is coupled to an input port of the conduction time control circuit;
the on-time control circuit comprises a voltage-current conversion circuit, a third PMOS tube, a third NMOS tube and a timing capacitor;
the gates of the third PMOS transistor and the third NMOS transistor are coupled to the input port of the on-time control circuit, the drain of the third PMOS transistor, the drain of the third NMOS transistor, and the first electrode of the timing capacitor are coupled to the output port of the on-time control circuit, the source of the third PMOS transistor is coupled to the output port of the voltage-current conversion circuit, the source of the third NMOS transistor is coupled to the ground voltage, the first input port of the voltage-current conversion circuit is coupled to the input voltage, the second input port is coupled to the drain of the second PMOS transistor, and the second electrode of the timing capacitor is coupled to the ground voltage.
CN202210390810.7A 2022-04-14 2022-04-14 Three-level step-down direct current converter Active CN114744869B (en)

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Publication number Priority date Publication date Assignee Title
CN115250061B (en) * 2022-09-23 2023-01-06 深圳市微源半导体股份有限公司 Voltage transformation circuit and electronic device
CN116667650B (en) * 2023-04-18 2024-02-20 华南理工大学 Single-inductor multi-level direct current converter based on self-adaptive slope calibration mode

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552554A (en) * 2009-05-11 2009-10-07 南京航空航天大学 Control circuit of cascade type buck-boost converter and control method thereof
CN103701325A (en) * 2013-12-19 2014-04-02 南京航空航天大学 Capacitor voltage control circuit for half-bridge three-level DC converter
CN107196523A (en) * 2017-05-26 2017-09-22 中南大学 A kind of three level active third-harmonic zero-sequence voltage matrix converters of T-type structure
US10090763B1 (en) * 2017-06-19 2018-10-02 Dialog Semiconductor (Uk) Limited Multi-level buck converter having a regulated flying capacitor voltage used for high-side drive
CN109687704A (en) * 2018-12-25 2019-04-26 南京矽力杰半导体技术有限公司 The Capacity control method, apparatus and decompression transformation system of three-level buck converter
CN112653328A (en) * 2020-12-10 2021-04-13 电子科技大学 High-voltage conversion ratio direct-current power supply converter
CN112968608A (en) * 2021-01-05 2021-06-15 电子科技大学 Pulse width modulation type power converter
CN113328622A (en) * 2021-06-04 2021-08-31 江南大学 Control method of flying capacitor type three-level direct current buck converter
CN113765368A (en) * 2021-07-30 2021-12-07 华为技术有限公司 Three-level direct current converter, power supply system and chip

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10498236B2 (en) * 2016-04-11 2019-12-03 Tianshu Liu Two-phase three-level converter and controller therefor
US20170201170A1 (en) * 2017-03-26 2017-07-13 Ahmed Fayez Abu-Hajar Method for generating highly efficient harmonics free dc to ac inverters
US11362587B2 (en) * 2017-08-15 2022-06-14 Texas Instruments Incorporated Hysteretic pulse modulation for charge balance of multi-level power converters
US20210067033A1 (en) * 2019-08-29 2021-03-04 Qualcomm Incorporated Differential sensing and maintenance of flying capacitor voltage in a switched-mode power supply circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552554A (en) * 2009-05-11 2009-10-07 南京航空航天大学 Control circuit of cascade type buck-boost converter and control method thereof
CN103701325A (en) * 2013-12-19 2014-04-02 南京航空航天大学 Capacitor voltage control circuit for half-bridge three-level DC converter
CN107196523A (en) * 2017-05-26 2017-09-22 中南大学 A kind of three level active third-harmonic zero-sequence voltage matrix converters of T-type structure
US10090763B1 (en) * 2017-06-19 2018-10-02 Dialog Semiconductor (Uk) Limited Multi-level buck converter having a regulated flying capacitor voltage used for high-side drive
CN109687704A (en) * 2018-12-25 2019-04-26 南京矽力杰半导体技术有限公司 The Capacity control method, apparatus and decompression transformation system of three-level buck converter
CN112653328A (en) * 2020-12-10 2021-04-13 电子科技大学 High-voltage conversion ratio direct-current power supply converter
CN112968608A (en) * 2021-01-05 2021-06-15 电子科技大学 Pulse width modulation type power converter
CN113328622A (en) * 2021-06-04 2021-08-31 江南大学 Control method of flying capacitor type three-level direct current buck converter
CN113765368A (en) * 2021-07-30 2021-12-07 华为技术有限公司 Three-level direct current converter, power supply system and chip

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