CN114744036A - Groove type field effect transistor with sectional type gate structure and preparation method thereof - Google Patents
Groove type field effect transistor with sectional type gate structure and preparation method thereof Download PDFInfo
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The application relates to a trench field effect transistor with a segmented gate structure and a preparation method thereof. The transistor includes: the device comprises a substrate region, a drift region, a base region, a source region, a shielding grid, a control grid, an insulating layer, a source electrode, a drain electrode and a metal grid; the drift region, the base region, the source region and the source electrode are sequentially arranged above the substrate region, and the drain electrode is arranged below the substrate region; the control grid and the shielding grid are sequentially arranged on one side of the drift region from top to bottom and are respectively connected with the drift region, the substrate region and the source region through insulating layers; the control grid and the shielding grid are separated by an insulating layer; the shielding grid is made of metal materials with different work functions from top to bottom; the control grid is made of metal materials with different work functions from top to bottom; the source electrode is arranged above the source region; the metal gate is arranged above the control gate. According to the scheme provided by the application, the breakdown voltage of the transistor device can be improved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a trench type field effect transistor with a sectional type gate structure and a preparation method thereof.
Background
The shielded gate trench field effect transistor SGT has the advantages of low specific on resistance, low static and dynamic loss, high switching speed, and the like. This is because it effectively isolates the control gate to drain coupling, with obvious advantages in terms of channel density, charge compensation effects and shielded gate structure.
An important aspect limiting the performance improvement of multi-sub conduction power devices is the contradictory relationship between breakdown voltage and specific on-resistance. The main limitation of the breakdown voltage comes from the non-uniformity of the electric field distribution in the voltage-resistant region, and the very important limitation in the SGT comes from the electric field concentration Effect (E-field generating Effect) at the corners of the shielding grid. Because the polysilicon heavy doping inherent in the traditional SGT shielding gate structure, when the device is in forward blocking, the ionization donor charge electric flux in a voltage-withstanding region is inevitably caused to be transitionally concentrated at the corner, a larger peak electric field is caused, and the capability of breakdown voltage is reduced.
Disclosure of Invention
In order to overcome the problems in the related art, the present application provides a trench field effect transistor having a segmented gate structure and a method for manufacturing the same, which can improve the breakdown voltage of the transistor device.
A first aspect of the present application provides a trench field effect transistor having a segmented gate structure, comprising: the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode 8, a drain electrode 9 and a metal grid; the drift region 2, the body region 3, the source region 4 and the source electrode 8 are sequentially arranged above the substrate region 1, and the drain electrode 9 is arranged below the substrate region 1;
the control grid 6 and the shielding grid 5 are sequentially arranged on one side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the source region 4 through the insulating layer 7; the control gate 6 and the shielding gate 5 are separated by the insulating layer 7; the shielding grid 5 is made of metal materials with different work functions from top to bottom; the control gate 6 is made of metal materials with different work functions from top to bottom;
the source electrode 8 is arranged above the source region; the metal gate is disposed over the control gate.
In one embodiment, the work function of the metal material in the shielding gate 5 increases from top to bottom.
In one embodiment, the work function of the metal material in the control gate 6 increases from top to bottom.
In one embodiment, in the shielding grid 5, the difference between work functions of every two adjacent metal materials is 0.2-1.
In one embodiment, in the control gate 6, the difference between work functions of every two adjacent metal materials is 0.2-1.
In one embodiment, the number of the metal material constituting the control gate 6 and the metal material constituting the shield gate 5 are the same.
In one embodiment, the thickness of each layer of metal material in the shielding grid 5 is the same.
In one embodiment, the thickness of each layer of metal material in the control gate 6 is the same.
In one embodiment, the number of metal materials constituting the control gate is greater than or equal to 3.
A second aspect of the present application provides a method for manufacturing a trench field effect transistor having a segmented gate structure, including:
preparing a substrate region by using a heavily doped semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region above the drift region by means of ion implantation or diffusion;
etching a groove on one side of the drift region;
sequentially depositing an oxide, metal materials with different work functions, the oxide and the metal materials with different work functions in the groove to form a shielding gate, a control gate, an insulating layer and a metal gate;
doping above the base region to form a source region;
depositing source metal above the source region to obtain a source electrode;
and manufacturing and forming a drain electrode below the substrate region.
The technical scheme provided by the application can comprise the following beneficial effects:
the shielding gate and the control gate of the trench field effect transistor with the segmented gate structure are different from the conventional shielding gate and the conventional control gate structure which adopt uniform polysilicon materials, and the gate materials are made of metal materials with different work functions from top to bottom; the shielding grid is made of different metal materials from top to bottom, so that when the device is in forward blocking, the electric field in the voltage-resistant area is modulated, relatively flat electric field distribution can be obtained, and the breakdown voltage of the device is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a schematic structural diagram of a trench field effect transistor having a segmented gate structure according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart illustrating a method for manufacturing a trench field effect transistor having a segmented gate structure according to an embodiment of the present disclosure.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
Because the polysilicon heavy doping inherent in the traditional SGT shielding gate structure, when the device is in forward blocking, the ionization donor charge electric flux in a voltage-withstanding region is inevitably caused to be transitionally concentrated at the corner, a larger peak electric field is caused, and the capability of breakdown voltage is reduced.
In view of the above problems, embodiments of the present application provide a trench field effect transistor with a segmented gate structure, which has a relatively flat electric field distribution and thus a relatively high breakdown voltage.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a trench field effect transistor having a segmented gate structure according to an embodiment of the present application.
Referring to fig. 1, the trench field effect transistor having a segmented gate structure includes: the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode 8, a drain electrode 9 and a metal grid;
the drift region 2, the base region 3, the source region 4 and the source electrode 8 are sequentially arranged above the substrate region 1, and the drain electrode 9 is arranged below the substrate region 1; the control grid 6 and the shielding grid 5 are sequentially arranged on one side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the base region 3 and the source region 4 through the insulating layer 7; the control gate 6 and the shielding gate 5 are separated by an insulating layer 7; the source electrode 8 is arranged above the source region 4; the metal gate is arranged above the control gate.
Further, the shielding grid 5 is made of metal materials with different work functions from top to bottom; the control gate 6 is made of metal materials having different work functions from top to bottom.
Specifically, the gate material used by the shielding gate 5 is from top to bottom, and the work function of each layer of metal material is sequentially increased; the gate material used for the control gate 6 is from top to bottom, and the work function of each layer of metal material is sequentially increased.
In the embodiment of the present application, there is no strict requirement on the increase value of the work function of each layer of metal material in the shielding gate and the control gate, that is, the work function of each layer of metal material in the gate materials used for the shielding gate and the control gate may be increased in equal value or increased in non-equal value from top to bottom, and preferably, the work functions of the gate materials used for the shielding gate and the control gate are increased in equal value from top to bottom.
In the embodiment of the application, the difference value of the work functions of every two adjacent metal materials in the shielding grid 5 is 0.2-1, and preferably, the difference value of the work functions of every two adjacent metal materials is 0.5; the difference value of work functions of every two adjacent metal materials in the control gate 6 is 0.2-1, and preferably, the difference value of the work functions of every two adjacent metal materials is 0.5.
It should be noted that, in the practical application process, if the shielding gate and the control gate both use gate materials with gradually increased work function values, the work function difference between two adjacent layers of metal materials of the shielding gate and the work function difference between two adjacent layers of metal materials of the control gate may be set to be the same.
Further, the number of layers of the metal material in the shielding gate 5 and the control gate 6 may be set to be uniform, that is, the number of the metal material constituting the control gate 6 and the number of the metal material constituting the shielding gate 5 are uniform.
Further, the maximum work function of the metal material in the shielding gate 5 and the control gate 6 may be set to be uniform, i.e. the structure of the shielding gate 5 and the control gate 6 is uniform.
In the practical application process, theoretically, the larger the number of the metal materials with different work functions in the shielding gate and the control gate is, the better the performance of the transistor is, but based on the cost and process considerations, the larger the number of the metal materials forming the control gate or the shielding gate is, the higher the breakdown voltage of the transistor can be achieved. Preferably, the amount of metal material in the shield or control gate is 3.
Taking the shielding gate as a three-layer structure as an example, the shielding gate 5 is divided into a first shielding gate layer 51, a second shielding gate layer 52 and a third shielding gate layer 53, wherein the work function of the metal material of the first shielding gate layer 51 is lower than that of the second shielding gate layer 52 and is lower than that of the third shielding gate layer 53;
taking the control gate as a three-layer structure, the control gate 6 is divided into a first control gate layer 61, a second control gate layer 62 and a third control gate layer 63, wherein the work function of the metal material of the first control gate layer 61 is lower than that of the second control gate layer 62 and lower than that of the third control gate layer 63.
When the grid electrode material is a single material, the electric field distribution along the channel is approximately in triangular distribution, and the specific on-resistance of the channel region is not fully utilized; if the gate material is designed to sequentially increase the work function from top to bottom, the approximately triangular electric field distribution of the channel region can be modulated into approximately rectangular distribution, so that the specific on-resistance of the channel region is effectively improved.
Furthermore, the thicknesses of all layers of metal materials in the shielding grids are the same; and the thickness of each layer of metal material in the control gate is the same.
In the embodiment of the application, the substrate region 1 is doped in an N type, and the doping concentration is a heavy doping concentration; the drift region 2 adopts N-type doping, and the doping concentration is light doping concentration; the substrate region 3 adopts P-type doping, and the doping concentration is medium doping concentration; the doping concentration of the source region 4 is a heavily doped concentration.
Further, the source region 4 is divided into an N-type source region 42 and a P-type source region 41.
In the embodiment of the present application, the value range of the lightly doped concentration is 1 × 1015cm-3To 5X 1016cm-3(ii) a The value range of the medium doping concentration is 1 multiplied by 1017cm-3To 5X 1018cm-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 1019cm-3To 5X 1020cm-3。
The trench field effect transistor with the segmented gate structure is different from the conventional shielding gate and the conventional control gate structure which adopt uniform polysilicon materials, and the gate materials are made of metal materials with different work functions from top to bottom; the shielding grid is made of different metal materials from top to bottom, so that when the device is in forward blocking, the electric field in the voltage-resistant area is modulated, relatively flat electric field distribution can be obtained, and the breakdown voltage of the device is further improved.
Example two
Corresponding to the embodiment of the trench field effect transistor with the segmented gate structure, the application also provides a preparation method of the trench field effect transistor with the segmented gate structure and corresponding embodiments.
Fig. 2 is a schematic flow chart illustrating a method for manufacturing a trench field effect transistor having a segmented gate structure according to an embodiment of the present disclosure.
Referring to fig. 2, the method for manufacturing the trench field effect transistor with the segmented gate structure includes:
201. preparing a substrate region by using a heavily doped semiconductor material;
specifically, the method comprises the following steps: and preparing and forming a substrate region by using an N-type heavily doped semiconductor material.
202. Epitaxially forming a drift region on the substrate region;
in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).
203. Forming a base region above the drift region by means of ion implantation or diffusion;
the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.
The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.
It should be noted that, in the embodiment of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the different processes may be selected according to actual requirements to complete the preparation of the substrate region.
204. Etching a groove on one side of the drift region;
205. sequentially depositing an oxide, metal materials with different work functions, the oxide and the metal materials with different work functions in the groove to form a shielding gate, a control gate, an insulating layer and a metal gate;
the following are exemplary:
and after the oxide, the metal materials with different work functions and the oxide are sequentially deposited in the groove, the deposition operation of the metal materials with different work functions is performed again according to the previous deposition of the metal materials with different work functions, and the shielding gate and the control gate structure with the same structure are obtained.
Taking three metal materials with different work functions as an example, the deposition sequence of each round of metal materials is to deposit a metal material with a higher work function first, then deposit a metal material with a second highest work function, and finally deposit a metal material with a lowest work function, so that the gate material of the shielding gate and/or the control gate is formed by metal materials with sequentially increasing work functions from top to bottom.
The deposition thickness of each layer of metal material can be consistent, so that the shielding gate and the control gate are in a metal material layer structure with the same height and the increasing work function.
206. Doping above the base region to form a source region;
specifically, the method comprises the following steps: and doping an N-type heavily doped semiconductor material and a P-type heavily doped semiconductor material above the base region to form an N-type source region and a P-type source region, wherein the arrangement direction of the N-type source region and the P-type source region is vertical to the interface of the insulating layer and the base region.
207. Depositing source metal above the source region to obtain a source electrode;
208. and manufacturing and forming a drain electrode below the substrate region.
It should be noted that the step 208 is performed after the substrate region is fabricated, i.e., the execution sequence of the step 208 is performed after the step 201.
It is understood that the timing of the execution of step 208 is not the only limitation of the present application.
The embodiment of the application provides a preparation method of a trench field effect transistor with a sectional type gate structure, metal materials with different work functions are sequentially filled in a trench obtained through etching to obtain the trench field effect transistor with the sectional type shielding gate and control gate structure, and due to the fact that the work functions of the different metal materials are different, channel electric fields formed at the interface of the different metal materials of the control gate and on the surface of a corresponding channel are more uniformly distributed, and therefore lower channel region on-resistance is obtained; the shielding grid is made of different metal materials from top to bottom, so that when the device is in forward blocking, the electric field in the voltage-resistant area is modulated, relatively flat electric field distribution can be obtained, and the breakdown voltage of the device is further improved.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. Those skilled in the art should also appreciate that acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A trench field effect transistor having a segmented gate structure, comprising: the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a shielding gate (5), a control gate (6), an insulating layer (7), a source electrode (8), a drain electrode (9) and a metal gate; the drift region (2), the base region (3), the source region (4) and the source electrode (8) are sequentially arranged above the substrate region (1), and the drain electrode (9) is arranged below the substrate region (1);
the control grid (6) and the shielding grid (5) are sequentially arranged on one side of the drift region (2) from top to bottom and are respectively connected with the drift region (2), the base region (3) and the source region (4) through the insulating layer (7); the control grid (6) and the shielding grid (5) are separated by the insulating layer (7); the shielding grid (5) is made of metal materials with different work functions from top to bottom; the control grid (6) is made of metal materials with different work functions from top to bottom;
the source electrode (8) is arranged above the source region; the metal gate is disposed over the control gate.
2. The trench field effect transistor with a segmented gate structure of claim 1,
in the shielding grid (5), the work functions of the metal materials are sequentially increased from top to bottom.
3. The trench field effect transistor having a segmented gate structure of claim 1,
in the control gate (6), the work functions of the metal materials are sequentially increased from top to bottom.
4. The trench field effect transistor having a segmented gate structure of claim 2,
in the shielding grid (5), the difference value of the work functions of every two adjacent metal materials is 0.2-1.
5. The trench field effect transistor having a segmented gate structure of claim 3,
in the control grid (6), the work function difference value of every two adjacent metal materials is 0.2-1.
6. The trench field effect transistor having a segmented gate structure of claim 1,
the number of the metal materials forming the control grid (6) is the same as that of the metal materials forming the shielding grid (5).
7. The trench field effect transistor having a segmented gate structure of claim 1,
the thickness of each layer of metal material in the shielding grid (5) is the same.
8. The trench field effect transistor with a segmented gate structure of claim 1,
and the thickness of each layer of metal material in the control gate (6) is the same.
9. The trench field effect transistor having a segmented gate structure of claim 6,
the number of metal materials constituting the control gate is greater than or equal to 3.
10. A method for preparing a trench field effect transistor with a segmented gate structure is characterized by comprising the following steps:
preparing a substrate region by using a heavily doped semiconductor material;
epitaxially forming a drift region on the substrate region;
forming a base region above the drift region by means of ion implantation or diffusion;
etching a groove on one side of the drift region;
sequentially depositing oxides, metal materials with different work functions, the oxides and the metal materials with different work functions in the groove to form a shielding gate, a control gate, an insulating layer and a metal gate;
doping above the base region to form a source region;
depositing source metal above the source region to obtain a source electrode;
and manufacturing and forming a drain electrode below the substrate region.
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