CN114744021A - 一种碳化硅槽栅功率mosfet器件及制备方法 - Google Patents

一种碳化硅槽栅功率mosfet器件及制备方法 Download PDF

Info

Publication number
CN114744021A
CN114744021A CN202210358599.0A CN202210358599A CN114744021A CN 114744021 A CN114744021 A CN 114744021A CN 202210358599 A CN202210358599 A CN 202210358599A CN 114744021 A CN114744021 A CN 114744021A
Authority
CN
China
Prior art keywords
sic
type column
gate
side wall
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210358599.0A
Other languages
English (en)
Inventor
王颖
沈培
包梦恬
曹菲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Dianzi University
Original Assignee
Hangzhou Dianzi University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Dianzi University filed Critical Hangzhou Dianzi University
Priority to CN202210358599.0A priority Critical patent/CN114744021A/zh
Publication of CN114744021A publication Critical patent/CN114744021A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供了一种碳化硅槽栅功率MOSFET器件及制备方法。本发明使用n型柱包裹侧壁p型柱构成一种侧壁超结电场调制区来改善SiC功率槽栅MOSFET电学性能。本发明侧壁超结电场调制区使得沟槽底部周围电场均匀，从而起到了进一步缓解沟槽底部拐角处高场强，保护了栅氧化层。通过改变n型柱与栅极之间的距离，选取一组最优距离使得击穿电压与比导通电阻之间很好地折中。并且由n型柱包裹层与侧壁p型柱构成的侧壁超结电场调制区具有的p‑n结的面积较SiC全超结槽栅MOSFET结构小，从而导致新结构的栅‑漏电荷Qgd比传统SiC全超结槽栅MOSFET结构的栅‑漏电荷Qgd略小。

Description

一种碳化硅槽栅功率MOSFET器件及制备方法
技术领域
本发明涉及半导体技术领域，具体而言，涉及一种具有N型柱包裹P柱层的碳化硅槽栅功率MOSFET器件。
背景技术
随着SiC功率MOSFET器件广泛地应用于电力电子系统中，其可能需要应用于更加严苛的环境场合，如高温、高压、高频、强辐照等。SiC功率MOSFET器件将面临一系列可靠性问题，将阻碍SiC功率MOSFET器件及其功率系统的快速发展。其中，SiC功率MOSFET器件按照结构分布主要分为两大类：横向结构的MOSFET、纵向结构的MOSFET。相较于横向结构的MOSFET而言，纵向结构中的槽栅MOSFET结构由于没有JFET区，将降低器件比导通电阻。然而，槽栅MOSFET结构在器件阻断时由于栅氧化层电场过高，影响器件的可靠性。因此，器件设计者应设计出新的结构来解决槽栅MOSFET结构栅氧化层高电场的问题，保证槽栅MOSFET器件可靠工作尤为重要。并且当SiC功率MOSFET器件工作于电力电子系统中的开关电路中时，SiC功率MOSFET器件长时间承受电应力使得寄生体二极管发生双极退化，导致SiC功率MOSFET器件动态损耗过大，制约了SiC功率MOSFET器件高频应用。针对在高频工作下SiC功率MOSFET器件的动态损耗过大的可靠性问题，尤其是SiC功率MOSFET器件的比导通电阻与栅-漏电荷之间的折中关系。因此，急需设计低动态损耗的SiC功率MOSFET新型器件结构具有重要意义。
发明内容
本发明的主要目的在于提供一种具有N型柱包裹P柱层的碳化硅槽栅功率MOSFET器件结构，以解决现有技术中的碳化硅槽栅MOSFET器件结构在高压情况下沟槽拐角处高电场问题。以及碳化硅槽栅MOSFET器件长时间承受电应力使得寄生体二极管发生双极退化，导致SiC功率MOSFET器件动态损耗过大，制约了SiC功率MOSFET器件高频应用的可靠性问题。
本发明一种具有N型柱包裹p柱层的碳化硅槽栅功率MOSFET器件结构，传统全超结SiC槽栅MOSFET器件通过多外延生长，在n型漂移层上形成超结结构。而该结构特点主要包括p+-SiC埋层、n型电流扩散层(NCSL)、p型柱(p-pillar)和包裹p-pillar的n型柱(n-pillar)。通过在SF6/O2气体环境中使用电感耦合等离子体刻蚀，在n型外延层上形成深条纹沟槽，进而构成一定厚度的n型柱。采用沟槽填充外延生长方法制备p型柱，在外延生长后，通过研磨和抛光将外延生长的晶片减薄至外延晶片初始厚度，使晶片表面变平，然后在表面平坦的晶片上生长一层n型电流扩散层(NCSL)。NCSL形成后，制造一定尺寸(两p型柱之间的距离)的掩膜版对NCSL进行掩膜，并在掩膜版两边通过离子注入的形式生成两侧p+-SiC埋层区。
作为优选，所述的在n型外延层上形成深条纹沟槽，进而构成一定厚度的n型柱的掺杂浓度为6.0×1016cm-3，侧边厚度为24.0μm。
作为优选，所述的在n型外延层上形成深条纹沟槽，进而构成一定厚度的n型柱的掺杂浓度为6.0×1016cm-3，底部包裹厚度为1.0μm。
作为优选，所述的沟槽填充外延生长方法制备一定厚度的p型柱的掺杂浓度为2.0×1016cm-3，厚度为24.0μm。
作为优选，所述的在表面平坦的晶片上生长一层n型电流扩散层(NCSL)掺杂浓度为4.0×1016cm-3，厚度为1.7μm。
作为优选，所述的离子注入一定厚度的p+-SiC埋层的掺杂浓度为1.0×1018cm-3，厚度为1.7μm。
本发明的有益效果在于：使用n型柱包裹侧壁p型柱构成一种侧壁超结电场调制区来改善SiC功率槽栅MOSFET电学性能。该结构中的n型柱包裹层与侧壁p型柱并没有复杂的工艺步骤与制备成本。具体而言，侧壁超结电场调制区使得沟槽底部周围电场均匀，从而起到了进一步缓解沟槽底部拐角处高场强，保护了栅氧化层。通过改变n型柱与栅极之间的距离，选取一组最优距离使得击穿电压与比导通电阻之间很好地折中。并且由n型柱包裹层与侧壁p型柱构成的侧壁超结电场调制区具有的p-n结的面积较SiC全超结槽栅MOSFET结构小，从而导致新结构的栅-漏电荷Qgd比传统SiC全超结槽栅MOSFET结构的栅-漏电荷Qgd略小。
附图说明
图1为传统SiC全超结槽栅MOSFET结构示意图；
图2为具有N型柱包裹层的SiC槽栅MOSFET(SNPPT-MOS)半元胞结构示意图；
图3为图2所示结构的制作流程示意图；
图4为图1所示结构与图2所示结构的IV曲线对比图；
图5为图1所示结构与图2所示结构的击穿特性曲线对比；
图6为根据图5分别提取了在x＝2.5μm与y从0μm到30μm时，图1所示结构与图2所示结构在y方向的电场强度曲线并进行了对比；
图7为图1所示结构与图2所示结构的特征栅电荷与栅-源电压关系曲线对比；
图8为图1所示结构的开关特性的开关波形
图9为图2所示结构的的开关特性的开关波形对比；
图10为图1所示结构与图2所示结构的开关能量损耗对比。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明进行具体阐述。
传统SiC全超结槽栅MOSFET(full-SJ-MOS)结构示意图，如图1所示。本发明提出的具有N型柱包裹层的SiC槽栅MOSFET(SNPPT-MOS)半元胞结构如图2所示。与传统SiC全超结槽栅MOSFET结构相比，本发明提出的SNPPT-MOS结构特点主要包括p+-SiC埋层、NCSL、p-pillar和包裹p-pillar的n型柱，如图3所示，其结构具体制作步骤如下：
1)首先在n型4H-SiC材料衬底上生长n型4H-SiC外延层n1与n2，其中n2的掺杂浓度大于n1，如图3(a)所示；
2)通过在SF6/O2气体环境中使用电感耦合等离子体刻蚀，在n2外延层上形成深条纹沟槽，制造该超结结构，如图3(b)所示；
3)采用沟槽填充外延(TFE)生长方法制备p型柱，如图3(c)所示；
4)TFE生长后，通过研磨和抛光将TFE生长的晶片减薄至外延晶片初始厚度，使晶片表面变平，如图3(d)所示；
5)然后在表面平坦的晶片上生长一层NCSL。CSL形成后，制造一定尺寸(两p型柱之间的距离)的掩膜版对NCSL进行掩膜，并在掩膜版两边通过离子注入的形式生成两侧p+-SiC埋层区域，最终形成的结构如图3(e)所示；
6)然后在图3(e)结构的基础之上移除掩膜版，再生长一层p型4H-SiC，形成p-body区。p-body区形成后，通过离子注入的方式形成n+-SiC源区，然后使用之前相同尺寸的掩膜版挡住一定的n+-SiC源区，并在掩膜版两边再通过离子注入的形式生成两侧p+-SiC区域，最终形成的结构如图3(f)所示；
7)在器件结构中间蚀刻一定宽度的深槽，并使得该槽的深度一定要穿过NCSL区达到n型漂移区中一定深度，并在深槽底部进行离子注入的方式形成p+-SiC区，结构如图3(g)所示；
8)对图3(g)所示结构中的深槽侧壁和底部进行干氧氧化，形成侧壁厚度为50nm的氧化层。然后，用n+-polySi材料填满器件的槽栅，作为器件的栅电极。之后，进行器件表面氧化，形成氧化层进行隔离。然后在器件表面两端蚀刻部分氧化层到p+和n+表面。之后，在器件上表面和背面淀积金属材料制造器件的源电极和漏电极。图3(h)显示了该新器件结构的一个元胞的整体截面图。
在导通状态下，full-SJ-MOS结构与SNNPT-MOS结构在Vgs＝20V、Vgs＝16V、Vgs＝12V、Vgs＝8V条件下的输出特性曲线对比，如图4所示。从图中可知，与full-SJ-MOS结构相比较，SNNPT-MOS结构的比导通电阻降低了。
在阻断状态下，full-SJ-MOS结构与SNNPT-MOS结构的击穿特性曲线对比，如图5所示。从图中可知，full-SJ-MOS结构的漏极偏置电压为4226V，SNNPT-MOS结构漏极偏置电压为4713V，与full-SJ-MOS结构相比较，SNPPT-MOS结构的击穿电压提高了27％。
同时根据图5分别提取了在x＝2.5μm与y从0μm到30μm时，full-SJ-MOS结构与SNPPT-MOS结构在y方向的电场强度曲线并进行了对比，如图6所示。从图中可知，两种结构的沟槽底部栅氧化层最大电场强度约在y＝2.5μm处。随着y的增加SNPPT-MOS结构与full-SJ-MOS结构的垂直电场强度曲线都趋于平坦，然而SNPPT-MOS结构的沟槽底部栅氧化层最大电场强度略低于full-SJ-MOS结构，正是由于SNPPT-MOS结构中n型柱包裹层与侧壁p型柱之间相互耗尽，靠近沟槽底部拐角处的p/n结界面电场强度分布更加均匀。
图7为full-SJ-MOS结构与SNPPT-MOS结构的特征栅电荷(Qg,sp)与栅-源电压Vgs关系曲线对比。从图中可知，SNPPT-MOS结构的栅-漏电荷Qgd,sp比full-SJ-MOS结构的栅-漏电荷Qgd,sp较小，主要由于SNPPT-MOS结构中侧壁p型柱与n型柱包裹层具有较小的p-n结的面积与有效地电场屏蔽能力。
图8为full-SJ-MOS结构的开关特性的开关波形。SNPPT-MOS结构的开关特性的开关波形对比，如图9所示。从图8、图9中可知，与SNPPT-MOS结构相比，full-SJ-MOS结构需要更长的时间才能达到高Vds和高Ids。其中，TOFF定义为关断延迟时间和关断下降时间。TON定义为开启延迟时间和开启下降时间。将开关过程中的电压与电流乘积并在时间上积分，可以得到SNPPT-MOS结构与full-SJ-MOS结构的开通能量损耗(Eon)与关断能量损耗(Eoff)。SNPPT-MOS结构与full-SJ-MOS结构开关能量损耗对比如图10所示。与full-SJ-MOS结构相比，SNPPT-MOS结构的Eon与Eoff分别减小了24.0％和15.1％。其中，Eon减小更加明显。
显然，本领域的技术人员可以对本发明进行各种改动和变形而不脱离本发明的精神和范围。应注意到的是，以上所述仅为本发明的具体实施例，并不限制本发明，凡在本发明的精神和原则之内，所做的调制和优化，皆应属本发明权利要求的涵盖范围。

Claims (7)

1.一种碳化硅槽栅功率MOSFET器件，其特征在于：在传统全超结SiC槽栅MOSFET器件上，使用n型柱包裹侧壁p型柱构成一种侧壁超结电场。
2.根据权利要求1所述的一种碳化硅槽栅功率MOSFET器件的制备方法，其特征在于：
1)首先在n型4H-SiC材料衬底上依次生长n型4H-SiC外延层n1与n2，其中n2的掺杂浓度大于n1；
2)通过在SF6/O2气体环境中使用电感耦合等离子体刻蚀，在n2外延层上形成深条纹沟槽，构成一定厚度的n型柱；
3)采用沟槽填充外延生长方法制备p型柱；
4)外延生长后，通过研磨和抛光将外延生长的晶片减薄至外延晶片初始厚度，使晶片表面变平；
5)然后在表面平坦的晶片上生长一层电流扩散层；电流扩散层形成后，制造一定尺寸的掩膜版对NCSL进行掩膜，并在掩膜版两边通过离子注入的形式生成两侧p+-SiC埋层区域；
6)移除掩膜版，再生长一层p型4H-SiC，形成p-body区；p-body区形成后，通过离子注入的方式形成n+-SiC源区，然后使用之前相同尺寸的掩膜版挡住一定的n+-SiC源区，并在掩膜版两边再通过离子注入的形式生成两侧p+-SiC区域；
7)在器件结构中间蚀刻一定宽度的深槽，并使得该槽的深度一定要穿过NCSL区达到n型漂移区中一定深度，并在深槽底部进行离子注入的方式形成p+-SiC区；
对深槽侧壁和底部进行干氧氧化，形成侧壁厚度为50nm的氧化层；然后，用n+-polySi材料填满器件的槽栅，作为器件的栅电极；之后，进行器件表面氧化，形成氧化层进行隔离；然后在器件表面两端蚀刻部分氧化层到p+和n+表面；之后，在器件上表面和背面淀积金属材料制造器件的源电极和漏电极。
3.根据权利要求2所述的一种碳化硅槽栅功率MOSFET器件的制备方法，其特征在于：
所述的n型柱的掺杂浓度为6.0×1016cm-3，侧边厚度为24.0μm。
4.根据权利要求2所述的一种碳化硅槽栅功率MOSFET器件的制备方法，其特征在于：所述的n型柱的掺杂浓度为6.0×1016cm-3，底部包裹厚度为1.0μm。
5.根据权利要求2所述的一种碳化硅槽栅功率MOSFET器件的制备方法，其特征在于：所述的p型柱的掺杂浓度为2.0×1016cm-3，厚度为24.0μm。
6.根据权利要求2所述的一种碳化硅槽栅功率MOSFET器件的制备方法，其特征在于：所述的电流扩散层掺杂浓度为4.0×1016cm-3，厚度为1.7μm。
7.根据权利要求2所述的一种碳化硅槽栅功率MOSFET器件的制备方法，其特征在于：所述的p+-SiC埋层的掺杂浓度为1.0×1018cm-3，厚度为1.7μm。
CN202210358599.0A 2022-04-06 2022-04-06 一种碳化硅槽栅功率mosfet器件及制备方法 Pending CN114744021A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210358599.0A CN114744021A (zh) 2022-04-06 2022-04-06 一种碳化硅槽栅功率mosfet器件及制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210358599.0A CN114744021A (zh) 2022-04-06 2022-04-06 一种碳化硅槽栅功率mosfet器件及制备方法

Publications (1)

Publication Number Publication Date
CN114744021A true CN114744021A (zh) 2022-07-12

Family

ID=82280104

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210358599.0A Pending CN114744021A (zh) 2022-04-06 2022-04-06 一种碳化硅槽栅功率mosfet器件及制备方法

Country Status (1)

Country Link
CN (1) CN114744021A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117316992A (zh) * 2023-11-29 2023-12-29 深圳基本半导体有限公司 一种双栅结构的碳化硅mosfet器件及其制备方法
CN117855280A (zh) * 2024-01-31 2024-04-09 深圳天狼芯半导体有限公司 超结碳化硅mosfet及其制备方法、芯片

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117316992A (zh) * 2023-11-29 2023-12-29 深圳基本半导体有限公司 一种双栅结构的碳化硅mosfet器件及其制备方法
CN117855280A (zh) * 2024-01-31 2024-04-09 深圳天狼芯半导体有限公司 超结碳化硅mosfet及其制备方法、芯片

Similar Documents

Publication Publication Date Title
CN107112276B (zh) 具有带锥形氧化物厚度的多晶硅填充渠沟的功率组件
US5298442A (en) Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
KR100869324B1 (ko) 베이스 리치-쓰루를 방지하는 측면 확장 베이스 차폐영역을 구비한 전력 반도체 소자 및 그 제조방법
CN104701178B (zh) 使用电化学蚀刻制造半导体器件的方法以及半导体器件
JP2004537162A (ja) パワーデバイスとその製造方法
CN109065621B (zh) 一种绝缘栅双极晶体管及其制备方法
CN114744021A (zh) 一种碳化硅槽栅功率mosfet器件及制备方法
CN109920839B (zh) P+屏蔽层电位可调碳化硅mosfet器件及制备方法
CN113611750B (zh) Soi横向匀场高压功率半导体器件及制造方法和应用
US6784488B2 (en) Trench-gate semiconductor devices and the manufacture thereof
CN111668312A (zh) 一种低导通电阻的沟槽碳化硅功率器件及其制造工艺
CN115148826B (zh) 一种深沟槽碳化硅jfet结构的制作方法
CN114038908B (zh) 集成二极管的沟槽栅碳化硅mosfet器件及制造方法
CN108198857A (zh) 一种集成凸块状肖特基二极管的碳化硅mosfet器件元胞结构
CN115579397A (zh) 双级沟槽栅碳化硅mosfet及其制备方法
CN113314613A (zh) 具有雪崩电荷渡越缓冲层的碳化硅mosfet器件及制备方法
CN105993076A (zh) 一种双向mos型器件及其制造方法
CN113066865B (zh) 降低开关损耗的半导体器件及其制作方法
CN117174756B (zh) 具有双重多层屏蔽结构的SiC MOSFET元胞结构、器件及制备方法
CN109148566A (zh) 碳化硅mosfet器件及其制造方法
CN110504313B (zh) 一种横向沟槽型绝缘栅双极晶体管及其制备方法
CN115224128B (zh) 一种金属氧化物半导体场效应晶体管及其制造方法
CN113078204B (zh) 一种氮化镓3d-resurf场效应晶体管及其制造方法
CN112802754B (zh) 一种隔离栅沟槽型mosfet器件及其制造方法
CN113838914A (zh) 具有分离栅结构的ret igbt器件结构及制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination