CN114726374A - Capacitor array structure - Google Patents

Capacitor array structure Download PDF

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Publication number
CN114726374A
CN114726374A CN202210427945.6A CN202210427945A CN114726374A CN 114726374 A CN114726374 A CN 114726374A CN 202210427945 A CN202210427945 A CN 202210427945A CN 114726374 A CN114726374 A CN 114726374A
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capacitor
split
module
capacitors
fingers
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CN202210427945.6A
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CN114726374B (en
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朱春艳
张超
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Shenzhen Adaps Photonics Technology Co ltd
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Shenzhen Adaps Photonics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Abstract

The embodiment of the application discloses capacitor array structure, including n split capacitors, first split capacitor is in the centre of array, second split capacitor divides into equally 2 the unit capacitance distributes in the both sides of first split capacitor, nth split capacitor divides into equally 2n‑1The unit capacitors are distributed on two sides of the first split capacitor; each split capacitor comprises 1 lower polar plate and 1 upper polar plate; all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.

Description

Capacitor array structure
Technical Field
The embodiment of the application relates to the field of electronics, in particular to a capacitor array structure.
Background
Successive approximation analog-to-digital converter (ADC) is capable of providing higher conversion speed and higher resolution, and has the advantages of low power consumption and small area, so that the application is more and more widespread.
The successive approximation ADC adopts the most widely charge redistribution type structure, in which the charge redistribution digital-to-analog converter circuit is the core circuit thereof, and the basic structure thereof is a capacitor array with binary weights. The capacitive array is a critical component of the transducer, and a critical factor in the capacitive array structure is capacitive matching. As the resolution requirement increases, the capacitance and area of the capacitor array will be larger, which becomes a key issue for matching the capacitors.
In the existing capacitor array structure, each capacitor is composed of unit capacitors, and the two capacitors are arranged in a common centroid scheme in two dimensions. However, as the resolution increases, the capacitance array increases, the difficulty of capacitance matching increases, and the occupied area increases greatly, which causes inconvenience to users.
Disclosure of Invention
The application provides a capacitor array structure, and the technical problem to be solved is: how to layout the split capacitors to reduce the chip area occupied by the capacitors.
The application provides a capacitor array structure, including n split capacitors, 1 times first split capacitor of unit electric capacity, 2 times second split capacitor of unit electric capacity and so on, 2n-1An nth split capacitor which is multiple times the unit capacitor, wherein n is an integer greater than or equal to 1; the first split capacitor is positioned in the middle of the array, the second split capacitor is divided into 2 unit capacitors distributed on two sides of the first split capacitor, and the nth split capacitor is divided into 2 unit capacitorsn-1The unit capacitors are distributed on two sides of the first split capacitor; each split capacitor comprises 1 lower polar plate and 1 upper polar plate; all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.
Preferably, the upper plate of the unit capacitor comprises 2 upper insertion fingers and 1 upper substrate; the plurality of upper insertion fingers of all the split capacitors are connected through the upper substrate; the lower polar plate of the unit capacitor comprises 1 lower insertion finger and 1 lower substrate, the lower insertion finger of the first split capacitor is connected through the first lower substrate, the 2 lower insertion fingers of the second split capacitor are connected through the second lower substrate, and so on, and 2 lower insertion fingers of the nth split capacitorn-1The lower insertion fingers are connected through the nth lower substrate.
Preferably, a diffusion region is formed by implantation within the chip directly beneath each of the upper fingers.
Preferably, polysilicon is disposed on the surface of the chip directly below each lower finger, and the polysilicon is electrically connected to the lower substrate.
It can be seen from this that: the unit capacitors are located in the middle of the array, the other capacitors are equally divided into even number of unit capacitors and are arranged on two sides of the middle capacitor, all the capacitors are located in the same row, every two adjacent capacitors share one upper inserting finger, the upper inserting fingers of all the capacitors of the array are connected through the upper substrate, and the lower inserting finger of each split capacitor is connected with the lower substrate of the split capacitor. All capacitors are in the same row, and all capacitors share the upper substrate, so that only one dimension is needed for capacitor matching, the occupied area can be greatly reduced, the size of a chip is reduced, and the cost is reduced.
The application also provides a capacitor array structure comprising n split capacitors, 2-k+1 First split capacitor 2 times module capacitor-k+2Second split capacitance, which is multiple of the module capacitance, and so on, 2-k+kThe kth split capacitance being multiple of the module capacitance, the kth +1 split capacitance being 2 multiple of the module capacitance, and so on, 2n-kAn nth split capacitor which is multiple of the module capacitor, wherein n is an integer which is greater than or equal to 1, and k is an integer which is less than n; the kth split capacitor is located in the middle of the array, the (k + 1) th split capacitor is divided into 2 module capacitors distributed on two sides of the kth split capacitor, and the nth split capacitor is divided into 2 module capacitorsn-kThe module capacitors are distributed on two sides of the k-th split capacitor; each split capacitor comprises 1 lower polar plate and 1 upper polar plate; all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.
Preferably, the upper plate of each split capacitor comprises a plurality of upper fingers and an upper substrate, and all the upper fingers are connected through the upper substrate; the lower plate of the module capacitor comprises a plurality of lower insertion fingers and a lower substrate, 2-k+1Multiple lower fingers of a first split capacitor, which is multiple of the module capacitor, are connected through a first lower substrate, 2-k+2A plurality of lower insertion fingers of a second split capacitor which is multiple of the module capacitor are connected through a second lower substrate, a plurality of lower insertion fingers of a kth split capacitor which is 1 multiple of the module capacitor are connected through a kth lower substrate, and a plurality of lower insertion fingers of a (k + 1) th split capacitor which is 2 multiple of the module capacitor are connected through a kth lower substrateThe (k + 1) th base substrate is connected, and so on, 2n-kA plurality of lower fingers of an nth split capacitor that is multiple of the module capacitor are connected through an nth lower substrate.
Preferably, when k is 4 and n is 10, the 4 th split capacitor is a module capacitor and is located in the middle of the array, the 5 th split capacitor is divided into 2 module capacitors and distributed on two sides of the 4 th split capacitor, and the 10 th split capacitor is divided into 26The module capacitors are distributed on two sides of the 4 th split capacitor; the lower plate of the module capacitor comprises 23A lower finger and a lower substrate; the upper plate of the module capacitor comprises 23+1 upper fingers and one upper substrate.
Preferably, 2 of said 10 th split capacitance6The module capacitance is distributed at 2 of the 9 th split capacitance5Two sides of each module capacitor.
Preferably, the 1 st split capacitor and the 2 nd split capacitor are distributed on the left outermost side of the 4 th split capacitor in sequence, and the 3 rd split capacitor is distributed on the right outermost side of the 4 th split capacitor.
Preferably, the 3 rd split capacitor is obtained by reducing the number of metal layers of the upper insertion finger or/and the lower insertion finger of the module capacitor; the module capacitor comprises L layers of metal, and the 3 rd split capacitor comprises L/2 layers of metal.
Preferably, the 1 st split capacitor is obtained by reducing the length of an up/down finger from the module capacitor; the length of the add/drop finger of the module capacitor is P, and the length of the add/drop finger of the 1 st split capacitor is P × 2-3。
The application also provides a digital-to-analog/analog-to-digital converter, which comprises the capacitor array structure and n control switches for respectively controlling the n split capacitors.
According to the technical scheme, the embodiment of the application has the following advantages:
locating a module capacitor in the middle of the array, wherein each split capacitor comprises 1 lower plate and 1 upper plate; all split capacitors of the array are in the same row, and the upper poles of all split capacitorsPlates are connected together from 1 module capacitor to 2 ndn-kIndividual module capacitors, capacitor matching and connections become easy and simple. All capacitors are in the same row, and all capacitors share the upper substrate, so that only one dimension is needed for capacitor matching, the occupied area can be greatly reduced, the size of a chip is reduced, and the cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a charge redistribution DAC circuit according to the present application;
FIG. 2 is a schematic diagram of one embodiment of a capacitor array structure according to the present application;
FIG. 3 is a schematic diagram of a cell capacitor according to the present application;
FIG. 4 is a cross-sectional view of a cell capacitor of the present application taken along section A;
FIG. 5 is a schematic diagram of another embodiment of a capacitor array structure according to the present application;
FIG. 6 is a schematic diagram of a capacitor with capacitance value twice that of a unit capacitor according to the present application;
FIG. 7 is a schematic diagram of a capacitor with a capacitance value of one half of the unit capacitor according to the present application;
FIG. 8 is a schematic diagram of an array provided with matching capacitors according to the present application;
fig. 9 is a diagram illustrating the distribution of split capacitances of the prior art.
Detailed Description
The embodiment of the application provides a capacitor array structure.
In the existing capacitor array structure, each capacitor is composed of unit capacitors, and the two capacitors are arranged in a common centroid scheme in two dimensions. However, as the resolution increases, the footprint increases significantly. The capacitor array structure of the present application is arranged in one dimension, which can solve the above problems.
The circuit corresponding to the capacitor array structure is a charge redistribution digital-to-analog converter circuit. Referring to fig. 1, the charge redistribution dac circuit of the present application includes: a plurality of capacitors, an operational amplifier, and a plurality of single pole double throw switches;
the capacitor with the minimum capacitance value in the plurality of capacitors is the unit capacitor, and the capacitance values of the other capacitors are 2 of the unit capacitorn-1Multiple, n is largeAnd in an integer of 0, one end of each capacitor is connected to the in-phase end of the operational amplifier, the other end of each capacitor is connected to the corresponding single-pole double-throw switch, the normally closed contact of each single-pole double-throw switch is grounded, the normally open contact of each single-pole double-throw switch is connected to a Vref end, and the inverting end and the output end of the operational amplifier are connected to the Vout end.
D0To Dn-1Is a digital signal and is used for controlling a corresponding single-pole double-throw switch. When the digital signal is 1, the normally open contact of the single-pole double-throw switch is connected with the fixed contact, the lower pole plate of the capacitor is connected with the Vref end, and Vout is equal to Vref.
Example one
The application provides capacitor array structure based on above-mentioned circuit design, including n split capacitor, 1 is multiplied by the first split capacitor of unit electric capacity, 2 is multiplied by the second split capacitor of unit electric capacity, analogizes with the same, 2n-1An nth split capacitor which is multiple of the unit capacitor, wherein n is an integer greater than or equal to 1; the first split capacitor is positioned in the middle of the array, the second split capacitor is divided into 2 unit capacitors distributed on two sides of the first split capacitor, and the nth split capacitor is divided into 2 unit capacitorsn-1The unit capacitors are distributed on two sides of the first split capacitor; each split capacitor comprises 1 lower polar plate and 1 upper polar plate; all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.
Referring to fig. 2, each C represents a cell capacitor, which is a first split capacitor located in the middle of the array, and 2C represents a second split capacitor 2 times the cell capacitor, which distributes the 2 cell capacitors equally on two sides of the first split capacitor, one on each side. 4C represents 22And the third split capacitor which is multiple of the unit capacitors evenly distributes the 4 unit capacitors to two sides of the middle capacitor, two on each side, and the like.
Each split capacitor comprises 1 lower polar plate and 1 upper polar plate; all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together. Therefore, the upper electrode plate can be shared, and the area occupied by the split capacitor is further reduced.
As shown in fig. 9, in the prior art, the first split capacitor, the second split capacitor and the third split capacitor are located in two-dimensional space, and are distributed in different rows, there is no way to share the upper plate, and there are many gaps between all the unit capacitors. Therefore, if the same n split capacitors are used, the area occupied by the split capacitors is much smaller than that of the two-dimensional arrangement in the prior art.
Further, referring to fig. 3, the upper plate of the unit capacitor includes 2 upper fingers 304 and 1 upper substrate 301; the plurality of upper insertion fingers of all the split capacitors are connected through the upper substrate; the lower plate of the unit capacitor comprises 1 lower insertion finger 307 and 1 lower substrate 305, the lower insertion fingers of the first split capacitor are connected through the first lower substrate, the 2 lower insertion fingers of the second split capacitor are connected through the second lower substrate, and so on, and the 2n-1 lower insertion fingers of the nth split capacitor are connected through the nth lower substrate.
Further, a diffusion region is formed by implantation inside the chip directly below each upper finger. And polysilicon is arranged on the surface of the chip right below each lower inserting finger and is electrically connected with the lower substrate.
Referring to fig. 3, an upper finger 304 is connected to an upper substrate 301 through an upper connection 302, a lower finger 307 is connected to a lower substrate 305 through a lower connection 306, a diffusion region 303 is formed on the chip surface by implantation right under the upper finger 304, a polysilicon 308 is disposed on the chip surface right under the lower finger 307, and the polysilicon 308 is electrically connected to the lower finger 307.
It is understood that the diffusion region 303 is used for shielding the upper insertion finger 304 from ground, the polysilicon 308 is used for keeping the capacitance to ground stable, and the diffusion region 303 and the polysilicon 308 may or may not be provided, and are not limited herein.
Referring to fig. 4, fig. 4 is a cross-sectional view of the cell capacitor of fig. 3 about a section a. And a capacitor is formed between the upper and lower polar plates, specifically, the effective capacitor of the upper and lower polar plates mainly comprises an upper inserting finger and a lower inserting finger, the upper and lower inserting fingers are formed by stacking multiple layers of metal, and an insulating layer is arranged between every two layers of metal. In fig. 4, taking 4 layers of metal as an example, the upper finger 401 and the lower finger 402 of each layer of metal form a small capacitor, the small capacitor includes two C1, and the capacitor between the upper finger 401 and the lower plate 402 is formed by 4 small capacitors.
In this embodiment, as shown in fig. 2, the unit capacitor is located in the middle of the array, the other capacitors are equally divided into an even number of unit capacitors and are disposed on two sides of the middle capacitor, all the capacitors are located in the same row, every two adjacent capacitors share one upper insertion finger, the upper insertion fingers of all the capacitors of the array are connected through the upper substrate, and the lower insertion finger of each split capacitor is connected with the respective lower substrate. All capacitors are in the same row, and all capacitors share the upper substrate, so that only one dimension is needed for capacitor matching, the occupied area can be greatly reduced, the size of a chip is reduced, and the cost is reduced.
Example two
This embodiment provides another capacitor array structure, comprising n split capacitors, 2-k+1First split capacitor 2 times module capacitor-k+2Second split capacitance, which is multiple of the module capacitance, and so on, 2-k+kThe kth split capacitance being multiple of the module capacitance, the kth +1 split capacitance being 2 multiple of the module capacitance, and so on, 2n-kAn nth split capacitor which is multiple of the module capacitor, wherein n is an integer which is greater than or equal to 1, and k is an integer which is less than n; the kth split capacitor is located in the middle of the array, the (k + 1) th split capacitor is divided into 2 module capacitors distributed on two sides of the kth split capacitor, and the nth split capacitor is divided into 2 module capacitorsn-kThe module capacitors are distributed on two sides of the k-th split capacitor; each split capacitor comprises 1 lower polar plate and 1 upper polar plate; all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.
The upper polar plate of each split capacitor comprises a plurality of upper insertion fingers and an upper substrate, and all the upper insertion fingers are connected through the upper substrate; the lower plate of the module capacitor comprises a plurality of lower insertion fingers and a lower substrate, 2-k+1Multiple lower fingers of a first split capacitor, which is multiple of the module capacitor, are connected through a first lower substrate, 2-k+2Is more than that ofA plurality of lower inserting fingers of a second split capacitor of the module capacitor are connected through a second lower substrate, a plurality of lower inserting fingers of a kth split capacitor which is 1 time as large as the module capacitor are connected through a kth lower substrate, a plurality of lower inserting fingers of a kth +1 split capacitor which is 2 times as large as the module capacitor are connected through a kth +1 lower substrate, and so on, 2 lower inserting fingers of a kth +1 split capacitor are connected through a kth +1 lower substraten-kA plurality of lower fingers of an nth split capacitor that is multiple of the module capacitor are connected through an nth lower substrate.
As shown in fig. 5, taking k as 4, n as 10 as an example, the 4 th split capacitor is a module capacitor C1 and is located in the middle of the array, the 5 th split capacitor is divided into 2 module capacitors distributed on two sides of the 4 th split capacitor, and the 10 th split capacitor is divided into 2 halves6(64) The module capacitors are distributed on two sides of the 4 th split capacitor; the lower plate of the module capacitor comprises 23A lower insert finger and a lower substrate; the upper plate of the module capacitor comprises 23+1 upper fingers and an upper substrate; 2 of the 10 th split capacitor6(64) The module capacitance is distributed at 2 of the 9 th split capacitance5(32) Two sides of each module capacitor.
The better the matching of the 10 split capacitors, the better the resolution of the conversion and the higher the conversion accuracy when used as an ADC or part of an ADC.
The 1 st split capacitor and the 2 nd split capacitor are sequentially distributed on the outermost side of the left side of the 4 th split capacitor, and the 3 rd split capacitor is distributed on the outermost side of the right side of the 4 th split capacitor.
The structure of the small split capacitor (the capacitance value is smaller than that of the module capacitor) is still the same as that of the module capacitor, and the 1 st split capacitor and the 2 nd split capacitor are the minimum and are placed on the outermost side of the left side of the 4 th split capacitor; the 3 rd split capacitor is placed at the outermost right side of the 4 th split capacitor. Thus, the 1 st and 2 nd split capacitances together can be matched to the 3 rd split capacitance relative to the 4 th split capacitance.
In one embodiment, if n is 10, the 10 th split capacitor comprises 29Unit capacitors from 1 to 29The unit capacitor needs to be matched and connected with the capacitor, and the difficulty is high. In the second embodiment, 2 is used3A unit capacitor is madeFor the module capacitance C1, if n is 10, the 10 th split capacitance comprises 26Module capacitors from 1 module capacitor to 2 nd module capacitor6The individual module capacitors, the capacitor matching and the connection, become easy and simple.
Smaller split capacitances can be obtained in a number of ways, including:
the first method is as follows: the 3 rd split capacitor is obtained by reducing the number of metal layers of an upper inserting finger or/and a lower inserting finger of the module capacitor; the module capacitor comprises L layers of metal, and the 3 rd split capacitor comprises L/2 layers of metal. If the module capacitor is 4 layers of metal, then the 3 rd split capacitor is 2 layers of metal, so only the 2 layers of upper fingers are connected to the upper substrate, and correspondingly, the 2 layers of lower fingers are connected to the lower substrate, thus forming a 3 rd split capacitor 1/2 times as much as the module capacitor. If the number of metal layers adopted by the module capacitor is more than 8, the 2 nd split capacitor can only use 2 layers of metal, and the 1 st split capacitor can only use 1 layer of metal.
The second method comprises the following steps: the 1 st split capacitor is obtained by reducing the length of an upper insert finger/a lower insert finger of the module capacitor; the length of the add/drop finger of the module capacitor is P, and the length of the add/drop finger of the 1 st split capacitor is P × 2-3. If the length of the upper insertion finger/the lower insertion finger of the module capacitor is 16um, the length of the upper insertion finger/the lower insertion finger of the 1 st split capacitor is 2um, the length of the insertion finger of the 2 nd split capacitor is 4um, and the length of the insertion finger of the 2 nd split capacitor is 8 um.
Mode III, 1 st to 3 rd split capacitors can be obtained by reducing the number of metal layers of the insertion finger and reducing the length of the insertion finger. Because if the number of metal layers of the module capacitor is small and the length of the inserted finger is short, 2 ways may be needed to be combined.
Directly below each upper finger, a diffusion region is formed in the chip by implantation. And polysilicon is arranged on the surface of the chip right below each lower inserting finger and is electrically connected with the lower substrate. Referring to fig. 3, an upper finger 304 is connected to an upper substrate 301 through an upper connection 302, a lower finger 307 is connected to a lower substrate 305 through a lower connection 306, a diffusion region 303 is formed on the chip surface by implantation right under the upper finger 304, a polysilicon 308 is disposed on the chip surface right under the lower finger 307, and the polysilicon 308 is electrically connected to the lower finger 307.
It is understood that the diffusion region 303 is used for shielding the upper insertion finger 304 from ground, the polysilicon 308 is used for keeping the capacitance to ground stable, and the diffusion region 303 and the polysilicon 308 may or may not be provided, and are not limited herein.
When the structure of the above embodiment needs to improve the yield of the structure, a matching capacitor, also called a dummy capacitor, needs to be provided. The reference capacitor that is close to with the mth split capacitor in the array, split and be provided with the matching capacitance between the capacitor with the mth, one side and the mth split capacitor of matching capacitance share 1 and go up the polar plate, the opposite side of matching capacitance and the reference capacitor that is close to with the mth split capacitor share 1 and go up the polar plate.
For example, referring to fig. 3, 6 and 7, the cell capacitor, the capacitor with capacitance value twice that of the cell capacitor and the capacitor with capacitance value half that of the cell capacitor are shown in the same array. However, the upper plate structure of the capacitor with a capacitance value of one half of the unit capacitor is different from the upper plate structure of the other two capacitors, and cannot be shared, and a matching capacitor needs to be arranged between the capacitor with a capacitance value of one half of the unit capacitor and the unit capacitor. Referring to fig. 8, the dotted line frame is the matching capacitor, which can improve the yield of the structure.
EXAMPLE III
The application provides a digital-to-analog/analog-to-digital converter, which comprises the capacitor array structure of the second embodiment and n control switches for respectively controlling the n split capacitors.
All the split capacitors are in the same row, and all the capacitors share the upper substrate, so that only one dimension is needed for capacitor matching, the occupied area can be greatly reduced, the size of a chip is reduced, and the cost is reduced.
The better the matching of the n split capacitors, the better the resolution of the conversion and the higher the conversion precision when used as an ADC or a part of an ADC.
The capacitor array structure provided by the present application is described in detail above, and the principle and the implementation of the present application are explained in the present application by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (14)

1. A capacitor array structure is characterized by comprising n split capacitors, a first split capacitor 1 time of a unit capacitor, a second split capacitor 2 times of the unit capacitor, and the like, and 2n-1An nth split capacitor which is multiple of the unit capacitor, wherein n is an integer greater than or equal to 1;
the first split capacitor is positioned in the middle of the array, the second split capacitor is divided into 2 unit capacitors distributed on two sides of the first split capacitor, and the nth split capacitor is divided into 2 unit capacitorsn-1The unit capacitors are distributed on two sides of the first split capacitor;
each split capacitor comprises 1 lower polar plate and 1 upper polar plate;
all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.
2. The capacitive array structure of claim 1,
the upper polar plate of the unit capacitor comprises 2 upper insertion fingers and 1 upper substrate; the plurality of upper insertion fingers of all the split capacitors are connected through the upper substrate;
the lower polar plate of the unit capacitor comprises 1 lower insertion finger and 1 lower substrate, the lower insertion finger of the first split capacitor is connected through the first lower substrate, the 2 lower insertion fingers of the second split capacitor are connected through the second lower substrate, and so on, and 2 lower insertion fingers of the nth split capacitorn -1The lower insertion fingers are connected through the nth lower substrate.
3. The capacitor array structure of claim 2, wherein a diffusion region is formed by implantation within the chip directly beneath each of the upper fingers.
4. The capacitor array structure of claim 2, wherein a polysilicon layer is disposed on the surface of the chip directly below each of the lower fingers, the polysilicon layer being electrically connected to the lower substrate.
5. A capacitor array structure, comprising n split capacitors, 2-k+1First split capacitor 2 times module capacitor-k+2Second split capacitor, which is multiple of the module capacitor, and so on, 2-k+kThe kth split capacitance being multiple of the module capacitance, the kth +1 split capacitance being 2 multiple of the module capacitance, and so on, 2n-kAn nth split capacitor which is multiple of the module capacitor, wherein n is an integer which is greater than or equal to 1, and k is an integer which is less than n;
the kth split capacitor is located in the middle of the array, the (k + 1) th split capacitor is divided into 2 module capacitors distributed on two sides of the kth split capacitor, and the nth split capacitor is divided into 2 module capacitorsn-kThe module capacitors are distributed on two sides of the k-th split capacitor;
each split capacitor comprises 1 lower polar plate and 1 upper polar plate;
all the split capacitors of the array are in the same row, and the upper electrode plates of all the split capacitors are connected together.
6. The capacitive array structure of claim 5,
the upper polar plate of each split capacitor comprises a plurality of upper insertion fingers and an upper substrate, and all the upper insertion fingers are connected through the upper substrate;
the lower plate of the module capacitor comprises a plurality of lower insertion fingers and a lower substrate, 2-k+1Multiple lower fingers of a first split capacitor, which is multiple of the module capacitor, are connected through a first lower substrate, 2-k+2Multiple lower insertion fingers of the second split capacitor of multiple module capacitors are connected via the second lower substrate, and multiple k-th split capacitors of 1 multiple module capacitorsThe lower insertion fingers are connected through a kth lower substrate, a plurality of lower insertion fingers which are 2 times of the kth +1 split capacitor of the module capacitor are connected through the kth +1 lower substrate, and the like, 2n-kA plurality of lower fingers of an nth split capacitor that is multiple of the module capacitor are connected through an nth lower substrate.
7. The capacitive array structure of claim 6, wherein when k is 4 and n is 10, the 4 th split capacitor is a module capacitor in the middle of the array, the 5 th split capacitor is divided into 2 module capacitors distributed on two sides of the 4 th split capacitor, and the 10 th split capacitor is divided into 2 halves6The module capacitors are distributed on two sides of the 4 th split capacitor;
the lower plate of the module capacitor comprises 23A lower finger and a lower substrate; the upper plate of the module capacitor comprises 23+1 upper fingers and one upper substrate.
8. The capacitor array structure of claim 7, in which 2 of the 10 th split capacitors6The module capacitance is distributed at 2 of the 9 th split capacitor5Two sides of each module capacitor.
9. The capacitor array structure according to claim 7, wherein the 1 st split capacitor and the 2 nd split capacitor are distributed on the left outermost side of the 4 th split capacitor in sequence, and the 3 rd split capacitor is distributed on the right outermost side of the 4 th split capacitor.
10. The capacitor array structure according to claim 7, wherein the 3 rd split capacitor is obtained by reducing the number of metal layers of the upper finger or/and the lower finger of the module capacitor;
the module capacitor comprises L layers of metal, and the 3 rd split capacitor comprises L/2 layers of metal.
11. The capacitor array structure of claim 7, wherein the 1 st split capacitor is derived from the module capacitor by reducing the length of the up/down fingers;
the length of the add finger/drop finger of the module capacitor is P, and the length of the add finger/drop finger of the 1 st split capacitor is P × 2-3。
12. The capacitive array structure of claim 5, wherein a diffusion region is formed by implantation within the chip directly beneath each of the upper fingers.
13. The capacitor array structure of claim 5, wherein a polysilicon layer is disposed on the surface of the chip directly below each of the lower fingers, the polysilicon layer being electrically connected to the lower substrate.
14. A digital-to-analog/analog-to-digital converter comprising the capacitor array structure of any one of claims 5 to 13, and further comprising n control switches for controlling the n split capacitors, respectively.
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