CN113708768A - Capacitor array, matching method and successive approximation type analog-to-digital converter thereof - Google Patents
Capacitor array, matching method and successive approximation type analog-to-digital converter thereof Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 262
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000011800 void material Substances 0.000 claims description 5
- 238000005070 sampling Methods 0.000 abstract description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 52
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
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- 239000004065 semiconductor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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Abstract
The application discloses a capacitor array, a matching method and a successive approximation type analog-to-digital converter thereof, wherein the capacitor array comprises a plurality of capacitor units which are positioned in a central area; the first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded; the plurality of second virtual capacitor units are arranged around the periphery of the plurality of capacitor units, the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, first electrodes and second electrodes of the second virtual capacitor units are suspended, and first electrode strips of partial capacitor units extend to the second virtual capacitor units adjacent to the partial capacitor units. Under the condition of improving the consistency of capacitance values at different positions of a sampling capacitor array formed by a plurality of capacitor units, the parasitic capacitance between a first electrode strip extending out of the capacitor units and a first virtual capacitor unit is also reduced. And correspondingly, the precision of the successive approximation register analog-to-digital converter is improved.
Description
Technical Field
The present application relates to the field of integrated circuit design, and more particularly, to a capacitor array, a matching method, and a successive approximation analog-to-digital converter thereof.
Background
A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) has characteristics of low power consumption, small size, and the like, and is widely used. The successive approximation register analog-digital converter is an analog-digital converter based on a binary approximation search algorithm, and achieves the purpose of binary division of total charges on a capacitor array by adopting a binary weighted capacitor array to attenuate a reference voltage.
The capacitor array comprises a large number of capacitors, and for a binary weighted capacitor array, the bit capacitance of the smallest unit is a single capacitor unit, the bit capacitance of the next smallest unit comprises two capacitor units, and the next smallest unit comprises four capacitor units, … and 2 in sequencen-1And a capacitor unit, wherein n is the bit resolution of the successive approximation register analog-to-digital converter. In the conventional capacitor array, the positive electrode of the capacitor unit is surrounded by the negative electrode, which may cause the capacitance values at different positions of the capacitor array to be inconsistent, thereby reducing the precision of the successive approximation register adc.
Disclosure of Invention
In view of the above, the present invention provides a capacitor array, a matching method and a successive approximation type analog-to-digital converter thereof, so as to solve the technical problems of capacitor mismatch in the capacitor array and accuracy reduction of the successive approximation register analog-to-digital converter due to differences in capacitance values at different positions of the capacitor array.
According to a first aspect of the present invention, there is provided a capacitive array comprising:
the capacitor units are positioned in the central area and each capacitor unit comprises a first electrode strip and a second electrode strip with opposite polarities;
the first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded;
a plurality of second virtual capacitor units arranged around the plurality of capacitor units, wherein the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, the first electrodes and the second electrodes of the second virtual capacitor units are suspended in the air,
wherein the first electrode strips of a partial capacitive unit extend into the second dummy capacitive unit adjacent to the partial capacitive unit.
In one embodiment, the partial capacitive units include the capacitive unit located at an outermost periphery of the central region.
In one embodiment, the second virtual capacitor unit includes a first electrode and a second electrode which are stacked and oppositely arranged, and the first electrode strip extending to the capacitor unit in the second virtual capacitor unit is stacked with the first electrode and the second electrode of the second virtual capacitor unit and is located between the first electrode and the second electrode of the second virtual capacitor unit.
In one embodiment, the capacitive array further comprises the first or second virtual capacitive unit located at a void of the capacitive array.
In one embodiment, the plurality of capacitor units, the plurality of first dummy capacitor units, and the plurality of second dummy capacitor units are symmetrically arranged in a horizontal or vertical direction, and at least one second dummy capacitor unit is disposed between the capacitor unit and the first dummy capacitor unit.
In one embodiment, the capacitor unit, the first dummy capacitor unit, and the second dummy capacitor unit have the same structure.
In one embodiment, the first electrode strip is a positive electrode and the second electrode strip is a negative electrode.
In a second aspect, an embodiment of the present invention provides a matching method for a capacitor array, including:
arranging a plurality of capacitor units in a central area, wherein each capacitor unit comprises a first electrode strip and a second electrode strip with opposite polarities;
a plurality of first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded;
a plurality of second virtual capacitor units are arranged around the peripheries of the capacitor units, the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, the first electrodes and the second electrodes of the second virtual capacitor units are suspended in the air,
wherein the first electrode strips of a partial capacitive unit extend into the second dummy capacitive unit adjacent to the partial capacitive unit.
In one embodiment, the partial capacitive units include the capacitive unit located at an outermost periphery of the central region.
In one embodiment, the plurality of capacitor units, the plurality of first dummy capacitor units, and the plurality of second dummy capacitor units are symmetrically arranged in a horizontal or vertical direction, and at least one second dummy capacitor unit is disposed between the capacitor unit and the first dummy capacitor unit.
In a third aspect, an embodiment of the present invention provides a successive approximation type analog-to-digital converter, including:
the capacitor array samples and outputs the reference voltage;
the first input end of the comparator is connected with the output end of the capacitor array, the second input end of the comparator receives input voltage, and the output end of the comparator outputs corresponding digital quantity based on the comparison result; and
a control circuit for sequentially controlling the electrodes of the bit capacitors in the capacitor array to be grounded or to receive a reference voltage,
wherein the capacitive array comprises:
the capacitor units are positioned in the central area and each capacitor unit comprises a first electrode strip and a second electrode strip with opposite polarities;
the first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded;
a plurality of second virtual capacitor units arranged around the plurality of capacitor units, wherein the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, the first electrodes and the second electrodes of the second virtual capacitor units are suspended in the air,
wherein the first electrode strips of a partial capacitive unit extend into the second dummy capacitive unit adjacent to the partial capacitive unit.
In one embodiment, the partial capacitive units include the capacitive unit located at an outermost periphery of the central region.
In one embodiment, the plurality of capacitor units, the plurality of first dummy capacitor units, and the plurality of second dummy capacitor units are symmetrically arranged in a horizontal or vertical direction, and at least one second dummy capacitor unit is disposed between the capacitor unit and the first dummy capacitor unit.
The embodiment of the invention provides a capacitor array structure, a matching method and a successive approximation type analog-to-digital converter. The successive approximation type analog-to-digital converter comprises a capacitor array, and the matching method is executed in the capacitor array. The capacitor array comprises a plurality of first virtual capacitor units and a plurality of second virtual capacitor units, wherein the plurality of first virtual capacitor units are arranged around the periphery of a sampling capacitor array formed by a plurality of capacitor units, the plurality of second virtual capacitor units are positioned between the first virtual capacitor units and the sampling capacitor array, a first electrode and a second electrode of each first virtual capacitor are grounded, and a first electrode and a second electrode of each second virtual capacitor unit are suspended. The first electrode bar (positive electrode) of a partial capacitor cell extends into a second dummy capacitor cell disposed adjacent thereto. The first electrode strip (positive electrode) of part of the capacitor units extends to the outside of the capacitor units so as to improve the consistency of the capacitance values at different positions of the sampling capacitor array formed by a plurality of capacitor units. The second virtual capacitor unit (the first electrode and the second electrode are suspended) is arranged between the first virtual capacitor unit (the grounding capacitor) and the capacitor unit, the first electrode strips (the positive electrodes) of part of the capacitor units extend into the second virtual capacitor unit, and under the condition of improving the consistency of capacitance values at different positions of a sampling capacitor array formed by a plurality of capacitor units, the parasitic capacitance between the first electrode strips extending out of the capacitor units and the first virtual capacitor unit is also reduced. And correspondingly, the precision of the successive approximation register analog-to-digital converter is improved.
In another embodiment, the partial capacitance comprises said capacitive cell located outermost in the central area. The first electrode strip of the capacitor unit located at the outermost periphery of the central area extends into the second virtual capacitor unit adjacent to the capacitor unit, so that the capacitance values at the edge position and the central position in the sampling capacitor array formed by the plurality of capacitor units are consistent, the capacitance value difference between the capacitor units located at different positions in the capacitor array is further reduced, and the precision of the successive approximation register analog-digital converter is correspondingly improved.
In another embodiment, the first electrode strip extending from the capacitor unit is located between the first electrode and the second electrode in the second virtual capacitor unit, thereby preventing the parasitic capacitance between the first electrode strip extending from a part of the capacitor unit and the first virtual capacitor unit from being greatly increased.
In another embodiment, the second dummy capacitor unit or the first dummy capacitor unit is disposed at a vacancy of the capacitor array, the vacancy being located in a central region of the capacitor array or an edge region surrounding the central region. So that the capacitor array can be more uniformly formed when the process for forming the capacitor array is manufactured. Furthermore, the capacitors in the capacitor array are symmetrically arranged in the horizontal or vertical direction, so that the design complexity of forming the capacitor array is reduced. And at least one second virtual capacitor unit is arranged between the capacitor unit and the first virtual capacitor unit, so that the area of the capacitor array can be reduced as much as possible under the conditions of solving the problem that the capacitance values at different positions in the capacitor array are consistent and reducing the parasitic capacitance. Furthermore, the capacitor unit and the first dummy capacitor unit have the same structure, thereby further reducing the complexity of the manufacturing process.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing embodiments of the present invention with reference to the following drawings, in which:
FIG. 1 is a schematic diagram of a capacitor array according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a layout pattern of a capacitor array according to an embodiment of the present invention;
fig. 3 is a perspective view showing a structure of a capacitor unit in the capacitor array according to the embodiment of the invention;
fig. 4 is a schematic diagram illustrating a layout pattern of a second layer of a capacitor unit in the capacitor array according to the embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present invention. The figures are not necessarily drawn to scale.
Fig. 1 shows a schematic structural diagram of a capacitor array according to an embodiment of the present invention. Fig. 2 is a schematic diagram showing a layout pattern of a capacitor array according to an embodiment of the present invention. Fig. 3 is a perspective view showing a structure of a capacitor unit in the capacitor array according to the embodiment of the invention. Fig. 4 is a schematic diagram illustrating a layout pattern of a second layer of a capacitor unit in the capacitor array according to the embodiment of the present invention. Fig. 2 is a schematic diagram illustrating the position relationship between the first virtual capacitor cell C1 and the second virtual capacitor cell C2 located at the periphery and the capacitor cell C located in the central region, so that the capacitors of the matched capacitor cells C are not shown in the central region 110 in fig. 2. It should be noted that, for example, by deleting the corresponding first electrode strips according to the target ratio and modifying the electrode plate layer patterns corresponding to the first electrode strips, each bit of capacitance corresponding to different capacitance values can be obtained through matching, and a scheme for forming different bits of capacitance through matching of the capacitance units is not described in detail in this embodiment.
As shown in fig. 1 and 2, the capacitor array 100 includes a plurality of capacitor cells C, a plurality of first dummy capacitor cells C1, and a plurality of second dummy capacitor cells C2.
The capacitor unit C is located in the central region 110 of the capacitor array 100, and the plurality of capacitor units C are matched to form a plurality of bit capacitors with different capacitance values, where the bit capacitor includes a bit capacitor of a single capacitor unit, a bit capacitor formed by two capacitor units in parallel matching, a bit capacitor formed by four capacitor units in parallel matching, …, and 2n-1The capacitor units are connected in parallel to form a bit capacitor, wherein n is a positive integer. The capacitor unit C includes first and second electrode bars having opposite polarities.
The capacitor unit C is, for example, an MOM capacitor, and its structure is shown in fig. 3. The capacitive unit C includes a substrate 111, a first layer 112, a second layer 113, and a third layer 114. The capacitor unit C further includes insulating layers filled between the respective layers and between the electrode bars of the same layer. The substrate 111 is, for example, a semiconductor material layer. The second layer 112 is formed on the substrate 111 via a dielectric, which is located between the substrate 111 and the second layer 112. The first layer 112, the second layer 113, and the third layer 114 are sequentially stacked, and each of the first layer 112, the second layer 113, and the third layer 114 is, for example, a metal layer. The first layer 112 and the third layer 114 are metal plates without any openings or openings formed therein. The second layer 113 is located between the first layer 112 and the third layer 114, the second layer 113 comprising a plurality of electrode stripes. Further, the second layer 113 includes a plurality of first electrode stripes and a plurality of second electrode stripes. The second electrode stripes in the second layer 113 are electrically connected to the first layer 112 and the third layer 114, respectively, via the via holes 115, and the first electrode stripes are not electrically connected to the other layers. Although the embodiment shows that the second electrode bar of the second layer 113 is electrically connected to the first layer 112 and the third layer 114 by providing 8 through holes at the edge positions of the capacitor cell C, the number and positions of the through holes may be arbitrarily set according to actual needs. In the capacitor cell C, the second electrode stripes in the first layer 112, the third layer 114, and the second layer 113 electrically connected to the first layer 112 and the third layer 114 serve as first electrodes (negative electrodes) of the capacitor cell C, and the remaining first electrode stripes in the second layer 112 serve as second electrodes (positive electrodes) of the capacitor cell C. The first electrode and the second electrode have opposite polarities, and a capacitance is formed between the first electrode and the second electrode. In an alternative embodiment, at least one protective layer is further provided in the capacitive cell C, for example provided between the substrate 111 and the first layer 112 and/or on the third layer 114 and away from the second layer 113. In an alternative embodiment, a second layer 113 structure with the same layout pattern is stacked and disposed in the capacitor unit C, for example, between the first layer 112 and the third layer 114. In alternative embodiments, the above alternatives can be freely combined according to actual requirements to obtain a new capacitor array structure.
As shown in fig. 1 and 2, the first virtual capacitor cell C1 is disposed around the periphery of the sampling capacitor array formed by the plurality of capacitor cells C, and the first electrode and the second electrode of the first virtual capacitor cell C1 are both grounded. The plurality of second dummy capacitor cells C2 are disposed around the plurality of capacitor cells C, and the second dummy capacitor cell C2 is disposed between the first dummy capacitor cell C1 and the capacitor cells C, and the first electrode and the second electrode of the second dummy capacitor cell C2 are floating. The outermost partial capacitive unit C of the capacitive array 100 has a first electrode bar extending into the second dummy capacitive unit C2 adjacent to the partial capacitive unit C. That is, the first electrode bar of at least one capacitor cell C adjacent to the second virtual capacitor cell C2 extends outside and into the second virtual capacitor cell C2. Further, fig. 4 shows a schematic diagram of a layout pattern of the second layer 113 of the partial capacitor unit C at the outermost periphery of the capacitor array 100. As shown in fig. 4, the plurality of second electrode stripes 1131 and the first electrode stripes 1132 in the second layer 113 are spaced apart from each other, and the second electrode stripes 1131 are disposed around the first electrode stripes 1132. Further, the second electrode strip 1131 is located at an edge position of the whole plane of the second layer 113, and the first electrode strip 1132 is located at a center position of the whole plane of the second layer 113 and extends outward. In this embodiment, the first electrode stripes 1132 are, for example, in a cross-shaped pattern, the second electrode stripes 1131 are, for example, in one of a plurality of shapes formed by combining "-" and "|" or any concentrated arrangement, and edge portions of the first electrode stripes 1132 extend outward beyond the pattern formed by the second electrode stripes 1131.
In this embodiment, the first electrode of the capacitor unit C faces the power ground, and the second electrode provides different potentials to provide charges in the capacitor unit C. In an alternative embodiment, the shape of the first electrode stripes in the second layer 113 of the capacitive unit C may also be "well", "font", "character" shapes. The capacitive unit C comprises different capacitor units C to obtain different bit capacitors, and the first electrode strips of the capacitor units C in each bit capacitor are connected with each other and connected to the same potential.
In another embodiment, the partial capacitive cells C include capacitive cells C located at the outermost periphery of the central region. That is, the first electrode bar of the capacitor cell C of the outermost circumference of the central region extends into the second dummy capacitor cell C2 adjacent thereto.
In another embodiment, the second dummy capacitor C2 includes a first electrode and a second electrode opposite to each other, the first electrode and the second electrode of the second dummy capacitor C2 are both floating, and no potential is provided at the first electrode and the second electrode of the second dummy capacitor C2. The first electrode bar of the capacitor cell C disposed adjacent to the second dummy capacitor cell C2 extends into the second dummy capacitor cell C2. The first electrode bar of the capacitor unit C extending outside is terminated in the second dummy capacitor unit C2. Wherein the first electrode bar of the capacitor unit C extending into the second dummy capacitor unit C2 is stacked with the first electrode and the second electrode of the second dummy capacitor unit C2 and is located between the first electrode and the second electrode of the second dummy capacitor unit C2.
In another embodiment, the capacitor array 100 may have a void after the capacitance matching, the void being located in a central region or an edge region surrounding the central region of the capacitor array 100. The second dummy capacitor unit C2 is arranged at the vacancy, so that the problem of inconsistent capacitance of the capacitor array can be solved. In an alternative embodiment, the first dummy capacitive unit C1 is provided in the void. Further, the capacitor cell C, the second dummy capacitor cell C2, and the first dummy capacitor cell C1 in the capacitor array 100 are symmetrically arranged in the horizontal or vertical direction, and the capacitor array 100 has a quadrilateral shape, for example. Wherein in an alternative embodiment, the capacitor array 100 is, for example, square in shape.
Specifically, the structures of the first and second dummy capacitor cells C1 and C2 are identical to those of the capacitor cell C, so that the capacitor array is uniformly formed in a semiconductor manufacturing process. In some embodiments, among the plurality of second virtual capacitor cells, the first electrode bar of the outermost second virtual capacitor cell C2 may extend into the first virtual capacitor cell C1, such as between the first layer and the second layer of the first virtual capacitor cell C1, and the length of the first electrode bar of the outermost second virtual capacitor cell C2 may be arbitrary. In some embodiments, the outermost second virtual capacitive unit C2 may not extend.
The application also provides a matching method of the capacitor array, which comprises the step of arranging a plurality of capacitor units C in the central area, wherein each capacitor unit C comprises a first electrode strip and a second electrode strip with opposite polarities, and the capacitor units C are in the capacitor structure provided by the method. And a plurality of first virtual capacitor units C1 are arranged around the periphery of the plurality of capacitor units C, and the first electrode and the second electrode of the first virtual capacitor unit C1 are grounded. And a plurality of second dummy capacitor cells C2 are disposed around the plurality of capacitor cells C, the second dummy capacitor cell C2 is located between the first dummy capacitor cell C1 and the capacitor cells C, the first electrode and the second electrode of the second dummy capacitor cell C2 are suspended, wherein the first electrode stripes of some of the capacitor cells C extend into the second dummy capacitor cell C2 adjacent to the capacitor cells C. Further, the partial capacitive units C include a capacitive unit C located at the outermost periphery of the central region.
The application also provides a successive approximation type analog-to-digital converter, which is a common structure with medium to high resolution and is often applied to the fields of portable/battery-powered instruments, pen input quantizers, industrial control, data/signal acquisition and the like. The basic structure of the successive approximation type analog-digital converter comprises a comparator, a capacitor array and a control circuit. The capacitor array employs the capacitor array 100 provided above. The comparator is used for comparing the input voltage with a plurality of outputs provided in the capacitor array and outputting corresponding digital quantities. The first input of the comparator receives an input voltage, which may also be connected to the first input of the comparator via a voltage holding circuit, for example. The second input end of the comparator receives the output end of the capacitor array, and the output end of the comparator outputs a digital signal corresponding to the input voltage. The capacitor array receives the reference voltage, the output of the reference voltage is one half of the reference voltage in an initial default setting, and the output of the capacitor array is controlled to be changed continuously along with the fact that the control circuit controls electrode grounding of each bit of the capacitor array or receives the reference voltage successively until all bits of the capacitor array are collected. And further, a digital signal corresponding to the input voltage is obtained, and analog-to-digital conversion processing is completed.
Those skilled in the art will appreciate that various modules or components according to the present invention may be implemented in hardware, firmware, or software. The software includes, for example, a code program formed using various programming languages such as JAVA, C/C + +/C #, SQL, and the like. Although the steps and sequence of steps of the embodiments of the present invention are presented in method and method diagrams, the executable instructions of the steps implementing the specified logical functions may be re-combined to create new steps. The sequence of the steps should not be limited to the sequence of the steps in the method and the method illustrations, and can be determined at any time according to the functional requirements. Such as performing some of the steps in parallel or in reverse order.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A capacitive array, comprising:
the capacitor units are positioned in the central area and each capacitor unit comprises a first electrode strip and a second electrode strip with opposite polarities;
the first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded;
a plurality of second virtual capacitor units arranged around the plurality of capacitor units, wherein the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, the first electrodes and the second electrodes of the second virtual capacitor units are suspended in the air,
wherein the first electrode strips of a partial capacitive unit extend into the second dummy capacitive unit adjacent to the partial capacitive unit.
2. The capacitive array of claim 1, wherein the partial capacitive units comprise the capacitive units located outermost the central region.
3. The capacitor array according to claim 1, wherein the second dummy capacitor unit comprises a first electrode and a second electrode stacked and disposed opposite to each other, and the first electrode bar extending to the capacitor unit in the second dummy capacitor unit is stacked on the first electrode and the second electrode of the second dummy capacitor unit and located between the first electrode and the second electrode of the second dummy capacitor unit.
4. The capacitive array of any of claims 1 to 3, wherein the capacitive array further comprises the first or second virtual capacitive cell located at a capacitive array void.
5. The capacitor array according to claim 4, wherein the plurality of capacitor units, the plurality of first dummy capacitor units, and the plurality of second dummy capacitor units are symmetrically arranged in a horizontal or vertical direction, and at least one second dummy capacitor unit is disposed between the capacitor unit and the first dummy capacitor unit.
6. The capacitive array of claim 1, wherein the capacitive unit, the first dummy capacitive unit, and the second dummy capacitive unit are identical in structure.
7. The capacitive array of claim 1, wherein the first electrode strip is a positive electrode and the second electrode strip is a negative electrode.
8. A method of matching a capacitive array, comprising:
arranging a plurality of capacitor units in a central area, wherein each capacitor unit comprises a first electrode strip and a second electrode strip with opposite polarities;
a plurality of first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded;
a plurality of second virtual capacitor units are arranged around the peripheries of the capacitor units, the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, the first electrodes and the second electrodes of the second virtual capacitor units are suspended in the air,
wherein the first electrode strips of a partial capacitive unit extend into the second dummy capacitive unit adjacent to the partial capacitive unit.
9. The method of matching a capacitive array of claim 8, wherein the partial capacitive units comprise the capacitive units located outermost the central region.
10. The matching method of a capacitor array according to claim 8, wherein the plurality of capacitor units, the plurality of first dummy capacitor units, and the plurality of second dummy capacitor units are symmetrically arranged in a horizontal or vertical direction, and at least one second dummy capacitor unit is provided between the capacitor unit and the first dummy capacitor unit.
11. A successive approximation analog to digital converter, comprising:
the capacitor array samples and outputs the reference voltage;
the first input end of the comparator is connected with the output end of the capacitor array, the second input end of the comparator receives input voltage, and the output end of the comparator outputs corresponding digital quantity based on the comparison result; and
a control circuit for sequentially controlling the electrodes of the bit capacitors in the capacitor array to be grounded or to receive a reference voltage,
wherein the capacitive array comprises:
the capacitor units are positioned in the central area and each capacitor unit comprises a first electrode strip and a second electrode strip with opposite polarities;
the first virtual capacitor units are arranged around the peripheries of the capacitor units, and first electrodes and second electrodes of the first virtual capacitor units are grounded;
a plurality of second virtual capacitor units arranged around the plurality of capacitor units, wherein the second virtual capacitor units are positioned between the first virtual capacitor units and the capacitor units, the first electrodes and the second electrodes of the second virtual capacitor units are suspended in the air,
wherein the first electrode strips of a partial capacitive unit extend into the second dummy capacitive unit adjacent to the partial capacitive unit.
12. The successive approximation analog to digital converter of claim 11, wherein the partial capacitive units comprise the capacitive units located at an outermost periphery of the central region.
13. The successive approximation type analog-to-digital converter according to claim 11, wherein the plurality of capacitance units, the plurality of first dummy capacitance units, and the plurality of second dummy capacitance units are symmetrically arranged in a horizontal or vertical direction, and at least one second dummy capacitance unit is provided between the capacitance unit and the first dummy capacitance unit.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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