CN212627864U

CN212627864U - SARADC layout structure

Info

Publication number: CN212627864U
Application number: CN202021975465.6U
Authority: CN
Inventors: 周云
Original assignee: Huada Semiconductor Co ltd
Current assignee: Xiaohua Semiconductor Co ltd
Priority date: 2020-09-10
Filing date: 2020-09-10
Publication date: 2021-02-26
Anticipated expiration: 2030-09-10

Abstract

The utility model provides a SARADC layout structure, SARADC layout structure's outline is square plane and spreads out, and wherein multiseriate electric capacity permutation and combination forms the capacitor array, include: one or more first intermediate capacitances arranged at an edge of a column or columns in the capacitive array; a plurality of sets of left column capacitances arranged in the capacitor array to the left relative to the first intermediate capacitances; a plurality of sets of right column capacitances arranged in the capacitor array to the right relative to the first intermediate capacitances; a plurality of the first intermediate capacitors are connected in parallel to form a first intermediate circuit, or one first intermediate capacitor forms a first intermediate circuit; the first end of each group of left-column capacitors is electrically connected with the first end of the first intermediate circuit and the first signal end; the first end of each group of the right column capacitors is electrically connected with the second end of the first middle circuit and the second signal end.

Description

SARADC layout structure

Technical Field

The utility model relates to the field of semiconductor technology, in particular to SARADC territory structure.

Background

A Successive Approximation Analog-to-Digital Converter (SAR ADC) is an ADC based on a binary search Approximation algorithm, and the basic working principle is to attenuate a reference voltage by using a binary-weighted capacitor array to achieve the purpose of binary division of total charge on the capacitor array, thereby implementing the binary Approximation search algorithm.

A conventional charge redistribution type SAR ADC mainly includes a capacitor array, a comparator, and a successive approximation logic control circuit. The capacitor array is one of important sources of energy consumption of the SAR ADC, and the capacitor array adopted by the SAR ADC with the traditional structure has capacitor mismatch and greatly influences the precision of the SAR ADC.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a SARADC territory structure to there is the capacitor mismatch and influences the problem of SAR ADC's precision greatly in solving current capacitor array.

In order to solve the technical problem, the utility model provides a SARADC layout structure, SARADC layout structure's outline is square plane and spreads out, and wherein multiseriate electric capacity arranges the combination and forms the capacitor array, include:

one or more first intermediate capacitances arranged at an edge of a column or columns in the capacitive array;

a plurality of sets of left column capacitances arranged in the capacitor array to the left relative to the first intermediate capacitances;

a plurality of sets of right column capacitances arranged in the capacitor array to the right relative to the first intermediate capacitances;

a plurality of the first intermediate capacitors are connected in parallel to form a first intermediate circuit, or one first intermediate capacitor forms a first intermediate circuit;

the first end of each group of left-column capacitors is electrically connected with the first end of the first intermediate circuit and the first signal end;

the first end of each group of the right column capacitors is electrically connected with the second end of the first middle circuit and the second signal end.

Optionally, in the sar adc layout structure, the column where the first intermediate capacitor is located is left vacant at other positions away from the edge direction.

Optionally, in the sar adc layout structure, the sar adc layout structure further includes one or more second intermediate capacitors, and at least one of the second intermediate capacitors and the first intermediate capacitor is located in the same column;

the second intermediate capacitors are connected in parallel to form a second intermediate circuit, the first end of the second intermediate circuit is electrically connected with the first end of the first intermediate circuit, and the second end of the second intermediate circuit is electrically connected with a third signal end.

Optionally, in the sar adc layout structure, the second ends of the left-row capacitors of each group are respectively electrically connected to a switch array, at least one group of the right-row capacitors is grounded, and the second ends of the remaining right-row capacitors of each group are respectively electrically connected to the switch array.

Optionally, in the sar adc layout structure, the grounded right column of capacitors is not located in the rightmost column of the capacitor array.

Optionally, in the sar adc layout structure, the plurality of groups of left-column capacitors include a first group of left-column capacitors gradually approaching the first intermediate capacitor, a second group of left-column capacitors …, and an nth group of left-column capacitors, where N is a natural number greater than or equal to 4, where two adjacent groups of left-column capacitors satisfy the following conditions:

the number of the N-1 th group of left column capacitors is 2 times that of the N-1 th group of left column capacitors.

Optionally, in the sar adc layout structure, the number of the first intermediate capacitors is 2, the number of the second intermediate capacitors is 3,

the number of the middle columns is 2, 2 first middle capacitors are respectively distributed in the fourth row of the 2 middle columns, and the second middle capacitors are distributed in the first row to the third row of the middle column on the left side;

the number of the first group of left column capacitors is 8;

the fourth group of left-column capacitors and the third group of left-column capacitors are distributed in the column closest to the first middle capacitor;

the number of the first group of right-row capacitors is 4, the number of the second group of right-row capacitors is 2, the number of the grounded right-row capacitors is 4, one of the capacitors is distributed in a right-side row closest to the first middle capacitor, and the number of the other groups of right-row capacitors is 1.

Optionally, in the sar adc layout structure, the sar adc layout structure further includes an isolation array,

at least one of the four sides of the capacitor array is surrounded by the isolation array.

Optionally, in the sar adc layout structure, the isolation array includes a first grounding module, a second grounding module, and a plurality of DUMMY modules, where the first grounding module is distributed in a right column closest to the first intermediate capacitor and adjacent to a grounded right column capacitor, and the second grounding module is distributed on the right side of the plurality of groups of right column capacitors and at the bottom ends of the plurality of right columns;

one of the DUMMY modules is distributed in a left column closest to the first middle capacitor, and the other DUMMY modules are distributed in a left side of the plurality of left column capacitors and bottom ends of a plurality of left columns.

The utility model provides an among the SARADC layout structure, arrange in the edge that certain or some were listed as in capacitor array through one or more first middle electric capacity, the left side of multiunit is listed as electric capacity arrange in capacitor array for in the left side of first middle electric capacity, the right side of multiunit is listed as electric capacity arrange in capacitor array for in the right side of first middle electric capacity, the left side is listed as electric capacity, the right side is listed as electric capacity and first middle electric capacity between do not need to control alternately to walk the line, has avoided increasing parasitic capacitance's risk because alternately walking the line, has realized improving SARADC circuit precision, reduces the mismatch, promotes the effect of SARADC performance. The utility model discloses putting of device among the well territory especially electric capacity is more reasonable, and when designing SARADC, the rational arrangement of electric capacity can improve SARADC's precision.

Drawings

Fig. 1 is a schematic diagram of a conventional sar adc layout structure;

fig. 2 is a schematic diagram of a sar adc layout circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a sar adc layout structure according to an embodiment of the present invention.

Detailed Description

The sar adc layout structure proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Furthermore, features in different embodiments of the invention may be combined with each other, unless otherwise specified. For example, a feature of the second embodiment may be substituted for a corresponding or functionally equivalent or similar feature of the first embodiment, and the resulting embodiments are likewise within the scope of the disclosure or recitation of the present application.

Fig. 2 is a circuit diagram of sar adc capacitors, the capacitor types are MIM capacitors, C0 is the most important first intermediate capacitor in the circuit, C1, C2, C3, and C4 are left-side capacitors of C0, the number ratio is 8:4:2:1, right-side capacitors are C5, C6, C7, C8, C9, C10, and C11, the number ratio is 4:2:1:1:1: 4, and C12 is a second intermediate capacitor connected to a point C0 at the outer side, and the circuit diagram is as shown in fig. 1.

As shown in fig. 1, a conventional capacitor layout structure is shown, C0 is laid out at the center, C4 is laid out at the edge of C0, a vacant position is filled with DUMMY capacitors, left and right 2C 5 capacitors are uniformly distributed on both sides of C0 and C4, C2 is distributed on both upper and lower sides of C0 and C4, C3 and C6 are laid out at diagonal positions of C0 and C4, C1 is laid out on both sides of C0, C4, C2, C5, C3 and C6, C7, C8, C9 and C10 are laid out on the right side, C11 is grounded capacitors and laid out on the right side of C1, C8, C9 and C10, C12 is distributed in a row closest to the left side of C1, in order to make them more uniformly distributed, DUMMY capacitors are filled on C12 as a supplement, and all capacitors are filled with mmy capacitors as their peripheries.

The capacitor layout shows that when the capacitor C0 is connected with other capacitors, cross wiring is easily generated, the wiring difficulty of the layout connecting line is increased, a plurality of parasitic capacitors are generated, and the circuit precision is reduced; and the circuit layout occupies a large area, which is not beneficial to the miniaturization and light weight of the circuit.

The utility model discloses a core thought lies in providing a SARADC territory structure to there is the electric capacity mismatch and influences the problem of SAR ADC's precision greatly in solving current capacitor array.

The utility model aims at providing unique layout mode, improve SAR ADC circuit's precision, promote SARADC circuit performance.

In order to realize the above idea, the utility model provides a SARADC layout structure, SARADC layout structure's outline is square plane and spreads out, and wherein multiseriate electric capacity permutation and combination forms the capacitor array, include: one or more first intermediate capacitances arranged at an edge of a column or columns in the capacitive array; a plurality of sets of left column capacitances arranged in the capacitor array to the left relative to the first intermediate capacitances; a plurality of sets of right column capacitances arranged in the capacitor array to the right relative to the first intermediate capacitances; a plurality of the first intermediate capacitors are connected in parallel to form a first intermediate circuit, or one first intermediate capacitor forms a first intermediate circuit; the first end of each group of left-column capacitors is electrically connected with the first end of the first intermediate circuit and the first signal end; the first end of each group of the right column capacitors is electrically connected with the second end of the first middle circuit and the second signal end.

The capacitor mismatch of the sar ADC greatly affects the accuracy of the ADC, resulting in poor chip performance, and this embodiment provides a sar ADC capacitor layout design with a new architecture to improve the accuracy and performance of the ADC. As shown in fig. 3, the outer contour of the sar adc layout structure is spread out in a square plane, wherein a plurality of rows of capacitors are arranged and combined to form a capacitor array, including: two first intermediate capacitors C0 arranged at the lower edges of the middle two columns in the capacitor array; four sets of left column capacitances (C1-C4) arranged on the left side of the capacitor array relative to the first intermediate capacitance C0; seven sets of right column capacitances (C5-C11) arranged in the capacitor array to the right relative to the first intermediate capacitance C0; the number of the left-column capacitors and the number of the right-column capacitors can be increased or decreased according to practical application occasions, and the number of the capacitors in each group can be adjusted according to the practical application occasions;

as shown in fig. 2, two first intermediate capacitors C0 are connected in parallel to form a first intermediate circuit C0:2, and those skilled in the art may use a single first intermediate capacitor C0 to form a first intermediate circuit in other embodiments, which will not be described in detail herein; the first ends of the left-column capacitors (C1-C4) of each group are electrically connected with the first end of the first intermediate circuit C0:2 and the first signal end CTOP; the first ends of the right column capacitors (C5-C11) of each group are electrically connected with the second end of the first middle circuit C0:2 and the second signal end CLSB. In the sar adc layout structure, the second ends of the left-row capacitors of each group are respectively electrically connected to a switch array, the second ends of the right-row capacitors of each group are respectively electrically connected to the switch array or the ground GND, at least one group of the right-row capacitors is grounded, the second ends of the remaining groups of the right-row capacitors are respectively electrically connected to the switch array, in this embodiment, a group of capacitors C11 is grounded, and the other capacitors C5-C10 are electrically connected to the switch array, wherein the grounded right-row capacitor C11 is not located in the rightmost row of the capacitor array.

Specifically, as shown in FIG. 3, the first intermediate capacitor C0 is typically distributed at the lower edge of the middle two columns to close the isolation array. If necessary in practical operation, the first intermediate capacitor C0 may also be disposed at the upper edge of the middle two columns, and those skilled in the art can perform layout arrangement according to the description, and details are not described here, as long as it is sufficient to place the first intermediate capacitor C0 at the edge position of the capacitor array.

The utility model provides an in the SARADC layout structure, through one or more first middle electric capacity arrange in certain one in the capacitor array or the edge of several certain rows, the left electric capacity that is listed as of multiunit arrange in the capacitor array for in the left side of first middle electric capacity, the right electric capacity that is listed as of multiunit arrange in the capacitor array for in the right side of first middle electric capacity, the left side is listed as electric capacity, the right side is listed as and does not need to control alternately to walk the line between electric capacity and the first middle electric capacity, avoided walking the risk that increases parasitic capacitance because alternately, realized improving SARADC circuit precision, reduce the mismatch, promote the effect of SARADC performance, and first middle electric capacity arranges and draws forth the signal in the edge is easier. The utility model discloses putting of device among the well territory especially electric capacity is more reasonable, and when designing SARADC, the rational arrangement of electric capacity can improve SARADC's precision.

As shown in fig. 3, in the sar adc layout structure, the sar adc layout structure further includes an isolation array, and at least one of four sides of the capacitor array is surrounded by the isolation array; a capacitive array is arranged in the center of the sar adc layout structure, which is arranged with at least one of the four sides surrounded by the isolation array.

Optionally, in the sar adc layout structure, the column where the first intermediate capacitor is located may have two embodiments, one of which is a vacant position away from the edge direction; another is as shown in fig. 3, the sar adc layout structure further includes one or more second intermediate capacitors C12, and each of the second intermediate capacitors C12 is located in the same column as at least one of the first intermediate capacitors C0; the second intermediate capacitor C12 is connected in parallel to form a second intermediate circuit C12:3, a first end of the second intermediate circuit C12:3 is electrically connected to a first end of the first intermediate circuit C0:2, and a second end of the second intermediate circuit C12:3 is electrically connected to a third signal terminal.

Further, in the sar adc layout structure, the plurality of groups of left-column capacitors include a first group of left-column capacitors C1, a second group of left-column capacitors C2, …, and an nth group of left-column capacitors CN which gradually approach the first intermediate capacitor in sequence, where N is a natural number greater than or equal to 4, where two adjacent groups of left-column capacitors satisfy the following conditions: the number of the N-1 group of left column capacitors is 2 times of that of the N group of left column capacitors; in this embodiment, the number of the first group of left column capacitors C1 is 8, which is 2 times the number of the second group of left column capacitors C2; the number of the second group of left column capacitors C2 is 4 and is 2 times that of the third group of left column capacitors C3; by analogy, the number of the third group of left column capacitors C3 is 2; the number of the fourth group of left column capacitors C4 is 1. The left column of capacitors are arranged to form a four-row capacitor array, the number of the first intermediate capacitors C0 is 2, the number of the second intermediate capacitors C12 is 3, the column occupied by the first intermediate capacitors C0 is an intermediate column, the number of the intermediate column is 2, 2 first intermediate capacitors are respectively distributed in a fourth row of the 2 intermediate columns, and the second intermediate capacitors are distributed in first to third rows of the intermediate column on the left side; the fourth and third sets of left column capacitances C4 and C3 are distributed in the first left column closest to the middle column; the second set of left column capacitances C2 occupy a second left column, the second left column being located to the left of the first left column; the first set of left column capacitances C1 occupy a third left column and a fourth left column, the third left column being located to the left of the second left column, the fourth left column being located to the left of the third left column.

Further, the number of the first group of right column capacitors C5 is 4, the number of the second group of right column capacitors C6 is 2, the number of the right column capacitors C11 connected to ground is 4, one of the right column capacitors is distributed in the right column closest to the first intermediate capacitor C0, and the number of the other groups of right column capacitors is 1 respectively and is 4 in total; in the sar adc layout structure, the right columns of capacitors are arranged to form a four-row capacitor array, and the second group of right columns of capacitors C6 is distributed in the first right column closest to the middle column; the first set of right column capacitances C5 occupies a second right side column, the second right side column being located to the right of the first right side column; the right column capacitors further comprise a plurality of groups of right column capacitors (C7-C10) positioned in the edge columns, and the plurality of groups of right column capacitors (C7-C10) positioned in the edge columns are distributed in the rightmost column of the capacitor array; the remaining 3 grounded right column capacitances C11 are distributed across the capacitor array except for the rightmost column.

In an embodiment of the present invention, in the sar adc layout structure, the number of the first intermediate capacitors C0 is 2, the number of the second intermediate capacitors C12 is 3, the number of the intermediate columns is 2, 2 first intermediate capacitors C0 are respectively distributed in the fourth row of the intermediate columns, and the second intermediate capacitors C12 are distributed in the left side from the first row to the third row of the intermediate columns; the number of the first group of left column capacitors C1 is 8, the number of the second group of left column capacitors C2 is 4, the number of the third group of left column capacitors C3 is 2, and the number of the fourth group of left column capacitors C4 is 1; the fourth set of left column capacitances C4 is distributed in a third row of a first left column, the third set of left column capacitances C3 is distributed in first and second rows of the first left column, the second set of left column capacitances C2 is distributed in first through fourth rows of the second left column, and the first set of left column capacitances C1 is distributed in third and fourth left columns;

the number of the first group of right column capacitors C5 is 4, the number of the second group of right column capacitors C6 is 2, the number of the grounded right column capacitors C11 is 4, one of the capacitors is distributed in the fourth row of the first right column, the remaining 3 capacitors C11 are distributed in the second row to the fourth row of the third right column, and the numbers of the third group of right column capacitors C7, the fourth group of right column capacitors C8, the fifth group of right column capacitors C9 and the sixth group of right column capacitors C10 are respectively 1 and are 4 in total; the second set of right column capacitors C6 is distributed in the first and second rows of the first right column, the first set of right column capacitors C5 is distributed in the first to fourth rows of the second right column, and the third, fourth, fifth, and sixth sets of right column capacitors C7, C8, C9, and C10 are distributed in the first to fourth rows of the fourth right column, respectively.

In an embodiment of the present invention, in the sar adc layout structure, the isolation array includes a first ground module GND, a second ground module GND and a plurality of DUMMY modules DM, the first ground module GND is distributed on a right column closest to the first middle capacitor and adjacent to a grounded right column capacitor, the second ground module GND is distributed on a right side of the plurality of right columns capacitors, that is, on a right side of the fourth right column, and bottom ends of the plurality of right columns; one of the DUMMY modules DM is distributed in the left column closest to the first middle capacitor, i.e. the fourth row of the first left column, and the other DUMMY modules DM is distributed in the left side of the first group of left capacitors, i.e. the left side of the fourth left column, and the bottom ends of the left columns.

As shown in fig. 3, which is a novel layout structure of capacitor matching, the first intermediate capacitor C0 is arranged at an edge position, with the following advantages: the peripheral capacitance has minimum influence on the device, and the advantages are two: the edge position facilitates the wiring and reduces the parasitic capacitance. The first group of left column capacitors C1, the second group of left column capacitors C2, the third group of left column capacitors C3 and the fourth group of left column capacitors C4 are proportionally arranged on the left side of C0, and the parasitic influence is small due to the arrangement mode, and the parasitic capacitors are increased without the need of left and right crossed routing. The second intermediate capacitor C12 is distributed over the first intermediate capacitor C0 with the shortest parasitic connection. The first right column capacitor C5, the second right column capacitor C6, the third right column capacitor C7, the fourth right column capacitor C8, the fifth right column capacitor C9, the sixth right column capacitor C10 and the grounded right column capacitor C11 are proportionally placed on the right side, wherein the grounded right column capacitor C11 is sensitive and is not placed close to the edge as much as possible, the four capacitors, namely the third right column capacitor C7, the fourth right column capacitor C8, the fifth right column capacitor C9 and the sixth right column capacitor C10, are placed on the rightmost side, the grounded right column capacitor C11 is placed on the right side of the CTOP by using one capacitor alone because the upper plate is grounded, and the first middle capacitor C0 has a small influence on the GND due to the fact that the grounded right column capacitor C11 is parasitic to the GND. DMUMMY module is not filled to first middle electric capacity C0 top, and direct vacancy is arranged down and right side ground connection GND in first middle electric capacity C0 to make parasitic capacitance minimum, through the actual measurement of back emulation, the utility model discloses a SARADC layout structure can effectively promote SARADC's circuit precision. Just the utility model discloses a domain structure only has five elements, and circuit area is little, the lightweight.

In summary, the foregoing embodiments have described in detail different configurations of the sar adc layout structure, and of course, the present invention includes, but is not limited to, the configurations listed in the foregoing embodiments, and any configuration that is transformed based on the configurations provided by the foregoing embodiments is within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims

1. A SARADC layout structure, the outline of SARADC layout structure is that square plane spreads out, and wherein the multi-column capacitance permutation is made up and is formed the capacitor array, its characterized in that includes:

2. The sar adc layout structure of claim 1, wherein the column in which the first intermediate capacitor is located is vacant away from other positions in the edge direction.

3. The sar adc layout structure of claim 1, wherein said sar adc layout structure further comprises one or more second intermediate capacitors, said second intermediate capacitors being in the same column as at least one of said first intermediate capacitors;

4. The sar adc layout structure of claim 3, wherein second ends of each group of the left column capacitors are electrically connected to a switch array, at least one group of the right column capacitors are grounded, and second ends of the remaining groups of the right column capacitors are electrically connected to the switch array, respectively.

5. The SARADC layout structure of claim 4, wherein the right column of capacitors connected to ground is not located in a rightmost column of the capacitor array.

6. The sar adc layout structure of claim 4 or 5, wherein the plurality of left column capacitors comprises a first left column capacitor, a second left column capacitor …, an nth left column capacitor, N being a natural number greater than or equal to 4, which gradually approximate the first intermediate capacitor in sequence, wherein two adjacent left column capacitors satisfy the following condition:

7. The SARADC layout structure of claim 6, wherein the number of the first intermediate capacitors is 2, the number of the second intermediate capacitors is 3,

the number of the first group of left column capacitors is 8;

8. The sar adc layout structure of claim 1, further comprising an isolation array, at least one of four sides of said capacitor array being surrounded by said isolation array.

9. The sar adc layout structure of claim 8, wherein said isolation array comprises a first ground module, a second ground module and a plurality of DUMMY modules, said first ground module being distributed in a right column closest to said first intermediate capacitor and adjacent to a grounded said right column capacitor, said second ground module being distributed in a right side of said plurality of sets of right column capacitors and a bottom end of a plurality of right columns;