CN111262585B - Capacitor and analog-digital converter chip - Google Patents
Capacitor and analog-digital converter chip Download PDFInfo
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- CN111262585B CN111262585B CN202010095886.8A CN202010095886A CN111262585B CN 111262585 B CN111262585 B CN 111262585B CN 202010095886 A CN202010095886 A CN 202010095886A CN 111262585 B CN111262585 B CN 111262585B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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Abstract
The invention provides a capacitor and an analog-digital converter chip, wherein the capacitor is applied to the analog-digital converter chip and comprises an effective capacitor and a redundant capacitor arranged around the effective capacitor, and the effective capacitor comprises a plurality of capacitor units arranged side by side. Each capacitor unit comprises a first electrode and a second electrode. In any one capacitor cell, the number of the first electrodes is one, and the number of the second electrodes is two. The two second electrodes are electrically connected and are respectively arranged on two sides of the first electrode. And a second electrode is shared between any two adjacent capacitor units. By arranging the first electrode and the two second electrodes in one capacitor unit, the first electrode is positioned between the two second electrodes, two capacitors can be formed in one capacitor unit, and the metal side walls of the electrodes are more effectively utilized to form the capacitors. By sharing one second electrode between any two adjacent capacitance units, the area occupied by the capacitor is reduced.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a capacitor and an analog-digital converter chip.
Background
In the field of ADC (Analog to Digital Converter) chip technology, SAR (Successive Approximation) ADCs have the characteristics of low power consumption, small size, high conversion efficiency, and the like. The SAR ADC generally adopts a basic structure of a capacitance scaling DAC (Digital to Analog Converter), and its operation principle is to use a charge principle to redistribute the total charge stored in the capacitor array. In this basic structure, the capacitor is a very important device in the ADC circuit, and this device has a significant influence on the chip area, the speed of the circuit, and the accuracy.
Common capacitor structures in an ADC chip include an MIM (Metal-Insulator-Metal) capacitor, an MOM (Metal-Oxide-Metal) capacitor, and an MOS (Metal-Oxide-Semiconductor) capacitor. The MIM capacitor requires an additional MASK layer during fabrication, which increases the cost. The MOS capacitor is affected by the process and has poor precision, and the MOM capacitor is a more suitable choice.
The basic structure of the present capacitor is as shown in fig. 1, which is composed of a capacitor array 102, wherein the capacitor array 102 includes a fixed ground capacitor 103, a first bit capacitor 104, a second bit capacitor 105, \8230 \ 8230:, from right to left (with reference to the structure shown in fig. 1) to an nth bit capacitor 108. Wherein, N is the digit of ADC, and represents that the number of capacitor units is 2 N Which determines the accuracy of the ADC. The capacitor array 102 comprises a plurality of capacitor units, an upper plate of each capacitor unit is connected to the positive terminal of the comparator 101, and a lower plate of each capacitor unit in the capacitor array 102 is connected to the corresponding switch array 109. The negative terminal of the comparator 101 is connected to ground. One end of the switch array 109 is connected to the corresponding capacitor unit in the capacitor array 102, and the other end can be connected to the corresponding capacitor unit according to different switch configurations and V REF (Reference Voltage), V IN (Input Voltage) or ground.
When a device is configured according to a standard MOM process, as shown in fig. 2, 201 is a PLUS (positive) terminal of a MOM capacitor, and is formed by metal layers provided by a process, and when the device is specifically configured, metal layers such as a first metal layer, a second metal layer, and the like can be selected by self. 202 is the MINUS terminal of the MOM capacitor, which is located in the same metal layer as the metal layer used for the PLUS terminal of the MOM capacitor. The reference numeral 203 denotes a metal connection hole for electrically connecting metal layers of different layers and the same layer or a plate of a capacitor. And when the metal layer is arranged, the corresponding connecting hole is selected according to the metal layer. 205 is the potential ring of the capacitor. And a capacitor is formed between each layer of metal.
The capacitor array of the designed SAR ADC adopts MOM standard capacitor layout as shown in fig. 3, where 301 is the MOM capacitor unit shown in fig. 2, and 2 in total N A capacitor unit. When the capacitor units are arranged specifically, the capacitors with low positions are placed in the center of the layout and are placed according to the common mass center, and the capacitors with high positions are placed in a staggered mode, so that the matching degree can be improved. And 302 is a Dummy (redundant) capacitor which is arranged at the periphery of the whole capacitor array 102 to improve the matching degree. With this layout, enough space 303 must be left between each capacitor unit to satisfy the process rule between metal and via, and to ensure the routing of the connection switch array 109 and the input end of the connection comparator 101.The space 303 needs to be additionally reserved, so that the occupied area of the capacitor is large, the design cost is high, and the miniaturization and integration of the chip are not facilitated.
Disclosure of Invention
The invention provides a capacitor and an analog-digital converter chip, which are used for reducing the occupied area of the capacitor, reducing the design cost and facilitating the miniaturization and integration of the chip.
In a first aspect, the present invention provides a capacitor for use in an analog-to-digital converter chip, the capacitor including an effective capacitance for converting an analog signal into a digital signal, and a redundant capacitance disposed around the effective capacitance, the effective capacitance including a plurality of capacitive units arranged side by side. Each capacitor unit comprises a first electrode and a second electrode. In any one capacitor cell, the number of the first electrodes is one, and the number of the second electrodes is two. The two second electrodes are electrically connected and are respectively arranged on two sides of the first electrode. And a second electrode is shared between any two adjacent capacitor units.
In the above scheme, one first electrode and two second electrodes are arranged in one capacitor unit, and the first electrode is located between the two second electrodes, so that an arrangement mode of two capacitors can be formed in one capacitor unit, and the metal side walls of the electrodes are more effectively utilized to form the capacitors. Through sharing a second electrode between two arbitrary adjacent electric capacity units to need not to reserve extra interval between the electric capacity unit, thereby make the shared area of condenser reduce, reduce design cost, be convenient for the miniaturization and the integration of chip.
In a specific embodiment, in any one capacitor unit, the two second electrodes are electrically connected through one metal connecting rod, so that the two second electrodes are conveniently connected and electrified; the metal connecting rods in any two adjacent capacitor units are fixedly connected, so that the first electrodes in the plurality of capacitor units are positioned on one side, and the plurality of second electrodes are positioned on the other side; and the second electrodes share one electrifying port, so that the second electrodes in the capacitor units can be electrified conveniently during application.
In a specific embodiment, in any one capacitor unit, two second electrodes and a metal connecting rod form an inverted-21274-shaped structure, and a first electrode is positioned in the inverted-21274-shaped structure, so that the two second electrodes and one first electrode form a shape similar to a Chinese character 'shan', and the metal side walls of the electrodes are utilized more effectively to form a capacitor.
In one embodiment, the first electrode and the second electrode are metal rods, which facilitates the arrangement of the first electrode and the second electrode.
In a specific implementation manner, in any one of the capacitor units, a first metal connection hole for electrically connecting with the outside is provided at one end of the first electrode, which is far away from the metal connection rod, and a second metal connection hole for electrically connecting with the outside is provided on the metal connection rod, so that the first metal connection holes in the plurality of capacitor units are located at one side, and the second metal connection holes are located at the other side, and therefore, a space for routing wires is not required to be reserved between the capacitor units, and the area occupied by the capacitor is reduced as much as possible.
In a specific embodiment, in any one capacitor unit, the second metal connection hole is positioned on a symmetrical line of the two second electrodes, so that the consistency of the capacitance in each capacitor unit is maintained.
In one specific embodiment, in any one of the capacitor units, the first electrode is a positive electrode, and the second electrode is a negative electrode, so that the capacitor is electrically connected with an external comparator and a switch.
In one specific embodiment, the plurality of capacitor units comprise a fixed capacitor, a first bit capacitor, a second bit capacitor, \8230 \ 8230;, sequentially to an nth bit capacitor; wherein the fixed capacitor comprises a capacitor unit, and the first bit capacitor comprises 2 0 A second bit capacitor including 2 1 The n-th capacitor comprises 2 n-1 Each capacitor unit (n is a positive integer of 2 or more). Each bit capacitor from the first bit capacitor to the n/2 th bit capacitorThe arrangement mode is as follows: the capacitors with odd number of digits are arranged on one side of the fixed capacitor, and the capacitors with even number of digits are arranged on the other opposite side of the fixed capacitor. The capacitance unit of each bit capacitance from the (n/2 + 1) th bit capacitance to the n th bit capacitance is divided by 2 n/2-1 The capacitor units are divided into at least two groups and are crossly arranged at two sides of the fixed capacitor and the capacitors from the first capacitor to the nth/2 th capacitor with the capacitor units of other capacitors; and at least one group of capacitor units of two capacitors with adjacent digits are arranged in a crossed manner. Through the arrangement mode, the precision of the analog-digital converter chip is improved.
In a specific embodiment, when the first bit capacitor to the n/2 th bit capacitor are arranged, the lower the number of bits, the closer the capacitor is to the fixed capacitor, so as to further improve the precision of the analog-digital converter chip.
In a specific embodiment, the redundant capacitors include two identical sets of first redundant capacitors, and the two sets of first redundant capacitors are disposed on two sides of the effective capacitor along the arrangement direction of the plurality of capacitor units. The redundant capacitors also comprise two groups of same second redundant capacitors, and the two groups of second redundant capacitors are arranged on two sides of the effective capacitors along the arrangement direction perpendicular to the plurality of capacitor units, so that the precision and the matching degree of the analog-digital converter chip are improved.
In one specific embodiment, the sum of the lengths of the first redundant capacitor and the second redundant capacitor is L 1 The sum of the lengths of the first redundant capacitor, the second redundant capacitor and the plurality of capacitor units is L 2 (ii) a Wherein L is 1 ≥5％L 2 . Thereby further improving the matching degree of the analog-digital converter chip.
In one embodiment, the capacitor further includes a shielding layer covering the effective capacitor and the redundant capacitor to improve the anti-interference capability of the plurality of capacitor units and improve the accuracy of the analog-to-digital converter.
In a particular embodiment, the capacitor further comprises a potential ring arranged around the redundant capacitor to meet the respective process standard.
In a second aspect, the present invention further provides an analog-to-digital converter chip, which includes any one of the capacitors described above, so as to reduce an area occupied by the capacitor, improve utilization efficiency of a metal sidewall of an electrode in the capacitor, reduce design cost, and facilitate miniaturization and integration of the chip.
Drawings
Fig. 1 is a schematic structural diagram of a capacitance scaling ADC in the prior art;
FIG. 2 is a schematic diagram of a standard MOM capacitor unit in the prior art;
FIG. 3 is a schematic structural diagram of an ADC capacitor array formed by MOM capacitor units in the prior art;
fig. 4 is a schematic structural diagram of a capacitor unit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a capacitor according to an embodiment of the present invention.
Reference numerals:
10-capacitive cell 11-first electrode 12-second electrode
13-Metal connection rod 111-first Metal connection hole
121-second metal connection hole 20-fixed capacitor 21-first bit capacitor
22-second bit capacitor 23-third bit capacitor 24-fourth bit capacitor
2 n-nth bit capacitor 31-first redundant capacitor 32-second redundant capacitor
40-shield 50-potential ring
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
To facilitate understanding of the capacitor provided in the embodiment of the present invention, an application scenario of the capacitor provided in the embodiment of the present invention is first described, where the capacitor is applied to an analog-to-digital converter chip, and is used for storing charges generated by an analog signal and converting the analog signal into a digital signal in cooperation with a comparator, a switch, a reference voltage, an input voltage, and the like in the analog-to-digital converter chip. The capacitor will be described in detail with reference to the accompanying drawings.
Referring to fig. 4 and 5, a capacitor provided by an embodiment of the present invention includes an effective capacitor for converting an analog signal into a digital signal and a redundant capacitor disposed around the effective capacitor. The effective capacitor includes a plurality of capacitor units 10, the plurality of capacitor units 10 may be disposed on any one metal layer, specifically, a first metal layer, a second metal layer, a third metal layer, and the like in the adc chip, and the specific metal layers may be selected according to the layers provided by the process. One electrode of each capacitor unit 10 is connected to one end of a comparator, and the other electrode of each capacitor unit 10 is selectively connected to a reference voltage, an input voltage or a ground through a switch, so as to store charges generated by an analog signal and convert the analog signal into a digital signal in cooperation with the comparator, the switch, the reference voltage and the like.
In providing each of the capacitor cells 10, referring to fig. 4, each of the capacitor cells 10 includes one first electrode 11 and two second electrodes 12. The two second electrodes 12 are electrically connected, and the two second electrodes 12 are arranged on both sides of the first electrode 11. By arranging the first electrode 11 and the two second electrodes 12 in one capacitor unit 10 and positioning the first electrode 11 between the two second electrodes 12, two capacitor arrangement modes can be formed in one capacitor unit 10, and the metal side walls of the electrodes can be used more effectively to form capacitors.
When the first electrode 11 and the second electrode 12 are specifically disposed, the first electrode 11 and the second electrode 12 may be both metal rods, and specifically, the first electrode 11 and the second electrode 12 may be long metal rods such as, but not limited to, cylinders, prisms, and the like, so as to facilitate the disposition of the first electrode 11 and the second electrode 12 and more efficiently form a capacitor by using metal sidewalls of the electrodes.
In connecting the two second electrodes 12 in each capacitor unit 10, referring to fig. 4, the two second electrodes 12 are electrically connected by one metal connecting rod 13, thereby facilitating connection of the two second electrodes 12 and facilitating energization of the two second electrodes 12. The metal connecting rod 13 may be a long metal rod such as, but not limited to, a cylinder, a prism, etc.
When the two second electrodes 12 and the metal connecting rod 13 are connected, referring to fig. 4, the two second electrodes 12 and the metal connecting rod 13 form a reversed structure in the shape of '21274', and the first electrode 11 is located in the reversed structure in the shape of '21274', so that the two second electrodes 12 and the first electrode 11 form a shape similar to a character 'shan', and the metal side walls of the electrodes are more effectively utilized to form a capacitor. Specifically, the two second electrodes 12 and the metal connecting rod 13 can be integrally processed in a pouring manner, so that the manufacturing is facilitated. It should be understood that the shape of the two second electrodes 12 and the metal connecting rod 13 is not limited to the inverted letter "21274" as shown in fig. 4, and other arrangements capable of electrically connecting the two second electrodes 12 may be adopted.
When specifically arranging a plurality of electric capacity units 10, refer to fig. 5, a plurality of electric capacity units 10 are arranged side by side, and share a second electrode 12 between two arbitrary adjacent electric capacity units 10 to need not to reserve extra interval between electric capacity unit 10, thereby make the shared area of condenser reduce, reduce design cost, be convenient for the miniaturization and the integration of chip.
In a specific arrangement, referring to fig. 5, the metal connecting rods 13 in any two adjacent capacitor units 10 are fixedly connected, and specifically, the metal connecting rods 13 in any two adjacent capacitor units 10 can be made into an integral structure, which is convenient for manufacturing. When the metal connecting rods 13 in any two adjacent capacitor units 10 are fixedly connected, the first electrodes 11 in the plurality of capacitor units 10 are located on one side, and the second electrodes 12 are located on the other side, specifically, as shown in fig. 5, the first electrodes 11 are located on the upper side in fig. 5, and the second electrodes 12 are located on the lower side in fig. 5, so that the first electrodes 11 and the second electrodes 12 are conveniently electrified. And the second electrodes 12 share one power-on port, so that the second electrodes 12 in the capacitor units 10 can be powered on conveniently in application.
When the metal connecting rods 13 in the plurality of capacitor units 10 are specifically connected, referring to fig. 5, the metal connecting rods 13 in the plurality of capacitor units 10 may be positioned on the same straight line, so as to facilitate electrical connection of the second electrodes 12 in the plurality of capacitor units 10, and reduce the length of the metal connecting rods 13, thereby reducing the area occupied by the capacitor. It should be understood that the arrangement of the metal connecting rods 13 is not limited to the arrangement on the same straight line shown above, and other arrangements capable of electrically connecting the second electrodes 12 of two adjacent capacitor units 10 may be adopted.
When the first electrode 11 and the second electrode 12 are electrically connected to the outside, referring to fig. 4 and 5, in any one of the capacitor units 10, a first metal connection hole 111 for electrically connecting to the outside is disposed at an end of the first electrode 11 away from the metal connection rod 13, so that the first metal connection holes 111 in the plurality of capacitor units 10 are located at one side, thereby facilitating the electrical connection between the first electrode 11 and the outside. The metal connecting rod 13 is provided with a second metal connecting hole 121 for electrically connecting with the outside, and the second metal connecting hole 121 is located at the other side, so that a space for wiring does not need to be reserved between the capacitor units 10, and the occupied area of the capacitor is reduced as much as possible. The first metal connection hole 111 and the second metal connection hole 121 are disposed in a manner of through holes, blind holes, and other hole metal holes that can be electrically connected in the prior art.
When the first metal connection hole 111 is formed, the first metal connection hole 111 may be formed at an end of the first electrode 11 far from the metal connection rod 13, so that the first metal connection hole 111 is located at an outer side of the capacitor, thereby facilitating electrical connection between the first electrode 11 and the outside. It should be understood that the position of the first metal connection hole 111 is not limited to the position shown in fig. 4 disposed at the end of the first electrode 11, and may be disposed at any position on the first electrode 11 as long as the first electrode 11 can be electrically connected to the outside. When the second metal connection hole 121 is provided, referring to fig. 4, the second metal connection hole 121 may be provided at any position of the metal connection rod 13 between the two second electrodes 12 of the capacitor unit 10 as long as the two second electrodes 12 can be electrified through the second metal connection hole 121. In a preferred arrangement, the second metal connection hole 121 may not be provided at a position where the second electrode 12 intersects the metal connection rod 13, thereby facilitating preservation of the uniformity of capacitance in each capacitive cell 10. The optimum arrangement is that the second metal connection holes 121 are arranged on the symmetry line of the two second electrodes 12, which further maintains the uniformity of capacitance in each capacitive unit 10.
When the first electrode 11 and the second electrode 12 of the capacitor are electrically connected to the outside, in any one of the capacitor units 10, the first electrode 11 may be a positive electrode, and the second electrode 12 is a negative electrode opposite to the first electrode 11, so that the capacitor is electrically connected to an external comparator and a switch. It should be understood that the first electrode 11 is not limited to be disposed as a positive electrode, and the first electrode 11 may be disposed as a negative electrode, in which case the second electrode 12 is a negative electrode opposite to the electrical direction of the first electrode 11.
In the specific connection of the plurality of capacitor cells 10, referring to fig. 5, the plurality of capacitor cells 10 include a fixed capacitor 20 for grounding, a first bit capacitor 21, a second bit capacitor 22, \8230 \ 8230;, and sequentially an nth bit capacitor 2n. Wherein n is the digit of the analog-digital converter chip, and represents that the number of the capacitor units 10 is 2 n Specifically, n may be any number greater than 1, such as 2, 3, 4, 8, 12, 16, 20, and the like.
In the case of disposing the fixed capacitor 20 and each bit capacitor, referring to fig. 5, the fixed capacitor 20 includes a capacitor unit 10, and the first bit capacitor 21 includes 2 0 A (i.e. one) capacitor unit 10, the second bit capacitor 22 comprising 2 1 The n-th capacitor 2n includes 2 (i.e., two) capacitor units 10, \8230;) 2n n-1 A capacitor unit 10.
When the fixed capacitors 20 and the capacitors are arranged, the capacitors from the first bit capacitor to the n/2 th bit capacitor are arranged in the following manner: the capacitors with odd number of digits are arranged on one side of the fixed capacitor, and the capacitors with even number of digits are arranged on the other opposite side of the fixed capacitor. In the specific arrangement, the capacitance with the lower number of bits may be closer to the fixed capacitance, and other arrangements may be adopted.
The capacitance unit of each bit of capacitance from (n/2 + 1) th bit of capacitance to n th bit of capacitance is calculated by 2 n/2-1 The capacitor units are divided into at least two groupsThe capacitor units and the capacitor units of other bit capacitors are arranged on two sides of the fixed capacitor and the capacitors from the first bit capacitor to the nth/2 th bit capacitor in a crossed manner; and at least one group of capacitor units of two capacitors with adjacent digits are arranged in a crossed manner. Through the arrangement mode, the precision of the analog-digital converter chip is improved.
The following description will be given by taking n =8 as an example. When n =8, n/2=4,2 n/2-1 And (8). As shown in fig. 5, the capacitors with odd number of bits (the first bit capacitor 21 and the third bit capacitor 23) are arranged on the left side of the fixed capacitor 20, and the capacitors with even number of bits (the second bit capacitor 22 and the fourth bit capacitor 24) are arranged on the right side of the fixed capacitor 20. In arranging the first to n/2 th bit capacitances specifically, the capacitance with the lower bit number may be made closer to the fixed capacitance 20. Specifically, referring to fig. 5, the number of the capacitor cells 10 in the first bit capacitor 21 is 1, and the capacitor cells are arranged on the left side of the fixed capacitor 20. The number of the capacitor units 10 in the second bit capacitor 22 is 2, that is, the second bit capacitor 22 is composed of two capacitor units 10, and the two capacitor units 10 of the second bit capacitor 22 are arranged side by side and are disposed on the right side of the fixed capacitor 20. The number of the capacitor units 10 in the third bit capacitor 23 is 4, that is, the third bit capacitor 23 is composed of 4 capacitor units 10, and the 4 capacitor units 10 of the third bit capacitor 23 are arranged side by side and on the left side of the first bit capacitor. The number of the capacitor units 10 in the fourth capacitor 24 is 4, that is, the fourth capacitor 23 is composed of 8 capacitor units 10, and the 8 capacitor units 10 of the fourth capacitor 23 are arranged side by side and on the right side of the second capacitor. Therefore, the capacitance deviation of each bit of capacitance and the adjacent bit is minimized, the total capacitance mismatch is reduced, and the influence of the capacitance error of each bit of capacitance on the precision of the capacitor is dispersed, so that the precision of the analog-digital converter chip is further improved. It should be understood that, when specifically arranging the first bit capacitors 22 to the n/2 th bit capacitors, the way of arranging the capacitors with lower number of bits closer to the fixed capacitor 20 is not limited to the above-described way, and other ways may be adopted, for example, the capacitors with higher number of bits may be arranged closer to the fixed capacitor 20, and the capacitors of the respective bits may be arranged in a mixed way. In addition, it should be understood that the capacitor cell 10 in the first bit capacitor 21The arrangement of (2) is not limited to the arrangement in the vicinity of the fixed capacitor 20, and capacitors of other bits may be provided between the first bit capacitor 21 and the fixed capacitor 20. The arrangement of the second bit capacitors 22 to the n/2 nd bit capacitors 2n is not limited to the above arrangement, and other arrangements may be adopted, for example, each of the second bit capacitors 22 to the n/2 nd bit capacitors may be arranged on one side of the fixed capacitor 20.
When the (n/2 + 1) th bit capacitance is arranged to the nth bit capacitance, n =8 is also taken as an example for explanation. The number of the capacitor units 10 in the fifth bit capacitor is 16, that is, the fifth bit capacitor is composed of 16 capacitor units 10, and the number is 2 n/2-1 (n =8, 2 n/2-1 = 8) capacitor units are divided into one group, and 16 capacitor units 10 of the fifth capacitor are divided into two groups, each group having 8 capacitor units 10; one group of the capacitor cells 10 is disposed on the right side of the fixed capacitor 20, and the other group of the capacitor cells 10 is disposed on the left side of the fixed capacitor 20. In a specific arrangement, two sets of capacitor units 10 in the fifth bit capacitor may be arranged on two sides of the third bit capacitor 23 and the fourth bit capacitor 24, specifically, one set of capacitor units 10 may be arranged on the right side of the fourth bit capacitor 24, and the other set of capacitor units 10 may be arranged on the left side of the third bit capacitor 23.
The number of the capacitor units 10 in the sixth bit capacitor is 32, and is 2 n/2-1 (n =8, 2 n/2-1 = 8) capacitor units are grouped, and the 32 capacitor units 10 of the sixth-bit capacitor are equally divided into 4 groups. The number of the capacitor units 10 in the seventh capacitor is 64, and is 2 n/2-1 (n =8, 2 n/2-1 = 8) capacitor units are grouped, and the 64 capacitor units 10 of the seventh capacitor are equally divided into 8 groups. The number of the capacitor units 10 in the eighth bit capacitor is 128 and is 2 n/2-1 (n =8, 2 n/2-1 = 8) capacitor elements are grouped, and 128 capacitor elements 10 of the eighth capacitor are equally divided into 16 groups. During arrangement, the two groups of capacitor units 10 in the sixth capacitor can be arranged on two sides of the fifth capacitor first, and then the two groups of capacitor units 10 in the seventh capacitor are arranged; then another two groups of capacitor units 10 in the sixth capacitor are arranged; then two of the seventh capacitors are arrangedA group capacitance unit 10; then two groups of capacitor units in the eighth capacitor are arranged, \8230;. In short, the number of the capacitor units 10 in each capacitor group 10 in each capacitor having a non-highest bit number is not more than 8, and if the number of the capacitor units exceeds 8, the capacitor units 10 in other capacitor groups in the bit are arranged to intersect with the capacitor units 10 in other adjacent bits. The capacitor with the highest bit number and the capacitor with the second highest bit number are at least arranged in a group of capacitor units 10 in a crossing way. The first bit capacitor to the nth bit capacitor 2n are arranged according to the arrangement mode so as to improve the precision of the analog-digital converter chip.
In addition, in the capacitor unit 10 shown in fig. 2 in the related art, the number of branches of the mom capacitor unit 10 is a fixed number, which lacks flexibility. The scheme provided by the invention can increase or reduce the number of the capacitor units 10 according to actual needs, thereby improving the flexibility.
Referring to fig. 5, the redundant capacitors provided by the embodiment of the present invention may include two identical sets of first redundant capacitors 31, and the two sets of first redundant capacitors 31 are disposed on two sides of the effective capacitor along the arrangement direction of the plurality of capacitor units 10, i.e. on the outermost side of the plurality of capacitor units 10. In a specific arrangement, each group of the first redundant capacitors 31 includes at least one first electrode 11 and at least one second electrode 12, and the second electrode 12 of each group of the first redundant capacitors 31 is insulated from the second electrodes 12 of the plurality of capacitor units 10. The first redundant capacitor 31 may be disposed in the same manner as the capacitor unit 10, and the detailed manner of disposing refers to the above description, which is not repeated herein. By arranging two groups of first redundant capacitors 31 on the outermost sides of the plurality of capacitor units 10, the gradient effect in manufacturing is improved, the difference of boundary environments is reduced, and the precision and the matching degree of an analog-digital converter chip are improved.
With continued reference to fig. 5, the redundant capacitors may further include two identical sets of second redundant capacitors 32, and the two sets of second redundant capacitors 32 are disposed on two sides of the effective capacitor along a direction perpendicular to the arrangement direction of the plurality of capacitor units 10. Taking fig. 5 as an example, one set of the second redundant capacitors 32 is disposed above the plurality of capacitor units 10, and the other set of the second redundant power sources is disposed below the plurality of capacitor units 10. The upper and lower environments of the plurality of capacitor units 10 are made to be consistent, thereby improving the accuracy and matching degree of the analog-digital converter chip. When the second redundant capacitor 32 is specifically provided, the second redundant capacitor 32 may be provided in the same manner as the first redundant capacitor 31, or may be provided in a manner of a redundant capacitor commonly used in the prior art.
When the first redundant capacitor 31 and the second redundant capacitor 32 are specifically set to have different sizes, the sum of the lengths of the first redundant capacitor 31 and the second redundant capacitor 32 is L 1 The sum of the lengths of the first redundant capacitor 31, the second redundant capacitor 32 and the plurality of capacitor units 10 is L 2 (ii) a Wherein L is 1 ≥5％L 2 . Specifically, L may be set 1 To 5% of L 2 、6％L 2 、7％L 2 、8％L 2 、9％L 2 Equal to or greater than 5% 2 Thereby further improving the matching degree of the analog-digital converter chip. The lengths of the first redundant capacitor 31 and the second redundant capacitor 32 refer to the sum of the lengths of the effective capacitors of the first redundant capacitor 31 and the second redundant capacitor 32 after all the capacitor units 10 in the digital-to-analog converter chip are placed; the sum of the lengths of the first redundant capacitor 31, the second redundant capacitor 32 and the plurality of capacitor units 10 refers to the sum of the lengths of the first redundant capacitor 31, the second redundant capacitor 32 and the effective capacitors of the plurality of capacitor units 10 after all the capacitor units 10 in the digital-to-analog converter chip are placed.
Referring to fig. 5, the capacitor provided in the embodiment of the present invention may further include a shielding layer 40 covering the effective capacitor and the redundant capacitor, so as to improve the interference immunity of the plurality of capacitor units 10 and improve the accuracy of the analog-to-digital converter. In a specific arrangement, a higher metal layer may be used as the shielding layer 40, and disposed above and below the effective capacitance and the redundant capacitance (referring to the capacitor shown in fig. 5), so as to facilitate the arrangement.
With continued reference to fig. 5, the capacitor provided by the embodiment of the invention may further include a potential ring 50 disposed around the redundant capacitor to meet the corresponding process standard. As shown in fig. 5, a metal connection hole for electrically connecting with other metal layers is provided on the potential ring 50 in a conventional manner in the related art.
In addition, the embodiment of the invention also provides an analog-digital converter chip which comprises any one of the capacitors, so that the occupied area of the capacitor is reduced, the utilization efficiency of the metal side wall of the electrode in the capacitor is improved, the design cost is reduced, and the miniaturization and integration of the chip are facilitated.
Claims (10)
1. A capacitor for use in an analog-to-digital converter chip, comprising:
an effective capacitor for converting an analog signal to a digital signal;
a redundant capacitor disposed around the effective capacitor;
the effective capacitor comprises a plurality of capacitor units arranged side by side, and each capacitor unit comprises a first electrode and a second electrode; in any one capacitor unit, the number of the first electrodes is one, and the number of the second electrodes is two; the two second electrodes are electrically connected and are respectively arranged at two sides of the first electrode;
any two adjacent capacitor units share one second electrode;
the plurality of capacitor units comprise fixed capacitors, first bit capacitors, second bit capacitors, \8230 \ 8230;, and capacitors sequentially reaching the nth bit; wherein the fixed capacitor comprises a capacitor unit, and the first bit capacitor comprises 2 0 A capacitor unit, the second bit capacitor including 2 1 The n-th capacitor comprises 2 n-1 A plurality of capacitor units; n is a positive integer greater than or equal to 2;
the arrangement mode of each capacitor from the first bit capacitor to the n/2 th bit capacitor is as follows: capacitors with odd digits are arranged on one side of the fixed capacitor, and capacitors with even digits are arranged on the other opposite side of the fixed capacitor;
capacitance at n/2+1 bit to the n bitCapacitance unit of each bit of capacitance in the capacitor with 2 n/2-1 The capacitor units are divided into at least two groups and are arranged at two sides of the fixed capacitor, the first bit capacitor and the (n/2) th bit capacitor in a crossed manner with the capacitor units of other bit capacitors; and at least one group of capacitor units of two capacitors with adjacent digits are arranged in a crossed manner.
2. The capacitor of claim 1, wherein in any one of the capacitor cells, the two second electrodes are electrically connected by a metal connecting rod;
and the metal connecting rods in any two adjacent capacitor units are fixedly connected.
3. The capacitor of claim 2, wherein in any one of the capacitive cells, the two second electrodes and the metal connecting rod form an inverted v-21274.
4. The capacitor as claimed in claim 3, wherein in any one of the capacitor cells, a first metal connection hole for electrical connection with the outside is provided at an end of the first electrode remote from the metal connection rod, and a second metal connection hole for electrical connection with the outside is provided at the metal connection rod.
5. The capacitor of claim 4, wherein in any one of the capacitive cells, the second metal connection hole is located on a line of symmetry of the two second electrodes.
6. The capacitor of claim 1, wherein the first through n/2 th bit capacitances are arranged such that a lower bit capacitance is closer to the fixed capacitance.
7. The capacitor of any one of claims 1-5, wherein the redundant capacitance comprises:
two groups of first redundant capacitors are arranged on two sides of the effective capacitor along the arrangement direction of the plurality of capacitor units, and the two groups of first redundant capacitors are the same;
and two groups of second redundant capacitors are arranged on two sides of the effective capacitor along the direction vertical to the arrangement direction of the plurality of capacitor units, and the two groups of second redundant capacitors are the same.
8. The capacitor of claim 7, wherein a sum of lengths of the first and second redundant capacitances is L 1 The sum of the lengths of the first redundant capacitor, the second redundant capacitor and the plurality of capacitor units is L 2 (ii) a Wherein L is 1 ≥5％L 2 。
9. The capacitor of claim 1, further comprising a shield layer overlying the effective and redundant capacitances.
10. An analog-to-digital converter chip comprising a capacitor according to any one of claims 1 to 9.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010095886.8A CN111262585B (en) | 2020-02-14 | 2020-02-14 | Capacitor and analog-digital converter chip |
| KR1020227019681A KR20220098781A (en) | 2020-02-14 | 2020-07-28 | Capacitor and Analog-to-Digital Converter Chip |
| PCT/CN2020/105103 WO2021159671A1 (en) | 2020-02-14 | 2020-07-28 | Capacitor and analog-to-digital converter chip |
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| CN202010095886.8A CN111262585B (en) | 2020-02-14 | 2020-02-14 | Capacitor and analog-digital converter chip |
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| KR (1) | KR20220098781A (en) |
| CN (1) | CN111262585B (en) |
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| CN111262585B (en) * | 2020-02-14 | 2023-03-28 | 深圳市紫光同创电子有限公司 | Capacitor and analog-digital converter chip |
| CN114582860B (en) * | 2022-05-05 | 2022-08-23 | 苏州领慧立芯科技有限公司 | Many electric capacity matching formula MOM condenser |
| CN114937557B (en) * | 2022-05-26 | 2024-06-11 | 北京奕斯伟计算技术股份有限公司 | Capacitor array module |
| CN115048899B (en) * | 2022-08-11 | 2023-01-03 | 北京智芯半导体科技有限公司 | Circuit structure of analog-to-digital converter, analog-to-digital converter and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1953181A (en) * | 2005-10-21 | 2007-04-25 | 松下电器产业株式会社 | Analog-digital converter |
| CN106464264A (en) * | 2015-03-04 | 2017-02-22 | 索尼公司 | Analog-digital converter, solid-state imaging device, and electronic apparatus |
| JP2017076829A (en) * | 2017-02-07 | 2017-04-20 | 株式会社ソシオネクスト | Capacitive element, capacitance array and a/d converter |
| CN107633128A (en) * | 2017-09-15 | 2018-01-26 | 北京华大九天软件有限公司 | The layout and Wiring method of MOM capacitor, MOM capacitor array and MOM capacitor array |
| CN108257952A (en) * | 2018-01-16 | 2018-07-06 | 北京智芯微电子科技有限公司 | The mos capacitance domain structure in parallel with MOM capacitor |
| CN109037211A (en) * | 2017-06-12 | 2018-12-18 | 扬智科技股份有限公司 | Capacitor array structure |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010140972A (en) * | 2008-12-09 | 2010-06-24 | Renesas Electronics Corp | Semiconductor device |
| CN103367308A (en) * | 2012-03-31 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Metal-oxide-metal capacitor |
| JP2014120615A (en) * | 2012-12-17 | 2014-06-30 | Fujitsu Semiconductor Ltd | Capacity element, capacity array, and a/d converter |
| CN108198802A (en) * | 2017-12-28 | 2018-06-22 | 上海华力微电子有限公司 | Capacitor |
| CN109755181A (en) * | 2019-01-22 | 2019-05-14 | 苏州华太电子技术有限公司 | MIM capacitor based on Dummy structure |
| CN111262585B (en) * | 2020-02-14 | 2023-03-28 | 深圳市紫光同创电子有限公司 | Capacitor and analog-digital converter chip |
-
2020
- 2020-02-14 CN CN202010095886.8A patent/CN111262585B/en active Active
- 2020-07-28 KR KR1020227019681A patent/KR20220098781A/en unknown
- 2020-07-28 WO PCT/CN2020/105103 patent/WO2021159671A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1953181A (en) * | 2005-10-21 | 2007-04-25 | 松下电器产业株式会社 | Analog-digital converter |
| CN106464264A (en) * | 2015-03-04 | 2017-02-22 | 索尼公司 | Analog-digital converter, solid-state imaging device, and electronic apparatus |
| JP2017076829A (en) * | 2017-02-07 | 2017-04-20 | 株式会社ソシオネクスト | Capacitive element, capacitance array and a/d converter |
| CN109037211A (en) * | 2017-06-12 | 2018-12-18 | 扬智科技股份有限公司 | Capacitor array structure |
| CN107633128A (en) * | 2017-09-15 | 2018-01-26 | 北京华大九天软件有限公司 | The layout and Wiring method of MOM capacitor, MOM capacitor array and MOM capacitor array |
| CN108257952A (en) * | 2018-01-16 | 2018-07-06 | 北京智芯微电子科技有限公司 | The mos capacitance domain structure in parallel with MOM capacitor |
Non-Patent Citations (1)
| Title |
|---|
| 10位10MS/s全电容SAR ADC的设计;宁可庆 等;《微电子学与计算机》;微电子学与计算机;第33卷(第1期);第135-139页 * |
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| KR20220098781A (en) | 2022-07-12 |
| CN111262585A (en) | 2020-06-09 |
| WO2021159671A1 (en) | 2021-08-19 |
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