CN108198802A - Capacitor - Google Patents

Abstract

The present invention provides a capacitor, the capacitor comprising: a substrate; at least one electrode layer located on the substrate, the electrode layer comprising: a first pole plate and a second pole plate, the first pole Both plates and the second pole plate are in an interdigitated structure and are relatively staggered, the first pole plate is used to connect the common mode voltage, and the second pole plate is used to connect the reference voltage; the conductive layer is located on the On the substrate, the conductive layer can generate parasitic capacitance with the first plate, and the conductive layer is connected to the second plate. In the present invention, by adding a conductive layer, the conductive layer can generate parasitic capacitance with the first pole plate, and block the parasitic capacitance generated between the original first pole plate and the adjacent layer; the conductive layer is connected with the second pole plate, and the The parasitic capacitance is introduced to the second plate, which ultimately reduces the parasitic capacitance of the first plate and improves the linearity of the ADC (analog-to-digital converter) including the capacitor.

Description

capacitor

technical field

The invention relates to the field of integrated circuits, in particular to a capacitor.

Background technique

The type of capacitor commonly used in the CMOS process of integrated circuit manufacturing is a MOM (metal-oxide-metal) capacitor with an interdigitated structure composed of electrode layers. The capacitance formed between adjacent layers becomes a parasitic capacitance. Fig. 1 is the capacitor structure of prior art, and this capacitor 100 is mainly made up of the first pole plate 121 of an interdigitated structure and the second pole plate 122 of an interdigitated structure, and the forked finger of two pole plates inserts the gap of the other side, Capacitance between fingers in the same layer is utilized, but parasitic capacitance is also generated between adjacent layers. In ADC (Analog-to-Digital Converter) design, usually the second plate 122 is connected to the reference voltage or ground through a switch, the first plate 121 is connected to the common mode voltage, and the parasitic capacitance Cpu from the first plate 121 to the substrate will participate in the charge transfer. Redistribution, thereby affecting the linearity of the ADC (analog-to-digital converter); while the parasitic capacitance Cpd of the second plate 122 has no effect on charge distribution, so it is necessary to reduce the parasitic capacitance of the first plate 121 to reduce the linearity of the ADC. degree of influence.

Contents of the invention

The object of the present invention is to provide a capacitor capable of reducing the parasitic capacitance of the first plate.

In order to achieve the above object, the present invention provides a capacitor comprising:

Substrate;

At least one electrode layer is located on the substrate, the electrode layer includes: a first pole plate and a second pole plate, the first pole plate and the second pole plate are interdigitated and relatively staggered Arranged, the first pole plate is used to connect the common mode voltage, and the second pole plate is used to connect the reference voltage;

The conductive layer is located on the substrate, the conductive layer can generate parasitic capacitance with the first plate, and the conductive layer is connected to the second plate.

Optionally, in the capacitor, the number of the conductive layer is multiple layers, at least one layer of the conductive layer is formed above and below the electrode layer, and the conductive layer is at least partially facing the first plate.

Optionally, in the capacitor, the number of the electrode layers is n layers, and the number of the conductive layers is at least n+1 layers, wherein n is a natural number.

Optionally, in the capacitor, the conductive layer has an interdigitated structure, the number of fingers of the conductive layer is the same as that of the first plate, and the number of fingers of the conductive layer is the same as that of the first plate. The plates are right up.

Optionally, in the capacitor, the capacitor further includes a connection hole, and the conductive layer is connected to the second plate through the connection hole.

Optionally, in the capacitor, there are multiple connection holes.

Optionally, in the capacitor, the material of the conductive layer is selected from metal or polysilicon.

Optionally, in the capacitor, the material of the electrode layer is selected from metals.

Optionally, in the capacitor, the capacitor also includes:

a first insulating layer, the first insulating layer is located on the substrate, and the electrode layer is located in the first insulating layer;

A second insulating layer, the second insulating layer is located on the substrate, the conductive layer is located in the second insulating layer, and the conductive layer passes through the second insulating layer or the first insulating layer insulated from the electrode layer.

In the capacitor provided by the present invention, by adding a conductive layer, the conductive layer can generate parasitic capacitance with the first pole plate, blocking the parasitic capacitance generated between the original first pole plate and the adjacent layer; The two plates are connected to lead the parasitic capacitance to the second plate, finally reducing the parasitic capacitance of the first plate and improving the linearity of the ADC (analog-to-digital converter) including the capacitor.

Description of drawings

Fig. 1 is the top view of prior art capacitor;

Fig. 2 is a top view of a capacitor according to Embodiment 1 of the present invention;

Fig. 3 is a sectional view of a capacitor according to an embodiment of the present invention at line A of Fig. 2;

Fig. 4 is a cross-sectional view of a capacitor at line B in Fig. 2 according to an embodiment of the present invention;

Fig. 5 is the cross-sectional view of the capacitor of the second embodiment of the present invention;

Fig. 6 is the SAR type ADC circuit of the embodiment of the present invention;

In the figure: 121-first pole plate, 122-second pole plate, 200-capacitor, 210-substrate, 220-electrode layer, 221-first pole plate, 222-second pole plate, 230-conductive layer, 231-first conductive layer, 232-second conductive layer, 241-first connection hole, 242-second connection hole, 310-substrate, 320-electrode layer, 321-first electrode layer, 322-second electrode layer, 330-conductive layer, 331-first conductive layer, 332 second conductive layer, 333-third conductive layer, MOM-capacitor, S1-first switch, S2-second switch, S3-third switch, VIN -Input voltage, VREF-reference voltage, GND-ground, SUB-substrate, Cpu-parasitic capacitance from the first plate to the substrate, Cpd-parasitic capacitance from the second plate to the substrate.

Detailed ways

The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[Example 1]

Referring to Fig. 2, Fig. 3 and Fig. 4, in order to reduce the parasitic capacitance of the first pole plate 221 (usually also referred to as the upper pole plate) of the capacitor 200, improve the linearity of the SAR type ADC comprising the capacitor 200, the present invention implements An example provides a capacitor 200, including: a substrate 210; at least one electrode layer 220, located on the substrate 210, the electrode layer 220 includes: a first plate 221 and a second plate 222, the Both the first pole plate 221 and the second pole plate 222 are in an interdigitated structure and relatively staggered, the first pole plate 221 is used to connect the common mode voltage, and the second pole plate 222 is used to connect the reference voltage a conductive layer 230 located on the substrate 210 , the conductive layer 230 can generate parasitic capacitance with the first plate 221 , and the conductive layer 230 is connected to the second plate 222 .

Preferably, the number of the conductive layer 230 is multiple layers, at least one layer of the conductive layer 230 is formed above and below the electrode layer 220, and the conductive layer 230 is at least partially facing the first plate 221. In this embodiment, the first pole plate 221 has an interdigitated structure, and the first conductive layer 231 added below it may also have an interdigitated structure. The first conductive layer 231 and the first pole plate In the case where part of the area of 221 faces directly, parasitic capacitance will be generated between the first plate 221 and the first conductive layer 231 . Blocking the parasitic capacitance between the first plate 221 and the substrate 210 means converting the original parasitic capacitance between the first plate 221 and the substrate 210 into the parasitic capacitance between the first plate 221 and the first conductive layer 231 . Similarly, the first pole plate 221 and the second conductive layer 232 are at least partially facing each other, and a parasitic capacitance will be generated between the first pole plate 221 and the second conductive layer 232, which blocks the first pole plate 221 from other adjacent layers. The parasitic capacitance is converted into the parasitic capacitance between the first plate 221 and the second conductive layer 232 . Preferably, the first pole plate 221 may be completely opposite to the first conductive layer 231 and the second conductive layer 232 .

Preferably, the number of the electrode layers 220 is n layers, and the number of the conductive layers 230 is at least n+1 layers, wherein n is a natural number. For example, when the electrode layer 220 is one layer, there is a conductive layer 230 above and below the electrode layer 220 respectively, and the number of the conductive layers 230 is two. In other embodiments of the present application, when the electrode layer 220 is one layer, the conductive layer 230 may also be more layers, such as three layers, wherein two conductive layers may be located below the electrode layer 220, and are respectively partially facing the electrode layer 220 , and another conductive layer is located on the electrode layer 220 and at least partially facing the electrode layer 220 .

In the first embodiment, the conductive layer 220 has an interdigitated structure, and the number of fingers of the conductive layer 220 is the same as that of the first pole plate 221. Board 221 is facing. The conductive layer 220 may also have other shapes besides the shape of the interdigitated structure. For example, the shape of the conductive layer 230 may be a whole sheet.

Further, the capacitor further includes a connection hole, and the conductive layer 230 is connected to the second plate 222 through the connection hole. The parasitic capacitance on the conductive layer 230 is led to the second plate 222 through the connection hole. In this embodiment, the first conductive layer 231 is communicated with the second pole plate 222 through the first connection hole 241, and the capacitance on the first conductive layer 231 can be led to the second pole plate 222; The second conductive layer 232 and the second polar plate 222 lead the parasitic capacitance on the second conductive layer 232 to the second polar plate 222 . Therefore, the parasitic capacitance on the first plate 221 is reduced.

Further, in the capacitor 200, the number of the connection holes is multiple, the multiple connection holes can improve the connection reliability between the conductive layer 231 and the second plate 222, and the The connection reliability between the conductive layer 232 and the second electrode plate 222 is improved. Here, the number of the first connection hole 241 and the number of the second connection hole 242 are plural.

In the first embodiment, the material of the conductive layer 230 is selected from metal or polysilicon. When the capacitor 200 has only one electrode layer 220, in the capacitor 200 of the first embodiment, the first conductive layer 231 is located between the substrate 210 and the first plate 221, at this time, the material of the first conductive layer 231 is preferably polysilicon.

Preferably, the material of the electrode layer 220 is selected from metals. The electrode layer 220 of the capacitor 200 is a conductor, and metal is a good conductive material, so the material of the electrode layer 220 is preferably metal.

Further, the capacitor 200 further includes: a first insulating layer 251, the first insulating layer 251 is located on the substrate 210, the electrode layer 220 is located in the first insulating layer 251; a second insulating layer 252, the second insulating layer 252 is located on the substrate 210, the conductive layer 230 is located in the second insulating layer 252, and the conductive layer 230 passes through the second insulating layer 252 or the first An insulating layer 251 is insulated from the electrode layer 220 . In the embodiment of the present application, the number of layers of the second insulating layer 252 is two layers, which are divided into the lower part and the upper part of the first insulating layer 251, wherein the first conductive layer is formed in one second insulating layer 252. layer 231 , another second insulating layer 252 forms a second conductive layer 232 .

In the first embodiment, the second insulating layer 252 can be formed on a semiconductor substrate 210 first, the second insulating layer 252 is etched to form a trench, and metal is filled in the trench to form a first conductive layer. 231; Next, form the first insulating layer 251 on the second insulating layer 252, and form the first groove representing the shape of the first pole plate 221 and the first groove representing the shape of the second pole plate 222 in the first insulating layer 251. shape of the second groove, filling the first groove and the second groove with metal, thereby forming the first pole plate 221 and the second pole plate 222; then, forming a layer of the first pole plate 222 in the first insulating layer 251 again second insulating layer 252 , and form a trench representing the shape of the second conductive layer 232 in the second insulating layer 252 , and fill the trench with metal to form the second conductive layer 232 .

Next, further explanation will be made according to FIG. 6. FIG. 6 is a circuit connection mode including a capacitor 200. The second plate (lower plate) of the capacitor 200 is connected to the input voltage VIN through the first switch S1 or connected to the reference voltage through the second switch S2. The voltage VREF is grounded to GND through the third switch S3, and the first plate (upper plate) of the capacitor is connected to the common-mode voltage VCM ⁻ . Finally, the measured value of the capacitor 200 in this embodiment is compared with the value of the capacitor 100 in the prior art as shown in Table 1 below.

Table 1

The capacitor of this example existing capacitor cpu 2.79fF 11.4fF Cpd 34.8fF 10.7fF MOM 534.8fF 519.0fF

In Table 1, the parasitic capacitance Cpu from the upper plate to the substrate SUB in the MOM capacitor commonly used in the prior art is 11.4fF, while the parasitic capacitance Cpu from the upper plate to the substrate in this embodiment is 2.79fF, and the upper plate in this embodiment The parasitic capacitance from the pole plate to the substrate SUB is reduced to about 1/4 compared with the parasitic capacitance from the upper plate to the substrate in the capacitor commonly used in the prior art, and finally the influence of the parasitic capacitance on the linearity of the SAR ADC is reduced to about 1/4 4.

[Example 2]

Referring to FIG. 5 , another capacitor 300 is provided in the second embodiment, the number of electrode layers 320 is 2 layers, including a first electrode layer 321 and a second electrode layer 322 respectively; the number of conductive layers 330 is set to 3 layers , respectively comprising a first conductive layer 331 , a second conductive layer 332 and a third conductive layer 333 . The first conductive layer 331 is located on the substrate 310 and below the first electrode layer 321 , and the material of the first conductive layer 331 is preferably polysilicon material. The second conductive layer 332 is located below the second electrode layer 322 and above the first electrode layer 321, that is, the second conductive layer 332 is located between the first electrode layer 321 and the second electrode layer 322, and the third conductive layer 333 is located at the first electrode layer 321. above the second electrode layer 322 . Here, the first conductive layer 331 may partially or completely face the first electrode plate in the first electrode layer 321 , and the second conductive layer 332 may partially or completely face the first electrode layer 321 part or all of the first electrode plate in the second electrode layer 322, the third conductive layer 333 may be part or all of the first electrode plate in the second electrode layer 322 plate. Wherein, the material of the second conductive layer 332 is preferably a metal material. At this time, the parasitic capacitance between the first pole plate of the first electrode layer 321 and the second electrode layer 322 is converted into a parasitic capacitance between the first pole plate and the second conductive layer 332, and is introduced into the first pole plate and the second conductive layer 332. An electrode layer 321 is on the second plate.

To sum up, in the capacitor 200 provided by the embodiment of the present invention, by adding the first conductive layer 231 below the first pole plate 221 and adding the second conductive layer 232 above the first pole plate 221, the original first pole plate 221 is blocked. The parasitic capacitance generated between a pole plate 231 and the adjacent layer, even if the original parasitic capacitance generated between the first pole plate 231 and the adjacent layer is converted into the first pole plate 221 and the first conductive layer 231 or the second conductive layer. The parasitic capacitance on the layer 232; the first conductive layer 231 and the second conductive layer 232 are connected to the second pole plate 222 respectively, and the parasitic capacitance on the first conductive layer 231 and the second conductive layer 232 is drawn to the second pole plate 222 , the parasitic capacitance of the first plate 221 is finally reduced, and the linearity of the ADC (Analog-to-Digital Converter) including the capacitor 200 is improved.

The foregoing are only preferred embodiments of the present invention, and do not limit the present invention in any way. Any person skilled in the technical field, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the technical solution of the present invention. The content still belongs to the protection scope of the present invention.

Claims (9)

1. A capacitor, characterized in that the capacitor comprises: Substrate; At least one electrode layer is located on the substrate, the electrode layer includes: a first pole plate and a second pole plate, the first pole plate and the second pole plate are interdigitated and relatively staggered Arranged, the first pole plate is used to connect the common mode voltage, and the second pole plate is used to connect the reference voltage; The conductive layer is located on the substrate, the conductive layer can generate parasitic capacitance with the first plate, and the conductive layer is connected to the second plate. 2. The capacitor according to claim 1, wherein the number of the conductive layer is multilayer, at least one layer of the conductive layer is formed above and below the electrode layer, and the conductive layer is at least partially facing the first plate. 3. The capacitor according to claim 2, wherein the number of the electrode layers is n layers, and the number of the conductive layers is at least n+1 layers, wherein n is a natural number. 4. The capacitor according to claim 2, wherein the conductive layer has an interdigitated structure, and the number of fingers of the conductive layer is the same as that of the first plate, and the number of fingers of the conductive layer is the same as that of the first plate. The first polar plate is opposite. 5 . The capacitor according to claim 1 , wherein the capacitor further comprises a connection hole, and the conductive layer is connected to the second plate through the connection hole. 6. The capacitor according to claim 5, wherein the number of the connecting holes is multiple. 7. The capacitor according to any one of claims 1-4, wherein the material of the conductive layer is selected from metal or polysilicon. 8. The capacitor according to any one of claims 1-4, wherein the material of the electrode layer is selected from metals. 9. The capacitor according to any one of claims 1 to 4, wherein the capacitor further comprises: a first insulating layer, the first insulating layer is located on the substrate, and the electrode layer is located in the first insulating layer; A second insulating layer, the second insulating layer is located on the substrate, the conductive layer is located in the second insulating layer, and the conductive layer passes through the second insulating layer or the first insulating layer insulated from the electrode layer.