TWI819776B - Metal-oxide-metal capacitor structure and semiconductor device thereof - Google Patents

Metal-oxide-metal capacitor structure and semiconductor device thereof Download PDF

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TWI819776B
TWI819776B TW111133635A TW111133635A TWI819776B TW I819776 B TWI819776 B TW I819776B TW 111133635 A TW111133635 A TW 111133635A TW 111133635 A TW111133635 A TW 111133635A TW I819776 B TWI819776 B TW I819776B
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metal
electrode structure
electrode
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capacitor
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TW202412326A (en
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游思穎
彭志龍
陳昱璋
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瑞昱半導體股份有限公司
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Abstract

A metal-oxide-metal (MOM) capacitor structure and a semiconductor device are provided. The MOM capacitor structure includes a first electrode structure arranged on a periphery and a second electrode structure that is surrounded by the first electrode structure. The electrode structure includes one or more metal lines. The first electrode structure and the second electrode structure are spaced with a gap for forming a coupling capacitance between adjacent metal lines of the first and the second electrode structures. The peripheral first electrode structure forms a shielding protection structure for the inside second electrode structure. In a semiconductor device, a plurality of MOM capacitor structures can be electrically connected in parallel and formed on a substrate side by side. The adjacent MOM capacitor structures share the same peripheral first electrode structure.

Description

金屬氧化物金屬電容結構及其半導體裝置Metal oxide metal capacitor structure and semiconductor device thereof

說明書公開一種電容結構,特別是一種外圍電極結構形成內部電極結構遮蔽的金屬氧化物金屬電容結構及採用此金屬氧化物金屬電容結構的半導體裝置。The description discloses a capacitor structure, particularly a metal oxide metal capacitor structure in which a peripheral electrode structure forms an internal electrode structure to shield it, and a semiconductor device using this metal oxide metal capacitor structure.

隨著製程發展演進,晶片面積逐漸縮小,因為開發出新型架構金屬電容,有助於減少使用面積。舉例來說,射頻(RF)相關應用的積體電路(integrated circuit,IC)中的被動元件如電容,最常用的電容之一即為金屬氧化物金屬(metal-oxide-metal,MOM)電容。With the development and evolution of manufacturing processes, the chip area is gradually shrinking, because the development of new structural metal capacitors helps reduce the area used. For example, passive components such as capacitors in integrated circuits (ICs) for radio frequency (RF) related applications, one of the most commonly used capacitors is metal-oxide-metal (MOM) capacitors.

根據金屬氧化物金屬電容的設計,一般是金屬連線形成的指狀(finger)結構,隨著工藝技術的進步,金屬線可以靠的更近,經過通電後,金屬線之間產生耦合效應(coupling effect),據此形成電路需要的電容值。然而,在習知技術中,金屬氧化物金屬電容的正極(PLUS)設計可接不同訊號,負極(MINUS)則設計接相同訊號,但卻會因為不能共用以及間隔規則(spacing rule)的限制而增加面積,且排列上會有諸多限制。According to the design of metal oxide metal capacitors, it is generally a finger structure formed by metal wires. With the advancement of process technology, the metal wires can be closer together. After energization, a coupling effect occurs between the metal wires ( coupling effect), based on which the capacitance value required by the circuit is formed. However, in the conventional technology, the positive electrode (PLUS) of the metal oxide metal capacitor is designed to be connected to different signals, and the negative electrode (MINUS) is designed to be connected to the same signal. However, it cannot be shared and is restricted by spacing rules. Increase the area, and there will be many restrictions on arrangement.

現行金屬氧化物金屬電容設計可以參考圖1至圖3,圖1顯示一對指狀交錯設置並相隔一定距離的金屬氧化物金屬結構,其中有多層設計,經疊層後,圖中顯示的金屬線路的第一端101用於連接電路的正極,可以連接各種訊號源,第二端102用於連接電路的負極,可以是接地端。分別對第一端101與第二端102通電後,連接兩個電極的金屬氧化物金屬結構中相鄰金屬線路之間形成耦合電容。The current design of metal oxide capacitors can be referred to Figures 1 to 3. Figure 1 shows a pair of metal oxide metal structures interlaced in a finger shape and separated by a certain distance. There are multiple layers in the design. After stacking, the metal shown in the figure The first end 101 of the line is used to connect the positive electrode of the circuit, which can be connected to various signal sources, and the second end 102 is used to connect the negative electrode of the circuit, which can be the ground end. After the first terminal 101 and the second terminal 102 are powered on respectively, a coupling capacitance is formed between adjacent metal lines in the metal oxide metal structure connecting the two electrodes.

再如圖2顯示的金屬氧化物金屬結構示意圖,其中顯示兩個如圖1顯示的金屬氧化物金屬結構並排的電容設計,同樣地,個別金屬氧化物金屬結構的兩端(如第一端101, 101’、第二端102, 102’)也分別連接正負極。根據需求,還可形成如圖3所示多個金屬氧化物金屬結構以陣列式排列形成的金屬氧化物金屬電容。Figure 2 shows a schematic diagram of a metal oxide metal structure, which shows a capacitor design of two metal oxide metal structures side by side as shown in Figure 1. Similarly, both ends of individual metal oxide metal structures (such as the first end 101 , 101', the second terminal 102, 102') are also connected to the positive and negative poles respectively. According to requirements, a metal oxide metal capacitor in which multiple metal oxide metal structures are arranged in an array as shown in FIG. 3 can also be formed.

根據上述習知技術以相互安插排列數顆指狀金屬氧化物金屬電容時,相鄰金屬線路之間的電容值容易受到周圍金屬層影響,例如圖3顯示在相鄰的金屬氧化物金屬結構之間(如標示於圖中的區域301與區域302)容易產生寄生電容值(parasitic capacitance)並形成干擾,將會改變整體電容值。When several finger-shaped metal oxide metal capacitors are arranged mutually according to the above-mentioned conventional technology, the capacitance value between adjacent metal lines is easily affected by the surrounding metal layers. For example, Figure 3 shows that between adjacent metal oxide metal structures Parasitic capacitance is easily generated between areas (such as area 301 and area 302 marked in the figure) and causes interference, which will change the overall capacitance value.

為了解決習知金屬氧化物金屬電容結構因為設計規則受到限制,加上相鄰金屬線路容易產生無法預期的寄生電容形成干擾,揭露書提出一種新型的金屬氧化物金屬電容結構及其半導體裝置,其中半導體裝置可由多組金屬氧化物金屬電容結構排列組成,裝置結構特點之一是使其中多組金屬氧化物金屬電容結構可共用電極端(正極(plus)或負極(minus)),共用電極端連接相同訊號,因為共用電極端還能減少面積,排列上也較為彈性。In order to solve the problem that the conventional metal oxide metal capacitor structure is limited by design rules, and adjacent metal lines are prone to produce unexpected parasitic capacitance and cause interference, the disclosure proposes a new type of metal oxide metal capacitor structure and its semiconductor device, in which Semiconductor devices can be composed of multiple groups of metal oxide metal capacitor structures arranged. One of the structural features of the device is that multiple groups of metal oxide metal capacitor structures can share electrode terminals (positive electrode (plus) or negative electrode (minus)), and the common electrode terminal connections The same signal, because the shared electrode terminals can also reduce the area, the arrangement is also more flexible.

根據實施例,金屬氧化物金屬電容結構主要分為設於外圍的第一電極結構,以及受到第一電極結構圍住的第二電極結構,第一電極結構與第二電極結構各由一或多層金屬線路形成。經電路佈局後,於一基材上,第一電極結構與第二電極結構之間以一間隙隔開,以在第一電極結構與第二電極結構的相鄰金屬線路之間形成耦合電容,並且設於外圍的第一電極結構對第二電極結構形成一屏蔽保護結構。According to the embodiment, the metal oxide metal capacitor structure is mainly divided into a first electrode structure located on the periphery and a second electrode structure surrounded by the first electrode structure. The first electrode structure and the second electrode structure each consist of one or more layers. Metal lines formed. After circuit layout, the first electrode structure and the second electrode structure are separated by a gap on a substrate to form a coupling capacitance between adjacent metal lines of the first electrode structure and the second electrode structure. And the first electrode structure located on the periphery forms a shielding protection structure for the second electrode structure.

優選地,所述第一電極結構的多層金屬線路共同接地,而第二電極結構的多層金屬線路分別連接相同或不同的訊號源。Preferably, the multi-layer metal circuits of the first electrode structure are commonly grounded, and the multi-layer metal circuits of the second electrode structure are respectively connected to the same or different signal sources.

優選地,第一電極結構與第二電極結構中的多層金屬線路之間以導通結構相互電性連接,並且各導通結構亦為電容值輸出端子。Preferably, the multi-layer metal circuits in the first electrode structure and the second electrode structure are electrically connected to each other through conductive structures, and each conductive structure is also a capacitance value output terminal.

進一步地,在上述第一電極結構與第二電極結構中的多層金屬線路的最外層可設有遮蔽層,遮蔽層為在一基材上形成的一整個表面的金屬材料所形成,其中還設有一導通結構。Further, the outermost layer of the multi-layer metal circuit in the first electrode structure and the second electrode structure may be provided with a shielding layer. The shielding layer is formed of an entire surface of metal material formed on a base material, wherein a shielding layer is also provided. There is a conductive structure.

在電路設計上,受到第一電極結構圍住的第二電極結構為I字型結構、方形結構、十字形結構、魚骨形結構或由多個十字形結構組合形成的結構,並且,第一電極結構根據第二電極結構的多個轉折結構對應設計相互穿插的突出結構。如此,第二電極結構可以通過一或多層金屬線路形成多個轉折結構,以與第一電極結構建立多處耦合電容。In terms of circuit design, the second electrode structure surrounded by the first electrode structure is an I-shaped structure, a square structure, a cross-shaped structure, a herringbone-shaped structure or a structure formed by a combination of multiple cross-shaped structures, and the first The electrode structure is designed with interpenetrating protruding structures corresponding to multiple turning structures of the second electrode structure. In this way, the second electrode structure can form multiple turning structures through one or more layers of metal lines to establish multiple coupling capacitances with the first electrode structure.

根據揭露書提出應用了一或多個金屬氧化物金屬電容結構形成的半導體裝置,其中,同樣地,金屬氧化物金屬電容結構的第一電極結構的多層金屬線路共同接地,而第二電極結構的多層金屬線路分別連接相同或不同的訊號源。According to the disclosure, a semiconductor device formed using one or more metal oxide metal capacitor structures is proposed, wherein, similarly, the multi-layer metal circuits of the first electrode structure of the metal oxide metal capacitor structure are commonly grounded, and the second electrode structure Multi-layer metal circuits connect the same or different signal sources respectively.

為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與圖式,然而所提供的圖式僅用於提供參考與說明,並非用來對本發明加以限制。In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and illustration and are not used to limit the present invention.

以下是通過特定的具體實施例來說明本發明的實施方式,本領域技術人員可由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用,本說明書中的各項細節也可基於不同觀點與應用,在不悖離本發明的構思下進行各種修改與變更。另外,本發明的附圖僅為簡單示意說明,並非依實際尺寸的描繪,事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容,但所公開的內容並非用以限制本發明的保護範圍。The following is a specific example to illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depictions based on actual dimensions, as is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of the present invention.

應當可以理解的是,雖然本文中可能會使用到“第一”、“第二”、“第三”等術語來描述各種元件或者訊號,但這些元件或者訊號不應受這些術語的限制。這些術語主要是用以區分一元件與另一元件,或者一訊號與另一訊號。另外,本文中所使用的術語“或”,應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。It should be understood that although terms such as “first”, “second” and “third” may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used in this article shall include any one or combination of more of the associated listed items depending on the actual situation.

揭露書公開一種金屬氧化物金屬(metal-oxide-metal,MOM)電容結構及其半導體裝置,所述金屬氧化物金屬電容結構一般以成對指狀設計,成對的指狀結構可區分為第一指狀結構與第二指狀結構,第一指狀結構與第二指狀結構相互交錯設置,使得在相鄰的金屬線路之間可以形成多方向的耦合電容,實現所述金屬氧化物金屬電容結構。在此一提的是,所述指狀結構為多層結構疊合形成的整體外觀,而事實上不是每層都是製作為指狀結構。The disclosure discloses a metal-oxide-metal (MOM) capacitor structure and its semiconductor device. The metal-oxide-metal capacitor structure is generally designed in a paired finger shape. The paired finger structures can be divided into A finger-like structure and a second finger-like structure, and the first finger-like structure and the second finger-like structure are arranged staggered with each other, so that multi-directional coupling capacitance can be formed between adjacent metal lines to realize the metal oxide metal capacitor structure. It should be mentioned here that the finger-like structure is an overall appearance formed by the superposition of multiple layers, but in fact not every layer is made into a finger-like structure.

圖4顯示金屬氧化物金屬電容結構的實施例之一範例圖。不同於習知相互穿插形成指狀金屬氧化物金屬電容結構,此圖例顯示為不同電極的金屬層結構在空間上以內外互補設計的方式形成的金屬氧化物金屬電容結構,其中主要結構包括設於外圍的第一電極結構401,以及設於內部的第二電極結構402,其中第一電極結構401與第二電極結構402都可由一或多層金屬線路形成。根據此電容結構的電路設計,第一電極結構401與第二電極結構402之間根據實施例需求以一間隙隔開,以能在第一電極結構401與第二電極結構402的相鄰金屬線路之間形成耦合電容。另一方面,內部的第二電極結構402受到第一電極結構401圍住,第一電極結構401在一實施例中連結一共用電位,如接地,可使得設於外圍的第一電極結構401對第二電極結構402形成一屏蔽保護結構,讓所形成的金屬氧化物金屬電容不易受到周遭電容金屬層影響電容值,因此電容值較為準確。FIG. 4 shows an example diagram of an embodiment of a metal oxide metal capacitor structure. Different from the conventional finger-like metal oxide metal capacitor structure formed by interpenetrating each other, this illustration shows a metal oxide metal capacitor structure formed by the metal layer structure of different electrodes in space in a complementary internal and external design. The main structure includes The first electrode structure 401 on the periphery, and the second electrode structure 402 provided on the interior, wherein both the first electrode structure 401 and the second electrode structure 402 can be formed of one or more layers of metal circuits. According to the circuit design of this capacitor structure, the first electrode structure 401 and the second electrode structure 402 are separated by a gap according to the embodiment requirements, so that the adjacent metal lines of the first electrode structure 401 and the second electrode structure 402 can be connected. A coupling capacitance is formed between them. On the other hand, the inner second electrode structure 402 is surrounded by the first electrode structure 401. In one embodiment, the first electrode structure 401 is connected to a common potential, such as ground, so that the first electrode structure 401 located on the periphery can pair The second electrode structure 402 forms a shielding protection structure, so that the formed metal oxide metal capacitor is not susceptible to the capacitance value being affected by the surrounding capacitor metal layer, so the capacitance value is more accurate.

進一步地,在以多層金屬線路形成的第一電極結構401與第二電極結構402的實施例中,第一電極結構401與第二電極結構402中的多層金屬線路之間以導通結構相互電性連接,如第一電極結構401設有導通其中各層金屬線路的第一導通結構403,以及第二電極結構402設有導通其中各層金屬線路的第二導通結構404。上述各金屬線路層由縱橫交錯的金屬線路形成於一基材製作得出,不同金屬線路層之間的導通結構可為各種形式的導電結構,例如以導孔(via)貫穿基材再注入金屬材料可形成導通結構,或是連接各層之間的其他形式的導體。並且各導通結構亦可為金屬氧化物金屬電容結構導出電容值的輸出端子。Further, in the embodiment in which the first electrode structure 401 and the second electrode structure 402 are formed with multi-layer metal circuits, the multi-layer metal circuits in the first electrode structure 401 and the second electrode structure 402 are electrically connected to each other through a conductive structure. Connection, for example, the first electrode structure 401 is provided with a first conductive structure 403 that conducts the metal circuits of each layer thereof, and the second electrode structure 402 is provided with a second conductive structure 404 that conducts the metal circuits of each layer thereof. Each of the above metal circuit layers is formed by crisscrossing metal circuits on a base material. The conductive structure between different metal circuit layers can be various forms of conductive structures, such as vias penetrating the base material and then injecting metal. Materials can form conductive structures or other forms of conductors connecting layers. Moreover, each conductive structure can also be an output terminal for deriving a capacitance value for the metal oxide metal capacitor structure.

在一實施例中,第一電極結構401與第二電極結構402相互電性絕緣,並可分別通過第一導通結構403與第二導通結構404連結特定訊號源的接地端與訊號端,以能在相互鄰近的金屬線路之間形成電容。In one embodiment, the first electrode structure 401 and the second electrode structure 402 are electrically insulated from each other, and can be connected to the ground end and the signal end of the specific signal source through the first conductive structure 403 and the second conductive structure 404 respectively, so as to enable Capacitance is formed between metal lines adjacent to each other.

根據揭露書提出的半導體裝置實施例,其中採用一或多個金屬氧化物金屬電容結構形成的電容器,可參考圖5所示並聯型式的金屬氧化物金屬電容結構,其中顯示多個金屬氧化物金屬電容結構相互電性並聯連接,且並排形成於一基材上,相鄰的金屬氧化物金屬電容結構共用設於外圍的第一電極結構,如圖示包括由第一電極結構401與第二電極結構402形成其中第一個金屬氧化物金屬電容結構;同理,第一電極結構401’與第二電極結構402’也形成第二個金屬氧化物金屬電容結構;第一電極結構401’’與第二電極結構402’’形成第三個金屬氧化物金屬電容結構,加上第一電極結構401’’’與第二電極結構402’’’形成第四個金屬氧化物金屬電容結構。According to the embodiment of the semiconductor device proposed in the disclosure, the capacitor formed by using one or more metal oxide metal capacitor structures can refer to the parallel type metal oxide metal capacitor structure shown in Figure 5, which shows a plurality of metal oxide metal capacitor structures. The capacitor structures are electrically connected in parallel to each other and are formed side by side on a substrate. The adjacent metal oxide metal capacitor structures share a first electrode structure located on the periphery. As shown in the figure, the capacitor structures include a first electrode structure 401 and a second electrode. The structure 402 forms the first metal oxide metal capacitor structure; similarly, the first electrode structure 401' and the second electrode structure 402' also form the second metal oxide metal capacitor structure; the first electrode structure 401'' and The second electrode structure 402'' forms a third metal oxide metal capacitor structure, and the first electrode structure 401'' and the second electrode structure 402'''' form a fourth metal oxide metal capacitor structure.

如上所述,各個金屬氧化物金屬電容結構中設於外圍的第一電極結構401, 401’, 401’’, 401’’’共用電氣訊號,形成相鄰第一電極結構之間縱向的共用結構501,以及橫向的共用結構502,並且第一電極結構401, 401’, 401’’, 401’’’可以是接地端,對各自的第二電極結構402, 402’, 402’’, 402’’’來說形成內部電極結構的屏蔽結構。另一方面,對整體金屬氧化物金屬電容結構而言,因為共用第一電極結構,整體上可以減少面積,電路設計上具有面積效率,排列上較為彈性。As mentioned above, the first electrode structures 401, 401', 401'', 401''' located on the periphery of each metal oxide metal capacitor structure share electrical signals, forming a vertical shared structure between adjacent first electrode structures. 501, and the lateral common structure 502, and the first electrode structure 401, 401', 401'', 401''' can be a ground terminal for the respective second electrode structure 402, 402', 402'', 402' ''In order to form a shielding structure of the internal electrode structure. On the other hand, for the overall metal oxide metal capacitor structure, because the first electrode structure is shared, the overall area can be reduced, the circuit design has area efficiency, and the arrangement is more flexible.

在一實施例中,依照需求,可重複圖4或圖5結構,形成的半導體裝置可參考圖6所示陣列形式排列金屬氧化物金屬電容結構形成的半導體裝置實施例,其中顯示多個金屬氧化物金屬電容結構相互電性並聯連接,且並排形成於一基材上,相鄰的金屬氧化物金屬電容結構共用設於外圍的第一電極結構。如此,將可提供更大的電容值,在此需求下,各部位的第一電極結構的多層金屬線路共同接地,而第二電極結構的多層金屬線路可分別連接相同或不同的訊號源。通過揭露書提出可共用電極結構的設計,能提供更大的面積效率,還能形成更有意義的屏蔽效應。In one embodiment, according to requirements, the structure of Figure 4 or Figure 5 can be repeated, and the semiconductor device formed can refer to the embodiment of the semiconductor device formed by arranging metal oxide metal capacitor structures in an array as shown in Figure 6, in which multiple metal oxide metal capacitor structures are shown. The metal-metal capacitor structures are electrically connected to each other in parallel and are formed side by side on a substrate. The adjacent metal-oxide metal capacitor structures share a first electrode structure located on the periphery. In this way, a larger capacitance value can be provided. Under this requirement, the multi-layer metal circuits of the first electrode structure in each part are commonly grounded, and the multi-layer metal circuits of the second electrode structure can be connected to the same or different signal sources respectively. The disclosure proposes a design that can share electrode structures, which can provide greater area efficiency and form a more meaningful shielding effect.

根據半導體裝置的實施例,半導體裝置可以根據實際需求採用一或多個金屬氧化物金屬電容結構,作為特定電路系統中的電容器,其中各金屬氧化物金屬電容結構主要如上述實施例描述包括有設於外圍的第一電極結構,以及受到第一電極結構圍住的第二電極結構。特別的是,各金屬氧化物金屬電容結構可由多層結構形成,各層之間可以用絕緣結構相互電性絕緣,相鄰金屬層之間也將形成電容。According to the embodiments of the semiconductor device, the semiconductor device may use one or more metal oxide metal capacitor structures as capacitors in a specific circuit system according to actual needs, wherein each metal oxide metal capacitor structure mainly includes a device as described in the above embodiments. a first electrode structure on the periphery, and a second electrode structure surrounded by the first electrode structure. In particular, each metal oxide metal capacitor structure can be formed by a multi-layer structure, and each layer can be electrically insulated from each other by an insulating structure, and capacitance will also be formed between adjacent metal layers.

以下以圖7至圖13所示的範例圖分層(layer by layer)描述揭露書所提出的金屬氧化物金屬電容結構實施例圖。The following is a layer by layer description of an embodiment of the metal oxide metal capacitor structure proposed in the disclosure using the example diagrams shown in FIGS. 7 to 13 .

首先,圖7顯示金屬氧化物金屬電容結構中遮蔽層70的實施例圖,遮蔽層70為在一基材上形成的一整個表面的金屬材料所形成,遮蔽層70用於阻隔相鄰金屬層之間訊號線以及外部電路的影響,成為如圖14顯示的金屬氧化物金屬電容結構實施例中最外層的第一金屬層與第五金屬層。圖中顯示的實施範例在遮蔽層70中的特定部位設計一個中空的導通結構701,導通結構701的形狀與大小依照實際需求設計,用途是提供金屬氧化物金屬電容結構中遮蔽層70以內以及以外電路相互電性連接的中空結構。First, FIG. 7 shows an embodiment of a shielding layer 70 in a metal oxide metal capacitor structure. The shielding layer 70 is formed of an entire surface of metal material formed on a substrate. The shielding layer 70 is used to block adjacent metal layers. The influence of the signal lines and external circuits in between becomes the outermost first metal layer and the fifth metal layer in the embodiment of the metal oxide metal capacitor structure as shown in FIG. 14 . The implementation example shown in the figure designs a hollow conductive structure 701 at a specific location in the shielding layer 70. The shape and size of the conductive structure 701 are designed according to actual requirements, and are used to provide a metal oxide metal capacitor structure inside and outside the shielding layer 70. A hollow structure in which circuits are electrically connected to each other.

圖8顯示金屬氧化物金屬電容結構中第二金屬層80實施例圖,圖中顯示的第二金屬層80由一基材上形成的多條縱橫交錯的金屬線路所組成,第二金屬層80為金屬氧化物金屬電容結構中產生電容的金屬層之一。Figure 8 shows an embodiment of the second metal layer 80 in a metal oxide metal capacitor structure. The second metal layer 80 shown in the figure is composed of a plurality of criss-crossing metal lines formed on a substrate. The second metal layer 80 It is one of the metal layers that generates capacitance in the metal oxide metal capacitor structure.

圖9則是顯示金屬氧化物金屬電容結構中在一基材上形成的多條縱橫交錯的金屬線路組成的第三金屬層90的實施例圖,而圖10顯示為第四金屬層100的實施例圖,皆同樣為電容結構中產生電容的金屬層之一。FIG. 9 shows an embodiment of a third metal layer 90 composed of a plurality of criss-crossing metal lines formed on a substrate in a metal oxide metal capacitor structure, and FIG. 10 shows an implementation of the fourth metal layer 100 The example diagrams are all one of the metal layers that generate capacitance in the capacitor structure.

在此一提的是上述形成金屬氧化物金屬電容結構中第二金屬層80、第三金屬層90以及第四金屬層100等多層金屬層具有相同外觀結構,此例顯示為魚骨形結構。It should be mentioned here that the multiple metal layers such as the second metal layer 80 , the third metal layer 90 and the fourth metal layer 100 in the above-mentioned metal oxide metal capacitor structure have the same appearance structure, which is a fishbone-shaped structure in this example.

圖11接著顯示金屬氧化物金屬電容結構中第一電容結構110實施例示意圖,由上述遮蔽層70、第二金屬層80以及兩者之間設置的導通結構111與112所組成。第一電容結構110中顯示在各層縱橫交錯的金屬線路中設有導通結構111與112,用以在各層之間以導孔(via)建立電連接關係。此例顯示的導通結構111與112用於電性導通遮蔽層70與第二金屬層80,對照圖7顯示的遮蔽層70中的導通結構701的結構設計,導通結構111與112形成在導通結構701的對應位置中。如此,導通結構111與112可使多層金屬線路之間相互電性連接之外,還可為電容值輸出端子,立體結構示意圖可參考圖14。FIG. 11 then shows a schematic diagram of an embodiment of the first capacitor structure 110 in the metal oxide metal capacitor structure, which is composed of the above-mentioned shielding layer 70, the second metal layer 80, and the conductive structures 111 and 112 provided between the two. The first capacitor structure 110 shows that conductive structures 111 and 112 are provided in the criss-crossing metal circuits of each layer to establish electrical connections through vias between each layer. The conductive structures 111 and 112 shown in this example are used to electrically conduct the shielding layer 70 and the second metal layer 80. Compared with the structural design of the conductive structure 701 in the shielding layer 70 shown in Figure 7, the conductive structures 111 and 112 are formed on the conductive structure. In the corresponding position of 701. In this way, the conductive structures 111 and 112 can not only electrically connect the multi-layer metal circuits to each other, but also serve as capacitance value output terminals. For a schematic diagram of the three-dimensional structure, refer to FIG. 14 .

接著圖12顯示金屬氧化物金屬電容結構中第二電容結構120的實施例圖,第二電容結構120通過導通結構電性導通第二金屬層80與第三金屬層90,第二電容結構120包括如圖示中設於環繞於外部的多個第一導通結構121以及設於內部的多個第二導通結構122,第一導通結構121與第二導通結構122可以多個導孔(via)形式建立第二金屬層80與第三金屬層90之間的電連接關係,並且可為此第二電容結構120的電容值輸出端子,立體結構示意圖同樣地可參考圖14。Next, FIG. 12 shows an embodiment diagram of the second capacitor structure 120 in the metal oxide metal capacitor structure. The second capacitor structure 120 electrically conducts the second metal layer 80 and the third metal layer 90 through the conductive structure. The second capacitor structure 120 includes As shown in the figure, there are a plurality of first conductive structures 121 surrounding the outside and a plurality of second conductive structures 122 disposed inside. The first conductive structures 121 and the second conductive structures 122 can be in the form of multiple vias. The electrical connection relationship between the second metal layer 80 and the third metal layer 90 is established, and the capacitance value output terminal of the second capacitor structure 120 can be used for this. The three-dimensional structure schematic diagram can also be referred to FIG. 14 .

圖13顯示金屬氧化物金屬電容結構中第三電容結構130的實施例圖,此例的第三電容結構130包括有環繞於外部金屬結構中的多個第三導通結構131以及內部魚骨狀金屬結構的多個第四導通結構132。同樣地,第三導通結構131與第四導通結構132作為內外層之間導通結構,可以多個導孔(via)形式電性導通第三金屬層90與第四金屬層100,並可為電容值輸出端子,立體結構示意圖亦可參考圖14。FIG. 13 shows an embodiment of the third capacitor structure 130 in the metal oxide metal capacitor structure. The third capacitor structure 130 in this example includes a plurality of third conductive structures 131 surrounding the outer metal structure and an inner fishbone metal. A plurality of fourth conductive structures 132 of the structure. Similarly, the third conductive structure 131 and the fourth conductive structure 132 serve as conductive structures between the inner and outer layers, can electrically conduct the third metal layer 90 and the fourth metal layer 100 in the form of multiple vias (vias), and can be capacitors. Value output terminal, the three-dimensional structure diagram can also refer to Figure 14.

圖14顯示組合上述實施例圖各層結構形成的多層金屬氧化物金屬電容結構的實施例圖。在此一提的是,所示金屬氧化物金屬電容結構的層疊結構係根據實際需求而定,其中的金屬層的層數、電路設計、遮蔽層設計,以及其中導通結構的設計可依照實際需求改變,並不限於所示的範例,並未限制在本實施例。FIG. 14 shows an embodiment diagram of a multi-layer metal oxide metal capacitor structure formed by combining the layer structures of the above embodiment diagrams. It should be mentioned here that the stacked structure of the metal oxide metal capacitor structure shown is determined according to actual needs. The number of metal layers, circuit design, shielding layer design, and the design of the conductive structure can be determined according to actual needs. Changes are not limited to the examples shown and are not limited to this embodiment.

圖示為金屬氧化物金屬電容結構垂直結構,主要結構包括上述圖7至圖13所示金屬結構,示意圖忽略上述實施例顯示的導通結構。此圖例由下往上順序為由遮蔽層70形成的第一金屬層、第二金屬層80、第三金屬層90、第四金屬層100,以及由另一遮蔽層70’形成的第五金屬層,各層緊密相鄰,並可以上述實施例所描述導通結構根據需求將不同層相互電性連接,各層疊層順序也不限於此圖式所示。The figure shows the vertical structure of the metal oxide metal capacitor structure. The main structure includes the metal structure shown in the above-mentioned Figures 7 to 13. The schematic diagram ignores the conductive structure shown in the above embodiment. This illustration shows, from bottom to top, the first metal layer formed by the shielding layer 70, the second metal layer 80, the third metal layer 90, the fourth metal layer 100, and the fifth metal layer formed by another shielding layer 70'. Each layer is closely adjacent to each other, and different layers can be electrically connected to each other according to the needs through the conductive structure described in the above embodiment. The stacking sequence of each layer is not limited to that shown in this figure.

此例顯示相鄰金屬層的第一電極結構與第二電極結構具有多層金屬線路,最外層則設有以遮蔽金屬面實現的遮蔽層70與70’,用以遮蔽半導體裝置中金屬氧化物金屬電容結構以外的其他電路的干擾。並且,在此多層結構中,除了各層金屬氧化物金屬電容結構中的第一電極結構與所包圍的第二電極結構之間可以通過多個轉折結構建立多處耦合電容,並且垂直方向的多層之間也將形成耦合電容。This example shows that the first electrode structure and the second electrode structure of adjacent metal layers have multi-layer metal circuits, and the outermost layers are provided with shielding layers 70 and 70' implemented by shielding metal surfaces to shield the metal oxide metal in the semiconductor device. Interference from circuits other than capacitive structures. Moreover, in this multi-layer structure, in addition to the first electrode structure in each layer of metal oxide metal capacitor structure and the surrounding second electrode structure, multiple coupling capacitances can be established through multiple turning structures, and between the multi-layers in the vertical direction Coupling capacitance will also be formed between them.

進一步地,可參考圖15至圖17所示實施例,設於外圍的第一電極結構可根據第二電極結構的多個轉折結構對應設計相互穿插的突出結構,形成多處相鄰金屬線路的結構,因此可以有效建立多處耦合電容。Further, with reference to the embodiments shown in FIGS. 15 to 17 , the first electrode structure located on the periphery can be designed with interpenetrating protruding structures according to the multiple turning structures of the second electrode structure to form multiple adjacent metal lines. structure, so multiple coupling capacitances can be effectively established.

根據半導體裝置實施例,其中各金屬氧化物金屬電容結構中的第二電極結構可為一I字型結構、一方形結構、一十字形結構、一魚骨形結構或由多個十字形結構組合形成的結構。According to the semiconductor device embodiment, the second electrode structure in each metal oxide metal capacitor structure may be an I-shaped structure, a square structure, a cross-shaped structure, a fishbone-shaped structure, or a combination of multiple cross-shaped structures. formed structure.

根據圖15所示實施例示意圖,其中顯示為魚骨形內部金屬結構150,包括由一或多層金屬線路形成的外部金屬結構151,外部金屬結構151有多處突出結構,以與魚骨形的內部金屬結構152相互穿插,能在多處轉折處的相鄰金屬線路之間形成電容。According to the schematic diagram of the embodiment shown in Figure 15, a fishbone-shaped internal metal structure 150 is shown, including an external metal structure 151 formed of one or more layers of metal lines. The external metal structure 151 has multiple protruding structures to match the fishbone-shaped structure. The internal metal structures 152 intersect with each other to form capacitance between adjacent metal lines at multiple turns.

圖16顯示的實施例示意圖為一種方框形內部金屬結構160,包括有以一或多層金屬線路形成的框形外部金屬結構161以及內部I字型的內部金屬結構162。The schematic diagram of the embodiment shown in FIG. 16 is a square frame-shaped internal metal structure 160, which includes a frame-shaped external metal structure 161 formed of one or more layers of metal lines and an internal I-shaped internal metal structure 162.

圖17的實施例示意圖為一種十字形內部金屬結構170,包括有外部金屬結構171,以及十字形的內部金屬結構172,彼此同樣也是以突出結構相互穿插設置,同樣能在多處轉折處形成電容。The schematic diagram of the embodiment in Figure 17 shows a cross-shaped internal metal structure 170, which includes an external metal structure 171 and a cross-shaped internal metal structure 172. They are also interspersed with each other in protruding structures, and can also form capacitors at multiple turning points. .

綜上所述,根據上述實施例所描述的金屬氧化物金屬(MOM)電容結構以及以一或多個金屬氧化物金屬電容結構組成的半導體裝置,其中個別的金屬氧化物金屬電容結構中具有共用的外圍電極結構,以及受到外圍電極結構圍住的內部電極結構,而外圍電極結構可以使內部電極結構不受到影響,也不易受到周遭電容金屬層影響電容值,因此電容值較為準確,又因為有共用電極結構,因此可以獲得額外面積效率,更者,金屬氧化物金屬電容結構中不同電極之間的正負極可以依照設計需求交換其端點位置。In summary, according to the metal oxide metal (MOM) capacitor structure described in the above embodiments and the semiconductor device composed of one or more metal oxide metal capacitor structures, each of the metal oxide metal capacitor structures has a common The peripheral electrode structure, and the internal electrode structure surrounded by the peripheral electrode structure, and the peripheral electrode structure can prevent the internal electrode structure from being affected, and the capacitance value is not easily affected by the surrounding capacitance metal layer, so the capacitance value is more accurate, and because there is The electrode structure is shared, so additional area efficiency can be obtained. Furthermore, the positive and negative electrodes between different electrodes in the metal oxide metal capacitor structure can exchange their endpoint positions according to design requirements.

以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,所以凡是運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的申請專利範圍內。The contents disclosed above are only preferred and feasible embodiments of the present invention, and do not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

101,101’:第一端101,101’: first end

102,102’:第二端102,102’: second end

301,302:區域301,302:Area

401,401’,401’’,401’’’:第一電極結構401, 401’, 401’’, 401’’’: first electrode structure

402,402’,402’’,402’’’:第二電極結構402, 402’, 402’’, 402’’’: second electrode structure

403:第一導通結構403: First conduction structure

404:第二導通結構404: Second conduction structure

501,502:共用結構501,502: shared structure

70,70’:遮蔽層70,70’: masking layer

701:導通結構701: conduction structure

80:第二金屬層80: Second metal layer

90:第三金屬層90:Third metal layer

100:第四金屬層100: The fourth metal layer

110:第一電容結構110: First capacitor structure

111,112:導通結構111,112: conduction structure

120:第二電容結構120: Second capacitor structure

121:第一導通結構121: First conduction structure

122:第二導通結構122: Second conduction structure

130:第三電容結構130:Third capacitor structure

131:第三導通結構131:Third conduction structure

132:第四導通結構132: Fourth conduction structure

150:魚骨形內部金屬結構150: Fishbone-shaped internal metal structure

151:外部金屬結構151:External metal structure

152:內部金屬結構152:Internal metal structure

160:方框形內部金屬結構160: Square frame internal metal structure

161:外部金屬結構161:External metal structure

162:內部金屬結構162:Internal metal structure

170:十字形內部金屬結構170: Cross-shaped internal metal structure

171:外部金屬結構171:External metal structure

172:內部金屬結構172:Internal metal structure

圖1顯示習知金屬氧化物金屬電容的元件佈局設計圖之一;Figure 1 shows one of the component layout design drawings of a conventional metal oxide metal capacitor;

圖2顯示習知金屬氧化物金屬電容的元件佈局設計圖之二;Figure 2 shows the second component layout design diagram of a conventional metal oxide metal capacitor;

圖3顯示習知金屬氧化物金屬電容的元件佈局設計圖之三;Figure 3 shows the third component layout design diagram of a conventional metal oxide metal capacitor;

圖4顯示金屬氧化物金屬電容結構的實施例之一範例圖;Figure 4 shows an example diagram of an embodiment of a metal oxide metal capacitor structure;

圖5顯示兩組金屬氧化物金屬電容結構形成的半導體裝置的實施例圖;Figure 5 shows an embodiment diagram of a semiconductor device formed by two sets of metal oxide metal capacitor structures;

圖6顯示陣列形式排列金屬氧化物金屬電容結構形成的半導體裝置的實施例圖;Figure 6 shows an embodiment of a semiconductor device formed by arranging metal oxide metal capacitor structures in an array;

圖7顯示金屬氧化物金屬電容結構中遮蔽層(第一金屬層、第五金屬層)的實施例圖;Figure 7 shows an embodiment diagram of the shielding layer (first metal layer, fifth metal layer) in the metal oxide metal capacitor structure;

圖8顯示金屬氧化物金屬電容結構中第二金屬層實施例圖;Figure 8 shows an embodiment diagram of the second metal layer in the metal oxide metal capacitor structure;

圖9顯示金屬氧化物金屬電容結構中第三金屬層實施例圖;Figure 9 shows an embodiment of the third metal layer in the metal oxide metal capacitor structure;

圖10顯示金屬氧化物金屬電容結構中第四金屬層的實施例圖;Figure 10 shows an embodiment diagram of the fourth metal layer in the metal oxide metal capacitor structure;

圖11顯示金屬氧化物金屬電容結構中第一電容結構的實施例圖;Figure 11 shows an embodiment diagram of the first capacitor structure in the metal oxide metal capacitor structure;

圖12顯示金屬氧化物金屬電容結構中第二電容結構的實施例圖;Figure 12 shows an embodiment diagram of the second capacitor structure in the metal oxide metal capacitor structure;

圖13顯示金屬氧化物金屬電容結構中第三電容結構的實施例圖;Figure 13 shows an embodiment diagram of the third capacitor structure in the metal oxide metal capacitor structure;

圖14顯示多層金屬氧化物金屬電容結構的實施例圖;Figure 14 shows an embodiment diagram of a multi-layer metal oxide metal capacitor structure;

圖15顯示金屬氧化物金屬電容結構的實施例之二示意圖;Figure 15 shows a schematic diagram of the second embodiment of the metal oxide metal capacitor structure;

圖16顯示金屬氧化物金屬電容結構的實施例之三示意圖;以及Figure 16 shows a schematic diagram of the third embodiment of the metal oxide metal capacitor structure; and

圖17顯示金屬氧化物金屬電容結構的實施例之四示意圖。Figure 17 shows a schematic diagram of the fourth embodiment of the metal oxide metal capacitor structure.

401:第一電極 401: first electrode

402:第二電極 402: Second electrode

403:第一導通結構 403: First conduction structure

404:第二導通結構 404: Second conduction structure

Claims (8)

一種金屬氧化物金屬電容結構,包括:設於外圍的一第一電極結構,由一或多層金屬線路形成;以及受到該第一電極結構圍住的一第二電極結構,該第二電極結構由一或多層金屬線路形成;其中該第一電極結構與該第二電極結構之間以一間隙隔開,受到該第一電極結構圍住的該第二電極結構通過該一或多層金屬線路形成多個轉折結構,且該第一電極結構根據該第二電極結構的該多個轉折結構對應設計相互穿插的突出結構,使該第一電極結構與該第二電極結構的相鄰金屬線路之間形成多處耦合電容,並且設於外圍的該第一電極結構對該第二電極結構形成一屏蔽保護結構。 A metal oxide metal capacitor structure includes: a first electrode structure located on the periphery, formed of one or more layers of metal circuits; and a second electrode structure surrounded by the first electrode structure, the second electrode structure is composed of One or more layers of metal circuits are formed; wherein the first electrode structure and the second electrode structure are separated by a gap, and the second electrode structure surrounded by the first electrode structure forms multiple layers of metal circuits through the one or more layers of metal circuits. A turning structure, and the first electrode structure correspondingly designs interpenetrating protruding structures according to the plurality of turning structures of the second electrode structure, so that a formation is formed between the adjacent metal lines of the first electrode structure and the second electrode structure. There are multiple coupling capacitors, and the first electrode structure located on the periphery forms a shielding protection structure for the second electrode structure. 如請求項1所述的金屬氧化物金屬電容結構,其中該第一電極結構的多層金屬線路共同接地,而該第二電極結構的多層金屬線路分別連接相同或不同的訊號源。 The metal oxide metal capacitor structure of claim 1, wherein the multi-layer metal circuits of the first electrode structure are commonly grounded, and the multi-layer metal circuits of the second electrode structure are respectively connected to the same or different signal sources. 如請求項2所述的金屬氧化物金屬電容結構,其中該第一電極結構與該第二電極結構中的多層金屬線路之間以導通結構相互電性連接,並且各導通結構亦為電容值輸出端子。 The metal oxide metal capacitor structure of claim 2, wherein the multi-layer metal circuits in the first electrode structure and the second electrode structure are electrically connected to each other through conductive structures, and each conductive structure is also a capacitance value output terminal. 如請求項3所述的金屬氧化物金屬電容結構,其中該第一電極結構與該第二電極結構中的多層金屬線路的最外層設有一遮蔽層,該遮蔽層為在一基材上形成的一整個表面的金屬材料所形成,其中還設有一導通結構。 The metal oxide metal capacitor structure of claim 3, wherein the outermost layer of the multi-layer metal circuits in the first electrode structure and the second electrode structure is provided with a shielding layer, and the shielding layer is formed on a substrate. An entire surface is formed of metal material, and a conductive structure is also provided therein. 如請求項1所述的金屬氧化物金屬電容結構,其中該第二電極結構為一I字型結構、一方形結構、一十字形結構、一魚骨形結構或由多個該十字形結構組合形成的結構。 The metal oxide metal capacitor structure as claimed in claim 1, wherein the second electrode structure is an I-shaped structure, a square structure, a cross-shaped structure, a fishbone-shaped structure or a combination of a plurality of the cross-shaped structures. formed structure. 一種半導體裝置,包括: 一或多個金屬氧化物金屬電容結構,其中各金屬氧化物金屬電容結構包括:設於外圍的一第一電極結構,由一或多層金屬線路形成;以及受到該第一電極結構圍住的一第二電極結構,該第二電極結構由一或多層金屬線路形成;其中該第一電極結構與該第二電極結構之間以一間隙隔開,受到該第一電極結構圍住的該第二電極結構通過該一或多層金屬線路形成多個轉折結構,且該第一電極結構根據該第二電極結構的該多個轉折結構對應設計相互穿插的突出結構,使該第一電極結構與該第二電極結構的相鄰金屬線路之間形成多處耦合電容,並且設於外圍的該第一電極結構對該第二電極結構形成一屏蔽保護結構。 A semiconductor device including: One or more metal oxide metal capacitor structures, wherein each metal oxide metal capacitor structure includes: a first electrode structure located on the periphery, formed of one or more layers of metal circuits; and a first electrode structure surrounded by the first electrode structure The second electrode structure is formed by one or more layers of metal circuits; wherein the first electrode structure and the second electrode structure are separated by a gap, and the second electrode structure is surrounded by the first electrode structure. The electrode structure forms a plurality of turning structures through the one or more layers of metal lines, and the first electrode structure is designed with interpenetrating protruding structures corresponding to the plurality of turning structures of the second electrode structure, so that the first electrode structure and the third electrode structure Multiple coupling capacitances are formed between adjacent metal lines of the two-electrode structure, and the first electrode structure located on the periphery forms a shielding protection structure for the second electrode structure. 如請求項6所述的半導體裝置,其中該金屬氧化物金屬電容結構的該第一電極結構的多層金屬線路共同接地,而該第二電極結構的多層金屬線路分別連接相同或不同的訊號源。 The semiconductor device of claim 6, wherein the multi-layer metal circuits of the first electrode structure of the metal oxide metal capacitor structure are commonly grounded, and the multi-layer metal circuits of the second electrode structure are respectively connected to the same or different signal sources. 如請求項7所述的半導體裝置,其中該第一電極結構與該第二電極結構中的多層金屬線路之間以導通結構相互電性連接,並且各導通結構亦為電容值輸出端子。The semiconductor device of claim 7, wherein the multi-layer metal circuits in the first electrode structure and the second electrode structure are electrically connected to each other through conductive structures, and each conductive structure is also a capacitance value output terminal.
TW111133635A 2022-09-06 2022-09-06 Metal-oxide-metal capacitor structure and semiconductor device thereof TWI819776B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752363A (en) * 2008-12-09 2010-06-23 美格纳半导体有限会社 Capacitor structure
TW201743349A (en) * 2016-06-02 2017-12-16 聯發科技股份有限公司 Metal-oxide-metal capacitor
CN107633128A (en) * 2017-09-15 2018-01-26 北京华大九天软件有限公司 The layout and Wiring method of MOM capacitor, MOM capacitor array and MOM capacitor array

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752363A (en) * 2008-12-09 2010-06-23 美格纳半导体有限会社 Capacitor structure
TW201743349A (en) * 2016-06-02 2017-12-16 聯發科技股份有限公司 Metal-oxide-metal capacitor
CN107633128A (en) * 2017-09-15 2018-01-26 北京华大九天软件有限公司 The layout and Wiring method of MOM capacitor, MOM capacitor array and MOM capacitor array

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