WO2020056705A1

WO2020056705A1 - Integrated circuit

Info

Publication number: WO2020056705A1
Application number: PCT/CN2018/106863
Authority: WO
Inventors: 邹小卫; 郑伟; 吴春蕾
Original assignee: 华为技术有限公司
Priority date: 2018-09-21
Filing date: 2018-09-21
Publication date: 2020-03-26
Also published as: CN112368831A

Abstract

An integrated circuit. The integrated circuit comprises a capacitor structure comprising multiple metal strip arrays provided at multiple metal layers. Each metal strip array comprises multiple metal strips (P1-P5, V1-V5) extending in the same direction. The metal strips (P1-P5, V1-V5) in each metal strip array include first-electrode metal strips and second-electrode metal strips. The first-electrode metal strips and the second-electrode metal strips are respectively electrically connected to different electrodes (E1, E2) so as to generate a lateral capacitance at the same metal layer. The metal strips in each metal strip array at each metal layer extend in a direction different from an extension direction of the metal strips in the metal strip array at the adjacent metal layer. A longitudinal capacitance can be generated between the first-electrode metal strip and the second-electrode metal strip which are located at two adjacent metal layers and projections thereof on a plane where the metal layers are located overlap. The capacitor structure achieves a higher capacitance density and has higher capacitance quality.

Description

Integrated circuit

Technical field

The present application relates to the field of semiconductor chip design and manufacturing, and in particular, to an integrated circuit.

Background technique

With the rapid progress and development of the semiconductor industry, it has become an inevitable trend to integrate various devices, such as resistors, capacitors and inductors, in the semiconductor process.

Capacitors are important components in integrated circuits and are widely used in various chips. In the semiconductor process, due to the manufacturing of the planar process, the conventional capacitor structure is usually a metal-insulator-metal (MIM) or a multi-layer interdigital (MOM) type.

Among them, the upper and lower plate-type capacitors require two additional layers of photoresist to make unique metal layers, and the process cost is relatively large.

Multi-layered interdigital capacitors use common interconnect metal layers and have lower cost, which can solve the problem of higher cost of MIM-type capacitor structures. However, multi-layered interdigital capacitors occupy a larger plane area and have a lower capacitance density.

Summary of the Invention

In view of this, the present application provides an integrated circuit to reduce the structure area of the capacitor, increase the density of the capacitor, and improve the quality of the capacitor.

In order to solve the above technical problems, the following technical solutions are adopted in this application:

A first aspect of the present application provides an integrated circuit in which a plurality of metal layers are provided, the integrated circuit includes a capacitor structure, and the capacitor structure includes: a first electrode and a second electrode; and The plurality of metal strip arrays on the multilayer metal layer, the metal strip array on each metal layer includes a plurality of metal strips extending in the same direction, and the extension of the metal strips in the metal strip array on each metal layer The direction is different from the extending direction of the metal bars in the metal array on the adjacent metal layer. The metal bars in each metal layer include a first pole metal bar and a second pole metal bar. The first electrode is electrically connected; the second electrode metal strip is electrically connected to the second electrode.

The integrated circuit provided based on the first aspect above includes a capacitor structure including a plurality of metal strip arrays disposed on a plurality of metal layers, and each of the metal strip arrays on each metal layer includes a plurality of extending in the same direction. Metal strips, the metal strips in the metal strip array on each metal layer include a first pole metal strip and a second pole metal strip, and the first pole metal strip and the second pole metal strip are respectively electrically connected to different electrodes, so A lateral capacitor can be formed on the same metal layer. In addition, the extending direction of the metal strips in the metal strip array on each metal layer is different from the extending direction of the metal strips in the metal array on the adjacent metal layer. Therefore, the Longitudinal capacitance may also be formed between the first and second metal strips projected on the plane where the layer is located. Therefore, not only the lateral capacitance but also the longitudinal capacitance can be formed in the capacitor structure. The capacitance density of the capacitor structure is large and the capacitance quality is high. Moreover, based on the horizontal and vertical capacitances that can be formed, when the capacitor structure produces the same capacitance, the planar area it occupies is small.

Based on the first aspect of the present application, in a first possible implementation manner, a projection of a metal bar of a metal bar array in each metal layer on an adjacent metal layer is the same as the metal bar on the adjacent metal layer. The metal bars in the array overlap. This possible implementation can further increase the capacitance density.

Based on the first aspect of the present application or its first possible implementation manner, in a second possible implementation manner, the integrated circuit further includes multiple conductive pillars extending in the same direction, wherein the multiple Parallel conductive pillars are arranged between two adjacent metal layers, and the plurality of conductive pillars extending in the same direction include a first pole conductive pillar and a second pole conductive pillar, and the first pole conductive pillar and the The first electrode is electrically connected, and the second electrode conductive post is electrically connected to the second electrode. This possible implementation can further increase the capacitance density.

Based on the second possible implementation manner of the first aspect of the present application, in a third possible implementation manner, both ends of the first conductive pillar are respectively connected to the first pole metal on two adjacent metal layers. The two conductive poles are connected to each other, and two ends of the second conductive pillar are respectively connected to two second pole metal bars on two adjacent metal layers. This possible implementation can further increase the capacitance density.

Based on the second possible implementation manner of the first aspect of the present application, in a fourth possible implementation manner, the first pole conductive pillars and the second pole conductive pillars are alternately disposed on the adjacent two metals. Between layers. This possible implementation can further increase the capacitance density.

Based on the second possible implementation manner of the first aspect of the present application, in a fifth possible implementation manner, the first pole conductive pillar and the second pole conductive pillar are disposed on the adjacent two metal layers. Between, and perpendicular to the two adjacent metal layers. This possible implementation can further increase the capacitance density.

Based on the first aspect of the present application, in a sixth possible implementation manner, the metal bars in the metal bar array in each metal layer include at least two first pole metal bars or at least two second pole metal bars. Strips, the first pole metal strips and the second pole metal strips in the metal strip array in each of the metal layers are alternately arranged. This possible implementation can further increase the capacitance density.

Based on the first aspect of the present application or any one of the foregoing possible implementation manners, in a seventh possible implementation manner, the extending directions of the metal bars in the metal bar array on each adjacent two metal layers are perpendicular to each other . This possible implementation can further increase the capacitance density.

Based on the first aspect of the present application or any one of the foregoing possible implementation manners, in an eighth possible implementation manner, the layer structures of the metal layers having the same extending direction of the metal strips are the same. This possible implementation can simplify the manufacturing process of the integrated circuit.

Based on the first aspect of the present application or any one of the foregoing possible implementation manners, in a ninth possible implementation manner, the widths of the metal bars in the multi-layer metal layer are equal, and are provided in each layer. The first conductive pillars between the metal layers are aligned vertically, and / or the second conductive pillars disposed between the metal layers of each layer are vertically aligned. This possible implementation can simplify the manufacturing process of the integrated circuit.

Compared with the prior art, the present application has the following beneficial effects:

Based on the above technical solutions, it can be known that the integrated circuit provided in the present application includes a capacitor structure. The capacitor structure includes a plurality of metal strip arrays disposed on a plurality of metal layers. Extended metal strips, the metal strips in the metal strip array on each metal layer include a first pole metal strip and a second pole metal strip, and the first pole metal strip and the second pole metal strip are respectively electrically connected to different electrodes, In this way, a lateral capacitor can be formed on the same metal layer. In addition, the extending direction of the metal strips in the metal strip array on each metal layer is different from the extending direction of the metal strips in the metal array on the adjacent metal layer. Therefore, the Longitudinal capacitance may also be formed between the first and second metal strips projected on the plane where the layer is located.

Therefore, not only the lateral capacitance but also the longitudinal capacitance can be formed in the capacitor structure. The capacitance density of the capacitor structure is large and the capacitance quality is high.

Moreover, based on the horizontal and vertical capacitances that can be formed, when the capacitor structure produces the same capacitance, the planar area it occupies is small.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to clearly understand the specific implementation manners of the present application, the following description will be made with reference to the accompanying drawings used for specific implementation manners of the present application. Obviously, these drawings are only some embodiments of the present application.

FIG. 1 is a schematic structural diagram of a multilayer interdigital capacitor structure provided by this application;

FIG. 2 is a schematic three-dimensional structure diagram of a capacitor structure according to an embodiment of the present application; FIG.

FIG. 3 is a top view of a capacitor structure according to an embodiment of the present application; FIG.

FIG. 4 is a cross-sectional view of the embodiment along the I-I direction in FIG. 3.

detailed description

A schematic structural diagram of a multilayer interdigital capacitor structure is shown in FIG. 1. It includes a common track 11 located in the peripheral area (the area outside the dashed box in FIG. 1) and an interdigital structure 12 located in the middle core area (the area inside the dashed box in FIG. 1), where the interdigital structure 12 and the common track 11 连接。 11 connections. Although the multilayer interdigital capacitor structure can solve the problem of higher cost of the MIM capacitor structure, its capacitance density is lower.

Based on this, in order to increase the capacitance density of the capacitor structure, the present application provides an integrated circuit based on the traditional interdigital capacitor structure. The integrated circuit is provided with multiple metal layers, and the integrated circuit is characterized in that Including a capacitor structure, the capacitor structure includes:

A first electrode and a second electrode; and

A plurality of metal strip arrays disposed on the multilayer metal layer, the metal strip array on each metal layer includes a plurality of metal strips extending in the same direction, and the metal strips in the metal strip array on each metal layer Is different from the extending direction of the metal bars in the metal array on the adjacent metal layer,

The metal strip in each metal layer includes a first pole metal strip and a second pole metal strip, the first pole metal strip is electrically connected to the first electrode; the second pole metal strip and the second electrode Electrical connection.

In this way, the capacitor structure included in the integrated circuit provided in the present application includes a plurality of metal strip arrays disposed on a plurality of metal layers, and the metal strip array on each metal layer includes a plurality of metal strips extending in the same direction. The metal bars in the metal bar array on each metal layer include a first pole metal bar and a second pole metal bar, and the first pole metal bar and the second pole metal bar are electrically connected to different electrodes, respectively. A lateral capacitor can be formed on the metal layer. In addition, the extending direction of the metal strips in the metal strip array on each metal layer is different from the extending direction of the metal strips in the metal array on the adjacent metal layer. Therefore, the Longitudinal capacitance may also be formed between the first and second metal strips projected on the plane where the layer is located.

It should be noted that, in the integrated circuit provided in the embodiment of the present application, a part that contributes to the prior art is mainly a capacitor structure included therein. In order to highlight the invention, the capacitor structure provided in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Please refer to FIG. 2 to FIG. 4, wherein FIG. 2 is a schematic view of the three-dimensional structure of the capacitor structure provided in the embodiment of the present application, FIG. 3 is a top view of the capacitor structure provided in the embodiment of the present application, and FIG. Sectional view in the II direction.

As shown in FIG. 2 to FIG. 4, the capacitor structure provided in the embodiment of the present application includes:

The first electrode E1 and the second electrode E2;

As an example, as shown in FIG. 2 and FIG. 4, the n metal layers are stacked in order from the bottom to the top: the first layer, the second layer, and so on, until the nth metal layer. n≥2, and n is a positive integer;

Each metal layer includes an array of metal bars. Each metal bar array includes at least two metal bars insulated from each other and spaced apart from each other, and the plurality of metal bars extend in the same direction. As an example, each metal strip array includes five metal strips that are insulated from each other as an example for illustration. As a more specific example, the metal bars on the same metal layer are parallel to each other. Moreover, in order to achieve an insulation interval between the metal bars, an insulating dielectric material is filled between adjacent metal bars.

In order to increase the capacitance density of the capacitor structure, the extending direction of the metal bars in the metal bar array on each metal layer is different from that of the metal bars in the metal array on the adjacent metal layer, and the metal in each metal layer The strip includes a first pole metal strip and a second pole metal strip, the first pole metal strip is electrically connected to the first electrode, and the second pole metal strip is electrically connected to the second electrode. In this way, a vertical capacitance can be formed between the first pole metal strip and the second pole metal strip that are overlapped and projected on the plane where the metal layer is located on the adjacent metal layer, thereby achieving the effect of increasing the capacitance density.

More specifically, in order to further increase the capacitance density of the capacitor structure, the projections of the metal bars of the metal bar array in each metal layer on adjacent metal layers intersect with the metal bars in the metal bar array on the adjacent metal layer. Stacked. In this way, a vertical capacitance can be formed between the first pole metal strip and the second pole metal strip on the adjacent metal layer, thereby achieving the effect of further increasing the capacitance density. For example, as shown in FIG. 2, the metal strip V1 on the second layer and the metal strip P2 on the first layer are respectively connected to different electrodes of the capacitor structure. Because the metal strips V1 and P2 are not parallel, there is an overlap between the metal strip V1 and the metal strip P2 on a vertical plane, and this overlap brings additional capacitance to the capacitor structure. A plurality of combinations similar to the metal strip V1 and the metal strip P2 on different metal layers, such as V1 and P2, P4, V2 and P1, P3, P5, etc., further improve the capacitance structure provided by the embodiment of the present invention. Capacitance density.

More specifically, the extending directions of the metal bars in the metal bar array on two adjacent metal layers are perpendicular to each other. Specifically, if the i-th metal layer and the i + 1th metal layer are set as two adjacent metal layers, the metal strips on the i-th metal layer and the metal strip array on the i + 1-th metal layer The extending directions of the metal bars in are perpendicular to each other, where i∈ {1,2,3, ..., n-1}.

As an example, as shown in FIG. 4, the extending direction of the metal strips on the first, third, and second j-1 metal layers is parallel to the paper surface, and the second, fourth, and second j metal layers The extending direction of the metal bars on the layer is perpendicular to the paper surface, where:

for

Round up the value. That is, in FIGS. 2 and 4, the extending direction of the metal strips on the odd-numbered layer is parallel to the paper surface direction, and the extending direction of the metal strips on the even-numbered metal layer is perpendicular to the paper surface direction. As an example, as shown in the figure, the metal strips on the odd-numbered layer are P1, P2, P3, P4, and P5 in order from the outside to the inside along the vertical direction of the paper, and the metal strips on the even-numbered layer are sequentially from left to right V1, V2, V3, V4, and V5.

It should be noted that, in the embodiment of the present application, in order to increase the capacitance density of the capacitor structure, as long as the extending directions of the metal strips on two adjacent metal layers are different, a vertical relationship is not necessarily required.

In addition, the n-stacked metal layers may be parallel to each other. However, due to the existence of a manufacturing process error, the n-stacked metal layers may have a substantially parallel positional relationship.

As an example of the present application, in order to increase the capacitance density of the capacitor structure, the first pole metal bars and the second pole metal bars on the metal bar array on the same metal layer are alternately disposed.

In order to achieve insulation between two adjacent metal layers, a dielectric layer (not shown in FIG. 2) is provided between the two adjacent metal layers, and in order to array the same polarity on the metal strip arrays on different metal layers. The metal bars are electrically connected together, and a plurality of conductive pillars extending in the same direction are provided on each dielectric layer. The plurality of conductive pillars extending in the same direction include a first-pole conductive pillar H1 and a second-pole conductive pillar H2 (see FIG. 3) And shown in Figure 4).

Among them, the first pole conductive pillar H1 is electrically connected to the first electrode, and the second pole conductive pillar H2 is electrically connected to the second electrode. The first pole metal strips in all the metal layers are connected to the first pole conductive pillar H1. Electrical connection; the second pole metal strips in all metal layers are electrically connected to the second pole conductive post H2.

Specifically, two ends of the first pole conductive pillar H1 are respectively connected to the first pole metal strips on two adjacent metal layers, and two ends of the second pole conductive pillar H2 are respectively connected to the two adjacent metal layers. The two second pole metal strips are connected. More specifically, the first pole conductive pillar H1 and the second pole conductive pillar H2 are perpendicular to between the two adjacent metal layers.

Because the electrodes connected to the first pole conductive pillar H1 and the second pole conductive pillar H2 are different, a capacitor can be formed between the first pole conductive pillar H1 and the second pole conductive pillar H2 in the same dielectric layer. The first pole conductive pillars H1 and the second pole conductive pillars H2 in the layer are alternately arranged, which can further increase the capacitance density. In the embodiment of the present invention, "the first pole conductive pillars H1 and the second pole conductive pillars H2 are alternately arranged" means that the second pole conductive pillars H1 adjacent to the first pole conductive pillars H1 are opposite to the second pole conductive pillars H2. Adjacent pole conductive pillars H2 are also first pole conductive pillars H1, so as to ensure that capacitance can be provided between adjacent conductive pillars. For example, in FIG. 3, the closest conductive pole H1 is the second diagonal conductive pole H2 in the diagonal direction, and the first pole conductive pole H1 at the middle position is further covered by four second pole conductive poles. H2 surrounds, thus providing capacitance in all four diagonal directions.

As an example, the specific structure of the capacitor structure in the embodiment of the present application will be described by taking the first electrode as the positive electrode of the capacitor structure and the second electrode as the negative electrode of the capacitor structure as an example.

As shown in FIG. 3, each metal strip P1 to P5 on the odd-numbered metal layer is a first pole metal strip, a second pole metal strip, a first pole metal strip, a second pole metal strip, and a first pole, respectively. Metal strips. Taking the first electrode as a positive electrode as an example, each of the metal strips P1 to P5 on the odd-numbered metal layer sequentially applies a positive voltage, a negative voltage, a positive voltage, a negative voltage, and a positive voltage, respectively.

Each of the metal strips V1 to V5 on the even-numbered metal layer is a first pole metal strip, a second pole metal strip, a first pole metal strip, a second pole metal strip, and a first pole metal strip, respectively. Since the first electrode is used as a positive electrode as an example, each of the metal strips V1 to V5 on the even-numbered metal layer sequentially applies a positive voltage, a negative voltage, a positive voltage, a negative voltage, and a positive voltage, respectively.

It can be seen from the figure that the odd-numbered metal strips P1, P3, and P5 and V1, V3, and V5 on each metal layer are connected together to form the positive electrode of the capacitor structure through the first electrode conductive pillar H1 on each dielectric layer. The even-numbered metal strips P2 and P4 and V2 and V4 on the metal layers of each layer are connected together through the second electrode conductive post H2 on each dielectric layer to form the negative electrode of the capacitor structure.

In the capacitor structure provided by the embodiment of the present invention, the metal bars on each metal layer are arranged into a three-dimensional three-dimensional grid structure, and adjacent metal bars of the same layer are connected to different electrodes of the capacitor, thereby achieving the same layer. The mixed capacitance effect between metal layers, between metal layers and between metal layers, and between adjacent conductive pillars makes the capacitance performance of the entire capacitor structure greatly amplified by the superposition of complex capacitance in the internal three-dimensional space.

Specifically, two adjacent metal strips on the same metal layer are connected to different electrodes, and a plurality of capacitors are formed on the same metal layer. The insulating dielectric material filled between the metal bars of the same metal layer is used as the dielectric material of the capacitor of the same layer. The insulating dielectric material filled between the metal bars can be selected according to the size of the formed capacitor. In order to form a capacitor structure with a higher capacitance value, the dielectric material can be selected from a dielectric material with a higher dielectric constant, for example, a high-k dielectric constant material commonly used in the semiconductor field, such as HfO ₂ .

Capacitors can also be formed between metal strips between two adjacent metal layers connected on different electrodes. For example, a capacitance may be formed between the metal strip P1 and the metal strip V2. Similarly, a capacitance may be formed between the metal strip P2 and the metal strip V1, and so on. In summary, a capacitor can be formed between the odd-numbered metal bars on the i-th layer and the even-numbered metal bars on the i + 1 layer. The dielectric layer between the two metal layers functions as a dielectric material for the capacitor. Therefore, the material of the dielectric layer can be selected according to the size of the formed capacitor. For example, silicon dioxide commonly used in the art can be selected. In order to form a capacitor structure with a higher capacitance value, the dielectric layer can be made of a dielectric material with a high dielectric constant, for example, a high-k dielectric constant material commonly used in the semiconductor field, such as HfO ₂ .

In addition, the first pole conductive pillar H1 and the second pole conductive pillar H2 located on the same dielectric layer are also connected to different electrodes. Therefore, the first pole conductive pillar H1 and the second pole conductive pillar H2 located on the same dielectric layer Capacitors can also be formed between them.

Therefore, in the capacitor structure provided in the embodiment of the present application, the capacitor may include a capacitor of the same metal layer, a capacitor of two adjacent metal layers, and a capacitor between conductive pillars. Therefore, it is beneficial to improve the capacitance density of the capacitor structure.

As an optional embodiment of the present application, in order to facilitate the manufacturing process of the capacitor structure, only two templates can be used to alternately generate metal layers. For example, as shown in FIG. 2, the metal layer of the first layer is uniformly laid with metal extending along the left and right. On the second layer, metal bars extending in the up-down direction are uniformly laid, and then the shape and position of the metal bars laid in the third metal layer are the same as those of the first layer.

In addition, the width of each metal strip on each metal layer may be the same or different. In order to further simplify the structure of the capacitor structure and facilitate the manufacturing process of the capacitor structure, as an example, the width of each metal strip on each metal layer is the same. In this example, each conductive pillar provided on each dielectric layer is provided. Align up and down, so that each first pole conductive pillar and each second pole conductive pillar form a multi-row arrangement structure.

As an example, the conductive pillar may be formed by forming a via in the dielectric layer and filling the via with a conductive material. The conductive material may be, for example, a metal. As another example, the conductive pillar may be a conductive structure plated with a copper layer on the surface of the via.

As a more specific example, the material of the conductive pillar may be copper or aluminum.

In addition, as a specific example of the present application, the material of each metal bar in the metal bar array on each metal layer may be copper or copper aluminum alloy.

The above is an example of the capacitor structure provided by the embodiment of the present application. The number of metal bars of each metal layer in the above example is not limited to the number of the above examples, in fact, the number of metal bars of each metal layer is at least two. In addition, the number of the first electrode metal bars and the second electrode metal bars of each metal layer is at least one. In order to form a capacitor structure with a higher capacitance density, the number of the first pole metal strip and the second pole metal strip on each metal layer may include at least two, and the first pole metal strip and the second metal strip on the same metal layer The pole metal strips are alternately distributed.

In the capacitor structure provided by the present application, a first pole conductive pillar between metal layers is used to electrically connect a first pole metal strip on each metal layer to a first electrode of the capacitor structure, and a second pole conductive pillar between metal layers is used. The second pole metal on each metal layer is electrically connected to the second electrode of the capacitor structure. In this way, the metal strips forming the first pole of the capacitor structure are connected together through the first pole conductive pillars between the metal layers, and the metal The second-pole conductive pillars between the layers connect the metal strips forming the second pole of the capacitor structure. This way, on the one hand, the useless space of the dielectric layer between the metal layers is used to realize the wiring between the capacitor plates and the electrodes, and On the one hand, the parallel and vertical conductive pillars connected to different electrodes can further provide capacitance and increase the capacitance density of the capacitor structure.

It should be noted that the metal bars V1 and V2 are labeled as the first electrodes E1 and E2 in FIG. 2, but in fact, in the capacitor structure provided by the embodiment of the present invention, the metal bars or conductive posts connected to the same electrode may be connected by metal wiring or The via is electrically connected to any of the same electrode points, and the electrode points can be on any one or more metal bars, or on any one or more conductive posts, or even a metal outside the capacitor structure. The wiring is used as an interface between the capacitor structure and an external circuit provided by the embodiment of the present invention. For example, as shown in FIG. 2, if the conductive posts V1 and V2 are used as the first electrodes E1 and E2, only the conductive posts and metal bars that need to be connected to the first electrode are electrically connected to the conductive post V1, and the second The conductive posts and metal bars of the electrodes are electrically connected to the conductive posts V2, and then connected to external circuits through the conductive posts V1 and V2. Of course, in the circuit structure of an actual product, the “electrode” in the embodiment of the present invention is also likely to be a virtual concept. The metal bars or conductive posts in the capacitor structure can be directly or indirectly connected to each other through multiple lines. On a signal path of an external circuit, it is only necessary to ensure that the first-pole type metal bar and the conductive post are finally electrically connected to each other, the second-pole type metal bar and the conductive post are finally electrically connected to each other, and the first-pole type metal bar The conductive pillar and the second-pole type metal strip and the conductive pillar are not electrically connected to each other, and eventually a capacitor can be provided in an external circuit.

The “electrical connection” described in the embodiments of the present application may be a direct connection or an indirect connection. For example, as shown in FIG. 2, the metal strip P1 is electrically connected to the first electrode E1 through the first conductive pillar H1 and the metal strip V1 connected to it.

Based on the capacitor structure provided in the foregoing embodiment, an embodiment of the present application further provides a semiconductor chip. The semiconductor chip includes a substrate and a capacitor structure located on the substrate. The capacitor structure is the capacitor structure provided in the above embodiment.

The foregoing is the specific implementation manner provided by the embodiment of the present application. It should be understood that the above-mentioned embodiments are only used to describe the technical solution of the present application, rather than limiting the present invention. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still The technical solutions described in the foregoing embodiments are modified, or some technical features are equivalently replaced; and these modifications or replacements do not deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

An integrated circuit in which a plurality of metal layers are provided, wherein the integrated circuit includes a capacitor structure, and the capacitor structure includes:

A first electrode and a second electrode; and

A plurality of metal strip arrays disposed on the multilayer metal layer, the metal strip array on each metal layer includes a plurality of metal strips extending in the same direction, and the metal strips in the metal strip array on each metal layer Is different from the extending direction of the metal bars in the metal array on the adjacent metal layer,

The metal strip in each metal layer includes a first pole metal strip and a second pole metal strip, the first pole metal strip is electrically connected to the first electrode; the second pole metal strip and the second electrode Electrical connection.
The integrated circuit according to claim 1, wherein the projection of the metal strips of the metal strip array in each metal layer on the adjacent metal layer and the metal in the metal strip array on the adjacent metal layer The bars overlap.
The integrated circuit according to claim 1 or 2, wherein the integrated circuit further comprises a plurality of conductive pillars extending in the same direction, wherein the plurality of parallel conductive pillars are disposed on two adjacent metals. Between layers,

The plurality of conductive pillars extending in the same direction include a first pole conductive pillar and a second pole conductive pillar, the first pole conductive pillar is electrically connected to the first electrode, and the second pole conductive pillar is connected to the first electrode The second electrode is electrically connected.
The integrated circuit according to claim 3, wherein two ends of the first conductive pillar are respectively connected to the first pole metal strip on two adjacent metal layers, and two of the second conductive pillar are The ends are respectively connected to two second pole metal bars on two adjacent metal layers.
The integrated circuit according to claim 3, wherein the first pole conductive pillars and the second pole conductive pillars are alternately disposed between the two adjacent metal layers.
The integrated circuit according to claim 3, wherein the first pole conductive pillar and the second pole conductive pillar are disposed between the adjacent two metal layers and are adjacent to the adjacent two metal layers. The metal layer is vertical.
The integrated circuit according to claim 1, wherein each of the metal bars in the metal bar array in the metal layer comprises at least two first pole metal bars or at least two second pole metal bars, each layer The first pole metal bars and the second pole metal bars in the metal bar array in the metal layer are alternately arranged.
The integrated circuit according to any one of claims 1 to 7, characterized in that the extending directions of the metal bars in the metal bar array on each adjacent two metal layers are perpendicular to each other.
The integrated circuit according to any one of claims 1 to 8, wherein the layer structures of the metal layers having the same extending direction of the metal strips are the same.
The integrated circuit according to any one of claims 1 to 9, wherein the width of each metal strip in the multilayer metal layers is equal, and is arranged above and below the first conductive pillar between the metal layers of each layer. Align, and / or, the second conductive pillars disposed between the metal layers of each layer are aligned vertically.