CN114725772A - EML chip structure with anti-reflection function and preparation method - Google Patents
EML chip structure with anti-reflection function and preparation method Download PDFInfo
- Publication number
- CN114725772A CN114725772A CN202210646936.6A CN202210646936A CN114725772A CN 114725772 A CN114725772 A CN 114725772A CN 202210646936 A CN202210646936 A CN 202210646936A CN 114725772 A CN114725772 A CN 114725772A
- Authority
- CN
- China
- Prior art keywords
- quantum well
- layer
- etching
- isolation region
- eam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/062—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
- H01S5/0625—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes in multi-section lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/12—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/3434—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer comprising at least both As and P as V-compounds
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention discloses an EML chip structure with an anti-reflection function and a preparation method thereof, wherein the preparation method comprises the following steps: the InP substrate, the grating layer, the grating covering layer and the conductive covering layer are sequentially stacked from bottom to top; the N-side electrode, the high-reflection coating layer, the anti-reflection coating layer and the conductive covering layer form a closed space; the high-reflection coating layer and the anti-reflection coating layer are oppositely arranged; the N-surface electrode and the conductive covering layer are arranged between the high-reflection coating layer and the anti-reflection coating layer and at two ends which are far away from each other; the DFB quantum well and the EAM quantum well are positioned on the InP substrate; a grating layer is arranged on the DFB quantum well, and the grating covering layer covers the DFB quantum well; the conductive covering layer covers the grating covering layer; the DFB light source electrode, the EAM absorption electrode and the light isolation region electrode are arranged on the upper surface of the conductive covering layer; the first isolation region, the second isolation region, and the third isolation region are located inside the conductive cap layer. The invention has the advantages of easy operation, obvious improvement effect and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductor laser chip preparation, and relates to an EML chip structure with an anti-reflection function and a preparation method thereof.
Background
The explosive growth of data traffic on the internet has resulted in a strong demand for higher speed optical systems, which has presented a greater challenge to the increasing demands on optical communication technology. There is therefore a need to develop higher speed transmission systems in which electro-absorption modulated lasers (EMLs) play an important role. Electro-absorption modulated lasers (EMLs) combine the excellent single-mode performance of Distributed Feedback (DFB) lasers with the high modulation efficiency of electro-absorption modulators EAM, which are integrated with (DFB) Laser Diodes (LDs) (EMLs) for their high speed and ease of use, with a wide range of medium and long distance optical transmitters. The EML has the working principle that when no external electric field exists, the wavelength of modulated light is outside an EAM absorption curve, and light signals almost pass through the EAM without loss; after a certain electric field is applied, the absorption curve of the EAM moves to the long wavelength, and the modulated light wavelength generates strong absorption, so that the on-off control of the laser is realized. Due to hole accumulation effects in the Quantum Well (QW) absorbing layer of the EAM, the EML frequency chirp increases with increasing EAM optical output power, thereby affecting optical power. Secondly, the reflection of light in the EAM can cause corresponding optical disturbance, and the side mode suppression ratio, the absorption curve and the optical power can be influenced during high-speed modulation. Therefore, how to reduce the chirp and reduce the light reflection is an important index for the EML to improve the laser performance.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides an EML chip structure with an anti-reflection function and a preparation method thereof, which can effectively reduce the end light reflection, reduce the chirp effect of an EML laser and meet the requirement of farther distance transmission.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
an EML chip structure having an anti-reflection function, comprising: the light-emitting diode comprises an N-surface electrode, a high-reflection coating layer, an anti-reflection coating layer, a conductive covering layer, an InP substrate, a DFB quantum well, an EAM quantum well, a grating layer, a grating covering layer, a DFB light source electrode, an EAM absorption electrode, a light isolation region electrode, a first isolation region, a second isolation region and a third isolation region;
the InP substrate, the grating layer, the grating covering layer and the conductive covering layer are sequentially stacked from bottom to top;
the N-side electrode, the high-reflection coating layer, the anti-reflection coating layer and the conductive covering layer form a closed space;
the high-reflection coating layer and the anti-reflection coating layer are arranged oppositely; the N-surface electrode and the conductive covering layer are arranged between the high-reflection coating layer and the anti-reflection coating layer and at two ends which are far away from each other;
the DFB quantum well and the EAM quantum well are positioned on the InP substrate;
a grating layer is arranged on the DFB quantum well, and the grating covering layer covers the DFB quantum well;
the conductive covering layer covers the grating covering layer; the DFB light source electrode, the EAM absorption electrode and the light isolation region electrode are arranged on the upper surface of the conductive covering layer;
the first isolation region, the second isolation region and the third isolation region are located inside the conductive covering layer.
The invention is further improved in that:
the DFB quantum well is made of InGaAsP; the DFB quantum well is positioned on the InP substrate and specifically comprises the following steps: obtaining a DFB quantum well on the InP substrate by adopting an MOCVD growth technology; the growth temperature is 600 ℃ and 800 ℃; the thickness of the grating covering layer is 100-200 nm.
The first isolation region is positioned in the middle of the upper surface of the conductive covering layer; the second isolation region and the third isolation region are located on the left side and the right side of the optical isolation region electrode.
Also includes a docking area; the butt-joint region is positioned between the DFB quantum well and the EAM quantum well; the grating structure also comprises a SiyOx mask layer, wherein the SiyOx mask layer covers the grating covering layer; etching one end of the SiyOx mask layer and one end of the grating covering layer by using a photoetching technology, and etching to the bottom of the DFB quantum well by using a wet etching method and a dry etching method to obtain a first etching area; growing an EAM quantum well in the first etching area by using an MOCVD selective area growth technology; etching the SiyOx mask layer above the junction of the EAM quantum well and the DFB quantum well, etching the contact area of the DFB quantum well and the EAM quantum well to obtain a second etching area, and generating InGaAsP in the second etching area to form a butt joint area.
The EAM quantum well is a tensile strain quantum well with a double-barrier structure; the EAM quantum well comprises a potential barrier and a potential well; the potential barriers comprise long-wavelength potential barriers and short-wavelength potential barriers, wherein the long-wavelength potential barriers are 1150-1250nm, and the short-wavelength potential barriers are 1050-1150 nm; the growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence; wherein the potential barrier is compressive stress, the stress range is +0.1 to +0.5 percent, the potential well is tensile stress, and the stress range is-0.2 to-0.7 percent.
The conductive covering layer covers the grating covering layer, and specifically comprises: etching the residual SiyOx mask layer, and growing a conductive covering layer on the grating covering layer by using MOCVD (metal organic chemical vapor deposition); the range of x/y in the SiyOx mask layer is 1.5-2.
A preparation method of an EML chip with an anti-reflection function comprises the following steps:
obtaining a DFB quantum well on the InP substrate by adopting an MOCVD growth technology, etching a grating layer on the DFB quantum well by adopting a photoetching technology, and obtaining a grating covering layer on the grating layer by adopting the MOCVD growth technology;
generating a SiyOx mask layer on the grating covering layer, etching one end of the SiyOx mask layer and one end of the grating covering layer by using a photoetching technology, and etching to the bottom of the DFB quantum well by using wet etching and dry etching to stop so as to obtain a first etching area; growing an EAM quantum well in the first etching area by using an MOCVD selective area growth technology;
etching the residual SiyOx mask layer by using wet etching, and growing a conductive covering layer by using MOCVD (metal organic chemical vapor deposition); etching a first isolation region, a second isolation region and a third isolation region on the conductive covering layer by using a photoetching technology and wet etching; carrying out MOCVD selective area growth on a semi-insulating InP layer in the first isolation area, the second isolation area and the third isolation area to form an electric isolation area; or injecting gas atoms into the first isolation region, the second isolation region and the third isolation region to form an optical isolation region;
forming a whole-surface electrode on the upper surface of the conductive covering layer by using a metallization technology, and stripping the whole-surface electrode by using a photoetching technology and a stripping technology to obtain a DFB light source electrode, an EAM absorption electrode and an optical isolation region electrode;
forming an N-surface electrode on the lower surface of the InP substrate by using a metallization technology; and manufacturing a high-reflection coating layer on one side of the DFB quantum well by using a coating technology, and forming an anti-reflection coating layer on one side of the EAM quantum well.
And etching the SiyOx mask layer above the junction of the EAM quantum well and the DFB quantum well by using wet etching, etching the contact area of the DFB quantum well and the EAM quantum well by using a photoetching technology to obtain a second etching area, and generating InGaAsP in the second etching area to form a butt joint area.
The range of x/y in the SiyOx mask layer is 1.5-2; the growth temperature of the DFB quantum well is 600-800 ℃; the thickness of the grating covering layer is 100-200 nm.
The wavelength of the growth material in the butt joint region is 1000-1200 nm;
the semi-insulating InP layer is made of a semi-insulating material, the semi-insulating material is an InP material doped with Cr, Ru, Fe and Ti, and the doping range is 5E 17-2E 18; the gas atoms are H2, Ar2 and O2, and the doping range is 8E 17-2E 9;
the EAM quantum well is a tensile strain quantum well with a double-barrier structure; the EAM quantum well comprises a potential barrier and a potential well; the potential barriers comprise long-wavelength potential barriers and short-wavelength potential barriers, wherein the long-wavelength potential barriers are 1150-1250nm, and the short-wavelength potential barriers are 1050-1150 nm; the growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence; wherein the potential barrier is compressive stress, the stress range is +0.1 to +0.5 percent, the potential well is tensile stress, and the stress range is-0.2 to-0.7 percent.
Compared with the prior art, the invention has the following beneficial effects:
the invention can effectively absorb the reflected light by using the electrode of the optical isolation area, and can achieve excellent anti-reflection effect; by applying reverse voltage to the isolation region, reflected light is continuously absorbed after the reverse voltage acts on the EAM quantum well, light disturbance is reduced, charge accumulation caused by photoproduction holes is absorbed, and the anti-reflection characteristic of the laser is enhanced.
Furthermore, the invention adopts the EAM quantum well as the tensile strain quantum well with the double-barrier structure, adopts the double-barrier tensile strain absorption layer to reduce the chirp of the EAM without sacrificing the extinction ratio characteristic, and introduces enough asymmetry into the quantum well structure of the EAM to change the wave function of electrons and holes in the potential well under the action of an electric field, thereby effectively reducing the chirp through the quenching of the absorption peak and the red shift of the absorption edge.
Drawings
In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a top view of an EML chip with an anti-reflection function according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a DFB quantum well and an EAM quantum well in direct butt joint according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an embodiment of the present invention in which the DFB quantum well and the EAM quantum well are indirectly connected;
FIG. 4 is a schematic structural diagram of the DFB quantum well, the grating layer and the grating cap layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first etching region according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure for forming an EAM quantum well according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of generating a docking area according to an embodiment of the present invention.
The solar cell comprises a 1-InP substrate, a 2-N surface electrode, a 3-DFB quantum well, a 4-EAM quantum well, a 5-grating layer, a 6-conductive covering layer, a 7-butt joint region, an 8-DFB light source electrode, a 9-first isolation region, a 10-EAM absorption electrode, a 11-second isolation region, a 12-third isolation region, a 13-grating covering layer, a 14-high-reflection coating layer, a 15-anti-reflection coating layer, a 16-first etching region, a 17-second etching region and an 18-optical isolation region electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the present invention is used, the description is merely for convenience and simplicity, and the indication or suggestion that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, cannot be understood as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1, 2 and 3, the present invention discloses an EML chip structure with an anti-reflection function, including: the light source device comprises an N-surface electrode 2, a high-reflection coating layer 14, an anti-reflection coating layer 15, a conductive covering layer 6, an InP substrate 1, a DFB quantum well 3, an EAM quantum well 4, a grating layer 5, a grating covering layer 13, a DFB light source electrode 8, an EAM absorption electrode 10, a light isolation region electrode 18, a first isolation region 9, a second isolation region 11 and a third isolation region 12;
the N-face electrode 2, the InP substrate 1, the grating layer 5, the grating covering layer 13 and the conductive covering layer 6 are sequentially stacked from bottom to top;
the N-side electrode 2, the high-reflection coating layer 14, the anti-reflection coating layer 15 and the conductive covering layer 6 form a closed space;
the high-reflection coating layer 14 and the anti-reflection coating layer 15 are oppositely arranged; the N-face electrode 2 and the conductive covering layer 6 are arranged between the high-reflection coating layer 14 and the anti-reflection coating layer 15 and at two ends which are far away from each other;
the DFB quantum well 3 and the EAM quantum well 4 are positioned on the InP substrate 1;
a grating layer 5 is arranged on the DFB quantum well 3, and a grating covering layer 13 covers the DFB quantum well 3;
the conductive covering layer 6 covers the grating covering layer 13; the DFB light source electrode 8, the EAM absorption electrode 10 and the optical isolation region electrode 18 are arranged on the upper surface of the conductive covering layer 6;
the first isolation region 9, the second isolation region 11 and the third isolation region 12 are located inside the conductive covering layer 6.
The DFB quantum well 3 is made of InGaAsP; the DFB quantum well 3 is located on the InP substrate 1, and specifically includes: obtaining a DFB quantum well 3 on the InP substrate 1 by adopting an MOCVD growth technology; the growth temperature is 600-800 ℃; the thickness of the grating covering layer 13 is 100-200 nm.
A first isolation region 9 is located in the middle of the upper surface of the conductive cap layer 6; the second isolation region 11 and the third isolation region 12 are located on both left and right sides of the optical isolation region electrode 18.
And a docking area 7; the butt-joint region 7 is positioned between the DFB quantum well 3 and the EAM quantum well 4; the grating structure further comprises a SiyOx mask layer, wherein the SiyOx mask layer covers the grating covering layer 13; etching one end of the SiyOx mask layer and one end of the grating covering layer 13 by using a photoetching technology, and etching to the bottom of the DFB quantum well 3 by using a wet etching method and a dry etching method to obtain a first etching area 16; growing the EAM quantum well 4 in the first etch region 16 using MOCVD selective area growth techniques; etching the SiyOx mask layer above the junction of the EAM quantum well 4 and the DFB quantum well 3, simultaneously etching the contact area of the DFB quantum well 3 and the EAM quantum well 4 to obtain a second etching area 17, and generating InGaAsP in the second etching area 17 to form a butt joint area 7.
The EAM quantum well 4 is a tensile strain quantum well with a double-barrier structure; the EAM quantum well 4 comprises a potential barrier and a potential well; the potential barriers comprise long-wavelength potential barriers and short-wavelength potential barriers, wherein the long-wavelength potential barriers are 1150-1250nm, and the short-wavelength potential barriers are 1050-1150 nm; the growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence; wherein the potential barrier is compressive stress, the stress range is +0.1 to +0.5 percent, the potential well is tensile stress, and the stress range is-0.2 to-0.7 percent.
The conductive covering layer 6 covers the grating covering layer 13, and specifically includes: etching the residual SiyOx mask layer, and growing a conductive covering layer 6 on the grating covering layer 13 by using MOCVD; the range of x/y in the SiyOx mask layer is 1.5-2.
A preparation method of an EML chip with an anti-reflection function comprises the following steps:
depositing and growing a DFB quantum well 3 on the InP substrate 1 by adopting MOCVD, wherein the adopted material is InGaAsP, and the growth temperature is 600-800 ℃; and etching the grating layer 5 on the DFB quantum well 3 by adopting a photoetching technology, and obtaining a grating covering layer 13 on the grating layer 5 by adopting an MOCVD growth technology, wherein the growth thickness is 100-200 nm.
And generating a SiyOx mask on the grating covering layer 13 by using vapor deposition, wherein x/y is between 1.5 and 2, etching the SiyOx mask layer and one end of the grating covering layer 13 by using a photoetching technology, and etching to the bottom of the DFB quantum well 3 by using a wet etching method and a dry etching method to stop to obtain a first etching area 16.
Growing the EAM quantum well 4 in the first etch region 16 using MOCVD selective area growth techniques; the EAM quantum well adopts a double-barrier structure tensile strain quantum well. The EAM quantum well 4 comprises a potential barrier and a potential well; the potential barrier adopts two wavelengths, namely one long and one short. The long wavelength potential barrier 1150-1250nm and the short wavelength potential barrier 1050-1150 nm. The growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier cycle structure in sequence, and the potential well potential barrier cycle number is 4-10 times. Wherein the potential barrier is compressive stress, the stress range is +0.1 to +0.5 percent, the potential well is tensile stress, and the stress range is-0.2 to-0.7 percent. And after the EAM quantum well is grown, direct butt joint is completed.
Etching the residual SiyOx mask layer by using wet etching, and growing a conductive covering layer 6 by using MOCVD; etching a first isolation region 9, a second isolation region 11 and a third isolation region 12 on the conductive covering layer 6 by using a photoetching technology and wet etching; carrying out MOCVD on the first isolation region 9, the second isolation region 11 and the third isolation region 12 to selectively grow a semi-insulating InP layer to form an electric isolation region, wherein the semi-insulating InP layer is made of a semi-insulating material, the semi-insulating material is an InP material doped with Cr, Ru, Fe and Ti, and the doping range is 5E 17-2E 18; or injecting gas atoms H2, Ar2 and O2 in the first isolation region 9, the second isolation region 11 and the third isolation region 12, wherein the doping range is 8E 17-2E 9, and forming a light isolation region.
Forming a whole-surface electrode on the upper surface of the conductive covering layer 6 by using a metallization technology, and stripping the whole-surface electrode by using a photoetching technology and a stripping technology to obtain a DFB light source electrode 8, an EAM absorption electrode 10 and a light isolation region electrode 18; forming an N-face electrode 2 on the lower surface of the InP substrate 1 by using a metallization technology; and (3) manufacturing a high-reflection coating layer 14 on one side of the DFB quantum well 3 by using a coating technology, and forming an anti-reflection coating layer 15 on one side of the EAM quantum well 4.
Further comprising: and etching the SiyOx mask layer above the junction of the EAM quantum well 4 and the DFB quantum well 3 by using wet etching, simultaneously etching the contact area of the DFB quantum well 3 and the EAM quantum well 4 by using a photoetching technology to obtain a second etching area 17, and generating InGaAsP in the second etching area 17, wherein the wavelength is 1000-1200 nm. Forming a docking area 7.
The light isolation region electrode can effectively absorb reflected light, and an excellent anti-reflection effect can be achieved; and secondly, a double-barrier tensile stress quantum well is used, the double-barrier tensile strain absorption layer is adopted to reduce the chirp of the EAM without sacrificing the extinction ratio characteristic, and sufficient asymmetry is introduced into the quantum well structure of the EAM to change the wave function of electrons and holes in a potential well under the action of an electric field, so that the chirp is effectively reduced through the quenching of an absorption peak and the red shift of an absorption edge. The whole process only needs to manufacture electrodes, or a long-short wavelength potential barrier is added in the quantum well growth process, a tensile strain potential well and a compressive strain potential barrier are grown, the process operation is simple, and the effect is obvious.
The specific method of the invention is described in detail below with reference to the accompanying drawings and specific process steps:
example 1:
referring to fig. 4, 5 and 6, the DFB quantum well 3 is grown on the InP substrate 1 by MOCVD using InGaAsP as a material at 750 ℃; and etching the grating layer 5 on the DFB quantum well by adopting a photoetching technology, and obtaining a grating covering layer 13 on the grating layer 5 by adopting an MOCVD growth technology, wherein the growth thickness is 150 nm.
Generating a SiyOx mask layer on the grating covering layer 13, wherein x/y = 2, etching the SiyOx mask layer and one end of the grating covering layer 13 by using a photoetching technology, and etching to the bottom of the DFB quantum well 3 by using wet etching and dry etching to obtain a first etching area 16; growing the EAM quantum well 4 in the first etch region 16 using MOCVD selective area growth techniques;
growing the EAM quantum well 4 in the first etch region 16 using MOCVD selective area growth techniques; the EAM quantum well adopts a double-barrier structure tensile strain quantum well. The EAM quantum well 4 comprises a potential barrier and a potential well; the potential barrier adopts two wavelengths, namely one long and one short. The long-wavelength barrier is 1200nm, and the short-wavelength barrier is 1100 nm. The growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence, and the potential well potential barrier circulating number is 8 times. The potential barrier comprises a long-wavelength potential barrier and a short-wavelength potential barrier, wherein the short-wavelength potential barrier is compressive stress, the stress range is +0.3%, the potential well is tensile stress, and the stress range is-0.45%. And after the EAM quantum well is grown, direct butt joint is completed.
Etching the residual SiyOx mask layer by using wet etching, and growing a conductive covering layer 6 by using MOCVD; etching a first isolation region 9, a second isolation region 11 and a third isolation region 12 on the conductive covering layer 6 by using a photoetching technology and wet etching; carrying out MOCVD on the first isolation region 9, the second isolation region 11 and the third isolation region 12 to selectively grow a semi-insulating InP layer to form an electrical isolation region, wherein the semi-insulating InP layer is made of a semi-insulating material, the semi-insulating material is a Cr-doped InP material, and the doping range is 9E 17.
Forming a whole-surface electrode on the upper surface of the conductive covering layer 6 by using a metallization technology, and stripping the whole-surface electrode by using a photoetching technology and a stripping technology to obtain a DFB light source electrode 8, an EAM absorption electrode 10 and a light isolation region electrode 18; forming an N-face electrode 2 on the lower surface of the InP substrate 1 by using a metallization technology; and (3) manufacturing a high-reflection coating layer 14 on one side of the DFB quantum well 3 by using a coating technology, and forming an anti-reflection coating layer 15 on one side of the EAM quantum well 4.
According to experimental data, when-0-2V voltage is applied to the electrode of the optical isolation region, the anti-reflectivity effect can reach 1.35 times that of the traditional EML laser chip without the electrode of the isolation region; compared with a traditional EML laser chip, the chirp of the adopted double-barrier tensile strain quantum well EAM is reduced to 10% of that of the traditional laser.
Example 2
Growing a DFB quantum well 3 on the InP substrate 1 by adopting MOCVD, wherein the adopted material is InGaAsP, and the growth temperature is 750 ℃; and etching the grating layer 5 on the DFB quantum well by adopting a photoetching technology, and obtaining a grating covering layer 13 on the grating layer 5 by adopting an MOCVD growth technology, wherein the growth thickness is 150 nm.
Generating a SiyOx mask layer on the grating covering layer 13, wherein x/y = 2, etching the SiyOx mask layer and one end of the grating covering layer 13 by using a photoetching technology, and etching to the bottom of the DFB quantum well 3 by using wet etching and dry etching to obtain a first etching area 16; growing an EAM quantum well 4 in the first etch zone 16 using an MOCVD selective zone growth technique;
referring to fig. 4, 5 and 7, the EAM quantum well 4 is grown in the first etch zone 16 using MOCVD selective zone growth techniques; the EAM quantum well adopts a double-barrier structure tensile strain quantum well. The EAM quantum well 4 comprises a potential barrier and a potential well; the potential barrier adopts two wavelengths, namely one long and one short. The long-wavelength barrier is 1200nm, and the short-wavelength barrier is 1100 nm. The growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence, and the potential well potential barrier circulating number is 8 times. The potential barrier comprises a long-wavelength potential barrier and a short-wavelength potential barrier, wherein the short-wavelength potential barrier is compressive stress, the stress range is +0.3%, the potential well is tensile stress, and the stress range is-0.45%. After the growth is finished, etching the SiyOx mask layer above the junction of the EAM quantum well 4 and the DFB quantum well 3 by using wet etching, simultaneously etching the contact area of the DFB quantum well 3 and the EAM quantum well 4 by using a photoetching technology to obtain a second etching area 17, generating InGaAsP in the second etching area 17, wherein the wavelength is 1200nm, and forming a butt joint area 7.
Etching the residual SiyOx mask layer by using wet etching, and growing a conductive covering layer 6 by using MOCVD; etching a first isolation region 9, a second isolation region 11 and a third isolation region 12 on the conductive covering layer 6 by using a photoetching technology and wet etching; carrying out MOCVD on the first isolation region 9, the second isolation region 11 and the third isolation region 12 to selectively grow a semi-insulating InP layer to form an electric isolation region, wherein the semi-insulating InP layer is made of a semi-insulating material, the semi-insulating material is a Cr-doped InP material, and the doping range is 9E 17.
Forming a whole-surface electrode on the upper surface of the conductive covering layer 6 by using a metallization technology, and stripping the whole-surface electrode by using a photoetching technology and a stripping technology to obtain a DFB light source electrode 8, an EAM absorption electrode 10 and a light isolation region electrode 18; forming an N-face electrode 2 on the lower surface of the InP substrate 1 by using a metallization technology; a high-reflection coating 14 is formed on one side of the DFB quantum well 3 by using a coating technique, and an anti-reflection coating 15 is formed on one side of the EAM quantum well 4.
According to experimental data, when-0-2V voltage is applied to the electrode of the optical isolation region, the anti-reflectivity effect can reach 1.25 times that of the traditional EML laser chip without the electrode of the isolation region; compared with a traditional EML laser chip, the chirp of the adopted double-barrier tensile strain quantum well EAM is reduced to 15% of that of the traditional laser.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An EML chip structure having an antireflection function, comprising: the light-emitting diode comprises an N-surface electrode (2), a high-reflection coating layer (14), an anti-reflection coating layer (15), a conductive coating layer (6), an InP substrate (1), a DFB quantum well (3), an EAM quantum well (4), a grating layer (5), a grating coating layer (13), a DFB light source electrode (8), an EAM absorption electrode (10), a light isolation region electrode (18), a first isolation region (9), a second isolation region (11) and a third isolation region (12);
the InP substrate comprises an N-surface electrode (2), an InP substrate (1), a grating layer (5), a grating covering layer (13) and a conductive covering layer (6), which are sequentially stacked from bottom to top;
the N-side electrode (2), the high-reflection coating layer (14), the anti-reflection coating layer (15) and the conductive covering layer (6) form a closed space;
the high-reflection coating layer (14) and the anti-reflection coating layer (15) are arranged oppositely; the N-surface electrode (2) and the conductive covering layer (6) are arranged between the high-reflection coating layer (14) and the anti-reflection coating layer (15) and at two ends which are far away from each other;
the DFB quantum well (3) and the EAM quantum well (4) are positioned on the InP substrate (1);
a grating layer (5) is arranged on the DFB quantum well (3), and the grating covering layer (13) covers the DFB quantum well (3);
the conductive covering layer (6) covers the grating covering layer (13); the DFB light source electrode (8), the EAM absorption electrode (10) and the optical isolation region electrode (18) are arranged on the upper surface of the conductive covering layer (6);
the first isolation region (9), the second isolation region (11) and the third isolation region (12) are located inside the conductive covering layer (6).
2. The EML chip structure with antireflection function according to claim 1, characterized in that the material of the DFB quantum well (3) is InGaAsP; the DFB quantum well (3) is positioned on the InP substrate (1) and specifically comprises the following steps: obtaining a DFB quantum well (3) on the InP substrate (1) by adopting an MOCVD growth technology; the growth temperature is 600-800 ℃; the thickness of the grating covering layer (13) is 100-200 nm.
3. The EML chip structure with anti-reflection functionality according to claim 2, wherein said first isolation region (9) is located in the middle of the upper surface of the conductive covering layer (6); the second isolation region (11) and the third isolation region (12) are positioned at the left and right sides of the optical isolation region electrode (18).
4. The EML chip structure with antireflection function according to claim 3, characterized by further comprising a docking area (7); the butt-joint region (7) is positioned between the DFB quantum well (3) and the EAM quantum well (4); the grating structure further comprises a SiyOx mask layer, wherein the SiyOx mask layer covers the grating covering layer (13); etching one end of the SiyOx mask layer and one end of the grating covering layer (13) by using a photoetching technology, and etching to the bottom of the DFB quantum well (3) by using a wet etching method and a dry etching method to stop so as to obtain a first etching area (16); growing the EAM quantum well (4) in a first etch zone (16) using a MOCVD selective zone growth technique; and etching the SiyOx mask layer above the junction of the EAM quantum well (4) and the DFB quantum well (3), simultaneously etching the contact area of the DFB quantum well (3) and the EAM quantum well (4) to obtain a second etching area (17), and generating InGaAsP in the second etching area (17) to form a butt joint area (7).
5. The EML chip structure with anti-reflection function according to claim 4, wherein the EAM quantum well (4) is a tensile strained quantum well with a double barrier structure; the EAM quantum well (4) comprises a potential barrier and a potential well; the potential barriers comprise long-wavelength potential barriers and short-wavelength potential barriers, wherein the long-wavelength potential barriers are 1150-1250nm, and the short-wavelength potential barriers are 1050-1150 nm; the growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence; wherein the potential barrier is compressive stress, the stress range is +0.1 to +0.5 percent, the potential well is tensile stress, and the stress range is-0.2 to-0.7 percent.
6. The EML chip structure with anti-reflection function according to claim 5, wherein the conductive coating layer (6) is coated on the grating coating layer (13), specifically: etching the residual SiyOx mask layer, and growing a conductive covering layer (6) on the grating covering layer (13) by using MOCVD; the range of x/y in the SiyOx mask layer is 1.5-2.
7. The method for preparing the EML chip with the anti-reflection function according to claim 6, comprising:
obtaining a DFB quantum well (3) on an InP substrate (1) by adopting an MOCVD growth technology, etching a grating layer (5) on the DFB quantum well (3) by adopting a photoetching technology, and obtaining a grating covering layer (13) on the grating layer (5) by adopting the MOCVD growth technology;
generating a SiyOx mask layer on the grating covering layer (13), etching the SiyOx mask layer and one end of the grating covering layer (13) by using a photoetching technology, and etching to the bottom of the DFB quantum well (3) by using wet etching and dry etching to stop so as to obtain a first etching area (16); growing an EAM quantum well (4) in a first etch zone (16) using a MOCVD selective zone growth technique;
etching the residual SiyOx mask layer by using wet etching, and growing a conductive covering layer (6) by using MOCVD; etching a first isolation region (9), a second isolation region (11) and a third isolation region (12) on the conductive covering layer (6) by using a photoetching technology and wet etching; carrying out MOCVD selective area growth on a semi-insulating InP layer in the first isolation area (9), the second isolation area (11) and the third isolation area (12) to form an electric isolation area; or gas atoms are injected into the first isolation region (9), the second isolation region (11) and the third isolation region (12) to form a light isolation region;
forming a whole-surface electrode on the upper surface of the conductive covering layer (6) by using a metallization technology, and stripping the whole-surface electrode by using a photoetching technology and a stripping technology to obtain a DFB light source electrode (8), an EAM absorption electrode (10) and an optical isolation region electrode (18);
forming an N-face electrode (2) on the lower surface of the InP substrate (1) by using a metallization technology; and (3) manufacturing a high-reflection coating layer (14) on one side of the DFB quantum well (3) by using a coating technology, and forming an anti-reflection coating layer (15) on one side of the EAM quantum well (4).
8. The method for manufacturing the EML chip with the anti-reflection function according to claim 7, further comprising etching the SiyOx mask layer above the boundary between the EAM quantum well (4) and the DFB quantum well (3) by using a wet etching process, simultaneously etching the contact region between the DFB quantum well (3) and the EAM quantum well (4) by using a photolithography technique to obtain a second etching region (17), and forming InGaAsP in the second etching region (17) to form the butt-joint region (7).
9. The method for manufacturing an EML chip with an anti-reflective function according to claim 8, wherein the range of x/y in the SiyOx mask layer is 1.5-2; the growth temperature of the DFB quantum well (3) is 600-800 ℃; the thickness of the grating covering layer (13) is 100-200 nm.
10. The method as claimed in claim 9, wherein the wavelength of the growth material of the butt-joint region (7) is 1000-1200 nm;
the semi-insulating InP layer is made of a semi-insulating material, the semi-insulating material is an InP material doped with Cr, Ru, Fe and Ti, and the doping range is 5E 17-2E 18; the gas atoms are H2, Ar2 and O2, and the doping range is 8E 17-2E 9;
the EAM quantum well (4) is a tensile strain quantum well with a double-barrier structure; the EAM quantum well (4) comprises a potential barrier and a potential well; the potential barriers comprise long-wavelength potential barriers and short-wavelength potential barriers, wherein the long-wavelength potential barriers are 1150-1250nm, and the short-wavelength potential barriers are 1050-1150 nm; the growth structure is a potential well, a short-wavelength potential barrier and a long-wavelength potential barrier circulating structure in sequence; wherein the potential barrier is compressive stress, the stress range is +0.1 to +0.5 percent, the potential well is tensile stress, and the stress range is-0.2 to-0.7 percent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210646936.6A CN114725772A (en) | 2022-06-09 | 2022-06-09 | EML chip structure with anti-reflection function and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210646936.6A CN114725772A (en) | 2022-06-09 | 2022-06-09 | EML chip structure with anti-reflection function and preparation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114725772A true CN114725772A (en) | 2022-07-08 |
Family
ID=82232557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210646936.6A Pending CN114725772A (en) | 2022-06-09 | 2022-06-09 | EML chip structure with anti-reflection function and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114725772A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115377799A (en) * | 2022-08-18 | 2022-11-22 | 武汉敏芯半导体股份有限公司 | Electro-absorption modulation laser chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100290489A1 (en) * | 2009-05-15 | 2010-11-18 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | electro-absorption modulated laser (eml) assembly having a 1/4 wavelength phase shift located in the forward portion of the distributed feedback (dfb) of the eml assembly, and a method |
| CN206820249U (en) * | 2017-06-12 | 2017-12-29 | 陕西源杰半导体技术有限公司 | A kind of electro-absorption modulation semiconductor laser chip of antireflection |
| WO2020093189A1 (en) * | 2018-11-05 | 2020-05-14 | 华为技术有限公司 | Anti-reflection laser |
| CN114188823A (en) * | 2021-11-03 | 2022-03-15 | 江苏华兴激光科技有限公司 | Preparation method of refrigeration-free anti-reflection InP-based quantum dot/quantum well coupled EML epitaxial wafer |
-
2022
- 2022-06-09 CN CN202210646936.6A patent/CN114725772A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100290489A1 (en) * | 2009-05-15 | 2010-11-18 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | electro-absorption modulated laser (eml) assembly having a 1/4 wavelength phase shift located in the forward portion of the distributed feedback (dfb) of the eml assembly, and a method |
| CN206820249U (en) * | 2017-06-12 | 2017-12-29 | 陕西源杰半导体技术有限公司 | A kind of electro-absorption modulation semiconductor laser chip of antireflection |
| WO2020093189A1 (en) * | 2018-11-05 | 2020-05-14 | 华为技术有限公司 | Anti-reflection laser |
| CN114188823A (en) * | 2021-11-03 | 2022-03-15 | 江苏华兴激光科技有限公司 | Preparation method of refrigeration-free anti-reflection InP-based quantum dot/quantum well coupled EML epitaxial wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115377799A (en) * | 2022-08-18 | 2022-11-22 | 武汉敏芯半导体股份有限公司 | Electro-absorption modulation laser chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7476558B2 (en) | Method for manufacturing selective area grown stacked-layer electro-absorption modulated laser structure | |
| US8319229B2 (en) | Optical semiconductor device and method for manufacturing the same | |
| CN112290382B (en) | Semiconductor laser and manufacturing method thereof | |
| CN107611776B (en) | Gain coupling distributed feedback semiconductor laser and manufacturing method thereof | |
| CN100391069C (en) | Device structure and its production for single-modulus quantum cascade laser | |
| CN106711761A (en) | Preparation method of DFB (Distributed Feedback) semiconductor laser device and laser device prepared by preparation method | |
| CN101316027A (en) | Production method of quantum well edge-emission semiconductor laser | |
| CN101938083B (en) | Manufacture method of bi-distributed feedback laser double-amplifier based on gamma waveguide | |
| CN105576502B (en) | High velocity vertical transmitting single-chip integration type directly modulates Distributed Feedback Laser and production method | |
| CN114649742B (en) | Efficient vertical cavity surface EML chip and preparation method thereof | |
| CN114725772A (en) | EML chip structure with anti-reflection function and preparation method | |
| CN108899761A (en) | Asymmetric mode extends small divergence angle semiconductor laser | |
| CN105140779B (en) | Backup type semiconductor laser based on reconstruction-equivalent chirp technology | |
| CN114188823A (en) | Preparation method of refrigeration-free anti-reflection InP-based quantum dot/quantum well coupled EML epitaxial wafer | |
| CN113422295A (en) | Multi-junction distributed feedback semiconductor laser and preparation method thereof | |
| CN109616870A (en) | The mutual injection type narrow linewidth semiconductor laser of single-chip integration | |
| US7638856B2 (en) | Optoelectronic transmitter integrated circuit and method of fabricating the same using selective growth process | |
| US9819153B2 (en) | Optical semiconductor device and manufacturing method thereof | |
| CN107623250B (en) | Short-cavity long-surface emitting laser and manufacturing method thereof | |
| CN114188819B (en) | 1342 nanometer wavelength high-power microstructure DFB laser | |
| CN101071935A (en) | Method for preparing buried structure AlInGaAs distributed feedback laser | |
| JP2000244059A (en) | Semiconductor laser device | |
| CN215771900U (en) | Multi-junction distributed feedback semiconductor laser | |
| CN116191205B (en) | Topological structure-based laser array and manufacturing method thereof | |
| CN214673449U (en) | Silicon-based C-waveband high-linearity surface emitting laser light source for optical communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220708 |
|
| RJ01 | Rejection of invention patent application after publication |