CN114721029B - Gamma photon detector reading electronics system based on inorganic perovskite - Google Patents

Gamma photon detector reading electronics system based on inorganic perovskite Download PDF

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CN114721029B
CN114721029B CN202210643028.1A CN202210643028A CN114721029B CN 114721029 B CN114721029 B CN 114721029B CN 202210643028 A CN202210643028 A CN 202210643028A CN 114721029 B CN114721029 B CN 114721029B
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CN114721029A (en
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胡坤
李玉英
李长裕
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Shandong University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/17—Circuit arrangements not adapted to a particular type of detector
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract

The invention belongs to the field of data acquisition systems of gamma imaging detectors, and particularly relates to a gamma photon detector reading electronic system based on inorganic perovskite f The digital circuit comprises an ADC converter and an FPGA, and the negative input ends of the amplifiers are respectively connected with a capacitor C f Controllable switch and detector, said capacitor C f The switch is connected with the output end of the amplifier after being connected in parallel, the positive input end of the amplifier is grounded, the output end of the amplifier is connected with the ADC, the ADC is connected with the FPGA, and the controllable switch is connected with the I/O buffer on the FPGA. The invention provides a multi-channel, low-noise and high-precision charge measurement scheme for the weak current pulse output by the novel detector.

Description

Gamma photon detector reading electronics system based on inorganic perovskite
Technical Field
The invention belongs to the field of data acquisition systems of gamma imaging detectors, and particularly relates to a gamma photon detector reading electronic system based on inorganic perovskite.
Background
Gamma ray detection has wide application in the fields of nuclear medicine imaging, nondestructive testing, space physics and the like, and people are always dedicated to developing high-performance gamma photon detectors. Gamma photons are higher in energy and more penetrating than x-rays, and therefore require higher average atomic number Z of the gamma detector material and thicker detector thickness. When the traditional high-purity germanium HPGe detector detects gamma rays, good energy resolution can be obtained, but because the band gap of the high-purity germanium HPGe detector is smaller, about 0.7eV is smaller than the band gap of a common semiconductor detector, a carrier is easy to jump from a valence band to a conduction band at normal temperature, so that the detector has high dark noise at normal temperature, and therefore the high-purity germanium HPGe detector can only work at low temperature. In order to find a detector with high energy resolution at normal temperature, people develop a novel gamma detector by utilizing a semiconductor synthesis technology, such as cadmium telluride (CdTe), Cadmium Zinc Telluride (CZT) and the like, and the detectors are also commercially available.
Gamma detection for higher energy resolutionInorganic perovskite CsPbBr with only holes as carriers 3 The detector takes place at the right moment. Inorganic perovskite CsPbBr 3 As an X-ray detector, two kinds of carriers, electrons and holes, are included. Due to the defects of the crystal lattice, electrons are easily trapped, resulting in poor signal-to-noise ratio of the detector. Recently, however, inorganic perovskites CsPbBr, which have only holes as carriers 3 The detector overcomes the defect that electrons are easy to capture, and realizes the ultra-high energy resolution (less than 1.4%) gamma detector only using holes as carriers by a crystal growth technology. Characteristic parameters of such detectionμτ h （μIs the mobility of the holes and is,τ h hole life) is high, resulting in a long duration of the detector output signal, and furthermore the detector has no avalanche multiplication effect, resulting in a small output current pulse of the detector. Because of the novelty of such detectors, there is no corresponding detector signal processing and data acquisition system on the market today.
Disclosure of Invention
Based on the above problems, the present application provides a method for producing a CsPbBr for a hole-type inorganic perovskite 3 The technical content of the detector charge measurement scheme is,
a gamma photon detector reading electronic system based on inorganic perovskite comprises a discharge type charge sensitive amplifying circuit and a digital circuit, wherein the discharge type charge sensitive amplifying circuit comprises an amplifier and a capacitor C f The digital circuit comprises an ADC converter and an FPGA, and the negative input ends of the amplifiers are respectively connected with a capacitor C f Controllable switch and detector, said capacitor C f The controllable switch is connected with the output end of the amplifier after being connected in parallel, the positive input end of the amplifier is grounded, the output end of the amplifier is connected with the ADC, the ADC is connected with the FPGA, and the controllable switch is connected with the I/O buffer on the FPGA.
Preferably, two ends of the detector are respectively connected with a resistor R 1 And a resistor R 2 Connection, the resistance R 1 Connected to a power supply HV and a resistor R 2 And (4) grounding.
Preferably, the FPGA is provided with a data acquisition module, a data cache module and a peak searching module, and the peak searching module is used for extracting a maximum value from the waveform.
Preferably, when the I/O buffer in the FPGA outputs a low level, the controllable switch is in an open state; when the I/O buffer is at a high level, the controllable switch is in a closed state.
Preferably, the controllable switch is in an open state in a quiescent state, i.e. when no current pulses are injected into the amplifier.
Preferably, when the detector outputs a positive current pulse, this current pulse is present in the capacitor C f Integrating, the amplifier outputs negative voltage pulse, and the capacitor C is in open state f The integrated charge is not provided with a leakage loop, the amplifier keeps an output voltage value all the time, the ADC performs full-waveform sampling on the waveform output by the amplifier, the waveform is sent to the FPGA for post-processing in real time, the FPGA receives waveform data sampled by the ADC, high-speed data caching is realized in the FPGA, the maximum value is extracted from the waveform, and after the maximum value is found, the controllable switch is immediately controlled through an I/O buffer of the FPGA to be in a closed state.
Preferably, after the FPGA finds the most significant value in one instance waveform, i.e., the minimum value, the I/O buffer closes the controllable switch, resulting in C f The charge integrated above is quickly discharged through the branch of the switch, and the voltage waveform of the amplifier quickly returns to the baseline value; and then, an I/O buffer in the FPGA changes the output state, so that the controllable switch is opened again, and the circuit returns to the working state in the static state.
Preferably, the discharge type charge sensitive amplifying circuit and the digital circuit are provided with a plurality of groups.
Advantageous effects
1. Inorganic perovskite CsPbBr of hole carrier type 3 The detector is a brand new imaging scheme as a gamma imaging detector, and the invention provides a multi-channel, low-noise and high-precision charge measurement scheme for weak current pulses output by the novel detector.
2. The invention solves the problems of signal extraction, high-speed digitization, case caching, data transmission and the like of the novel gamma detector.
3. The charge measurement scheme provided by the invention can be easily expanded in a system level, and has potential application value in the fields of nuclear medicine imaging (such as Single Photon Emission Computed Tomography (SPECT), aerospace and the like.
Drawings
Fig. 1 is a schematic block diagram of a charge measurement based on a charge sensitive amplifier of the fast discharge type.
Fig. 2 is a schematic diagram of a discharge-type charge-sensitive front discharge in the case of hole signal input.
Fig. 3 is a schematic diagram of a discharge type charge sensitive amplifier based on FET analog switches.
FIG. 4 is a perovskite CsPbBr 3 Gamma imaging detector 128 channel readout electronics system block diagram.
Fig. 5 is a voltage waveform diagram of a discharge-type charge-sensitive front discharge output in the case of a hole signal input.
Detailed Description
The following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application.
A gamma photon detector reading electronic system based on inorganic perovskite comprises a plurality of groups of discharge type charge sensitive amplifying circuits and digital circuits, wherein each group of discharge type charge sensitive amplifying circuits comprises an amplifier (the amplifier has high input impedance, the input impedance is about 1T omega), and a capacitor C f Each group of digital circuits comprises an ADC (analog to digital converter) and an FPGA (field programmable gate array), and the negative input ends of the amplifiers are respectively connected with a capacitor C f The controllable switch and the detector are arranged, and two ends of the detector are respectively connected with the resistors R 1 Resistance R 2 Connection, the resistance R 1 Connected to a power supply HV and a resistor R 2 Ground (resistor R) 1 Resistance R 2 A bias resistor). The capacitor C f The controllable switch is connected with the output end of the amplifier after being connected in parallel, the positive input end of the amplifier is grounded, the output end of the amplifier is connected with the ADC, the ADC is connected with the FPGA, and the controllable switch is connected with the I/O buffer on the FPGA.
The capacitor C f And the amplifier and the charge integrating circuit form a charge integrating circuit, and integrate and amplify the input weak current signal.
The FPGA realizes the following functions: 1) buffer-storing the sampling waveform of the ADC; 2) the peak searching module searches the most value of the waveform sampled by the ADC; 3) the controllable switch/FET switch in the feedback loop of the charge sensitive amplifier is controlled to be switched on/off; 4) the DDR3 SDRAM control engine module is realized, and the processed ADC sampling data is stored in real time; 5) and a PCIe control engine module is realized, and data of an external DDR3 memory are read in real time.
The FPGA is provided with a data acquisition module, a data cache module and a peak searching module, and the peak searching module is used for extracting a maximum value from a waveform.
When the I/O buffer in the FPGA outputs a low level, the controllable switch is in an open state; when the I/O buffer is at a high level, the controllable switch is in a closed state.
In a quiescent state, i.e. when no current pulses are injected into the amplifier, the controllable switch is in an open state.
When the detector outputs a positive current pulse, this current pulse is present in the capacitor C f Integrating, the amplifier outputs negative voltage pulse, and the capacitor C is in open state f The integrated charge is not provided with a leakage loop, the amplifier keeps an output voltage value all the time, the ADC performs full-waveform sampling on the waveform output by the amplifier, the waveform is sent to the FPGA for post-processing in real time, the FPGA receives waveform data sampled by the ADC, high-speed data caching is realized in the FPGA, the maximum value is extracted from the waveform, and after the maximum value is found, the controllable switch is immediately controlled through an I/O buffer of the FPGA to be in a closed state.
Finding an instance waveform in an FPGAAfter the minimum value, i.e., minimum value, the I/O buffer closes the switch, resulting in C f The charge integrated above is quickly discharged through the branch of the switch, and the voltage waveform of the amplifier quickly returns to the baseline value; and then, an I/O buffer in the FPGA changes the output state, so that the controllable switch is opened again, and the circuit returns to the working state in the static state.
The controllable switch belongs to an analog component, can be realized by a single transistor or a Field Effect Transistor (FET), and can also be realized by a commercial analog switch. The controllable switch is controlled by an I/O pin of the FPGA, and is controlled by three states of an I/O driver inside the FPGA: high level (typically 2.5V), low level (typically 0V), high impedance hz. According to the control mode of the controllable switch, the opening and the closing of the controllable switch can be controlled in any two states.
Inorganic perovskite CsPbBr 3 The gamma imaging detector belongs to multi-channel imaging application. The technical scheme of the invention can be used for multi-channel expansion. Because the scheme needs fewer analog components which can be put together and are collectively called front-end electronics FEE, the DAQ of the digital part comprises a multichannel ADC, a high-performance FPGA and a large-capacity external memory, wherein the multichannel ADC adopts commercial ADS52J90 and can be configured into 16 channels and 100M sampling and can also be configured into 32 channels and 50M sampling; the high performance FPGA is in the Stratix IV series from Intel corporation. In order to realize charge measurement of 128 channels, the FEE consists of 128 paths of AD8065, a capacitor and a controllable switch; the DAQ consists of 4 ADS52J90 (configured as 50M sample, 32 channel), a Stratix IV FPGA, and a high-capacity DDR3 SDRAM memory. Simple structure, the flexibility is strong.
As shown in fig. 5, the dotted line represents the voltage waveform of the output of the conventional RC type charge-sensitive amplifier in order to avoid the integration capacitor C f The charge loss, the value of the feedback resistance R (the invention replaces R with a controllable switch) is typically large, in the order of 10-500M omega. The purpose is to let C f During the charge integration process, the charge is discharged as little as possible, so that the requirement that the output voltage amplitude of the charge sensitive amplifier is proportional to the input charge quantity is met. The solid-line waveform shown in fig. 5 is an output waveform of the amplifying circuit in the present invention,sending the digital signal subjected to real-time full-waveform sampling by the ADC into the FPGA, finding the maximum value by a peak searching module in the FPGA, and immediately closing the controllable switch to enable the capacitor C f The charge integrated above is all drained off quickly. Therefore, the voltage waveform of the discharge-type charge-sensitive front-discharge output includes only a rising edge and a short voltage holding time. Compared with the traditional RC type charge sensitive amplifier, the discharge type charge sensitive amplifier has narrower output voltage pulse width and is suitable for application under high counting rate.
For the convenience of understanding and implementing the technical solution of the present invention, taking fig. 3 as an example, an NMOS FET is selected as the controllable switch. The gate G of the NMOS FET serves as the control terminal of the controllable switch, the source S is connected to the output of the amplifier, and the drain D is connected to the negative input terminal of the amplifier. Because the I/O pin output of the FPGA has only three states: high level (2.5V in the example), low level (0V in the example) and high impedance hz, the first two states high and low being chosen to control the opening and closing of the controllable switch. When the NMOS FET is used as a switch, if the voltage difference between the gate G and the source S is greater than the threshold voltage V for opening the door GS(th) (generally about 0.7V), the drain D and the source S of the NMOS FET are conducted, which is equivalent to the controllable switch being closed; if the voltage difference between the gate G and the source S is less than V GS(th) When the drain D and the source S of the NMOS FET are in the off state, the leakage current through the NMOS FET is small, resulting in a large equivalent impedance of this branch, which is equivalent to the M Ω resistor R in the RC-type charge sensitive amplifier, and is equivalent to the switch being in the on state.
In practical use, the voltage difference between the gate G and the source S is much smaller than V for obtaining a better reverse cut-off characteristic of the NMOS FET GS(th) . Thus, in fig. 3 a level V is introduced at the positive input of the amplifier b In this example, 1V. When the I/O buffer of the FPGA outputs a low level of 0V, the voltage difference between the grid G and the source S of the NMOS FET is-1V, so that the reverse cut-off equivalent impedance of the NMOS FET is far greater than M omega; and under the condition of discharge operation, the I/O buffer of the FPGA outputs 2.5V, and the voltage difference between the grid G and the source S is 1.5V at the moment>VGS (th), make NMOS FEThe T switch is normally conducted, and normal use is not influenced.
The invention can easily expand multiple channels, and by taking fig. 4 as an example, a 128-channel full-waveform sampling DAQ system is realized by combining a commercial ADS52J90 high-speed, multi-channel ADC converter (64-channel 100M sampling or 128-channel 50M sampling can be realized by configuration). Due to inorganic perovskite CsPbBr 3 The duration of the current pulse output by the detector is long, and for the slow signal, a sampling rate of 50M or lower can be adopted. The discharge type charge sensitive front amplifier comprises only an amplifier, a controllable switch and a capacitor C f The total size of the front end panel FEE of the three main components, 128 channels, may be limited to a certain range.
AD8065 high-input impedance amplifier packaged by SOT23, and 4 ADS52J90, FPGA and DDR3 SDRAM large-capacity memory are added to realize CsPbBr-based 3 A gamma imaging detector 128 channel readout electronics system for the material. The 128-channel readout electronics system includes a front end plate FEE and a back end DAQ system.
The front-end FEE comprises a 128-path discharge type charge sensitive amplifying circuit; the back-end DAQ system comprises 4 ADS52J90 pieces, a Stratix IV FPGA and a large-capacity external memory. Wherein, each ADS52J90 is configured to 50MSPS, 10bit, 32 channel working mode, and four chips constitute 128 channel ADC. The high-performance Stratix IV FPGA implements functions such as ADC data caching, peak-finding/control switching, write control of the DDR3 SDRAM memory, read control of the DDR3 SDRAM by the PCIe engine, and the like.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (6)

1. The gamma photon detector reading electronic system based on inorganic perovskite is characterized by comprising a discharge type charge sensitive amplifying circuit and a digital circuit, wherein the discharge type charge sensitive amplifying circuit comprisesAmplifier, capacitor C f The digital circuit comprises an ADC converter and an FPGA, and the negative input ends of the amplifiers are respectively connected with a capacitor C f Controllable switch and detector, said capacitor C f The controllable switch is connected with the output end of the amplifier after being connected in parallel, the positive input end of the amplifier is grounded, the output end of the amplifier is connected with the ADC, the ADC is connected with the FPGA, and the controllable switch is connected with the I/O buffer on the FPGA;
when the detector outputs a positive current pulse, the current pulse is present in the capacitor C f Integrating, the amplifier outputs negative voltage pulse, and the capacitor C is in open state f The integrated charge is added, no bleeding loop exists, the amplifier keeps an output voltage value all the time, the ADC performs full-waveform sampling on the waveform output by the amplifier, the waveform is sent to the FPGA for post-processing in real time, the FPGA receives waveform data sampled by the ADC, high-speed data caching is realized in the FPGA, the maximum value is extracted from the waveform, and after the maximum value is found, the controllable switch is controlled through an I/O buffer of the FPGA immediately to be in a closed state;
after the FPGA finds the most significant value in one instance waveform, the minimum, the I/O buffer closes the controllable switch, resulting in C f The charge integrated above is quickly discharged through the branch of the switch, and the voltage waveform of the amplifier quickly returns to the baseline value; and then, an I/O buffer in the FPGA changes the output state, so that the controllable switch is opened again, and the circuit returns to the working state in the static state.
2. The inorganic perovskite-based gamma photon detector readout electronics system of claim 1, wherein the detector is terminated by a resistor R 1 Resistance R 2 Connection, the resistance R 1 Connected to a power supply HV and a resistor R 2 And is grounded.
3. The inorganic perovskite-based gamma photon detector readout electronics system as claimed in claim 1, wherein said FPGA is configured with a data acquisition module, a data buffer module and a peak finding module, said peak finding module being configured to extract a maximum value from the waveform.
4. The inorganic perovskite-based gamma photon detector readout electronics system of claim 1, wherein the controllable switch is in an open state when an I/O buffer internal to the FPGA outputs a low level; when the I/O buffer is at a high level, the controllable switch is in an off state.
5. An inorganic perovskite based gamma photon detector readout electronics system as claimed in claim 1 wherein the controllable switch is in an open state in quiescent state, i.e. when no current pulse is injected into the amplifier.
6. An inorganic perovskite-based gamma photon detector readout electronics system as claimed in claim 1 wherein the discharge type charge sensitive amplification circuit and the digital circuit are provided in sets.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103685991A (en) * 2013-12-31 2014-03-26 北京国药恒瑞美联信息技术有限公司 Serial read photon counting chip
CN112087208A (en) * 2020-09-02 2020-12-15 西安交通大学 Preamplifier with wide dynamic range read out at front end of radiation detector
WO2022101071A1 (en) * 2020-11-12 2022-05-19 Ams International Ag Front-end electronic circuitry for a photon counting application

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101806630B (en) * 2010-01-20 2011-08-17 南通大学 Reading circuit based on relaxor ferroelectric monocrystal pyroelectric detector
US8565380B2 (en) * 2010-10-05 2013-10-22 Varian Medical Systems, Inc. Method and apparatus pertaining to use of a switched voltage clamp with an x-ray detector amplifier
CN105115606B (en) * 2015-05-21 2018-08-14 常州大学 A kind of twin-stage reading circuit based on relaxor ferroelectric monocrystal pyroelectric detector
CN105549064B (en) * 2016-01-05 2018-10-02 成都理工大学 A kind of high-resolution X-ray energy disperse spectroscopy based on Si-PIN detector arrays
CN112149787B (en) * 2020-09-11 2022-11-25 上海联影医疗科技股份有限公司 Counting device and counting system based on capacitance feedback charge sensitive amplifying circuit
CN113848580A (en) * 2021-09-26 2021-12-28 中国科学院高能物理研究所 X/gamma ray radiation quantity detection system and detection method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103685991A (en) * 2013-12-31 2014-03-26 北京国药恒瑞美联信息技术有限公司 Serial read photon counting chip
CN112087208A (en) * 2020-09-02 2020-12-15 西安交通大学 Preamplifier with wide dynamic range read out at front end of radiation detector
WO2022101071A1 (en) * 2020-11-12 2022-05-19 Ams International Ag Front-end electronic circuitry for a photon counting application

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
基于FET开关阵列的GEM成像探测器电子学系统设计;曹双僖等;《核电子学与探测技术》;20090920(第05期);全文 *

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