CN114543990B - Free-running single photon detector and reading circuit - Google Patents
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Abstract
The invention provides a free-running single photon detector and a reading circuit, comprising: the device comprises a single photon detection array, at least two avalanche readout discrimination circuits, a low-noise direct-current bias circuit, a dead time timing circuit and at least two bias amplifying circuits; the single photon detection array comprises at least two negative feedback avalanche photodiodes, and the tail fibers of the negative feedback avalanche photodiodes are densely arranged into a tail fiber array; the avalanche reading discrimination circuit is connected with the cathode of the negative feedback avalanche photodiode through a capacitor, the output end of the avalanche reading discrimination circuit is connected with the bias amplifying circuit, and the output end of the bias amplifying circuit is connected with the anode of the negative feedback avalanche photodiode; the dead time timing circuit is connected with the output end of the avalanche readout screening circuit; and the low-noise direct current bias circuit is connected with the cathode of each negative feedback avalanche photodiode through a high-resistance resistor. The technical problems of low counting rate, high noise and low integration level of the single photon detector array are solved.
Description
Technical Field
The invention belongs to the technical field of photoelectric detection, and particularly relates to a free-running single photon detector array and a readout circuit.
Background
Photons are the smallest energy unit of light and the information carrier, and an efficient detection of photons will reach the quantum-extreme sensitivity. The single photon detection technology has photon level detection sensitivity and sub-nanosecond time precision, and has important application in the fields of quantum information technology, biological fluorescence analysis, medical imaging, laser remote sensing and the like. The near-infrared wavelength single photon detection technology has important values in scientific research and engineering application, such as quantum secret communication, eye safety laser detection and the like, and the InGaAs/InP geiger Avalanche Photodiode (APD) is the most widely applied near-infrared wavelength single photon detection technology at present, and has the advantages of high technical maturity, low requirements on working environment and the like. The single photon detector array integrates a large number of single photon detectors, has great advantages in detection breadth, imaging efficiency, photon number resolution and the like, and is a trend of development of single photon detection technology. At present, a single photon detector array is limited by factors such as device performance, a readout circuit and the like, mainly works in a gating mode, and is difficult to realize non-cooperative target detection and imaging; in addition, the frame frequency of the gating mode single photon detector array is usually low, the counting is easy to saturate under the daytime working condition, and the application condition of the gating mode single photon detector array cannot be met all the day.
In order to realize single photon detection, reverse bias voltages applied to two ends of the Geiger APD are higher than breakdown voltages of the Geiger APD, and photoelectrons are generated with a certain probability after the APD absorbs photons; under the acceleration of external electric field, the photoelectrons collide with crystal lattice to generate avalanche multiplication effect, so that saturated avalanche current is quickly formed, and the gain is up to about 10 6 . After avalanche multiplication occurs in the Geiger APD, the avalanche process needs to be quenched, and the avalanche multiplication can be detected next time after the avalanche multiplication disappears. The Geiger APD cannot detect single photons in the process from avalanche multiplication to avalanche disappearance, and the period of time is the detection dead time. To improve single photon detection performance, detection dead time is often increased on peripheral circuits. Free-running single photon detectionThe detection state is always in before the avalanche triggering, and the detection state is restored again after the dead time passes after the avalanche triggering. Therefore, the free-running single photon detection can respond to photons arriving at any moment before avalanche triggering, and has important significance for asynchronous quantum communication and non-cooperative target detection. The counting rate of free-running single photon detection mainly depends on the detection dead time, so that a higher counting rate can be achieved, and the detection in whole day is realized.
The invention patent with application number 202110050014.4 discloses a semiconductor refrigeration type SPAD single photon detector, which comprises a single chip microcomputer module, a relay module, a TEC refrigeration module, an interaction module, a digital temperature sensor circuit, a detection module, a comparator module and a switch module, wherein the interaction module comprises a display screen circuit and a key circuit, a signal pin of the digital temperature sensor circuit is connected with a data receiving pin of the single chip microcomputer module, and a signal output pin of the single chip microcomputer module is connected with an input end of the relay module and the switch module. The free-running single photon detection is realized mainly by two modes of active quenching and passive quenching. The active quenching realizes avalanche quenching by rapidly reducing the bias voltages at two ends of the Geiger APD, the performance of the active quenching depends on the bias voltage control speed, and the requirement on a circuit is higher; to achieve higher performance, active quenching is often designed with Application Specific Integrated Circuits (ASICs) for avalanche quenching, which is difficult to design and has a long period. The passive quenching mode connects the Geiger APD with the quenching resistor with large resistance in series, and after avalanche triggering, avalanche quenching is realized by dividing the avalanche current on the quenching resistor, so that the structure is simple. To achieve higher performance, single photon detection is typically performed with a negative feedback avalanche photodiode (NFAD); the NFAD adopts a monolithic integration process to integrate a quenching resistor beside the APD, and eliminates parasitic parameters on a wire, thereby improving detection performance. Due to the nature of InGaAs/InP geiger APD materials, post-pulse events are the largest contributor to their single photon detection performance, with noise being high in free-running mode, which relies solely on NFAD self-quenching. In addition, since the NFAD avalanche quench speed is faster, the avalanche gain is smaller and is easily interfered by external noise. The prior art has the technical problems of low counting rate, high noise, low integration level and the like of the single photon detector array.
Disclosure of Invention
The invention aims to solve the technical problems of low counting rate, high noise and low integration level of a single photon detector array.
The invention adopts the following technical scheme to solve the technical problems: a free-running single photon detector and readout circuit includes: the device comprises a single photon detection array, at least two avalanche readout discrimination circuits, a low-noise direct-current bias circuit, a dead time timing circuit and at least two bias amplifying circuits;
the single photon detection array comprises at least two negative feedback avalanche photodiodes, wherein the tail fibers of a plurality of negative feedback avalanche photodiodes are densely arranged into a tail fiber array and are used for receiving optical signals through the tail fiber array, and the tail fiber array is used for coupling the optical signals to the negative feedback avalanche photodiodes;
the avalanche reading and discriminating circuit is connected with the cathode of the negative feedback avalanche photodiode through a capacitor, the output end of the avalanche reading and discriminating circuit is connected with the bias amplifying circuit, the output end of the bias amplifying circuit is connected with the anode of the negative feedback avalanche photodiode and is used for generating and driving a field effect transistor in the bias amplifying circuit to amplify direct current bias voltage by utilizing an avalanche reading signal so as to control the anode level of the negative feedback avalanche photodiode and actively quench the avalanche process of the optical signal;
the dead time timing circuit is connected with the output end of the avalanche reading screening circuit and used for controlling the dead time of the multi-path reading circuit and the switching of the states of the free-running single photon detector;
the low-noise direct current bias circuit is connected with the cathode of each negative feedback avalanche photodiode through a high-resistance resistor and is used for providing reverse direct current bias higher than the breakdown voltage of the negative feedback avalanche photodiode so as to switch the dead time control state and the detector state of the multi-path reading circuit.
The invention realizes a free-running single photon detector array by utilizing the optical fiber close-packed and NFAD, has flexible array scale and arrangement form, and can independently work between the NFAD, thereby achieving high saturation count rate and meeting the application condition of all day time; according to the technical scheme, the avalanche readout signal is adopted to drive the field effect transistor to amplify the direct current bias voltage, so that the fast control of the NFAD anode level is realized, the avalanche process can be actively quenched, the probability of post-pulse is reduced, and the problem of high noise only depending on NFAD self-quenching in the prior art is solved.
In a more specific technical scheme, the number of the avalanche readout screening circuits is adapted to the single photon detection array, and the avalanche readout screening circuits include: the dead time timing circuit comprises a low noise amplifier, a high speed comparator, a D trigger and a level conversion chip, wherein the output end of the dead time timing circuit is connected with the asynchronous reset end of the D trigger.
In a more specific technical scheme, the free-running single photon detector and the readout circuit further comprise a temperature control circuit, the negative feedback avalanche photodiode comprises an airtight packaging integrated thermoelectric cooler, a thermistor and a heat sink flange, a temperature control circuit acquisition end is connected with the thermistor, and an output end of the temperature control circuit is connected with the airtight packaging integrated thermoelectric cooler.
In a more specific technical scheme, the pigtails of the negative feedback avalanche photodiodes in the single photon detection array are distributed into the pigtail array according to a preset close-packed mode by utilizing an optical fiber close-packed technology.
In a more specific technical scheme, the number of the bias amplifying circuits is adapted to the single photon detection array, and the bias amplifying circuits further include: the output end of the low-noise amplifier is connected with the non-inverting input end of the high-speed comparator through a capacitor;
the non-inverting input end of the high-speed comparator is connected with an adjustable discrimination level, and the inverting input end of the high-speed comparator is grounded; the output end of the high-speed comparator is connected with the clock of the D trigger, and the output end of the D trigger is connected with the latch control end of the high-speed comparator.
In a more specific technical scheme, the low noise amplifier adopts a 50 ohm input/output impedance SiGe heterojunction device, and the frequency band covers 100 MHz-1 GHz.
In a more specific technical scheme, the negative feedback avalanche photodiode generates negative avalanche current after avalanche triggering, and the negative feedback avalanche current is converted into a negative voltage signal through capacitive coupling to a low noise amplifier; the NFAD avalanche signal is screened through the voltage zero-crossing comparison of the high-speed comparator.
According to the technical scheme, the avalanche readout signal is adopted to drive the field effect transistor to amplify the direct current bias voltage, so that the fast control of the NFAD anode level is realized, the avalanche process can be actively quenched, and the probability of the post pulse is reduced.
In a more specific technical scheme, the dead time timing circuit adopts an FPGA to time the output signals of the multipath avalanche reading and screening circuit, generates a recovery signal according to the dead time set outside, and asynchronously resets the D trigger.
The invention realizes the reverse direct current bias of a plurality of NFAD by using one path of low-noise direct current bias circuit, realizes the dead time control and the detector state switching of the multi-path reading circuit by using one FPGA, and improves the integration level of the reading circuit.
In a more specific technical scheme, a direct-current stabilized power supply is connected with the anode of the negative feedback avalanche photodiode through a current limiting resistor, so that the voltage at two ends of the negative feedback avalanche photodiode is reduced to be lower than the breakdown voltage; the drain electrode of the field effect transistor is connected with the anode of the negative feedback avalanche photodiode, and the source electrode of the field effect transistor is grounded; outputting and controlling the grid voltage of the field effect transistor by using the avalanche read-out discrimination circuit; when the grid voltage of the field effect transistor is at a high level, the drain electrode and the source electrode are conducted, and the voltage at two ends of the negative feedback avalanche photodiode is higher than the breakdown voltage; when the field effect transistor gate voltage is low, the drain-source is disconnected and the voltage across the negative feedback avalanche photodiode is below the breakdown voltage.
In a more specific technical scheme, the implementation dead time control process is as follows:
after the NFAD avalanche signal is detected by the avalanche reading and discriminating circuit, the high-speed comparator is switched to a latch state through a D trigger output signal; the avalanche reading screening circuit outputs high level through level conversion, disconnects the drain electrode-source electrode of the field effect transistor, so that the NFAD exits from the Geiger detection mode, and the dead time timing circuit starts timing; and after the FPGA dead time of the dead time timing circuit is finished, outputting high voltage, asynchronously resetting the D trigger, controlling the high-speed comparator to recover a comparison mode, controlling the drain electrode-source electrode of the field effect transistor to be conducted, and recovering the NFAD geiger detection mode.
Compared with the prior art, the invention has the following advantages: the invention realizes a free-running single photon detector array by utilizing optical fiber close-packed and NFAD, has flexible array scale and arrangement form, can independently work between NFAD, can achieve high saturation count rate and meet the application condition of whole day, realizes the reverse direct current bias of a plurality of NFAD by utilizing one path of low-noise direct current bias circuit, realizes the dead time control and detector state switching of a multi-path reading circuit by utilizing one FPGA, improves the integration level of the reading circuit, adopts avalanche reading signals to drive a field effect transistor to amplify the direct current bias, realizes the rapid control of the anode level of the NFAD, can actively quench the avalanche process, and reduces the probability of rear pulses. The technical problems of low counting rate, high noise and low integration level of the single photon detector array in the prior art are solved.
Drawings
Fig. 1 is a block diagram of the circuit architecture of a free-running single photon detector array and readout circuitry of the present invention.
Fig. 2 is a diagram of the fiber array architecture of a free-running single photon detector array and readout circuitry of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, a free-running single photon detector array and readout circuitry includes a negative feedback avalanche photodiode (NFAD), a low noise dc bias circuit, an avalanche readout discrimination circuit, a bias amplification circuit, a dead time timing circuit, and a temperature control circuit; the NFAD adopts a 62.5/125 mu m multimode optical fiber self-quenching single photon detector developed by Prlington photoelectricity, and a three-stage thermoelectric refrigerator and a thermistor are integrated inside the NFAD; the avalanche reading screening circuit comprises a low noise amplifier, a high speed comparator, a D trigger and a level conversion chip; the bias amplifying circuit comprises a direct-current stabilized power supply and a field effect transistor;
as shown in fig. 2, 8 NFAD pigtails are arranged in a line array by an optical fiber close-packed technology, and optical signals received on the array are coupled to NFAD through the pigtails; the low-noise direct current bias circuit adopts a DC-DC boost power supply, generates 90V voltage at most, has ripple wave lower than 0.1mVpp, adopts metal shell shielding, is connected with 8 NFAD cathodes through a 1k omega resistor, and provides reverse direct current bias higher than NFAD breakdown voltage; the avalanche reading discrimination circuit is connected with the NFAD cathode through a capacitor; the output of the avalanche reading discrimination circuit is respectively connected with the bias amplifying circuit and the dead time timing circuit; the dead time timing circuit output is connected with an asynchronous reset end of a D trigger in the avalanche readout discrimination circuit; the output of the bias amplifying circuit is connected with the NFAD anode; the acquisition end of the temperature control circuit is connected with the NFAD thermistor, and the output end of the temperature control circuit is connected with the NFAD thermoelectric refrigerator.
The low-noise amplifier is a 50 ohm input/output impedance SiGe heterojunction device, and the frequency band covers 100 MHz-3 GHz; the output of the low noise amplifier is connected with the non-inverting input end of the high speed comparator through a capacitor; the non-inverting input end of the high-speed comparator is connected with the adjustable discrimination level, and the inverting input end of the high-speed comparator is connected with the ground; the output of the high-speed comparator is connected with a D trigger clock; the D flip-flop output is connected with the high speed comparator latch control.
The NFAD avalanche trigger generates negative avalanche current, and the negative avalanche current is converted into a negative voltage signal through capacitive coupling to a low noise amplifier; the adjustable discrimination level pulls the negative voltage signal up to above noise, and the NFAD avalanche signal is discriminated through the high-speed comparator voltage zero-crossing comparison.
And the dead time timing circuit adopts an FPGA to time the output signals of the multipath avalanche reading and screening circuit, generates a recovery signal according to the dead time set outside, and asynchronously resets the D trigger.
The direct-current stabilized power supply is connected with the NFAD anode through a current limiting resistor, so that the voltage at two ends of the NFAD can be reduced below breakdown voltage; the drain electrode of the field effect transistor is connected with the NFAD anode, and the source electrode is grounded; the avalanche reading screening circuit outputs and controls the grid voltage of the field effect transistor; when the grid voltage of the field effect transistor is at a high level, the drain electrode and the source electrode are conducted, and the voltage at two ends of the NFAD is higher than the breakdown voltage; when the field effect transistor gate voltage is low, the drain-source is off and the voltage across NFAD is below the breakdown voltage.
After the NFAD avalanche signal is detected by the avalanche readout screening circuit, the high-speed comparator is switched to a latch state through a D trigger output signal; outputting a high level through level conversion, and disconnecting the drain electrode and the source electrode of the field effect transistor so that the NFAD exits from the Geiger detection mode; simultaneously, the dead time timing circuit starts timing; and after the FPGA dead time is timed, outputting high voltage, asynchronously resetting the D trigger, controlling the high-speed comparator to recover the comparison mode, controlling the drain electrode-source electrode of the field effect transistor to be conducted, and recovering the NFAD geiger detection mode.
In summary, the invention utilizes optical fiber close-packed and NFAD to realize a free-running single photon detector array, the array scale and arrangement form are flexible, the NFAD works independently, high saturation count rate can be achieved, the application condition of the NFAD all day is satisfied, the invention utilizes a path of low noise DC bias circuit to realize the reverse DC bias of a plurality of NFAD, utilizes a piece of FPGA to realize the dead time control and the detector state switching of a multi-path readout circuit, improves the integration level of the readout circuit, adopts avalanche readout signals to drive a field effect transistor to amplify the DC bias, realizes the rapid control of the anode level of the NFAD, can actively quench the avalanche process, and reduces the post pulse probability. The technical problems of low counting rate, high noise and low integration level of the single photon detector array in the prior art are solved.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A free-running single photon detector and a reading circuit are characterized in that the single photon detector comprises a single photon detection array, at least two avalanche reading screening circuits, a low-noise direct current bias circuit, a dead time timing circuit and at least two bias amplifying circuits;
the single photon detection array comprises at least two negative feedback avalanche photodiodes, wherein the tail fibers of a plurality of negative feedback avalanche photodiodes are densely arranged into a tail fiber array and are used for receiving optical signals through the tail fiber array, and the tail fiber array is used for coupling the optical signals to the negative feedback avalanche photodiodes;
the avalanche reading and discriminating circuit is connected with the cathode of the negative feedback avalanche photodiode through a capacitor, the output end of the avalanche reading and discriminating circuit is connected with the bias amplifying circuit, the output end of the bias amplifying circuit is connected with the anode of the negative feedback avalanche photodiode and is used for generating and driving a field effect transistor in the bias amplifying circuit to amplify direct current bias voltage by utilizing an avalanche reading signal so as to control the anode level of the negative feedback avalanche photodiode and actively quench the avalanche process of the optical signal;
the dead time timing circuit is connected with the output end of the avalanche reading screening circuit and used for controlling the dead time of the multi-path reading circuit and the switching of the states of the free-running single photon detector;
the low-noise direct current bias circuit is connected with the cathode of each negative feedback avalanche photodiode through a high-resistance resistor and is used for providing reverse direct current bias higher than the breakdown voltage of the negative feedback avalanche photodiode so as to switch the dead time control state and the detector state of the multi-path reading circuit.
2. The free-running single photon detector and readout circuit of claim 1, wherein the number of avalanche readout screening circuits is adapted to the single photon detection array, the avalanche readout screening circuit comprising: the dead time timing circuit comprises a low noise amplifier, a high speed comparator, a D trigger and a level conversion chip, wherein the output end of the dead time timing circuit is connected with the asynchronous reset end of the D trigger.
3. The free-running single photon detector and readout circuit according to claim 1, wherein the free-running single photon detector and readout circuit further comprises a temperature control circuit, the negative feedback avalanche photodiode comprises an airtight packaged integrated thermoelectric cooler, a thermistor and a heat sink flange, a collection end of the temperature control circuit is connected with the thermistor, and an output end of the temperature control circuit is connected with the airtight packaged integrated thermoelectric cooler.
4. The free-running single-photon detector and readout circuit according to claim 1, wherein the pigtails of the plurality of negative feedback avalanche photodiodes in the single-photon detection array are arranged into the pigtail array in a preset close-packed manner by using an optical fiber close-packed technology.
5. The free-running single photon detector and readout circuit of claim 2, wherein the number of bias amplifying circuits is adapted to the single photon detection array, the bias amplifying circuits further comprising: the output end of the low-noise amplifier is connected with the non-inverting input end of the high-speed comparator through a capacitor;
the non-inverting input end of the high-speed comparator is connected with an adjustable discrimination level, and the inverting input end of the high-speed comparator is grounded; the output end of the high-speed comparator is connected with the clock of the D trigger, and the output end of the D trigger is connected with the latch control end of the high-speed comparator.
6. The free-running single photon detector and readout circuit according to claim 5, wherein the low noise amplifier uses a 50 ohm input/output impedance SiGe heterojunction device, and the frequency band covers 100 MHz-1 GHz.
7. The free-running single photon detector and readout circuit of claim 1 wherein the negative feedback avalanche photodiode avalanche trigger produces a negative avalanche current which is capacitively coupled to a low noise amplifier for conversion to a negative voltage signal; the NFAD avalanche signal is screened through the voltage zero-crossing comparison of the high-speed comparator.
8. The free-running single photon detector and readout circuit according to claim 1, wherein the dead time timing circuit uses FPGA to time the output signal of the multiplex avalanche readout discrimination circuit, generates a recovery signal according to the dead time set externally, and asynchronously resets the D flip-flop.
9. The free-running single photon detector and readout circuit according to claim 1, wherein a direct current stabilized power supply is connected with the anode of the negative feedback avalanche photodiode through a current limiting resistor, so as to reduce the voltage across the negative feedback avalanche photodiode below a breakdown voltage; the drain electrode of the field effect transistor is connected with the anode of the negative feedback avalanche photodiode, and the source electrode of the field effect transistor is grounded; outputting and controlling the grid voltage of the field effect transistor by using the avalanche read-out discrimination circuit; when the grid voltage of the field effect transistor is at a high level, the drain electrode and the source electrode are conducted, and the voltage at two ends of the negative feedback avalanche photodiode is higher than the breakdown voltage; when the field effect transistor gate voltage is low, the drain-source is disconnected and the voltage across the negative feedback avalanche photodiode is below the breakdown voltage.
10. The free-running single photon detector and readout circuit of claim 1, wherein the dead time control process is implemented as:
after the NFAD avalanche signal is detected by the avalanche reading and discriminating circuit, the high-speed comparator is switched to a latch state through a D trigger output signal; the avalanche reading screening circuit outputs high level through level conversion, disconnects the drain electrode-source electrode of the field effect transistor, so that the NFAD exits from the Geiger detection mode, and the dead time timing circuit starts timing; and after the FPGA dead time of the dead time timing circuit is finished, outputting high voltage, asynchronously resetting the D trigger, controlling the high-speed comparator to recover a comparison mode, controlling the drain electrode-source electrode of the field effect transistor to be conducted, and recovering the NFAD geiger detection mode.
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