CN212012846U - Gate-controlled integral high background signal readout circuit - Google Patents

Abstract

The patent discloses a gate-control integrated high background signal reading circuit, which comprises a modulator, a gate-control multi-period integrated GMCI circuit, a sampling hold circuit, a time sequence generating circuit and an output stage buffer circuit. The integral integration process is divided into two parts, wherein the first part injects signal current in a direct integration DI stage, repeats n periods, stores the current processed by the GMCI circuit and outputs a signal outD; and secondly, injecting signal current in the stage of transferring integral TI, repeating n periods, sampling, holding and outputting a signal outT. When both background and useful infrared signals exist, the background and the infrared signals are simultaneously integrated, when the infrared signals are chopped and only the background exists, the background is subtracted, and the two operations are alternately carried out for multiple times, so that the background can be effectively removed. The background suppression circuit is connected with a correlated double sampling circuit, and by utilizing the correlation of noise in time, sampling is performed twice in a very short time for subtraction, so that the noise is reduced, and the reading problem that a weak signal is submerged in a high background is solved.

Description

Gate-controlled integral high background signal readout circuit

Technical Field

The patent relates to a CMOS circuit, in particular to a gate-controlled integral quantum well high background signal reading circuit.

Background

Quantum well infrared detectors will produce extremely large background currents, often referred to as dark currents. According to the preliminary device test of the quantum well infrared detector, the photocurrent of the quantum well detection pixel is about 10nA, and the background current is about 10 times of the photocurrent and is about 100 nA. Therefore, a background suppression circuit is required to be added in a unit reading circuit designed for the quantum well infrared detector to read a weak small signal which is much smaller than background current and needs to be measured. The quantum well infrared detector generally works under a certain bias voltage and temperature, and due to the existence of the pressure difference, detector dark current composed of surface leakage current, intrinsic dark current and the like exists in current input to a reading circuit. In addition, the dark current of the quantum well infrared detector can be reduced, and noises of the device, such as various noises including thermal noise, 1/f noise, photon noise, shot noise and the like, can be suppressed. In order to improve the performance of the quantum well infrared detector, the device is also subjected to noise reduction, that is, dark current of the quantum well infrared detector is suppressed, which is also one aspect of background suppression.

The useful infrared signal and the background signal are input together into a readout circuit connected to the detector when the quantum well infrared detector is in operation. The reading circuit can integrate and amplify the input signal, and in the process, the infrared signal is integrated and amplified, and the background signal is also amplified. Therefore, the phenomenon that the integrating capacitor is saturated when the integrating period is not finished easily occurs, so that the detector loses the function of detecting the infrared intensity of the target. Therefore, when a readout circuit is designed, the integration capacitance is generally required to be large enough, but the excessive integration capacitance is in conflict with the limited layout area. This means that it is not possible to increase the integration capacitance at once, so that it is necessary to delete or suppress the background signal by means of a background current suppression circuit before integrating the signal output by the quantum well detector pixel, so that the readout circuit integrates only the useful infrared signal. Background suppression is the suppression or deletion of background current in the presence of both signal and background and the integration of only the useful infrared signal to be measured.

In the existing literature, a background suppression circuit is designed by Zhao Chen and Byunghyuk Kim and the like based on a current replication method, and the principle is that firstly, background current is recorded and replicated, and then the replicated background current is subtracted from a signal current output by a pixel element to realize the function of background suppression. Before working, firstly controlling a reset tube to reset an integral capacitor to a set reset voltage value, and then directly integrating charges output by a detector pixel on the integral capacitor after passing through an injection tube; the current copy circuit copies background current, and the control tube switches on or off the current copy circuit and selectively outputs the obtained integral signal. The working process of the current copy background suppression circuit is divided into two stages. Firstly, a circuit is calibrated, background current is copied, so that a pixel only generates current caused by background, a switching tube in the current copying circuit is conducted at the time and is in a saturated state, and a reset tube is controlled to reset an integral capacitor, so that the background current (including dark current) generated by the pixel is copied to the capacitor and the gate source voltage value generating the background current is recorded; the second step is an integral reading stage, so that the detector works normally, the current generated by the pixel is the sum of the signal current and the background current, and the control signal outputs the previously recorded background current under the action of the storage voltage on the memory capacitor, thereby realizing the function of background suppression. The working principle of the current copying method is that a memory capacitor is used for recording a voltage difference value required by generating the suppression current, but as time goes on, the capacitor has the reasons of leakage current and the like, the generated suppression current is not equal to the background current, and the background suppression function gradually deteriorates until the suppression function is lost.

After analyzing the background current suppression method mentioned above and its corresponding schematic diagram, it was found that the key to suppress the background current is to generate an accurate background suppression current and subtract it from the current output by the picture element (background current + signal current). Other researchers at home and abroad also design background suppression circuits such as a voltage-current conversion method, a current replication method, a dark pixel compensation method and the like. However, the application of these circuits to quantum well detection for high background operation still has some disadvantages or shortcomings: the current copying unit has a complex structure, occupies a large layout area and is limited by the size of a device unit; the voltage-current conversion method background suppression circuit has a simple structure, but the background suppression current provided by the voltage-current conversion method is fixed, and the error is large; the background suppression circuit of the dark pixel compensation method has a complex structure, and the area and the power consumption of the layout are both large. Therefore, the research and development of a novel quantum well infrared focal plane array reading circuit applied to the reading of weak signals under a large background are urgently needed.

In order to solve the problem that a signal to be detected is submerged in a high background environment in the current project development, the method overcomes the defects of the method adopted in the literature, designs a GMCI (Gated Multi-Cycle Integration) structure, designs a novel quantum well focal plane detection array reading circuit with adjustable precision, strong background suppression capability and high reading resolution, and has a reading circuit with high background suppression function, so that the aim of reading a weak signal in the high background environment can be fulfilled.

Disclosure of Invention

The patent relates to a gate-controlled integral high background signal reading circuit, which comprises a modulator, a gate-controlled multi-period integral circuit GMCI, a sampling hold circuit, a time sequence generating circuit and an output stage buffer circuit; the connection relationship is as follows: the modulator is positioned in front of the detector, the output end of the modulated detector is connected with the input end of the gated multi-period integrating circuit GMCI, the output end of the gated multi-period integrating circuit GMCI is connected with the input end of the adoption holding circuit, the output end of the sampling holding circuit is connected with the input end of the output buffer circuit, the time sequence generating circuit is respectively connected with the modulator, the gated multi-period integrating circuit GMCI and the sampling holding circuit, and finally the output end of the output buffer circuit outputs a read-out signal.

The modulator is a passive or active modulator placed in front of the detector. When the modulator is in a first stage when being opened, the current generated by the detector is from the signal photocurrent of a scene plus the direct background current; in another stage, the radiation of the imaging target is blocked, only the direct background current appears, and the two stages are alternated to obtain the pulse signal current;

the gated multi-period integrating circuit GMCI comprises an operational amplifier, a front-end integrating capacitor C1 and two parallel integrating capacitors C_2a、C_2bA reset switch S4 and five control switches S1, S2, S3, S4, S_C2. The negative phase input end of the operational amplifier is connected with S3, the positive phase input end of the operational amplifier is connected with S1 and S3, C2a and S4 are connected across the negative phase input end and the output end of the operational amplifier, S_C2And C_2bThe series connection is also connected across the negative input and output of the operational amplifier. The integration process is divided into two parts, a direct integration DI stage and a transition integration TI stage. The first part is that signal current is injected in a direct integration DI stage, n periods are repeated, each period contains TI + DI, signals and backgrounds in the DI stage exist, the TI stage only has the background, the signals are cut off by a chopper at the moment, and a current output signal outD processed by a GMCI circuit is stored; the second part is to inject signal current in the transfer integration TI stage, only background exists in the DI stage, background and signal exist in the TI stage, and the sampling, holding and output signal outT are repeated for n periods. Integrating both background and infrared signals simultaneously in the presence of both background and useful infrared signals; subtracting the background when the infrared signal is chopped with only background present; the two operations are performed alternately for a plurality of times to effectively remove the background.

The holding circuit is adopted as a background suppression circuit and then connected with a correlated double sampling circuit, and by utilizing the correlation of noise in time, sampling is carried out twice in a very short time for subtraction, so that the noise can be reduced to a great extent, and the problem that a weak signal is submerged in a high background and cannot be read out can be effectively solved.

Based on the reading of weak signals under a large background, a novel quantum well focal plane detection array reading circuit with adjustable precision, strong background suppression capability and high reading resolution is designed by adopting a Gated Multi-Cycle Integration (GMCI).

The gated multi-cycle integration structure comprises a modulator of an input signal, a GMCI circuit, a sample hold circuit, a timing generation circuit, an output stage circuit and the like. In operation of the circuit, an incoming infrared light signal is detected by the QWIP via a modulator (here, optionally a mechanical chopper) and converted into an electrical signal, and the photo-generated current includes two components: the constant background current and the alternating current pulse signal current obtained by signal modulation are kept in direct current.

Integrating both background and infrared signals simultaneously in the presence of both background and useful infrared signals; subtracting the background when the infrared signal is chopped with only background present; the two operations are performed alternately for a plurality of times to effectively remove the background. The background suppression circuit is connected with a correlated double sampling circuit, and by utilizing the time correlation of noise, sampling is carried out twice in a very short time and then subtraction is carried out, so that the noise can be reduced to a great extent. Therefore, the problem that weak signals are submerged in a high background and cannot be read out can be effectively solved.

The method is characterized in that: aiming at the key problem of signal flooding of the background in the development of quantum well infrared detector projects, the influence of background current can be eliminated, and therefore the working performance of a reading circuit, such as signal-to-noise ratio and sensitivity, is effectively improved.

Background suppression readout circuits based on gated multi-cycle integration are able to read out small signals in high backgrounds. The useful signal current between 10nA and 20nA can be effectively read when the background current is 100 nA. The method can solve the problem that the background inundation signal is encountered in the current project development process, and has important guiding significance for the design of a background suppression reading circuit of a future high-performance large-area array quantum well infrared detector.

The advantages of this patent are as follows:

1. after analyzing several background current suppression methods of the predecessors Chih-Cheng Hsieh, Zhang Zhi, Zhao Chen and Byunghyuk Kim and the corresponding schematic diagrams thereof, the key point of suppressing the background current is to generate accurate background suppression current and subtract the current (background current + signal current) output by the pixel. Researchers at home and abroad also design background suppression circuits such as a voltage-current conversion method, a current replication method, a dark pixel compensation method and the like. However, the application of these circuits to quantum well detection for high background operation still has some disadvantages or shortcomings: the current copying unit has a complex structure, occupies a large layout area and is limited by the size of a device unit; the voltage-current conversion method background suppression circuit has a simple structure, but the background suppression current provided by the voltage-current conversion method is fixed, and the error is large; the background suppression circuit of the dark pixel compensation method has a complex structure, and the area and the power consumption of the layout are both large. Therefore, the research and development of a novel quantum well infrared focal plane array reading circuit applied to the reading of weak signals under a large background are urgently needed. The patent aims at solving the problem that a signal to be detected is submerged in a high background environment in the current project development, and designs a novel quantum well focal plane detection array reading circuit with adjustable precision, strong background suppression capability and high reading resolution ratio based on a Gated Multi-Cycle Integration (GMCI) structure. The circuit can have a reading circuit with a high background suppression function, and can achieve the purpose of reading weak signals in a high background environment.

2. The background suppression circuit is connected with a correlated double sampling circuit, and by utilizing the time correlation of noise, the noise can be reduced to a great extent by carrying out subtraction twice in sampling in a very short time.

3. The gate-control integrated high background signal reading circuit can work normally from normal temperature 300K to low temperature 77K, can be applied to signal reading of a quantum well high background detector, and can also be used as signal reading of other high background signal detectors.

Drawings

FIG. 1 is a schematic diagram of a gated multi-cycle integrator circuit.

Fig. 2 is an overall architecture diagram of a gated multi-cycle integration structure.

Fig. 3 is an equivalent circuit model of the direct integration process.

Fig. 4 is an equivalent circuit model at the start of integration.

Fig. 5 is an equivalent circuit model of the transfer process of the charge.

Fig. 6 is a correlated double sample and hold circuit.

Fig. 7 is a circuit schematic diagram of the shift register.

Detailed Description

The following detailed description of embodiments of the present patent refers to the accompanying drawings in which:

example 1

Fig. 1 and fig. 2 are a schematic diagram and an overall architecture diagram of a gated multi-cycle integration unit circuit, respectively, and include a modulator for an input signal, a GMCI circuit, a sample-and-hold circuit, a timing generation circuit, an output stage circuit, and the like. When the circuit works, an input infrared light signal is detected by QWIP through the modulator and converted into an electric signal, and a photo-generated current comprises two parts: the constant background current and the alternating current pulse signal current obtained by signal modulation are kept in direct current.

The key to suppress the high background is to modulate the signal source detected by the detector and then to control the corresponding readout circuit in two stages of modulation, and to place a passive (mechanical chopper, electro-optical switching polarizer or other devices) or active (pulsed laser produces fluorescence or other signals) modulator in front of the quantum well detector. In the first phase when the modulator Is on, the detector generates a current from the signal photocurrent Is of the scene plus a direct background current Ib (from the radiation or dark current when unmodulated). In the other phase, the radiation of the imaging target is blocked and only a direct current Ib is present. The two phases are alternated, so that the pulse-type signal current Is can be obtained.

The specific gating circuit principle is a CTIA structure, as shown in FIG. 1, and is a GMCI circuit with a selectable capacitor. By utilizing the virtual short characteristic of the operational amplifier, a stable bias voltage Vref is applied to the detector through a high-gain operational amplifier, so that the stability of the bias voltage of the detector is ensured.

When switch S1 is closed, the input current will be conducted through S1 to the voltage source V +. The blocking function is realized. When S1, S3 are open and S2 is closed, the input current will integrate first over C1. At the end of the integration phase, the charge stored on C1 will be transferred to C2 by closing S1, S3 after opening S2. Assuming the input current flows into the integrator, the right plate of C1 will collect negative charge during the integration period. During charge transfer, the negative charge stored by the right plate of C1 must be transferred to the left plate of C2 and the output voltage rises. Here a stage of integration is performed. This Integration process is called Transfer Integration (TI), i.e. the charge is first integrated on the capacitor C1 and then transferred to the capacitor C2.

When S1, S2 are open and S3 is closed, the input current will integrate directly over C1 and C2. During this integration phase, if the input current flows into the integrator, positive charge will be collected on the left plate of C2 (equal negative charge on the right plate of C1), which will result in a drop in the output voltage. Here, inverse integration is completed. This Integration process is called Direct Integration (DI), i.e. the charge is integrated directly on the capacitor C2.

Modulating the signal so that only background generated current (referred to as background current) is input to the readout circuit during DI; in the TI process, there is both background current and the infrared target signal (signal current) to be measured, which are input to the readout circuit. Thus, the signal and background are integrated simultaneously during DI; TI process subtracts background. The two operations are carried out alternately for a plurality of times, so that the background can be effectively reduced, and the required infrared target signal can be read.

Example 2

To further illustrate the principle of the circuit arrangement, a current source i is used as shown in FIG. 3_s,DIResistance R_dAnd an equivalent capacitance C_dTo simulate an equivalent model of a detector biased at V_sub. The current input by the detector is firstly applied to a capacitor C in the process of transferring integration through a sequential logic control read-out circuit₁Integrating up, storing in C by switch in the final stage of direct integration₁The charge on is transferred to the capacitor C₂The above step (1); while the current input during direct integration is directly at capacitor C₁And C₂And (4) integrating.

In the direct integration process, the current is directly in the capacitor C₁And C₂Upper integral according to node current law

According to the conservation of charge, there are

And according to the transfer function of the operational amplifier, have

V_o,DI＝A_o(V₊-V_-) (2.3)

From the formulae 2.2 and 2.3

Initial time

V_in,DI(0)＝V₊，V_o(0)＝V₊ (2.6)

Here, the signal current i is set_sEquivalent resistance R with detector_detThe input terminal (i.e. capacitor C) is available without changing over time₁Left plate) voltage

Wherein,

and also

Obtain the voltage of the output terminal

Integrating t in a direct integration process (see FIG. 4)_DITime, voltage difference of output terminal is

When the gain of the operational amplifier is A_o>>1，A_oC₂>>C₁When the difference between the output ends is

In the same way, in the process of transferring integrals (as shown in FIG. 5)

Here, the

τ_TI＝R_det(C_det+C_p+C₁) (2.15)

Integral t of transfer integration process_TITime, at this moment the capacitance C₁Has a charge of

Q_1a＝C₁[V_in,TI(t_TI)-V₊] (2.16)

Setting the voltage value of the reverse input terminal of the operational amplifier at the initial time to

The voltage value of the output end is

Then initially stored in capacitor C₂Has a charge of

The switches S1, S3 are closed and S2 is opened, and the charge stored on the capacitor C1 is transferred to the capacitor C2, where the charges on the capacitors C1, C2 are respectively

Q_1b＝C₁(V₊-V_-) (2.18a)

Q_2b＝C₂(V_o,TI-V_-) (2.18b)

Because of the conservation of charge at the V-point, there are

Q_1a+Q_2a＝Q_1b+Q_2b (2.19)

The voltage variation difference of the output end can be given

According to the characteristics of the operational amplifier, there are

V_o,TI＝A_o(V₊-V_-) (2.21b)

Obtained from the formulae 2.21a and 2.21b

In combination with the formula 2.20, the formula is shown in the specification,

is simplified to obtain

When the open loop gain A of the operational amplifier_o>>When the pressure of the mixture is 1, the pressure is lower,

voltage change at output terminal after a DI and a TI process

Then, the integration time of DI and TI processes is set to be tau/2, namely

Here, the input current i of the detector during the direct integration process and during the transfer integration process is assumed_s,DI、i_s,TIAre respectively as

Wherein i_sIs a modulated input signal current, I_bIs the background current. Thus, equation 2.25 is converted to

Carry-in 2.7 and formula 2.14, having

From the above, equation 2.29 becomes

The expression 2.30 is the voltage variation value of the output end after a transfer integration process and a direct integration process. The first term in the equation is caused by the signal current and the second term is the fixed noise of the readout circuit. As can be seen from equation 2.30, as the number of integration cycles increases, the stationary noise also increases. Is provided with

The C1 value can be properly selected to be far larger than the equivalent capacitance Cdet and the parasitic capacitance Cp of the detector, so that the equivalent capacitance Cdet and the parasitic capacitance Cp of the detector can be obtained

By using

Represents the initial reference voltage value of the m-th integration period (the reference voltage of the first integration period is

)，V_o,m-1Representing the value of the output voltage at the end of the (m-1) th integration period.

The voltage at the output terminal after the integration is completed for n periods (one period includes a TI process and a DI process) is

The second term on the right side in equation 2.34 is the fixed image noise after integrating n times, and is caused by the offset of the input voltage of the operational amplifier. It can be seen that the output voltage after multi-period integration is not strictly linear with the number n of integration periods, but is basically linear with the signal current i_s∝V_sIs linear in magnitude.

In general, equation 2.24 can be viewed as

If the input currents of the detector in the direct integration process and the transfer integration process are is, DI, is, TI respectively

The output will become

The difference between the formula (2.35) and the formula (2.37) is

At this time, the result is independent of the offset of the input voltage of the operational amplifier at the initial time, and the fixed image noise caused by the charge injection effect can be subtracted.

Example 3

According to the analysis, the integral integration process is divided into two parts, the first part injects signal current in the Direct Integration (DI) stage, repeats n periods (each period contains TI + DI, signals and backgrounds in the DI stage exist, the TI stage only has background, the signals are cut off by a chopper at the moment), stores the current processed by the GMCI circuit, outputs a signal VoutD, injects signal current in the Transfer Integration (TI) stage (the DI stage only has background, the TI stage has background and signals), repeats n periods, samples, keeps and outputs the signal VoutT. In the first integration part, the switch SHD is first closed and the switch SHT is opened, and the charge is in the capacitor C_H1Integrating upwards; in the second integration process, the switch SHD is opened and the switch SHT is closed, and the charge is in the capacitor C_H2And (4) integrating. The two integration parts are used for storing signals at intervals, then the output of the two signals VoutD and VoutT is controlled by a control signal Ctrl from a shift register (figure 6), namely, the holding circuit is used as a background suppression circuit and then is connected with a correlated double sampling circuit, and by utilizing the correlation of noise in time, sampling is carried out twice in a very short time for subtraction, so that the noise can be reduced to a great extent, and the problem that a weak signal is submerged in a high background and cannot be read out can be effectively solved.

In terms of the selection of the integrating capacitance, because of the integrating capacitance C₂The influence on the integration of dark leakage current and photocurrent of the infrared detector is large, so that the selection of a proper integration capacitor in the circuit design is very important. C₂Determines the charge capacity and noise of the capacitor. The main role of the readout circuit is KTC noise, and the operation of the readout circuit needs the integral capacitor C₁、C₂A periodic reset is performed, thereby generating KTC noise.

The KTC noise voltage may be expressed as

Wherein V_NIndicating the KTC noise voltage due to the reset of the integrating capacitor; k is Boltzmann's constant (1.38X 10)^-23J/K); t is the temperature in Fahrenheit. It can be seen that the noise of the circuit is inversely proportional to the size of the integrating capacitor, i.e. the larger the capacitance, the smaller the circuit noise. But because of layout area limitations, the integration capacitance cannot be infinite.

C_intThe larger the value is, the larger the charge capacity of the integrating capacitor is, and the sensitivity of the circuit is reduced along with the increase of the integrating capacitor; too small an integration capacitor may cause premature saturation of the capacitor (i.e., too high a voltage across the capacitor), resulting in too large an integration voltage input to the amplifier, which may result in non-linear distortion. Thus determining C_intMust balance the two requirements.

The maximum frequency of the chopper to be adopted is 20kHz, and the period is 50 us.

The GMCI outputs a peak value during integration that is related to an initial value, a single-period integration of the background current, and a total integration time of the signal current. Let the difference between the output peak and the initial value be DeltaV, have

Wherein T is the period of the chopper, N is the number of integration periods, and Δ V is the voltage difference of the integration capacitor. The output voltage should be the initial value plus the variation difference at this time

V_out＝V_o,i+ΔV (3.5)

V_outIs less than the power supply voltage (5V) of the circuit, the initial value of which is determined by the bias of the operational amplifier, is initially set to 2.5V, and the differential pressure av is less than 2.5V. Setting I according to parameters provided by the device_back＝100nA， I_s10 nA. So that there are

C≥(100+10×N)×10^-9×10×10^-6＝(10+N)×10^-13 (3.6)

The integrating capacitance C should be of the order pF. Based on the above consideration, the circuit adopts the design of the selectable integral capacitor (fig. 1).

Wherein, C₁＝2pF，C_2a＝C_2b1 pF. When the switch Sc2 is turned off, C₂Is 1 pF; when Sc2 is closed, C₂Is 2 pF. The size of the integrating capacitor can thus be selected in dependence on the actual current.

Example 4

When a gated integral high background signal reading circuit layout is designed, in order to reduce the total noise of a circuit, all digital PADs and analog PADs are separately arranged, a digital power supply and an analog power supply are separately supplied with power, and the coupling of digital pulse impact to an analog part through a substrate is reduced as much as possible. In the circuit, because the differential input geminate transistors are vertically and horizontally symmetrical, the input offset of the whole differential operational amplifier is reduced to a great extent, the symmetrical performance of the circuit is improved, and the total circuit noise caused by dark current due to offset voltage is reduced.

In layout design, the number of substrate contacts and well contacts formed by a P + region and an N + region is increased as much as possible to inhibit latch-up effect, an N + ring connected with a power supply is added around an NMOS transistor in an N well, a P + ring with ground potential is added around the NMOS transistor, and then the diffusion rings are in short circuit by metal to reduce the resistance connected with the power supply and the low potential, so that the resistance voltage drop formed by most current carriers in the substrate or the well is collected by a protection ring before the resistance voltage drop is injected into a parasitic transistor base region, the resistance value of a parasitic resistor can be reduced, the current gain of a PNP tube can be reduced, and latch-up is effectively prevented.

Example 5

The patent also discloses a shift register to complete the selective output of the 32-bit line array readout circuit, which mainly controls the sequential readout of the signals stored in the sample-and-hold circuit. The shift register can register digital codes and can shift the digital codes (namely, the digital codes registered in the shift register circuit are sequentially shifted to the left or to the right under the action of shift pulses). Fig. 7 is a schematic circuit diagram of a 32-bit shift register, which is composed of 32D flip-flops connected in series. Before working, the data needs to be cleared, then the data is input from the serial input end, and the output of the flip-flop Dm on the left side is used as the input of the adjacent flip-flop Dm +1 on the right side (m is 0,1,2, …, 31).

The table below is the transition conversion table for shift register operation, where d32d31d30 … d3d2d1 is the serial input; CLK is a shift pulse signal; qk (k-1, 2, …,32) is the output signal of flip-flop Dk, which is inverted

And is connected with the Ctrl signal in the corresponding sampling and holding circuit to control the signal readout of the kth GMCI unit. Qk, t represents the state at the present time, and Qk, t +1 represents the state after the rising edge of the next shift pulse CLK comes. Qk, t +1 is not only related to the serial input but also depends on the output state Qk, t at the previous moment. For convenience of control, the shift register is cleared before each operation, that is, the output transition state Q32Q31Q30 … Q3Q2Q1 is 000 … 000. Then, control data is input to obtain a corresponding output for selectively reading out the signal stored in the hold circuit.

State table of shift register

Example 6

According to different simulation results, the output and the pulse signal Is are in a linear relation, so that the pulse signal Is kept constant, the background current Ib Is different, and simulation Is carried out under the condition that integration Is carried out for 5 periods (the single period duration Is 51us, and the effective integration time Is 125us), and the simulation results in the following table are obtained.

Ib(nA)	V0	outD	|outD|	outT	|outT|	out
							0.00	1066.31	1503.61	437.29	655.85	410.46	847.75
10.00	1066.31	1503.62	437.31	655.84	410.48	847.79
							20.00	1066.31	1503.62	437.31	655.88	410.43	847.74
30.00	1066.31	1503.64	437.33	655.92	410.40	847.72
							40.00	1066.31	1503.59	437.28	655.97	410.34	847.61
50.00	1066.31	1503.50	437.18	655.90	410.41	847.59
							60.00	1066.31	1503.22	436.91	655.90	410.42	847.33
70.00	1066.31	1503.01	436.70	655.79	410.52	847.22
							80.00	1066.31	1501.80	435.49	655.61	410.70	846.19
90.00	1066.31	1499.39	433.08	654.65	411.67	844.75
							100.00	1066.31	1495.18	428.86	652.59	413.72	842.59
110.00	1066.31	1487.13	420.82	649.03	417.28	838.10
							120.00	1066.31	1470.72	404.41	641.92	424.39	828.79
130.00	1066.31	1440.65	374.33	628.79	437.53	811.86
							140.00	1066.31	1388.42	322.11	605.39	460.93	783.04
150.00	1066.31	1277.01	210.69	566.01	500.30	710.99
							160.00	1066.31	1121.81	55.50	477.78	588.53	644.03

Similarly, the constant pulse signal Is 10nA, only the background current Is changed to obtain the out-Ib relation curve, and when the background current Ib Is greater than 110nA, the out-Ib relation curve has a downward trend, which indicates that the circuit Is saturated and cannot work normally. The input background current range which can enable the circuit to work normally is 0 nA-110 nA. The result shows that the circuit can better read small signals in a high background, the background current input range is 0 nA-110 nA, the useful signal current between 2.5 nA-25 nA can be effectively read, and the output swing of the circuit is larger than 2V.

The patent is described above by way of specific examples, but the patent is not limited to these specific examples. It will be understood by those skilled in the art that various changes, substitutions of equivalents, variations, and so forth can be made to the patent without departing from the spirit of the patent and are intended to be within the scope of the patent.

Claims (2)

1. A gate-control integrated high background signal reading circuit comprises a modulator, a gate-control multi-period integrating circuit GMCI, a sampling hold circuit, a time sequence generating circuit and an output stage buffer circuit; the method is characterized in that:

the modulator is positioned in front of the detector, the output end of the modulated detector is connected with the input end of the gated multi-period integrating circuit GMCI, the output end of the gated multi-period integrating circuit GMCI is connected with the input end of the holding circuit, the output end of the sampling holding circuit is connected with the input end of the output buffer circuit, the time sequence generating circuit is respectively connected to the modulator, the gated multi-period integrating circuit GMCI and the sampling holding circuit, and finally the output end of the output buffer circuit outputs a read-out signal.

2. A gated integration high background signal readout circuit according to claim 1, wherein: the gate-controlled multi-period integrating circuit comprises an operational amplifier, a front-end integrating capacitor C1 and two parallel integrating capacitors C_2a、C_2bA reset switch S4 and five control switches S1, S2, S3, S4, S_C2(ii) a The negative phase input end of the operational amplifier is connected with S3, the positive phase input end of the operational amplifier is connected with S1 and S3, C2a and S4 are connected across the negative phase input end and the output end of the operational amplifier, S_C2And C_2bThe series connection is also connected across the negative input and output of the operational amplifier.

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