CN212012846U - Gate-controlled integral high background signal readout circuit - Google Patents

Abstract

The patent discloses a gate-control integrated high background signal reading circuit, which comprises a modulator, a gate-control multi-period integrated GMCI circuit, a sampling hold circuit, a time sequence generating circuit and an output stage buffer circuit. The integral integration process is divided into two parts, wherein the first part injects signal current in a direct integration DI stage, repeats n periods, stores the current processed by the GMCI circuit and outputs a signal outD; and secondly, injecting signal current in the stage of transferring integral TI, repeating n periods, sampling, holding and outputting a signal outT. When both background and useful infrared signals exist, the background and the infrared signals are simultaneously integrated, when the infrared signals are chopped and only the background exists, the background is subtracted, and the two operations are alternately carried out for multiple times, so that the background can be effectively removed. The background suppression circuit is connected with a correlated double sampling circuit, and by utilizing the correlation of noise in time, sampling is performed twice in a very short time for subtraction, so that the noise is reduced, and the reading problem that a weak signal is submerged in a high background is solved.

Description

High background signal readout circuit for gated integration

technical field

This patent relates to a CMOS circuit, in particular to a gate-integrated quantum well high background signal readout circuit.

Background technique

Quantum well infrared detectors will generate a very large background current, which is often referred to as dark current. According to the preliminary device test of the quantum well infrared detector, the photocurrent of the quantum well detection pixel is about 10nA, and the background current is about 10 times of the photocurrent, which is about 100nA. This causes the problem that the signal to be measured is buried in the background and cannot be read out. Therefore, a background suppression circuit must be added to the readout circuit of the quantum well infrared detector design unit in order to read out the weak signal that needs to be measured, which is much smaller than the background current. Signal. Quantum well infrared detectors generally work under a certain bias voltage and temperature. Due to the existence of the voltage difference, there will be a detector dark current composed of surface leakage current and intrinsic dark current in the current input to the readout circuit. In addition, reducing the dark current of the quantum well infrared detector can also suppress the noise of the device, such as thermal noise, 1/f noise, photon noise and shot noise. In order to improve the performance of the quantum well infrared detector, the device should also be denoised, that is, to suppress the dark current of the quantum well infrared detector, which is also an aspect of background suppression.

The infrared signal and the background signal useful in the operation of the quantum well infrared detector are input together into a readout circuit connected to the detector. The readout circuit integrates and amplifies the input signal. In this process, it not only integrates and amplifies the infrared signal, but also amplifies the background signal. Therefore, it is easy to appear that the integration capacitor is saturated before the integration period ends, so that the detector loses the function of detecting the infrared intensity of the target. Therefore, when designing a readout circuit, the integrating capacitor is generally required to be large enough, but an excessively large integrating capacitor will conflict with the limited layout area. This means that it is impossible to blindly increase the integrating capacitance, so it is necessary to use the background current suppression circuit to delete or suppress the background signal before integrating the signal output by the quantum well detector pixel, so that the readout circuit can only integrate the useful signal. infrared signal. Background suppression is to suppress or delete the background current in the presence of both signal and background and only integrate the useful infrared signal to be measured.

In the existing literature, Zhao Chen and Byunghyuk Kim et al designed a background suppression circuit based on the current replication method. The principle is to first record and copy the background current, and then compare the copied background current with the signal current output by the pixel. Subtract, to achieve the function of background suppression. The specific process is as follows: first control the reset tube to reset the integrating capacitor to the set reset voltage value before working, and then the charge output by the detector pixel is directly integrated on the integrating capacitor after passing through the injection tube; the current copy circuit copies the background current, and the control tube In order to switch the current copy circuit, turn on or off the strobe tube to select and output the integral signal obtained. The working process of the current replication background suppression circuit is divided into two stages. The first step is to calibrate the circuit, copy the background current, so that the pixel only generates the current caused by the background. At this time, the switch tube in the current copy circuit is in a saturated state, and at the same time, the reset tube is controlled to reset the integrating capacitor, so that the pixel generated by the current is in saturation. The background current (including the dark current) is copied to the capacitor and the gate-source voltage value that generates the background current is recorded; the second step is the integration readout stage to make the detector work normally, and the current generated by the pixel is the signal current. The sum of the background current and the control signal will output the previously recorded background current under the action of the stored voltage on the memory capacitor, thus realizing the function of background suppression. The working principle of the current replication method is that a memory capacitor is used to record the voltage difference required to generate the suppression current. However, as the time increases, the capacitor has leakage current and other reasons, and the generated suppression current is no longer equal to the background current. The inhibitory function gradually deteriorates until the inhibitory function is lost.

After analyzing the background current suppression methods mentioned above and their corresponding schematic diagrams, it is found that the key to suppressing the background current is to generate an accurate background suppression current and subtract it from the current (background current + signal current) output by the pixel. Other domestic and foreign researchers have also designed background suppression circuits such as voltage-current conversion method, current replication method, and dark pixel compensation method. However, there are still some shortcomings or deficiencies in the application of these circuits to the detection of quantum wells with high background: the structure of the current replication unit is complex, the layout area occupied is large, and it is limited by the size of the device unit; the voltage-current conversion method background suppression circuit has a simple structure, However, the background suppression current provided by it is fixed, and the error is large; the background suppression circuit of the dark pixel compensation method has a complex structure, and the layout area and power consumption are relatively large. Therefore, there is an urgent need to develop a novel quantum well infrared focal plane array readout circuit for weak signal readout in a large background.

In order to solve the problem that the signal to be measured is submerged in a high background environment encountered in the development of the current project, this patent overcomes the shortcomings of the method used in the above literature, and designs a gated multi-cycle integration (Gated Multi-Cycle Integration, GMCI) structure, a novel quantum well focal plane detection array readout circuit with adjustable precision, strong background suppression capability and high readout resolution is designed. The purpose of reading out weak signals.

SUMMARY OF THE INVENTION

This patent is a gated integration high background signal readout circuit, including a modulator, a gated multi-cycle integration circuit GMCI, a sample and hold circuit, a timing generation circuit and an output stage buffer circuit; the connection relationship is: the modulator is located in the detection In front of the detector, the modulated detector output end is connected to the input end of the gated multi-cycle integration circuit GMCI, the output end of the gated multi-cycle integration circuit GMCI is connected to the input end of the hold circuit, and the output end of the sample and hold circuit is connected to the output buffer The input end of the circuit and the timing generation circuit are respectively connected to the modulator, the gated multi-cycle integration circuit GMCI and the sample and hold circuit, and finally the output end of the output buffer circuit outputs the readout signal.

The modulator is a passive or active modulator placed in front of the detector. When the modulator is turned on, in the first stage, the current generated by the detector comes from the signal photocurrent of the scene plus the DC background current; in the other stage, the radiation of the imaging target is blocked, only the DC background current appears, and the two The phases are alternated, and a pulsed signal current is obtained;

The gated multi-cycle integration circuit GMCI includes an operational amplifier, a front-end integration capacitor C1 and two parallel integration capacitors C _2a , C _2b , a reset switch S4 and five control switches S1 , S2 , S3 , S4 , S _C2 . The negative phase input terminal of the operational amplifier is connected to S3, the positive phase input terminal is connected to S1 and S3, C2a and S4 are connected across the negative phase input terminal and output terminal of the operational amplifier, and S _C2 and C _2b are also connected across the operational amplifier after being connected in series. of the negative input and output. The integration process is divided into two parts, the direct integration DI stage and the transfer integration TI stage. The first part is to inject the signal current in the direct integration DI stage, repeating n cycles, each cycle includes TI+DI, both the signal and the background in the DI stage, only the background in the TI stage, at this time the signal is cut off by the chopper and stored The current output signal outD after being processed by the GMCI circuit; the second part is to inject the signal current in the TI stage of the transfer integration, only the background exists in the DI stage, and the background and the signal exist in the TI stage, repeating n cycles, sampling and holding and outputting the signal outT. When both the background and the useful infrared signal exist, the background and the infrared signal are integrated at the same time; when the infrared signal is cut off and only the background exists, the background is subtracted; these two operations can be performed alternately for many times to effectively remove the background.

The holding circuit is used as the background suppression circuit, followed by the correlated double sampling circuit. Using the correlation of noise in time, sampling twice in a very short time for subtraction, the noise can be greatly reduced, so it can effectively Solve the problem that the weak signal is submerged in the high background and cannot be read.

This patent is based on the readout of weak signals in a large background, and adopts a gated multi-cycle integration (GMCI) structure to design a new type of quantum well focus with adjustable precision, strong background suppression capability and high readout resolution. Planar probing array readout circuit.

The gated multi-cycle integration structure includes the modulator of the input signal, the GMCI circuit, the sample and hold, the timing generation circuit and the output stage circuit. When the circuit is working, the input infrared light signal is detected by the QWIP through the modulator (here, a mechanical chopper is selected) and converted into an electrical signal. The photo-generated current consists of two parts: the background current that is DC and remains constant and the result obtained by signal modulation. The AC pulse signal current.

When both the background and the useful infrared signal exist, the background and the infrared signal are integrated at the same time; when the infrared signal is cut off and only the background exists, the background is subtracted; these two operations can be performed alternately for many times to effectively remove the background. After the background suppression circuit is connected to the correlated double sampling circuit, the noise can be greatly reduced by sampling twice in a very short time and then subtracting by using the time correlation of the noise. This can effectively solve the problem that the weak signal is submerged in the high background and cannot be read.

It is characterized in that: Aiming at the key problem of background submerged signal in the development of quantum well infrared detector project, this patent can eliminate the influence of background current, thereby effectively improving the working performance of the readout circuit, such as signal-to-noise ratio and sensitivity. .

The background suppression readout circuit based on gated multi-cycle integration is able to read out small signals in high background. When the background current is 100nA, the useful signal current between 10nA and 20nA can be effectively read out. This patent can not only solve the background submerged signal problem encountered during the development of the current project, but also has important guiding significance for the design of the background suppression readout circuit of the high-performance large-area-array quantum well infrared detector in the future.

The advantages of this patent are as follows:

1. After analyzing the background current suppression methods and their corresponding schematic diagrams of predecessors Chih-Cheng Hsieh, Zhang Zhi, Zhao Chen, Byunghyuk Kim, etc., it is found that the key to suppressing background current is to generate accurate background suppression current and It is subtracted from the current output by the pixel (background current + signal current). Researchers at home and abroad have also designed background suppression circuits such as voltage-current conversion method, current replication method, and dark pixel compensation method. However, there are still some shortcomings or deficiencies in the application of these circuits to the detection of quantum wells with high background: the structure of the current replication unit is complex, the layout area occupied is large, and it is limited by the size of the device unit; the voltage-current conversion method background suppression circuit has a simple structure, However, the background suppression current provided by it is fixed, and the error is large; the background suppression circuit of the dark pixel compensation method has a complex structure, and the layout area and power consumption are relatively large. Therefore, there is an urgent need to develop a novel quantum well infrared focal plane array readout circuit for weak signal readout in a large background. This patent is aimed at solving the problem that the signal to be measured is submerged in a high background environment encountered in the development of the current project. Based on the gated multi-cycle integration (GMCI) structure, the design of adjustable precision and background suppression A novel quantum well focal plane detection array readout circuit with strong capability and high readout resolution. The circuit can have a readout circuit with a high background suppression function, and can achieve the purpose of reading out weak signals in a high background environment.

2. The background suppression circuit is followed by a correlated double sampling circuit. Using the correlation of noise in time, sampling twice in a very short time for subtraction, the noise can be greatly reduced.

3. The high background signal readout circuit of the gated integration can work normally from normal temperature 300K to low temperature 77K. It can not only be applied to the signal readout of quantum well high background detectors, but also can be used as the signal of other high background signal detectors. read out.

Description of drawings

Figure 1 is a schematic diagram of a gated multi-cycle integrating circuit unit.

Figure 2 is the overall architecture diagram of the gated multi-cycle integration structure.

Figure 3 shows the equivalent circuit model of the direct integration process.

Figure 4 shows the equivalent circuit model at the start of integration.

FIG. 5 is an equivalent circuit model of the charge transfer process.

Figure 6 is a correlated double sampling and holding circuit.

FIG. 7 is a circuit schematic diagram of a shift register.

Detailed ways

Below in conjunction with accompanying drawing, the specific embodiment of this patent is described in further detail:

Example 1

Figure 1 and Figure 2 are the circuit schematic diagram and overall structure diagram of the gated multi-cycle integration unit, including the modulator of the input signal, the GMCI circuit, the sample and hold, the timing generation circuit, and the output stage circuit. When the circuit is working, the input infrared light signal is detected by the QWIP through the modulator and converted into an electrical signal. The photo-generated current includes two parts: the background current that is DC and remains constant and the AC pulse signal current obtained by signal modulation.

The key to suppressing high background is to modulate the signal source detected by the detector, and then control the corresponding readout circuit in the two stages of modulation, placing a passive (mechanical chopper, electro-optical switch polarization) in front of the quantum well detector. device) or active (pulsed laser to generate fluorescence or other signal) modulator. When the modulator is turned on in the first phase, the detector produces a current from the scene's signal photocurrent Is plus the DC background current Ib (either from radiation or dark current when unmodulated). In another phase, the radiation from the imaging target is blocked and only DC Ib appears. The two phases are alternated, and the pulsed signal current Is can be obtained.

The specific gate control circuit principle is the CTIA structure, as shown in Figure 1, which is a GMCI circuit with optional capacitors. Using the "virtual short" feature of the operational amplifier, a stable bias voltage Vref is applied to the detector through a high-gain operational amplifier to ensure the stability of the detector bias voltage.

When the switch S1 is closed, the input current will conduct to the voltage source V+ through S1. The blocking function is realized. When S1 and S3 are open and S2 is closed, the input current will first integrate on C1. In the final stage of integration, the charge stored on C1 will be transferred to C2 by opening S2 and closing S1, S3. Assuming the input current flows into the integrator, the C1 right plate will collect negative charge during integration. During charge transfer, the negative charge stored on the right plate of C1 must be transferred to the left plate of C2, and the output voltage rises. Here one stage of integration is performed. This integration process is called transfer integration (TI), that is, the charge is first integrated on the capacitor C1 and then transferred to the capacitor C2.

When S1 and S2 are open and S3 is closed, the input current will be directly integrated across C1 and C2. During this integration phase, if the input current flows into the integrator, positive charge will be collected on the left plate of C2 (and an equal negative charge will be collected on the right plate of C1), which will cause the output voltage to drop. The reverse integration is done here. This integration process is called direct integration (DI), that is, the charge is directly integrated on the capacitor C2.

Modulate the signal so that only the current generated by the background (called background current) is input to the readout circuit in the DI process; in the TI process, both the background current and the infrared target signal to be measured (signal current) are input to the readout circuit. . In this way, signal and background are integrated simultaneously during DI; background is subtracted during TI. The two operations are interleaved for many times, which can effectively reduce the background and read out the required infrared target signal.

Example 2

In order to further illustrate the principle of the circuit structure, as shown in Figure 3, a current source is _,DI , resistance R _d , equivalent capacitance C _d is used to simulate the equivalent model of the detector, and the detector bias is V _sub . During the transfer integration process, the readout circuit is controlled by sequential logic to integrate the current input by the detector on the capacitor C ₁ first, and in the final stage of the direct integration, the charge stored on C ₁ is transferred to the capacitor C ₂ through the switch; and The current input during direct integration is directly integrated across capacitors _C1 and _C2 .

During direct integration, the current is integrated directly across capacitors _C1 and _C2 , according to the nodal current law

According to the conservation of charge, we have

According to the transfer function of the operational amplifier, we have

V _o,DI = A _o (V ₊ -V _- ) (2.3)

From Equation 2.2 and Equation 2.3, we can get

initial moment

V _in,DI (0)=V ₊ , V _o (0)=V ₊ (2.6)

Here, it is _{assumed that the signal current is and the equivalent resistance R det of} the detector do not change with time, and the voltage at the input end (ie the left plate of the capacitor C ₁ ) can be obtained

in,

again

get the voltage at the output

The direct integration process (as shown in Figure 4) integrates t _DI time, and the voltage difference at the output is

When the operational amplifier gain A _o >> 1, A _o C ₂ >> C ₁ , the difference at the output is

Similarly, in the process of transfer integration (as shown in Figure 5)

here

τ _TI =R _det (C _det +C _p +C ₁ ) (2.15)

The transfer integration process integrates t _TI time, and the charge on capacitor C ₁ at this time is

Q _1a =C ₁ [V _in,TI (t _TI )-V ₊ ] (2.16)

输出端电压值为

那么初始时存储在电容器C₂上的电荷为Set the initial op amp's inverting input voltage to be

The output voltage is

Then the charge initially stored _on capacitor C2 is

The switches S1 and S3 are closed and S2 is opened at the same time, and the charge stored in the capacitor C1 will be transferred to the capacitor C2. At this time, the charges on the capacitors C1 and C2 are

Q _1b =C ₁ (V ₊ -V _- ) (2.18a)

Q _2b = C ₂ (V _{o, TI} -V _- ) (2.18b)

Because of the conservation of charge at the V-point, we have

Q _1a +Q _2a =Q _1b +Q _2b (2.19)

Can give the difference in voltage change at the output

According to the characteristics of the operational amplifier, there are

V _o,TI =A _o (V ₊ -V _- ) (2.21b)

Obtained by Equation 2.21a and Equation 2.21b

Recombining Equation 2.20,

Simplify to get

When the open-loop gain of the op amp A _o >> 1,

After a DI and a TI process, the voltage change at the output terminal is

Then set the process integration time of DI and TI as τ/2, that is,

Here, the input currents is _,DI , is _,TI of the detector in the direct integration process and the transfer integration process are set as

where is is the _{modulated input signal current and Ib is} the background current. In this way, Equation 2.25 is converted into

Bringing in Equation 2.7 and Equation 2.14, we have

In summary, Equation 2.29 becomes

Equation 2.30 is the voltage change value at the output terminal after a transition integration process and a direct integration process. where the first term is due to the signal current and the second term is the fixed noise of the readout circuit. From Equation 2.30, it can be known that with the increase of the number of integration periods, the stationary noise will also increase. Assume

A suitable value of C1 can be taken to make it much larger than the equivalent capacitance Cdet of the detector and the parasitic capacitance Cp, then we can get

表示第m个积分周期的初始参考电压值(第一个积分周期的参考电压为

)，V_o,m-1表示第m-1个积分周期结束时的输出电压值。use

Indicates the initial reference voltage value of the mth integration period (the reference voltage of the first integration period is

), V _o,m-1 represents the output voltage value at the end of the m-1th integration period.

After n cycles (one cycle includes one TI process and one DI process), the voltage at the output terminal is

The second term on the right side of Equation 2.34 is the fixed image noise after n integrations, caused by the input voltage offset of the op amp. It can be seen that the output voltage after multi-cycle integration is not strictly linear with the number of integration periods n, but basically has a linear relationship with the magnitude of the signal current i _s ∝ V _s .

Normally, Equation 2.24 can be seen as

If the input currents is, DI, is, TI of the detector in the direct integration process and the transfer integration process are set as

the output will become

The difference between formula (2.35) and formula (2.37) is

In this case the result is independent of the initial op amp's input voltage offset, and the fixed image noise caused by the charge injection effect can also be subtracted.

Example 3

According to the aforementioned analysis, the overall integration process is divided into two parts. The first part injects the signal current in the direct integration (DI) stage, which is repeated for n cycles (each cycle contains TI+DI, both the signal and the background exist in the DI stage, the TI stage There is only background in the stage; the signal is cut off by the chopper at this time), the current processed by the GMCI circuit is stored, the output signal VoutD is output, and the signal current is injected in the transfer integral (TI) stage (only the background exists in the DI stage, and the background and the signal exist in the TI stage. ), repeating for n cycles, sampling and holding and outputting the signal VoutT. In the first integration part, the switch SHD is closed and the SHT is disconnected, and the charge is integrated on the capacitor _CH1 at this time; in the second integration process, the switch SHD is opened and the SHT is closed, and the charge is integrated on the capacitor _CH2 . . The two integral parts are used to store the signals at an interval for a period of time, and then the output of the two signals VoutD and VoutT are controlled by the control signal Ctrl from the shift register (Fig. 6), that is, the holding circuit is used as the background suppression circuit. Connected to the correlated double sampling circuit, using the correlation of noise in time, sampling twice in a very short time for subtraction, the noise can be greatly reduced, which can effectively solve the problem that the weak signal is submerged in the high background. Unable to read the problem.

In terms of the selection of the integrating capacitor, because the integrating capacitor C ₂ has a great influence on the integration of the dark leakage current and the photocurrent of the infrared detector, it is very important to select the appropriate integrating capacitor in the circuit design. _The size of C2 determines the charge capacity and noise of this capacitor. The KTC noise plays a major role in the readout circuit. During the operation of the readout circuit, it is necessary to periodically reset the integrating capacitors C ₁ and C ₂ , thereby generating the KTC noise.

其中V_N表示积分电容的复位而引起的KTC噪声电压；K是玻尔兹曼常数(1.38×10^-23J/K)；T是华氏温度。可以看出，电路的噪声与积分电容的大小呈反比，即电容越大，电路噪声越小。但因为版图面积限制，积分电容不可能无限大。The KTC noise voltage can be expressed as

Wherein V _N represents the KTC noise voltage caused by the reset of the integrating capacitor; K is the Boltzmann constant (1.38×10 ^-23 J/K); T is the temperature in Fahrenheit. It can be seen that the noise of the circuit is inversely proportional to the size of the integrating capacitor, that is, the larger the capacitor, the smaller the circuit noise. However, due to the limitation of the layout area, the integrating capacitor cannot be infinitely large.

The larger the value of C _int , the greater the charge capacity of the integrating capacitor, and the sensitivity of the circuit decreases with the increase of the integrating capacitor; if the integrating capacitor is too small, the capacitor may saturate prematurely (that is, the voltage across the capacitor is too high), resulting in As a result, the integrated voltage input to the amplifier is too large, resulting in nonlinear distortion. Therefore, determining the size of C _int must balance two requirements.

The maximum frequency of the chopper to be used is 20kHz, and the period is 50us.

The output peak value of GMCI in the integration process is related to the initial value, the single-cycle integration of the background current and the total integration time of the signal current. Set the difference between the output peak value and the initial value as ΔV, we have

Among them, T is the chopper period, N is the integral period number, ΔV is the voltage difference of the integral capacitor. At this time, the output voltage should be the initial value plus the change difference

V _out =V _o,i +ΔV (3.5)

V _out should be less than the power supply voltage (5V) of the circuit, and its initial value is determined by the bias of the operational amplifier. It is initially set to 2.5V, and the differential pressure ΔV should be less than 2.5V. According to the parameters provided by the device, set I _back = _100nA and Is = 10nA. F

C≥(100+10×N)×10 ^-9 ×10×10 ^-6 =(10+N)×10 ^-13 (3.6)

The integrating capacitor C should be on the order of pF. Based on the above considerations, this circuit uses an optional integrating capacitor design (Figure 1).

Wherein, C ₁ =2pF, C _2a =C _2b =1pF. When switch Sc2 is open, _C2 is 1pF; when Sc2 is closed, _C2 is 2pF. In this way, the size of the integrating capacitor can be selected according to the actual current.

Example 4

When designing the high background signal readout circuit layout of gated integration, in order to reduce the total noise of the circuit, all digital PADs and analog PADs are laid out separately, and the digital power supply and the analog power supply are separately supplied to minimize the digital pulse impact through the substrate coupling to the simulation section. When drawing the layout, all amplifier pairs of tubes use interdigital transistors, and try to ensure up-down and left-right symmetry, which can reduce the input offset of the CMOS differential operational amplifier, especially the input tube of the differential amplifier, which is particularly important. In this circuit Since the differential input pair tube adopts up-down and left-right symmetry, which greatly reduces the input offset of the entire differential operational amplifier, improves the symmetrical performance of the circuit, and reduces the total circuit total caused by the dark current caused by the offset voltage. noise.

In the layout design, try to increase the number of substrate contacts and well contacts formed by the P+ region and the N+ region to suppress the latch-up effect, add an N+ ring connected to the power supply around the NMOS transistor in the N well, and add a ground around the NMOS transistor. The potential P+ ring, and then these diffusion rings are short-circuited with metal to reduce the resistance of the power supply and the low potential, so that the resistance voltage drop formed by the majority carrier in the substrate or well can be injected into the parasitic transistor base. The area is collected by the guard ring before, which can not only reduce the parasitic resistance value, but also reduce the current gain of the PNP tube, effectively preventing latch-up.

Example 5

The patent also designs a shift register to complete the selection output of the 32-element line-column readout circuit, and its main function is to control the sequential readout of the signals stored in the sample-and-hold circuit. The shift register can not only register numbers, but also shift the numbers (that is, under the action of the shift pulse, the numbers registered in the shift register circuit are shifted left or right in turn). Figure 7 is a circuit schematic diagram of a 32-bit shift register, which consists of 32 D flip-flops in series. It needs to be cleared to zero before working, and then the data is input from the serial input terminal, and the output of the flip-flop Dm on the left is used as the output of the adjacent flip-flop Dm+1 (m=0,1,2,...,31) on the right. enter.

与对应的采样保持电路中的Ctrl信号相连，用以控制第k个GMCI单元的信号读出。Qk,t表示当前时刻的状态，Qk,t+1表示下一移位脉冲CLK上升沿到来之后的状态。Qk,t+1不仅与串行输入有关，还取决于前一时刻的输出状态Qk,t。为了方便控制，每次工作前都将移位寄存器清零，即输出转态 Q32Q31Q30…Q3Q2Q1＝000…000。然后再输入控制数据，得到相应输出用以选择读出存储在采用保持电路中的信号。The following table is the transition table of the shift register work, in which d32d31d30...d3d2d1 is the serial input; CLK is the shift pulse signal; Qk (k=1,2,...,32) is the output signal of the flip-flop Dk, which obtained by negation

It is connected with the Ctrl signal in the corresponding sample and hold circuit to control the signal readout of the kth GMCI unit. Qk,t represents the state at the current moment, and Qk,t+1 represents the state after the rising edge of the next shift pulse CLK arrives. Qk,t+1 is not only related to the serial input, but also depends on the output state Qk,t at the previous moment. In order to facilitate control, the shift register is cleared before each work, that is, the output transition state Q32Q31Q30...Q3Q2Q1=000...000. Then input the control data, and get the corresponding output to select and read the signal stored in the holding circuit.

Shift register state table

Example 6

According to different simulation results, it is shown that the output has a linear relationship with the pulse signal Is. For this reason, the pulse signal Is is kept constant and the background current Ib is different, and the simulation is carried out under the condition of 5 cycles of integration (the duration of a single cycle is 51us, and the effective integration time is 125us). , the simulation results in the table below are obtained.

I_b(nA) V₀ outD |outD| outT |outT| out 0.00 1066.31 1503.61 437.29 655.85 410.46 847.75 10.00 1066.31 1503.62 437.31 655.84 410.48 847.79 20.00 1066.31 1503.62 437.31 655.88 410.43 847.74 30.00 1066.31 1503.64 437.33 655.92 410.40 847.72 40.00 1066.31 1503.59 437.28 655.97 410.34 847.61 50.00 1066.31 1503.50 437.18 655.90 410.41 847.59 60.00 1066.31 1503.22 436.91 655.90 410.42 847.33 70.00 1066.31 1503.01 436.70 655.79 410.52 847.22 80.00 1066.31 1501.80 435.49 655.61 410.70 846.19 90.00 1066.31 1499.39 433.08 654.65 411.67 844.75 100.00 1066.31 1495.18 428.86 652.59 413.72 842.59 110.00 1066.31 1487.13 420.82 649.03 417.28 838.10 120.00 1066.31 1470.72 404.41 641.92 424.39 828.79 130.00 1066.31 1440.65 374.33 628.79 437.53 811.86 140.00 1066.31 1388.42 322.11 605.39 460.93 783.04 150.00 1066.31 1277.01 210.69 566.01 500.30 710.99 160.00 1066.31 1121.81 55.50 477.78 588.53 644.03

Similarly, the constant pulse signal Is is 10nA, only the background current is changed, and the out-Ib relationship curve is obtained. It can be obtained that when the background current Ib is greater than 110nA, the out-Ib relationship curve shows a clear downward trend, indicating that the circuit is saturated and cannot be normal work. The input background current range that can make the circuit work normally is 0nA～110nA. The results show that the circuit can read small signals in high background well, the input range of background current is 0nA～110nA, and the useful signal current between 2.5nA～25nA can be effectively read out, and the output swing of the circuit is greater than 2V.

The present patent has been described above through specific embodiments, but the present patent is not limited to these specific embodiments. Those skilled in the art should understand that various modifications, equivalent substitutions, changes, etc. can also be made to this patent, and these changes shall fall within the protection scope of this patent as long as they do not deviate from the spirit of this patent.

Claims (2)

1. A gate-control integrated high background signal reading circuit comprises a modulator, a gate-control multi-period integrating circuit GMCI, a sampling hold circuit, a time sequence generating circuit and an output stage buffer circuit; the method is characterized in that:

the modulator is positioned in front of the detector, the output end of the modulated detector is connected with the input end of the gated multi-period integrating circuit GMCI, the output end of the gated multi-period integrating circuit GMCI is connected with the input end of the holding circuit, the output end of the sampling holding circuit is connected with the input end of the output buffer circuit, the time sequence generating circuit is respectively connected to the modulator, the gated multi-period integrating circuit GMCI and the sampling holding circuit, and finally the output end of the output buffer circuit outputs a read-out signal.

2. A gated integration high background signal readout circuit according to claim 1, wherein: the gate-controlled multi-period integrating circuit comprises an operational amplifier, a front-end integrating capacitor C1 and two parallel integrating capacitors C_2a、C_2bA reset switch S4 and five control switches S1, S2, S3, S4, S_C2(ii) a The negative phase input end of the operational amplifier is connected with S3, the positive phase input end of the operational amplifier is connected with S1 and S3, C2a and S4 are connected across the negative phase input end and the output end of the operational amplifier, S_C2And C_2bThe series connection is also connected across the negative input and output of the operational amplifier.

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