CN114709203B - A single-phase full-bridge intelligent power module based on gallium nitride power chips - Google Patents

A single-phase full-bridge intelligent power module based on gallium nitride power chips

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Publication number
CN114709203B
CN114709203B CN202111528391.0A CN202111528391A CN114709203B CN 114709203 B CN114709203 B CN 114709203B CN 202111528391 A CN202111528391 A CN 202111528391A CN 114709203 B CN114709203 B CN 114709203B
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chip
driver
copper layer
copper
chips
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CN114709203A (en
Inventor
王来利
姚乙龙
杨奉涛
孔航
王振宇
张轶凡
汪岩
齐志远
张翅
苏宇泉
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Meiken Semiconductor Technology Co ltd
Xian Jiaotong University
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Meiken Semiconductor Technology Co ltd
Xian Jiaotong University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes

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Abstract

一种基于氮化镓功率芯片的单相全桥智能功率模块，包括驱动板、功率板、模块外壳和散热器；驱动板和功率板均设置在模块外壳内，且驱动板设置在功率板上，功率板和驱动板通过键合线连接；散热器设置在模块外壳底部；功率板包括两个氮化镓芯片和两个硅芯片，两个氮化镓芯片和两个硅芯片组成全桥电路；驱动板包括四个用于驱动功率板上四个芯片的驱动芯片；本发明基于氮化镓芯片设计单相全桥智能功率模块，氮化镓器件相比传统的硅器件拥有更高的开关速度，因而在开关过程中相比传统硅器件对寄生参数更加敏感。本模块设计出一种基于氮化镓功率芯片的全桥布局，并实现驱动芯片在模块内的集成。

A single-phase full-bridge intelligent power module based on gallium nitride (GaN) power chips includes a driver board, a power board, a module housing, and a heat sink. Both the driver board and the power board are housed within the module housing, with the driver board mounted on the power board. The power board and driver board are connected via bonding wires. The heat sink is located at the bottom of the module housing. The power board includes two GaN chips and two silicon chips, forming a full-bridge circuit. The driver board includes four driver chips for driving the four chips on the power board. This invention designs a single-phase full-bridge intelligent power module based on GaN chips. Compared to traditional silicon devices, GaN devices have higher switching speeds and are therefore more sensitive to parasitic parameters during switching. This module designs a full-bridge layout based on GaN power chips and integrates the driver chips within the module.

Description

Single-phase full-bridge intelligent power module based on gallium nitride power chip
Technical Field
The invention belongs to the technical field of power modules, and particularly relates to a single-phase full-bridge intelligent power module based on a gallium nitride power chip.
Background
The power module is a module for packaging and integrating the power electronic chip. Compared to discrete devices, it has higher reliability, lower parasitic parameters, higher power density and lower losses, playing a vital role in power electronics applications. The IPM realizes the integration of the driving chip and the driving chip in the design process, and reduces the design difficulty of the peripheral circuit. The current packaging technology also provides customized packaging for characteristic topology, so that the efficiency of the power electronic converter can be improved, and the reliability of the power electronic device can be improved.
Most of the current wide bandgap semiconductors still use the packaging integration mode of the traditional silicon-based semiconductors, so that the exertion of the excellent characteristics of the wide bandgap semiconductors is limited, and the wide bandgap semiconductors are the bottleneck problem of the application of the wide bandgap semiconductor power devices. If the chip packaging technology is improper, serious overvoltage, electromagnetic interference and other problems can be caused, so that the loss of the power electronic switch device is increased, and the reliability of the device is deteriorated.
Disclosure of Invention
The invention aims to provide a single-phase full-bridge intelligent power module based on a gallium nitride power chip so as to solve the problems.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the single-phase full-bridge intelligent power module based on the gallium nitride power chip comprises a driving plate, a power plate, a module shell and a radiator, wherein the driving plate and the power plate are arranged in the module shell, the driving plate is arranged on the power plate, and the power plate is connected with the driving plate through a bonding wire;
The power board comprises two gallium nitride chips and two silicon chips, and the two gallium nitride chips and the two silicon chips form a full-bridge circuit;
The driving plate comprises four driving chips used for driving the four chips on the power plate, the four driving chips are located on the side face of the chip on the power plate, and decoupling capacitors and driving resistors are arranged on the periphery of the driving chips.
Further, the bottom plate of the power board is a ceramic substrate, a first copper layer, a second copper layer, a third copper layer, a fourth copper layer and a fifth copper layer are sintered on the top surface of the ceramic substrate, the whole copper is sintered on the bottom surface of the ceramic substrate, a first chip is arranged on the first copper layer, a second chip is arranged on the second copper layer, a third chip is arranged on the third copper layer, a fourth chip is arranged on the fourth copper layer, and the fifth copper layer.
Further, the upper surface of the third chip source electrode is connected with the second copper layer, the upper surface of the second chip source electrode is connected with the fifth copper layer, the first chip source electrode is connected with the third copper layer, the first chip drain electrode is connected with the first copper layer, the fourth chip source electrode is connected with the first copper layer, and the fourth chip drain electrode is connected with the fourth copper layer.
Further, the first chip and the fourth chip are gallium nitride chips, and the second chip and the third chip are silicon MOS chips.
Further, two pins are arranged on the second copper layer, the third copper layer, the fourth copper layer and the fifth copper layer, and one pin is arranged on the first copper layer.
Furthermore, four decoupling capacitors are welded between the third copper layer and the fourth copper layer, and four decoupling capacitors are welded between the third copper layer and the fifth copper layer.
The four driving chips are a first driving chip, a second driving chip, a third driving chip and a fourth driving chip, wherein the first driving chip is used for driving the first chip, the second driving chip is used for driving the fourth chip, the third driving chip is used for driving the third chip, and the fourth driving chip is used for driving the second chip;
The periphery of the first driving chip is provided with two capacitors and three resistors to form a first driving chip peripheral circuit, the second bootstrap diode, four capacitors and one resistor to form a bootstrap circuit, the periphery of the second driving chip is provided with four capacitors and three resistors to form a second driving chip peripheral circuit, the periphery of the third driving chip is provided with two capacitors to form a third driving chip peripheral circuit, the periphery of the fourth driving chip is provided with four capacitors to form a fourth driving chip peripheral circuit, and the first bootstrap diode, four capacitors and one resistor to form the bootstrap circuit.
Further, pins of the first driving chip, the second driving chip, the third driving chip and the fourth driving chip are all connected to the copper sheet;
The copper surface connected with the GND port of the first chip driving chip is connected with the Kelvin of the source electrode of the first chip, the copper surface connected with the VO port of the first driving chip is connected with the Kelvin of the source electrode of the first chip, the copper surface connected with the GND port of the second driving chip is connected with the Kelvin of the source electrode of the fourth chip, the copper surface connected with the GND port of the third driving chip is connected with the Kelvin of the source electrode of the fourth chip, the copper surface connected with the VO port of the third driving chip is connected with the Kelvin of the copper surface connected with the Kelvin of the third chip, and the copper surface connected with the Kelvin of the VO port of the fourth driving chip is connected with the Kelvin of the third chip.
Further, a pin is welded on the copper surface connected with the VI port of the first chip driving chip, the copper surface connected with the VDD port of the first chip driving chip, the copper surface connected with the a port of the second bootstrap diode, the copper surface connected with the VI port of the second driving chip, the copper surface connected with the VDD port of the second driving chip, the copper surface connected with the GNDI port of the second driving chip, the copper surface connected with the a port of the first bootstrap diode, the copper surface connected with the VDD port of the third driving chip, the copper surface connected with the VI port of the fourth driving chip, and the copper surface connected with the VDD port of the fourth driving chip.
Further, insulating resin is sealed and filled in the module shell, and the ceramic substrate and the radiator are connected by heat conduction silicone grease.
Compared with the prior art, the invention has the following technical effects:
The invention designs a single-phase full-bridge intelligent power module based on a gallium nitride chip. Gallium nitride devices possess higher switching speeds than conventional silicon devices and are therefore more sensitive to parasitic parameters during switching than conventional silicon devices. The module designs a full-bridge layout based on the gallium nitride power chip and realizes the integration of the driving chip in the module. Through optimization of the power loop, the parasitic inductance value of each half-bridge current-converting loop is small, so that overvoltage and current oscillation phenomena in the on-off process of the chip are effectively reduced, and the overvoltage and overcurrent phenomena of the gallium nitride chip are avoided. Meanwhile, the parasitic inductance of the driving loop is optimized aiming at the bonding wire driving loop, and the false opening phenomenon of the gallium nitride chip is reduced. Adopts a ceramic substrate to realize heat dissipation, the thermal resistance of the module is reduced. And meanwhile, the silicon gel is sealed and filled, so that the insulating property of the module is improved.
The module is suitable for occasions with high power density requirements, plays an important role in application of new energy automobiles to the ground and energy conservation and emission reduction of household energy, can bring great economic benefit, and provides support for industrial ground of modularized packaging of gallium nitride power chips.
Drawings
Fig. 1 is a three-dimensional external structural view of the present invention.
Fig. 2 is a three-dimensional schematic of the drive and power board bonding of the present invention.
Fig. 3 is a three-dimensional schematic view of a ceramic substrate of the present invention.
Fig. 4 is a three-dimensional schematic of the drive PCB of the present invention.
Fig. 5 is a schematic diagram of a half-bridge loop circuit of the present invention.
Wherein the method comprises the steps of
1. A module housing; 2, a radiator; a second chip source electrode bonding wire; the semiconductor device comprises a first chip, a second chip grid bonding wire, a third chip source bonding wire, a third chip grid bonding wire, a fourth chip source bonding wire, a first chip grid bonding wire, a first chip source bonding wire, a first chip, a first copper layer, a second chip, a decoupling capacitor, a third chip, a third copper layer, a fourth copper layer, a decoupling capacitor, a fourth chip, a fourth driving chip, a third driving chip, a fourth driving chip, a third bootstrap diode, a fourth driving chip, a third bootstrap diode, a fourth driving chip, a fifth copper layer, a fourth copper layer, a fifth copper layer and a fifth copper layer.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
Referring to fig. 1 to 5, a single-phase full-bridge intelligent power module based on a gallium nitride power chip includes a power loop, a driving loop, a high-frequency decoupling capacitor, a lead terminal, a package housing and a heat sink. The power loop is a full bridge circuit formed by two gallium nitride chips and two silicon chips. The full-bridge circuit is connected with the decoupling capacitor and the driving circuit and is led out by adopting a terminal. The exterior and the radiator and the package shell are connected to form the whole module circuit.
Specifically, the bottom plate of the power loop adopts a ceramic substrate so as to obtain better heat dissipation capacity and mechanical stress characteristics.
The internal topology of the power loop adopts a full-bridge circuit based on a gallium nitride power chip.
The chip adopts a bonding process to realize the connection among the grid electrode, the source electrode and the copper foil. Each half-bridge requires parallel decoupling capacitors to provide a commutation loop for high frequency currents.
The driving chip is suitable for gallium nitride power chips, and the driving chip is distributed near the power chips and is used for reducing parasitic inductance of a grid driving loop. And bonding connection is adopted between the chip electrode and the driving bonding pad. And the periphery of the driving chip is provided with a corresponding decoupling capacitor and a driving resistor which are used as peripheral circuits.
Ceramic substrate for power loop the bottom surface is smeared with heat-conducting silicone grease, the other side of the heat conducting resin is connected with a fin radiator. And insulating silicone grease is filled in the module.
The top surface of the ceramic substrate 122 is sintered with the first copper layer 12, the second copper layer 15, the third copper layer 28, the fourth copper layer 31 and the fifth copper layer 124, and the bottom surface is sintered with the whole copper, so that the connection of the first chip 11 and the first copper layer 12, the fourth chip 39 and the fourth copper layer 31, the third chip 26 and the third copper layer 28, and the second chip 18 and the second copper layer 15 in the designated area is realized by welding.
Bonding wire 27 connects the upper surface of the source electrode of the third chip 26 with the second copper layer 15, bonding wire 19 connects the upper surface of the source electrode of the second chip 18 with the fifth copper layer 124, bonding wire 13 connects the source electrode of the first chip 11 with the third copper layer 28, bonding wire 123 connects the drain electrode of the first chip 11 with the first copper layer 12, bonding wire 14 connects the source electrode of the fourth chip 39 with the first copper layer 12, and bonding wire 125 connects the drain electrode of the fourth chip 39 with the fourth copper layer 31. The number of the bonding wires is increased to reduce parasitic inductance and increase the current capacity.
Four decoupling capacitors 32 are welded between the third copper layer 28 and the fourth copper layer 31, and four decoupling capacitors 22 are welded between the third copper layer 28 and the fifth copper layer 124.
Two pins are provided on the second copper layer 15, the third copper layer 28, the fourth copper layer 31 and the fifth copper layer 124, and the first copper layer 12 is connected with the pins
The copper surface connected with the port of the first chip driving chip 117VI, the copper surface connected with the port of the first chip driving chip 117VDD, the copper surface connected with the port of the second bootstrap diode 99A, the copper surface connected with the port of the second driving chip 84VI, the copper surface connected with the port of the second driving chip 84VDD, the copper surface connected with the port of the second driving chip 84GNDI, the copper surface connected with the port of the first bootstrap diode 65A, the copper surface connected with the port of the third driving chip 61VDD, the copper surface connected with the port of the third driving chip 61VI, the copper surface connected with the port of the fourth driving chip 47VI and the copper surface connected with the port of the fourth driving chip 47VDD are welded with one lead pin
The bonding wire realizes that the copper surface connected with the GND pin of the first driving chip 117 is connected with the Kelvin source electrode of the first chip 11, and the bonding wire realizes that the VO pin of the first driving chip 117 is connected with the copper surface and the grid electrode of the first chip 11. The bonding wire realizes that the GND pin of the second driving chip 84 is connected with the copper surface and the Kelvin source electrode of the fourth chip 39, and the bonding wire realizes that the VO pin of the second driving chip 84 is connected with the copper surface and the grid electrode of the fourth chip 39. The bonding wire realizes that the copper surface connected with the GND pin of the fourth driving chip 47 is connected with the Kerr Wen Yuanji of the second chip 18, and the bonding wire realizes that the copper surface connected with the VO pin of the fourth driving chip 47 is connected with the grid electrode of the second chip 18. The bonding wire realizes that the GND pin of the third driving chip 61 is connected with the copper surface and the Kerr Wen Yuanji of the third chip 26, and the bonding wire realizes that the VO pin of the third driving chip 61 is connected with the copper surface and the gate of the third chip 26.
Two pins are provided on each of the second copper layer 15, the third copper layer 28, the fourth copper layer 31 and the fifth copper layer 124, and the first copper layer 12 is connected to the pins.
The inside of the module is sealed and filled with insulating resin, and the ceramic substrate and the radiator are connected by heat conduction silicone grease.
Connection relationship between driver chip and power chip layout:
The first driving chip 117 is used for driving the first chip 11, the second driving chip 84 is used for driving the fourth chip 39, the third driving chip 61 is used for driving the third chip 26, and the fourth driving chip 47 is used for driving the second chip 18;
The capacitor 120, the capacitor 121, the resistor 114, the resistor 115 and the resistor 116 form a peripheral circuit of the first driving chip 117, the second bootstrap diode 99, the capacitor 97, the capacitor 98, the capacitor 106, the capacitor 107 and the resistor 105 form a bootstrap circuit, the capacitor 82, the capacitor 83, the resistor 93, the resistor 95, the resistor 96, the capacitor 91 and the capacitor 92 form a peripheral circuit of the second driving chip 84, the capacitor 56 and the capacitor 57 form a peripheral circuit of the third driving chip 61, the capacitor 43, the capacitor 44, the capacitor 50 and the capacitor 51 form a peripheral circuit of the fourth driving chip 47, and the first bootstrap diode 65, the capacitor 63, the capacitor 64, the capacitor 73, the capacitor 75 and the resistor 66 form a bootstrap circuit.
The housing structure used in the package of the present invention is not fixed and is not limited to the illustrated form.

Claims (6)

1.一种基于氮化镓功率芯片的单相全桥智能功率模块，其特征在于，包括驱动板、功率板、模块外壳（1）和散热器（2）；驱动板和功率板均设置在模块外壳（1）内，且驱动板设置在功率板上，功率板和驱动板通过键合线连接；散热器（2）设置在模块外壳（1）底部；1. A single-phase full-bridge intelligent power module based on gallium nitride power chip, characterized in that it includes a driver board, a power board, a module housing (1) and a heat sink (2); the driver board and the power board are both disposed inside the module housing (1), and the driver board is disposed on the power board, and the power board and the driver board are connected by bonding wires; the heat sink (2) is disposed at the bottom of the module housing (1); 功率板包括两个氮化镓芯片和两个硅芯片，两个氮化镓芯片和两个硅芯片组成全桥电路；The power board includes two gallium nitride (GaN) chips and two silicon chips, which together form a full-bridge circuit. 驱动板包括四个用于驱动功率板上四个芯片的驱动芯片，且四个驱动芯片位于功率板上芯片的侧面，且驱动芯片外围放置有解耦电容以及驱动电阻；The driver board includes four driver chips for driving four chips on the power board. The four driver chips are located on the side of the chips on the power board, and decoupling capacitors and driving resistors are placed around the driver chips. 功率板的底板为陶瓷基板（122），陶瓷基板（122）顶面烧结有第一铜层（12）、第二铜层（15）、第三铜层（28）、第四铜层（31）和第五铜层（124），陶瓷基板（122）底面烧结整块铜，第一铜层（12）上设置第一芯片（11），第二铜层（15）上设置第二芯片（18），第三铜层（28）上设置第三芯片（26），第四铜层（31）上设置第四芯片（39），第五铜层（124）；The base plate of the power board is a ceramic substrate (122). The top surface of the ceramic substrate (122) is sintered with a first copper layer (12), a second copper layer (15), a third copper layer (28), a fourth copper layer (31) and a fifth copper layer (124). The bottom surface of the ceramic substrate (122) is sintered with a whole piece of copper. The first chip (11) is disposed on the first copper layer (12), the second chip (18) is disposed on the second copper layer (15), the third chip (26) is disposed on the third copper layer (28), the fourth chip (39) is disposed on the fourth copper layer (31), and the fifth copper layer (124). 四个驱动芯片为第一驱动芯片（117）、第二驱动芯片（84）、第三驱动芯片（61）和第四驱动芯片（47）；第一驱动芯片（117）用于驱动第一芯片（11），第二驱动芯片（84）用于驱动第四芯片（39），第三驱动芯片（61）用于驱动第三芯片（26），第四驱动芯片（47）用于驱动第二芯片（18）；The four driving chips are the first driving chip (117), the second driving chip (84), the third driving chip (61), and the fourth driving chip (47); the first driving chip (117) is used to drive the first chip (11), the second driving chip (84) is used to drive the fourth chip (39), the third driving chip (61) is used to drive the third chip (26), and the fourth driving chip (47) is used to drive the second chip (18). 第一驱动芯片（117）外围设置两个电容和三个电阻组成第一驱动芯片（117）外围电路；第二自举二极管（99）、四个电容和一个电阻组成自举电路；第二驱动芯片（84）外围设置四个电容、三个电阻组成第二驱动芯片（84）外围电路；第三驱动芯片（61）外围设置两个电容组成第三驱动芯片（61）外围电路；第四驱动芯片（47）外围设置四个电容组成第四驱动芯片（47）外围电路；第一自举二极管（65）、四个电容和一个电阻（66）组成自举电路；The first driver chip (117) is surrounded by two capacitors and three resistors to form the peripheral circuit of the first driver chip (117); the second bootstrap diode (99), four capacitors and one resistor form the bootstrap circuit; the second driver chip (84) is surrounded by four capacitors and three resistors to form the peripheral circuit of the second driver chip (84); the third driver chip (61) is surrounded by two capacitors to form the peripheral circuit of the third driver chip (61); the fourth driver chip (47) is surrounded by four capacitors to form the peripheral circuit of the fourth driver chip (47); the first bootstrap diode (65), four capacitors and one resistor (66) form the bootstrap circuit; 第三芯片（26）源极上表面和第二铜层（15）连接；第二芯片（18）源极上表面和第五铜层（124）连接；第一芯片（11）源极和第三铜层（28）连接；第一芯片（11）漏极和第一铜层（12）连接；第四芯片（39）源极和第一铜层（12）连接；第四芯片（39）漏极和第四铜层（31）连接；The upper surface of the source of the third chip (26) is connected to the second copper layer (15); the upper surface of the source of the second chip (18) is connected to the fifth copper layer (124); the source of the first chip (11) is connected to the third copper layer (28); the drain of the first chip (11) is connected to the first copper layer (12); the source of the fourth chip (39) is connected to the first copper layer (12); the drain of the fourth chip (39) is connected to the fourth copper layer (31); 第一驱动芯片（117）、第二驱动芯片（84）、第三驱动芯片（61）和第四驱动芯片（47）的管脚均连接在铜片上；第一驱动芯片（117）GND端口连接的铜面和第一芯片（11）源极开尔文连接，第一驱动芯片（117）VO+、VO-端口连接的铜面和第一芯片（11）栅极连接；第二驱动芯片（84）GND端口连接的铜面和第四芯片（39）源极开尔文连接，第二驱动芯片（84）VO+、VO-端口连接的铜面和第四芯片（39）栅极连接；第三驱动芯片（61）GND端口连接的铜面和第三芯片（26）源极开尔文连接，第三驱动芯片（61）VO+、VO-端口连接的铜面和第三芯片（26）栅极连接；第四驱动芯片（47）GND端口连接的铜面和第二芯片（18）源极开尔文连接，第四驱动芯片（47）VO+、VO-端口连接的铜面和第二芯片（18）栅极连接。The pins of the first driver chip (117), the second driver chip (84), the third driver chip (61), and the fourth driver chip (47) are all connected to copper plates; the copper surface connected to the GND port of the first driver chip (117) is connected to the source Kelvin of the first chip (11), and the copper surface connected to the VO+ and VO- ports of the first driver chip (117) is connected to the gate of the first chip (11); the copper surface connected to the GND port of the second driver chip (84) is connected to the source Kelvin of the fourth chip (39), and the pins of the second driver chip (84) are all connected to copper plates; the copper surface connected to the GND port of the second driver chip (84) is connected to the source Kelvin of the fourth chip (39), and the pins of the fourth driver chip (61 ... connected to the source Kelvin of the fourth chip (39). The copper surface connected to the VO+ and VO- ports is connected to the gate of the fourth chip (39); the copper surface connected to the GND port of the third driver chip (61) is connected to the source Kelvin of the third chip (26); the copper surface connected to the VO+ and VO- ports of the third driver chip (61) is connected to the gate of the third chip (26); the copper surface connected to the GND port of the fourth driver chip (47) is connected to the source Kelvin of the second chip (18); the copper surface connected to the VO+ and VO- ports of the fourth driver chip (47) is connected to the gate of the second chip (18). 2.根据权利要求1所述的一种基于氮化镓功率芯片的单相全桥智能功率模块，其特征在于，第一芯片（11）和第四芯片（39）为氮化镓芯片，第二芯片（18）和第三芯片（26）为硅MOS芯片。2. A single-phase full-bridge intelligent power module based on gallium nitride power chips according to claim 1, characterized in that the first chip (11) and the fourth chip (39) are gallium nitride chips, and the second chip (18) and the third chip (26) are silicon MOS chips. 3.根据权利要求1所述的一种基于氮化镓功率芯片的单相全桥智能功率模块，其特征在于，第二铜层（15）、第三铜层（28）、第四铜层（31）和第五铜层（124）上均设置有两个引针，第一铜层（12）上设置有一个引针。3. A single-phase full-bridge intelligent power module based on a gallium nitride power chip according to claim 1, characterized in that two pins are provided on the second copper layer (15), the third copper layer (28), the fourth copper layer (31) and the fifth copper layer (124), and one pin is provided on the first copper layer (12). 4.根据权利要求1所述的一种基于氮化镓功率芯片的单相全桥智能功率模块，其特征在于，第三铜层（28）和第四铜层（31）之间焊接四个解耦电容（32）；第三铜层（28）和第五铜层（124）之间焊接有四个解耦电容（22）。4. A single-phase full-bridge intelligent power module based on a gallium nitride power chip according to claim 1, characterized in that four decoupling capacitors (32) are welded between the third copper layer (28) and the fourth copper layer (31); and four decoupling capacitors (22) are welded between the third copper layer (28) and the fifth copper layer (124). 5.根据权利要求1所述的一种基于氮化镓功率芯片的单相全桥智能功率模块，其特征在于，第一驱动芯片（117）VI端口连接的铜面、第一驱动芯片（117）VDD端口连接的铜面、第二自举二极管（99）A端口连接的铜面、第二驱动芯片（84）VI端口连接的铜面、第二驱动芯片（84）VDD端口连接的铜面、第二驱动芯片（84）GNDI端口连接的铜面、第一自举二极管（65）A端口连接的铜面、第三驱动芯片（61）VDD端口连接的铜面、第三驱动芯片（61）VI端口连接的铜面、第四驱动芯片（47）VI端口连接的铜面、第四驱动芯片（47）VDD端口连接的铜面上均焊接有一个引针。5. A single-phase full-bridge intelligent power module based on a gallium nitride power chip according to claim 1, characterized in that a pin is soldered on the copper surface connected to the VI port of the first driver chip (117), the copper surface connected to the VDD port of the first driver chip (117), the copper surface connected to the A port of the second bootstrap diode (99), the copper surface connected to the VI port of the second driver chip (84), the copper surface connected to the VDD port of the second driver chip (84), the copper surface connected to the GNDI port of the second driver chip (84), the copper surface connected to the A port of the first bootstrap diode (65), the copper surface connected to the VDD port of the third driver chip (61), the copper surface connected to the VI port of the third driver chip (61), the copper surface connected to the VI port of the fourth driver chip (47), and the copper surface connected to the VDD port of the fourth driver chip (47). 6.根据权利要求1所述的一种基于氮化镓功率芯片的单相全桥智能功率模块，其特征在于，模块外壳（1）内部封灌绝缘树脂，陶瓷基板（122）和散热器（2）之间采用导热硅脂连接。6. A single-phase full-bridge intelligent power module based on a gallium nitride power chip according to claim 1, characterized in that the module shell (1) is encapsulated with insulating resin, and the ceramic substrate (122) and the heat sink (2) are connected by thermally conductive silicone grease.
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