CN114695599A

CN114695599A - Method for forming grid line electrode of photovoltaic device and photovoltaic device

Info

Publication number: CN114695599A
Application number: CN202210315214.2A
Authority: CN
Inventors: 郁操; 董刚强
Original assignee: Suzhou Maxwell Technologies Co Ltd
Current assignee: Suzhou Maxwell Technologies Co Ltd
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2022-07-01
Also published as: WO2023185350A1

Abstract

The application provides a method for forming a grid line electrode of a photovoltaic device and the photovoltaic device, and relates to the field of solar cells. A method for forming a gate line electrode of a photovoltaic device, comprising: providing a semiconductor substrate comprising a first surface and a second surface which are oppositely arranged; forming a first graphical mask layer on the first surface; utilizing light to induce electroplating, enabling a light source to irradiate the second surface, and enabling the first surface to be in contact with electroplating solution so as to form a first grid line electrode on the first surface; forming a second patterned mask layer on the second surface; and forming a second grid line electrode on the second surface by electroplating or light-induced combination electroplating. The invention can improve the utilization rate of the cell to the light source, avoid the use of copper seed layer process steps, reduce sputtering damage and copper removal damage, is beneficial to improving the pulling-out force and electroplating uniformity of the grid line electrode, can realize electroplating of the extremely fine metal grid line electrode, and further can improve the short circuit current of the cell and improve the photoelectric conversion efficiency of the cell.

Description

Method for forming grid line electrode of photovoltaic device and photovoltaic device

Technical Field

The present application relates to the field of solar cell technology, and more particularly, to a method for forming a gate line electrode of a photovoltaic device and a photovoltaic device.

Background

Solar cells are based on semiconductor materials with electrodes to form electrically conducting devices. In recent years, with the development of the solar cell industry, it is a goal pursued by photovoltaic enterprises to improve the conversion efficiency of solar cells and reduce the cost. The electrode technology of solar cells is the key. The electrode structure of the existing solar cell is mainly prepared by adopting a screen printing technology. For example, the preparation of the positive electrode grid line by adopting screen printing is to stamp silver-containing conductive paste on a silicon wafer grid through a screen mesh, and then to form a good grid line electrode through procedures such as high-temperature rapid sintering and the like. However, with the increasing market competition, the disadvantages of low aspect ratio of electrode grid lines, high cost, large contact resistance, etc. in the screen printing mode are gradually revealed. Therefore, how to manufacture a lower-cost and good-performance electrode structure by using a simple process is one of the important points in the research of solar cells.

Chemical plating technology, electroplating technology and light-induced electroplating technology can be used as the technology for preparing the solar cell electrode. The electroless plating is to reduce metal ions in the plating solution into metal by means of a suitable reducing agent under the condition of no external current and deposit the metal ions on the surface of the solar cell. Electroplating is that metal cations in the electroplating solution are deposited on the surface of a cathode conductive solid under the condition of an external power supply; and the anode metal electrode is dissolved into metal cations dissolved in the plating solution so as to maintain the balance of the metal cations. The photoinduction electroplating is characterized in that due to the photovoltaic effect of the solar cell, when light irradiates the surface of the solar cell, a photo-generated carrier is generated in the PN junction, the photo-generated carrier is separated into electrons and holes under the action of an internal electric field, the holes move to the p-type doped layer, the electrons move to the n-type doped layer, and finally the electrons reach the upper surface and the lower surface of the solar panel. The electrons reach the surface of the n-type doped layer to participate in reduction reaction, metal ions in the solution are consumed, and the generated metal is deposited on the surface of the solid.

However, the existing electroless plating process, electroplating process or light-induced electroplating process have certain disadvantages. For example, the current stage of the chemical plating process has the disadvantages that although the equipment is simple and the operation does not need a power supply, the deposition rate cannot be accurately controlled; after the substrate surface is completely covered by the deposited metal, the deposition rate is greatly reduced, the thickness of the coating can not be controlled, and the large-scale industrial application is not achieved in the industry. Although the current stage of the electroplating process can control the deposition rate of metal cations by regulating and controlling the current density, the thickness of the metal layer is controlled by controlling the total charge quantity, the electroplating area and the electroplating time; however, in the electroplating process, a power supply needs to be added, the surface of the part to be plated needs to have good conductivity, and thus a copper seed layer needs to be pre-plated on the surface to be plated to meet the conductivity. The conventional method is to pre-plate the copper seed layer by using a magnetron sputtering method, which additionally increases more equipment investment, and sputtering damage is easily caused to the battery when the copper seed layer is pre-plated (about 5 nm-500 nm of metal copper). The metal electrode is electroplated by a mode of needing an external power supply, an electrode pinch point needs to be arranged, the hidden crack of a battery piece is easily caused, and after electroplating, the effective working area of the battery is reduced and the performance of the battery is influenced because the area of the pinch point is covered by copper. In addition, conventional electroplating also needs a copper seed layer removing process, and when the copper seed layer is removed, the used acid liquor can damage the transparent conductive film while corroding the copper seed layer. With the application of electroplating technology in solar cells (such as HJT cells), the desired openings of the gate lines can be made to be less than 20 μm, which creates great challenges for the introduction of an external current and the uniformity of the density of the introduced current.

Disclosure of Invention

In view of the above-mentioned problems, the present application aims to solve at least one of the technical problems in the related art to some extent. Therefore, the method for forming the grid line electrode of the photovoltaic device and the photovoltaic device can be used for preparing the grid line electrode by utilizing photo-induced electroplating or a combination mode of photo-induced electroplating and electroplating, copper seed layers are not needed on the two sides of a battery, electroplating pinch points cannot be introduced, electroplating of the ultra-thin grid lines (below 20 micrometers) can be achieved, the manufacturing cost is low, the related performance of the photovoltaic device can be improved, and the defects in the prior art can be overcome.

In order to achieve the purpose, the technical scheme adopted by the application is as follows:

according to one aspect of the present application, there is provided a method for forming a gate line electrode of a photovoltaic device, the method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, the first surface is an n-type doping layer of a battery, and the second surface is a p-type doping layer of the battery;

manufacturing a first mask layer on the first surface only; carrying out graphical processing on the first mask layer to form a first graphical mask layer;

utilizing light induction electroplating to enable a light source to irradiate the second surface, enabling the first surface to be in contact with electroplating solution, and forming a first grid line electrode on the first surface, wherein light generated by the light source does not pass through the electroplating solution (in the step, the first grid line electrode is formed through a light induction process);

forming a second patterned mask layer on the second surface;

when the first graphical mask layer is made of opaque materials, a power supply is applied to the first grid line electrode, and a second grid line electrode is formed on the second surface by using an electroplating process; removing the first patterned mask layer and the second patterned mask layer; or,

before a second patterned mask layer is formed on the second surface, removing the first patterned mask layer, and forming a second grid line electrode on the second surface by utilizing electroplating combined with a light induction process; removing the second graphical mask layer;

when the first graphical mask layer is made of a transparent material, a power supply is externally applied to the first grid line electrode, and a second grid line electrode is formed on the second surface by utilizing electroplating or electroplating combined with a light induction process; and removing the first patterned mask layer and the second patterned mask layer.

In the method for forming the gate line electrode provided by the application, the subsequent preparation method can be different according to different material types of the first patterned mask layer. For example, when the first patterned mask layer is made of a transparent material, after the second patterned mask layer is formed, the second gate line electrode may be formed by electroplating or electroplating combined with a photo-induced process.

When the first patterned mask layer is made of an opaque material, the second patterned mask layer is formed and then the second gate line electrode is formed directly through an electroplating process, or the second patterned mask layer is formed after the opaque first patterned mask layer is removed and then the second gate line electrode is formed through electroplating or an electroplating combined light induction process.

The present application also provides a method for forming a gate line electrode of a photovoltaic device, the method comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, the first surface is a cell n-type doping layer surface, and the second surface is a p-type doping layer surface;

manufacturing a first mask layer on the first surface; manufacturing a second mask layer on the second surface, wherein the second mask layer is of a transparent mask structure; only carrying out graphical processing on the first mask layer to form the first graphical mask layer;

utilizing light to induce electroplating, enabling a light source to irradiate the second surface, enabling the first surface to be in contact with electroplating solution, and forming a first grid line electrode on the first surface, wherein light generated by the light source does not pass through the electroplating solution;

carrying out patterning processing on the second mask layer positioned on the second surface to form a second patterned mask layer;

when the first graphical mask layer is made of opaque materials, a power supply is applied to the first grid line electrode, and a second grid line electrode is formed on the second surface by using an electroplating process; or,

removing the first patterned mask layer before patterning the second mask layer on the second surface to form the second patterned mask layer, and forming a second gate line electrode on the second surface by using electroplating combined with a light induction process; removing the second graphical mask layer;

In one possible implementation, a water film is formed on the electroless plating layer prior to the electroplating process step.

In one possible implementation manner, the first patterned mask layer includes an electroplating-resistant material, the electroplating-resistant material is deposited by using a photosensitive material, and a patterned opening is formed after exposure and development processing;

and/or the second patterned mask layer comprises an electroplating-resistant material, wherein the electroplating-resistant material is deposited by adopting a photosensitive material, and a patterned opening is formed after exposure and development treatment.

In one possible implementation, the process conditions of the light-induced plating include: the illumination intensity is 1000-500001 ux, and the temperature of the electroplating solution is 20-50 ℃.

In one possible implementation, the process conditions of the electroplating include: the current is 0.001-20A, and the temperature of the electroplating solution is 20-50 ℃.

In one possible implementation manner, the width of the first grid line electrode is 2-35 μm;

and/or the width of the second grid line electrode is 2-35 mu m.

In one possible implementation, the semiconductor substrate further includes:

a first intrinsic amorphous silicon layer formed on the first surface;

an n-type doped layer formed on the first intrinsic amorphous silicon layer;

a first transparent conducting layer formed on the n-type doped layer;

the first patterned mask layer is formed on the first transparent conductive layer;

a second intrinsic amorphous silicon layer formed on the second surface;

a p-type doping layer formed on the second intrinsic amorphous silicon layer;

a second transparent conductive layer formed on the p-type doped layer;

the second patterned mask layer is formed on the second transparent conductive layer;

the semiconductor substrate is a P-type silicon wafer or an N-type silicon wafer.

It should be noted that the above numerical ranges are inclusive of the endpoints.

According to another aspect of the present application, there is provided a method for forming a photovoltaic device, the method for forming a first gate line electrode and a second gate line electrode in the photovoltaic device being formed by the method as described above, further, the method for forming the photovoltaic device further includes: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged; the first surface is a cell n-type doped layer surface, and the second surface is a p-type doped layer surface;

forming a second intrinsic amorphous silicon layer on the second surface;

forming a first intrinsic amorphous silicon layer on the first surface;

forming an n-type doped layer on the first intrinsic amorphous silicon layer;

forming a p-type doped layer on the second intrinsic amorphous silicon layer;

forming a second transparent conducting layer on the p-type doping layer;

forming a first transparent conducting layer on the n-type doping layer;

according to the method for forming a gate line electrode of a photovoltaic device as described above, a first gate line electrode and a second gate line electrode are formed on the first transparent conductive layer and the second transparent conductive layer, respectively.

According to another aspect of the present application, there is provided a photovoltaic device made using the method for forming a photovoltaic device as described above.

Compared with the prior art, the technical scheme provided by the application can achieve the following beneficial effects:

when the light-induced electroplating is carried out, the light source is utilized to irradiate the second surface, so that the first surface is contacted with the electroplating solution, namely, the surface to be plated is separated from the light injection surface, the light-receiving surface is protected by the water film, so that the light-receiving surface is not contacted with the electroplating solution completely, and the light-receiving surface has no change in the whole electroplating process and is stable in the whole process of absorbing the irradiated light; the nonuniformity of photo-generated current density caused by the nonuniformity of the mask layer is avoided, and the electroplating uniformity of the whole electroplating surface is improved; in addition, an external power supply is not needed in the step, an electroplating pinch point and a copper seed layer in the traditional electroplating process are avoided, a copper removing process is not needed to be added after the electroplating is finished, the copper seed layer is not needed when the second surface is electroplated, the electroplating pinch point cannot be introduced, the electroplating of the ultrathin grid lines (below 20 micrometers) can be realized, the electroplating speed and the uniformity of the grid lines are improved, the manufacturing cost is lower, the related performance of the photovoltaic device can be improved, and the defects in the prior art can be overcome.

The method for forming the grid line electrode of the photovoltaic device further comprises the steps of forming a first graphical mask layer on the first surface of the semiconductor substrate, forming the first grid line electrode on the first surface by utilizing a light-induced electroplating technology, fully utilizing a light source, directly irradiating the second surface when the light source does not pass through an electroplating solution, and improving the efficiency of light-induced electroplating.

In addition, the method can also comprise the steps of forming a first mask layer on the first surface of the semiconductor substrate and forming a transparent second mask layer on the second surface of the semiconductor substrate, the process can simplify the mask layer preparation process and reduce the cost, and the second mask layer is formed on the second surface of the semiconductor substrate and plays a role in protecting the battery piece in the electroplating process.

Compared with the existing production process of screen printing silver grid electrode, the width of the grid electrode is 40-50 microns and cannot be reduced continuously, and the grid electrode prepared by the method in some preferred embodiments of the inventionThe width of the electrode grid can be controlled to be 2-35 microns, so that shielding of the electrode grid line to incident light can be reduced, and the short-circuit current density J of the battery is improved_SC。

The grid line electrode electroplated by the method is compact and uniform, the conductivity of the grid line electrode is obviously superior to that of a low-temperature silver grid line (the conductivity is 4-6 mu omega cm) subjected to screen printing, the internal resistance of the battery can be reduced, and the fill factor FF of the battery is improved. In addition, the method of the invention can adopt metal materials with relatively low price, can reduce the manufacturing cost and has lower production cost.

The method for forming a photovoltaic device and the photovoltaic device of the present application, including the aforementioned method for forming a gate line electrode of a photovoltaic device, have at least all the features and advantages of the aforementioned method for forming a gate line electrode of a photovoltaic device, and are not described herein again.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1(a) and 1(b) are schematic flow charts of methods for forming a gate line electrode of a photovoltaic device according to exemplary embodiments of the present disclosure;

fig. 2 is a schematic partial process view of a method for forming a gate line electrode of a photovoltaic device according to an exemplary embodiment of the present disclosure;

fig. 3 is a schematic view of light-induced plating in a method for forming a gate line electrode of a photovoltaic device according to an exemplary embodiment of the present disclosure;

fig. 4 is a schematic process view of a further portion of a method for forming a gate line electrode of a photovoltaic device according to an exemplary embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of a photovoltaic device provided in accordance with an exemplary embodiment of the present application;

fig. 6 is a schematic structural diagram of another photovoltaic device provided in an exemplary embodiment of the present application.

Reference numerals:

1-a semiconductor substrate;

10-a first surface;

20-a second surface;

101-a first intrinsic amorphous silicon layer; a 102-n type doped layer; 103-a first transparent conductive layer; 104-a first patterned mask layer; 105-a first gate line electrode;

201-a second intrinsic amorphous silicon layer; 202-p type doped layer; 203-a second transparent conductive layer; 204-a second patterned mask layer; 205-second gate line electrode.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The endpoints of the ranges and any values disclosed herein are not limited to the precise range or value, and such ranges or values should be understood to encompass values close to those ranges or values. For numerical ranges, one or more new numerical ranges may be obtained by combining the individual values, or by combining the individual values.

It should be understood that the terms "upper" and "lower" used in the description of the embodiments of the present application are used in a descriptive sense only and not for purposes of limitation. Further, it will be understood that when an element is referred to as being "on" or "under" another element, it can be directly on or under the other element or be indirectly on or under the other element via an intermediate element. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As the background art, the chemical plating technique, the electroplating technique, and the light-induced electroplating technique can be used as the technique for preparing the solar cell electrode; however, each process technology in the related art has certain defects and needs to be further improved. For example, in the related art, the solar cell electrode is prepared by utilizing a photo-induced electroplating process, and the main problem is that the light receiving surface and the electroplating surface are on the same surface, and incident light needs to penetrate through the electroplating solution and the mask material covered on the surface to be plated to be absorbed by the cell, so as to generate a photo-generated carrier to provide electrons required by electroplating for the surface to be plated. This results in a reduced utilization of the lamp source illumination by the battery. In addition, most of the conventional mask materials are opaque materials, and the applied light is difficult to penetrate through the materials, so that the design has a large defect. In addition, the uniformity of the incident light reaching the surface of the cell is affected by the uniformity of the thickness of the mask, which affects the uniformity of the photo-generated carriers and the uniformity of the plating, and this presents a great challenge to the product discreteness and product yield control in mass production.

In view of this, in order to overcome the defects in the prior art, the technical solutions of the embodiments of the present invention provide a method for forming a gate line electrode of a photovoltaic device, a method for forming a photovoltaic device, and a photovoltaic device formed according to the methods.

Referring to fig. 1(a), fig. 1(b), and fig. 2 to fig. 6, an embodiment of the present invention provides a method for forming a gate line electrode of a photovoltaic device, the method comprising:

a semiconductor substrate 1 is provided, the semiconductor substrate 1 includes a first surface 10 and a second surface 20 which are oppositely disposed, wherein the first surface 10 is a cell n-type doped layer, and the second surface 20 is a p-type doped layer.

Forming a first patterned mask layer 104 only on the first surface 10; specifically, a first mask layer is formed only on the first surface 10, and the first mask layer is patterned to form a first patterned mask layer 104.

The second surface 20 is irradiated with a light source by light-induced electroplating, and the first surface 10 is brought into contact with the electroplating solution to form the first gate line electrode 105 on the first surface 10, without passing through the electroplating solution.

Because the first patterned mask layer 104 is formed only on the first surface 10, in the light-induced electroplating process, light generated by the light source does not pass through electroplating solution, and can directly illuminate the second surface 20, so that the utilization rate of the battery to light is improved, and the light-induced electroplating rate is greatly increased.

A second patterned masking layer 204 is formed on second surface 20.

The subsequent fabrication may vary depending on the type of material used in the first patterned mask layer 104. In some cases, when the first patterned mask layer 104 is an opaque material, a power source is applied to the first gate line electrode, and a second gate line electrode is formed on the second surface 20 by an electroplating process; removing the first patterned mask layer 104 and the second patterned mask layer 204; or,

before forming the second patterned mask layer 204 on the second surface 20, removing the first patterned mask layer 104, and forming a second gate line electrode on the second surface 20 by using electroplating or electroplating combined with a light induction process; the second patterned mask layer 204 is removed.

In other cases, when the first patterned mask layer 104 is made of a transparent material, a power source is applied to the first gate line electrode, and a second gate line electrode is formed on the second surface 20 by electroplating or a process combining electroplating and light induction; the first patterned mask layer 104 and the second patterned mask layer 204 are removed.

The method provided by the embodiment of the invention can improve the utilization rate of the cell to a light source, avoid the use of a copper seed layer process step, reduce sputtering damage and copper removal damage, contribute to improving the pull-off force and electroplating uniformity of the grid line electrode, realize electroplating of the extremely fine metal grid line electrode, further improve the short-circuit current of the cell and improve the photoelectric conversion efficiency of the cell.

Further, a water film is formed on the electroless plating layer before the step of the plating process. Specifically, before the electroplating process step, a water film protective film is further formed on the non-electroplating surface through a water film mechanism, so that the non-electroplating surface is protected in the electroplating and light induction process processes, the non-electroplating surface is completely not contacted with the electroplating solution, and in the whole electroplating process, the light receiving surface has no change, and the whole process of light absorption is stable.

In the embodiment of the application, the equipment for forming the photovoltaic device comprises the water film mechanism and the material supplementing mechanism, before the cell enters the electroplating bath, the water film mechanism forms an even water layer protective film on the non-plated surface, the concentration of electroplating solution near the upper surface of the cell can be diluted, the cell is protected, the main component of the water film is pure water (more than 0.1M omega), the damage to the non-plated surface is effectively reduced, and the yield is improved as shown in the following table. Still set up the feed supplement mechanism when setting up the water film mechanism, its main effect is the change that leads to the cell liquor concentration because of the water film mechanism, if not set up the feed supplement mechanism, it can influence the concentration near the battery piece of plating solution, influences the technology, leads to electroplating quality to descend.

	Corrosion resistance time (min)	Yield (%)
			Conventional electroplating	0.2	45
Water film electroplating	5	98

It is understood that in the embodiment of the present application, the photovoltaic device may be a crystalline silicon solar cell, and the semiconductor substrate may be a silicon substrate material based on a silicon material.

The method for forming the grid line electrode of the photovoltaic device is suitable for being applied to the field of solar cells, and can be applied to preparation of various double-sided cells, such as heterojunction cells (such as HJT cells), double-sided PERC cells, HBC cells and the like. The method of the present invention will be described in detail below mainly using HJT cells as an example, but it will be understood by those skilled in the art that the method of the present invention is not limited to the application to HJT cells, but is applicable to various bifacial cells.

The semiconductor substrate 1 may be a silicon substrate, such as a polysilicon substrate, a monocrystalline silicon substrate, or a quasi-monocrystalline silicon substrate, and the embodiment of the present invention is not limited to a specific type of the semiconductor substrate. And the semiconductor substrate can be doped P-type or doped N-type, that is, the semiconductor substrate can be a P-type or N-type semiconductor substrate. The photovoltaic device provided by the embodiment of the invention can be a P-type double-sided solar cell or an N-type double-sided solar cell.

The semiconductor substrate 1 is a solar cell substrate which can be used for light-induced electroplating and is a solar cell substrate with a PN junction; that is, the semiconductor substrate 1 is a solar cell substrate obtained after pretreatment. For example, the semiconductor substrate includes an N-type or P-type doped silicon substrate, an intrinsic amorphous silicon layer, a phosphorus-doped N-type silicon layer, a boron-doped P-type silicon layer, a Transparent Conductive Oxide (TCO) layer, and the like. The semiconductor substrate may also be referred to as a blue diaphragm or a cell.

The semiconductor substrate 1 comprises a first surface 10 and a second surface 20 which are oppositely arranged, wherein the first surface 10 is a cell n-type doping layer, and the second surface 20 is a cell p-type doping layer. When the semiconductor substrate 1 is n-type crystalline silicon or p-type crystalline silicon, in the process step of forming the gate line, n-type doped silicon is contacted with electroplating solution to carry out a light induction process.

In the embodiment of the present application, the method for forming a gate line electrode of a photovoltaic device includes forming a first patterned mask layer 104 on a first surface 10 of a semiconductor substrate 1, and then performing a first electroplating, that is, forming a first gate line electrode 105 on the first surface 10 by using a light-induced electroplating technique; forming a second patterned mask layer 204 on the second surface 20 of the semiconductor substrate 1, performing a second electroplating, that is, forming a second gate line electrode 205 on the second surface 20 by using an electroplating technique, and then removing the first patterned mask layer 104 and the second patterned mask layer 204. The invention particularly relates to a method for manufacturing a light-induced electroplating device, which is characterized in that when light-induced electroplating is carried out, a light source is used for directly irradiating the second surface protected by a water film, so that the first surface is contacted with electroplating solution, namely, a surface to be plated is separated from a light injection surface, and the light receiving surface and the electroplating surface (the surface to be plated) are not on the same side.

Specifically, when the light-induced electroplating is carried out, the surface to be plated is the N-shaped surface of the cell, compared with the conventional light-induced electroplating, the light-induced electroplating method has the advantages that when the light-induced electroplating is carried out, the light injection of the second surface, namely the P-shaped surface is utilized, electrons generated in the cell flow to the surface of the N-layer doped layer, holes flow to the surface of the P-type doped layer, and the deposition of metal on the N-shaped surface of the cell and the balance of metal ions in the electroplating solution are ensured. In the time, the P-type surface is irradiated by a light source, the N-type surface is contacted with the electroplating solution, and the P-type surface of the cell has a transparent conductive oxide material, covers the water film and is not contacted with the electroplating solution. Furthermore, when the second electroplating is carried out, a power supply is additionally arranged on the grid line electrode electroplated with the N-shaped surface, so that the problems that current is fed into a pinch point and the like in the traditional electroplating are solved, the current which points from P to N is generated after the PN junction is conducted, the current is uniformly dispersed along the electroplated electrode on the first surface, and a copper seed layer is not required to be prepared to meet the conductive requirement, so that the operation is more convenient, the process steps of manufacturing the electrode on a piece to be electroplated can be reduced, and the electroplating speed of the surface to be electroplated and the uniformity of the grid line are favorably improved.

Therefore, the method provided by the embodiment of the invention belongs to a selective electroplating technology, and is characterized in that a patterning technology is utilized to carry out metal (such as nickel, cobalt, copper, silver, tin and the like) electroplating on the area needing electroplating, and electroplating material blocking resistant treatment is carried out on the non-electroplating area.

Based on the above, in the method for forming the gate line electrode of the embodiment of the invention, the surface to be plated, such as the n-type doped layer surface, is separated from the light injection surface, so that the shielding of the electroplating-resistant material and the electroplating solution on incident light on the surface to be plated can be avoided, the utilization rate of a light source can be improved, the nonuniformity of photo-generated current density caused by the nonuniformity of a mask layer can also be avoided, the electroplating quality is improved, a copper seed layer does not need to be prepared on both sides of the battery, the copper seed layer preparation and copper removal process by magnetron sputtering are reduced, a large amount of equipment cost is saved, the sputtering damage and the influence of acid liquid etching in the copper removal process are reduced, and the pull-out force of the electrode is more excellent than that of the traditional electroplating; in addition, in the electroplating process, the current feed-in electrode pinch point is not required to be additionally increased, the light receiving area of the battery is increased, and the improvement of the battery performance is facilitated; water film protection can be carried out on the surface which is not to be plated, so that the structure of the surface to be plated is prevented from being damaged by electroplating solution. Compared with the existing production process of screen printing silver grid electrode, the width of the grid electrode is 40-50 microns and cannot be reduced continuously, and the width of the grid electrode prepared by the method in some preferred embodiments of the invention can be controlled to be 2-35 microns, so that the shielding of the grid electrode on incident light can be reduced, and the short-circuit current density J of the battery can be improved_SC. This is due to the large passageExperimental study of the quantity shows that if the width of the grid line electrode exceeds 35 micrometers, the shielding of incident light can affect the conversion efficiency, and if the width of the grid line electrode is too small, such as less than 2 micrometers, the difficulty of the manufacturing process of the grid line can be increased, and certain influence can be exerted on the electrical performance and stability of the battery.

Furthermore, the grid line electrode electroplated by the method is compact and uniform, the conductivity of the grid line electrode is obviously superior to that of a screen-printed low-temperature silver grid line (the conductivity is 4-6 mu omega cm), the internal resistance of the battery can be reduced, and the fill factor FF (fill factor) of the battery is improved. In addition, the method of the invention can adopt metal materials with relatively low price, can reduce the manufacturing cost and has lower production cost.

In some embodiments, forming the first patterned mask layer 104 on the first surface 10 includes:

a first mask layer is manufactured on the first surface 10; the first mask layer is patterned to form a first patterned mask layer 104. Further, when forming the second patterned mask layer 204 on the second surface 20, a second mask layer needs to be formed on the second surface 20; the second mask layer is patterned to form a second patterned mask layer 204.

In other embodiments, a first mask layer 104 is formed on the first surface 10, and a transparent second mask layer is simultaneously formed on the second surface; only the first mask layer is patterned to form a first patterned mask layer 104. The process can simplify the mask layer preparation process and reduce the cost, and the transparent second mask layer is formed on the second surface of the semiconductor substrate, so that the battery piece is protected in the electroplating process.

Further, in the subsequent step of forming the second patterned mask layer 204 on the second surface 20, the second mask layer only needs to be patterned to form the second patterned mask layer 204.

In the two specific embodiments, the first is to fabricate a first mask layer only on the first surface before performing the photo-induced electroplating, and perform the patterning process on the first mask layer; the second method is that before the light induction electroplating, a first mask layer is manufactured on the first surface, a transparent second mask layer is manufactured on the second surface, and only the first mask layer is subjected to patterning processing. Therefore, when the first mode is adopted, the utilization rate of the light source is improved, and the light-induced electroplating operation is easier. And when the second mode is adopted, masks are respectively formed on the N-type surface and the P-type surface at one time, which is beneficial to reducing the cost and simplifying the process, and the transparent second mask layer is formed on the second surface of the semiconductor substrate, so that the battery piece is protected in the electroplating process, but the light source intensity needs to be enhanced for light-induced electroplating when the light-induced electroplating is carried out.

In some embodiments, the first patterned mask layer 104 includes an electroplating-resistant material deposited using a photosensitive material, and subjected to an exposure and development process to form patterned openings.

In some embodiments, the second patterned mask layer 204 is a transparent structure that includes an electroplating-resistant material, which is deposited using a photosensitive material, and is exposed and developed to form the patterned openings.

It should be understood that the first patterned mask layer may be a plating-resistant material having patterned openings. The second patterned mask layer may also be an electroplating-resistant material having patterned openings.

In the embodiment of the present invention, the implementation method of the photosensitive material includes, but is not limited to, spraying, spin coating, screen printing, physical or chemical vapor deposition, and the like. The patterned opening is related to the wavelength of the laser source, the optical power, and the photosensitive material, exposure time, and other processing parameters.

It should be noted that, the specific operation manner of forming the first patterned mask layer and forming the second patterned mask layer in the embodiments of the present invention is not limited, and a fabrication manner that is conventional in the art may be adopted. For example, in some embodiments, taking the fabrication of the first patterned mask layer as an example, the fabrication may include: coating a photoresist film, drying/curing the photoresist film, exposing and curing the photoresist film, developing a pattern, washing and drying. The photoresist coating film can be photosensitive ink/photoresist, and the coating mode can be ultrasonic spraying, compressed air spraying, rolling coating, screen printing and the like. The raw material for pattern development can comprise potassium carbonate aqueous solution, the mass concentration is 0.7-1.5%, the temperature can be 28-32 ℃, and the pressure can be about 30 psi. The water washing can be carried out by using tap water, the temperature of the water washing can be room temperature, and the pressure can be about 25 psi. The drying temperature can be 25-85 ℃.

Alternatively, in some embodiments, taking the fabrication of the first patterned mask layer as an example, it may include: adopting a photosensitive dry film to obtain a pressed film, exposing and curing a photoresist film, developing a pattern, washing and drying. The raw material for pattern development can comprise a potassium carbonate aqueous solution, the mass concentration of the potassium carbonate aqueous solution is 0.7-1.5%, the temperature can be 28-32 ℃, and the pressure can be about 30 psi. The water washing can be carried out by using tap water, the temperature of the water washing can be room temperature, and the pressure can be about 25 psi. The drying temperature can be 25-85 ℃.

In addition, the manner of forming the first mask and the second mask may also be simply changed, as shown in fig. 1(b), specifically as follows:

providing a semiconductor substrate 1, wherein the semiconductor substrate 1 comprises a first surface 10 and a second surface 20 which are oppositely arranged, the first surface 10 is a cell n-type doping layer, and the second surface 20 is a p-type doping layer;

a first mask layer is manufactured on the first surface 10; manufacturing a second mask layer on the second surface 20, wherein the second mask layer is of a transparent mask structure; patterning only the first mask layer to form a first patterned mask layer 104;

using light-induced electroplating to make the light source illuminate the second surface 20, and making the first surface 10 contact with the electroplating solution to form the first grid line electrode 105 on the first surface 10, wherein the light generated by the light source does not pass through the electroplating solution;

patterning the second mask layer on the second surface 20 to form a second patterned mask layer 204;

a second gate line electrode 205 is formed on the second surface, which may be the same as the process steps in the above embodiments.

As shown in fig. 2 or fig. 3, in some embodiments, the process conditions of the light-induced plating include: the illumination intensity is 100-100000 lux, and the temperature of the electroplating solution is 20-50 ℃. Furthermore, the illumination intensity can be 1000-30000 lux, and the temperature of the electroplating solution is 25-45 ℃. Furthermore, the illumination intensity can be 1000-10000 lux, and the temperature of the electroplating solution is 28-38 ℃.

The principle of light-induced electroplating is as follows: due to the photovoltaic effect of the solar cell, when light irradiates the surface of the solar cell, photogenerated carriers are generated in the cell, the photogenerated carriers are separated into electrons and holes under the action of the built-in electric field, the holes move to the second surface, namely the p-type doped silicon layer surface under the action of the built-in electric field, the electrons move to the first surface, namely the n-type doped silicon layer surface, and finally the upper surface and the lower surface of the solar cell are achieved. The electrons undergo a reduction reaction at the interface of the n-type doped silicon surface with the solution, whereby the metal ions in the solution are consumed and the resulting metal is deposited on the solid surface.

During actual operation, can pass through the gyro wheel transmission with the battery piece, the semiconductor substrate promptly, carry out illumination, the illumination face is switched on through electrode line and plating solution, forms closed-loop. The temperature of the electroplating solution for the light-induced electroplating can be normal temperature (RT), and the illumination intensity can be within the range of 1000-50000 lux.

In some embodiments, the process conditions of the electroplating comprise: the current is 0.001-20A, and the temperature of the electroplating solution is 20-50 ℃. Further, the current may be 0.001 to 15A, and the temperature of the plating solution may be 25 to 40 ℃. Further, the current may be 0.01 to 10A, and the temperature of the plating solution may be 28 to 38 ℃.

According to the embodiment of the present application, the light-induced plating is performed for the first time, the plating is performed for the second time, and when the plating is performed for the second time, the semiconductor substrate cell, which is the cell, is transported by the roller, the non-plated surface is in contact with the positive electrode (anode) of the power supply through the electrode, the negative electrode (cathode) of the power supply is in contact with the plating solution to form a closed loop, and the plating is performed by applying a current from the power supply. The temperature of the electroplating solution for the second electroplating can be normal temperature (RT), and the current can be in the range of 0.001-20A.

In some embodiments, the width of the first gate line electrode 105 is 2 to 35 μm. In some embodiments, the width of the first gate line electrode 105 may be 10 to 25 μm.

In some embodiments, the width of the second gate line electrode 205 is 2 to 35 μm. In some embodiments, the width of the second gate line electrode 205 may be 10 to 25 μm.

According to the embodiment of the invention, the width of the main grid line can be 10-35 μm, and the width of the secondary grid line can be 2-20 μm, or can be 2-35 μm.

In some embodiments, the material of the first gate line electrode 105 may include nickel, cobalt, copper, silver, tin, and the like; the material of the second gate line electrode 205 may include nickel, cobalt, copper, silver, tin, and the like.

In some embodiments, the first patterned mask layer 104 may have a thickness of 3 to 50 μm; the second patterned mask layer 204 may have a thickness of 3 to 50 μm.

In some embodiments, the height of the first gate line electrode 105 may be 2 to 50 μm; the height of the second gate line electrode 205 may be 2 to 50 μm.

Considering the thickness of the mask, generally below 20 μm, the developing resolution width is 1: 1 to the thickness of the mask, but the electroplating thickness is not greater than the thickness of the mask, therefore, the height-to-width ratio of the grid line electrode can be controlled at about 0.8: 1, thereby reducing the process difficulty.

It should be noted that the numerical ranges in the examples of the present invention include the endpoints.

In some embodiments, there is also provided a method for forming a photovoltaic device, the method comprising:

forming a second intrinsic amorphous silicon layer 201 on the second surface 20;

forming a first intrinsic amorphous silicon layer 101 on the first surface 10;

forming an n-type doped layer 102 on the first intrinsic amorphous silicon layer 101;

forming a p-type doped layer 202 on the second intrinsic amorphous silicon layer 201;

forming a second transparent conductive layer 203 on the p-type doped layer 202;

forming a first transparent conductive layer 103 on the n-type doped layer 102;

a first gate line electrode 105 and a second gate line electrode 205 are formed on the first transparent conductive layer 103 and the second transparent conductive layer 203, respectively.

As described above, the semiconductor substrate provided is a solar cell substrate having a structure that can be used for light-induced plating and electroplating, and is a solar cell substrate having a PN junction. The semiconductor substrate may include an N-type or P-type doped silicon substrate, an intrinsic amorphous silicon layer, an N-type doped silicon layer doped with phosphorus (P), a P-type doped silicon layer doped with boron (B), and a transparent conductive oxide layer (TCO).

In some embodiments, there is also provided a photovoltaic device made using the method for forming a photovoltaic device as described above. As shown in fig. 5 or 6, for example, the photovoltaic device includes:

the semiconductor device comprises a semiconductor substrate 1, wherein the semiconductor substrate 1 comprises a first surface 10 and a second surface 20 which are oppositely arranged;

a first intrinsic amorphous silicon layer 10l on the first surface 10;

an n-type doped layer 102 on the first intrinsic amorphous silicon layer 101;

a first transparent conductive layer 103 on the n-type doped layer 102;

a first gate line electrode 105 on the first transparent conductive layer 103;

a second intrinsic amorphous silicon layer 201 on the second surface 20;

a p-type doped layer 202 on the second intrinsic amorphous silicon layer 201;

a second transparent conductive layer 203 on the p-type doped layer 202;

and a second gate line electrode 205 on the second transparent conductive layer 203.

It is to be understood that the method of forming a gate line electrode of the present invention can be applied to various double-sided batteries, and thus the above-described method for forming a photovoltaic device and photovoltaic device are merely exemplary and not intended to limit the present invention.

As can be appreciated by those skilled in the art, the method for forming a photovoltaic device and the photovoltaic device are based on the same inventive concept, and the features and advantages described above with respect to the method for forming a gate line electrode of a photovoltaic device are equally applicable to the method for forming a photovoltaic device and the application of the photovoltaic device, and thus, the method for forming a photovoltaic device and the photovoltaic device have at least the same or similar features and advantages as the aforementioned method for forming a gate line electrode of a photovoltaic device, and will not be described herein again.

In summary, the method for forming a gate line electrode of a photovoltaic device according to the embodiments of the present invention has at least the following advantages compared to the prior art:

(1) the difference between the light-induced electroplating (first electroplating) in the method of the embodiment of the invention and the conventional light-induced electroplating is that the light-receiving surface and the electroplating surface are not on the same side, so that incident light can be prevented from penetrating through the mask layer and the electroplating solution to reach a battery, the utilization rate of a light source is improved, the nonuniformity of photo-generated current density caused by the nonuniformity of the mask layer is also avoided, and the electroplating quality is improved.

(2) The light-induced electroplating (first electroplating) in the method provided by the embodiment of the invention does not need to sputter a Cu seed layer on the surface to be plated before electroplating, and does not need a reverse etching process of the Cu seed layer after electroplating, so that the process steps are reduced, and the corrosion resistance requirement of TCO is greatly reduced. The problem that the conventional cheap non-In TCO such as AZO and GZO cannot tolerate the Cu seed layer back etching solution can be solved. The reduction of the process steps of the invention also protects the damage of the silicon film and the TCO film and improves the pFF of the cell.

(3) In the electroplating process (secondary electroplating) in the method provided by the embodiment of the invention, the electroplated metal grid lines (including the main grid and the auxiliary grid) are skillfully used as electrodes to lead in current, so that the electroplating speed of the surface to be plated and the uniformity of the grid lines can be improved. Since TCOs are inherently much less conductive than metals, a seed layer of Cu is typically sputtered over the TCO.

(4) In the electroplating process (secondary electroplating) of the method provided by the embodiment of the invention, the TCO on the surface to be plated has mask protection.

(5) By adopting the method of the embodiment of the invention, metal materials with relatively low price can be adopted, the manufacturing cost can be reduced, and the production cost is lower.

(6) The solar cell finally obtained by the method of the embodiment of the present invention has the following relevant performance compared to the solar cell obtained by the conventional screen printing and the conventional electroplating process as shown in table 1 below.

TABLE 1

Process scheme	Eta(％)	Voc(V)	Isc(A)	FF(％)	pFF(％)
						The invention	25.61	0.747	10.968	85.72	87.17
Conventional screen printing	25.33	0.747	10.940	85.03	87.39
						Conventional electroplating	25.31	0.745	10.955	85.02	86.98

As can be seen from table 1, the solar cell obtained by the method of the embodiment of the present invention has a conversion efficiency at least 0.28% higher than that of the solar cell obtained by using the conventional screen printing low temperature paste.

(7) The method does not need an external power supply, avoids using electroplating pinch points in the traditional electroplating, improves the electroplating speed of the surface to be plated and the uniformity of the grid lines, and can realize the electroplating of the extremely thin grid lines (below 20 micrometers). In addition, a water film is also arranged, the light receiving surface is protected by the water film, so that the light receiving surface is not contacted with the electroplating solution at all, and the light receiving surface does not change at all in the whole electroplating process and is stable to the whole absorption process of the irradiating light.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It is noted that a portion of this patent application contains material which is subject to copyright protection. The copyright owner reserves copyright rights except for copies of patent documents or patent document contents of records at the patent office.

Claims

1. A method for forming a gate line electrode of a photovoltaic device, the method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, the first surface is a cell n-type doping layer surface, and the second surface is a p-type doping layer surface;

manufacturing a first mask layer on the first surface; carrying out graphical processing on the first mask layer to form a first graphical mask layer;

forming a second patterned mask layer on the second surface;

2. A method for forming a gate line electrode of a photovoltaic device, the method comprising:

manufacturing a first mask layer on the first surface; manufacturing a second mask layer on the second surface, wherein the second mask layer is of a transparent mask structure; carrying out graphical processing on the first mask layer to form a first graphical mask layer;

carrying out patterning processing on the second mask layer positioned on the second surface to form a second patterned mask layer:

3. The method of claim 1 or 2, wherein a water film is formed on the electroless plating layer prior to the step of the electroplating process.

4. The method according to claim 1 or 2, wherein the first patterned mask layer comprises an electroplating-resistant material, the electroplating-resistant material is deposited by using a photosensitive material, and a patterned opening is formed after exposure and development processing;

5. The method of claim 1 or 2, wherein the process conditions of the light-induced electroplating comprise: the illumination intensity is 100 to 100000lux, and the temperature of the electroplating solution is 20 to 50 ℃.

6. The method of claim 1 or 2, wherein the electroplating process conditions comprise: the current is 0.001-20A, and the temperature of the electroplating solution is 20-50 ℃.

7. The method for forming a gate line electrode of a photovoltaic device according to claim 1 or 2, wherein the width of the first gate line electrode is 2 to 35 μm;

and/or the width of the second grid line electrode is 2-35 mu m.

8. The method of claim 1 or 2, wherein the semiconductor substrate further comprises:

a first intrinsic amorphous silicon layer formed on the first surface;

an n-type doped layer formed on the first intrinsic amorphous silicon layer;

a first transparent conducting layer formed on the n-type doped layer;

a second intrinsic amorphous silicon layer formed on the second surface;

a p-type doping layer formed on the second intrinsic amorphous silicon layer;

a second transparent conductive layer formed on the p-type doped layer;

9. A method for forming a photovoltaic device, wherein the method of forming a first gate line electrode and a second gate line electrode in a photovoltaic device is formed by the method of any of claims 1-8, further the method for forming a photovoltaic device further comprises:

forming a second intrinsic amorphous silicon layer on the second surface;

forming a first intrinsic amorphous silicon layer on the first surface;

forming an n-type doped layer on the first intrinsic amorphous silicon layer;

forming a p-type doped layer on the second intrinsic amorphous silicon layer;

forming a second transparent conducting layer on the p-type doping layer;

forming a first transparent conducting layer on the n-type doping layer;

and respectively forming a first grid line electrode and a second grid line electrode on the first transparent conducting layer and the second transparent conducting layer.

10. A photovoltaic device made by the method for forming a photovoltaic device of claim 9.