CN112635590B - Preparation method of high-efficiency monocrystalline silicon SE-PERC battery piece - Google Patents
Preparation method of high-efficiency monocrystalline silicon SE-PERC battery piece Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 title claims abstract description 11
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- 238000005520 cutting process Methods 0.000 claims abstract description 44
- 238000000151 deposition Methods 0.000 claims abstract description 33
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- 239000002994 raw material Substances 0.000 claims abstract description 12
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- 230000003647 oxidation Effects 0.000 claims description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece, which comprises the steps of selecting a raw material silicon chip, texturing, diffusing, laser doping, removing phosphorosilicate glass, depositing a passivation film, depositing a passivation antireflection film, performing laser grooving on the back surface, performing screen printing and sintering; the method comprises the following steps of preparing a raw material silicon wafer, wherein the raw material silicon wafer is prepared by a wire cutting method, cutting lines on the silicon wafer are set to be in an X direction, the conveying direction of the silicon wafer is controlled to be in a Y direction in the phosphorosilicate glass removing step, and an included angle is formed between the Y direction and the X direction. The preparation method provided by the invention can effectively improve the overall conversion efficiency of the battery piece.
Description
Technical Field
The invention relates to the technical field of production and manufacturing of monocrystalline silicon batteries, in particular to a preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece.
Background
The biggest difference between the PERC battery (Passivated emitter and reactor Cell) and the conventional battery is that the back surface of the battery is Passivated by a dielectric film, and local metal contact is adopted to reduce back surface recombination and improve open-circuit voltage. The back surface reflection is increased to improve the short circuit current, thereby improving the battery efficiency. PERC cells are currently and in the future mainstream production processes due to their relatively simple processes and low cost increases.
The PERC technology is highly compatible with the existing production line, and the production line is easy to upgrade, for example, in the SE-PERC technology, a selective emitter and local boron doping are further adopted, and screen printing and doping technologies are combined to realize local opening and form a boron doped layer, so that the efficiency is improved by 0.2% -0.3%.
However, in order to further improve the conversion efficiency of the battery piece, the conventional SE-PERC technology tends to shallow junction high sheet resistance, but the integrity of the PN junction is easily damaged during diffusion, the proportion of the EL blacking low-efficiency piece is improved, and the overall conversion efficiency is further influenced; in addition, in order to reduce the consumption of the silver paste, the risk of EL grid breakage is easily caused in the preparation process of the prior art along with the line width and the film thickness of the silver paste screen printing plate are lower and lower, and the conversion efficiency of the battery piece is further influenced.
In addition, the photovoltaic cells currently on the market, which are made based on P-type boron-doped silicon wafers, have long been plagued with the problem of initial Light Induced Degradation (LID). Research shows that the cost of the boron-doped silicon wafer is basically equal to that of the gallium-doped silicon wafer, and the gallium-doped silicon wafer can solve the problems of component failure and annual power attenuation of 2% in a high-temperature and high-humidity environment, so that the gallium-doped silicon wafer gradually becomes a mainstream product in recent years.
However, as is well known, the sheet resistance and the junction depth are one embodiment of the doping concentration, and the high sheet resistance indicates that the doping is less, and the junction depth is shallower, which may cause Rs to be higher, contact resistance to be increased, and the conversion efficiency of the cell to be affected; the low sheet resistance indicates that the doping is more, the junction depth is deeper, and the doping is too much, so that a dead layer is caused, and the passivation quality is seriously reduced. In the doping process of the gallium-doped silicon wafer, if the doping concentration of a base region silicon substrate is increased, the reduction of saturated dark current is facilitated, but the doping concentration is too high, so that the minority carrier diffusion length is shortened, when the minority carrier diffusion length is smaller than the base region thickness, a photon-generated carrier can not be effectively collected, so that a silicon substrate doping concentration which is compromised is required, the sheet resistance of the existing gallium-doped silicon wafer is not unified, and the resistivity standard of 0.5-1.5 omega cm in the existing shallow junction high sheet resistance diffusion process is only suitable for a boron-doped silicon wafer and is not suitable for the gallium-doped silicon wafer.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece, which can effectively improve the overall conversion efficiency of the battery piece.
In order to achieve the above purpose, the invention provides the following technical scheme:
a preparation method of a high-efficiency monocrystalline silicon SE-PERC cell comprises the steps of selecting a raw material silicon wafer, texturing, diffusing, laser doping, dephosphorized silicate glass, depositing a passivation film, depositing a passivation antireflection film, laser grooving on the back surface, screen printing and sintering;
the raw material silicon wafer is prepared by a wire cutting method, cutting lines on the silicon wafer are set to be in the X direction, the conveying direction of the silicon wafer is controlled to be in the Y direction in the phosphorosilicate glass removing step, and the Y direction and the X direction form an included angle.
In one embodiment, the Y direction is at an angle of 90 ° to the X direction.
Considering that the preparation of the cell is the assembly line work, when the conveying direction of the silicon wafer is perpendicular to the cutting lines on the silicon wafer, the production operation is convenient, and meanwhile, the friction of the roller on the cutting lines can be better reduced.
As a practical manner, the direction of the laser image on the silicon wafer is controlled to be the X direction in the laser doping step, the direction of the groove is controlled to be the X direction in the back laser grooving step, and the direction of the secondary grid line on the silicon wafer is controlled to be the X direction in the screen printing step.
As an implementation manner, the secondary gate line includes an aluminum gate line screen-printed on the back surface of the silicon wafer and a fine gate line screen-printed on the front surface of the silicon wafer.
According to the laser doping step, according to the metalized graph of the screen printing, a PSG layer on the surface of the silicon wafer after diffusion treatment is used as an impurity source, and laser is irradiated corresponding to the metalized graph to carry out selective doping treatment so as to realize local heavy doping; the laser grooving method is characterized in that the position of the metallization pattern is the position of a subsequent secondary grid line, laser grooving needs to be carried out on the position of the metallization pattern on the back of the silicon wafer before screen printing of the secondary grid line, the laser image direction is controlled to be parallel to the cutting line from the laser doping step, the laser grooving direction on the back is made to be parallel to the cutting line, and finally the direction of the screen printed secondary grid line on the silicon wafer is controlled to be parallel to the cutting line.
As a practical manner, the substrate silicon rod is gallium-doped substrate silicon, the raw material silicon wafer is a gallium-doped silicon wafer, the resistivity of the gallium-doped silicon wafer is 0.3-1.1 Ω · cm, and preferably the resistivity of the gallium-doped silicon wafer is 0.3-0.8 Ω · cm; preferably, the resistivity of the gallium-doped silicon wafer is 0.8-1.1 omega cm.
The invention adopts the gallium-doped silicon wafer as the raw material silicon wafer, can solve the problems of component failure and 2% power attenuation in the first year in a high-temperature and high-humidity environment, and in addition, the resistivity of the gallium-doped silicon wafer is limited to be 0.3-1.1 omega cm, so that the doping concentration change of the gallium-doped silicon wafer in crystalline silicon can be reduced, further the longitudinal resistivity change of the silicon wafer is reduced, and an optimal battery efficiency interval is obtained.
As one practical way, the slicing way is diamond wire cutting.
Compared with mortar cutting, diamond wire cutting has a relatively smoother surface and has a remarkable advantage of low cost, so that diamond wire cutting instead of mortar cutting has become a development trend of photovoltaic slice technology. However, the microscopic morphology revealed parallel grooves, i.e., cutting lines, due to the friction of the diamond wires, and some concave-convex pits were present along the cutting lines.
As a practical way, the depositing of the passivation film is to deposit a passivation film on the back surface of the silicon wafer, or to deposit passivation films on both surfaces of the silicon wafer; preferably, the passivation film is an aluminum oxide passivation film.
As one practical way, the depositing of the passivation antireflection film includes depositing silicon nitride/silicon oxynitride on the back surface and depositing silicon nitride/silicon oxynitride on the front surface.
As an implementable manner, the manner of depositing the passivation film and the manner of depositing the passivation antireflection film are an atomic layer manner or a PECVD manner, and the PECVD manner includes deposition by using a plate-type PECVD apparatus or deposition by using a tube-type PECVD apparatus.
As an implementable manner, after the step of removing phosphorosilicate glass is completed on the silicon wafer, a passivation film and a passivation antireflection film are integrally deposited on the back surface of the silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) manner, wherein the passivation film is aluminum oxide, and the passivation antireflection film is silicon nitride/silicon oxynitride.
As a practical mode, a thermal oxidation step is added after the phosphorosilicate glass is removed and before a passivation film is deposited.
After the phosphorosilicate glass is removed and before the passivation film is deposited, a thermal oxidation process is added, namely silicon is exposed in a high-temperature oxidation environment (oxygen and water), so that the oxidation steps of the silicon wafer can be increased, and the surface defect state is reduced.
As a practical way, the sintering is followed by the steps of detection of electrical properties, detection of EL and sorting of colors.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece, which makes directional requirements on the cutting line direction of a silicon chip in the manufacturing process of the battery piece process, and ensures that the conveying direction of the silicon chip and the cutting line direction form an included angle in the step of removing phosphorosilicate glass, wherein the method adopted in the step of removing phosphorosilicate glass is known to a person skilled in the art is wet etching, the wet etching is to adopt a roller to convey the silicon chip and realize the purpose of removing back junction and peripheral junction.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 shows the direction of silicon wafer transfer and the direction of cut lines during the pre-wet etching step;
FIG. 2 shows the direction of silicon wafer transfer and the direction of cut lines during the wet etching step after improvement;
fig. 3 is a graph comparing the efficiency and yield trends of the cells before and after improvement.
Description of reference numerals:
1. cutting lines; 2. a roller of a wet etching device.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings, wherein the direction indicated by the arrow in the drawings is the conveying direction of the silicon wafer in wet etching.
The invention provides a preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece, which mainly comprises the following steps:
selecting a raw material silicon wafer: preparing a silicon rod doped with gallium, cutting the silicon rod doped with gallium by adopting a linear cutting method to obtain a raw material silicon wafer, and setting the direction of cutting lines on the silicon wafer to be the X direction;
texturing: forming a textured suede on the surface of the silicon wafer;
diffusion: carrying out phosphorus diffusion treatment on the textured silicon wafer to form a PN junction;
laser doping: carrying out laser heavy doping on the diffused silicon wafer, and controlling a graph line formed by the laser doping to be parallel to a cutting line, namely in the X direction;
removing phosphorus silicon glass: removing phosphorosilicate glass on the back and the periphery of the silicon wafer, and during the phosphorosilicate glass removal, adopting wet etching equipment, and controlling the direction of transporting the silicon wafer by the wet etching equipment to be Y-direction, wherein the Y-direction and the X-direction form an included angle, and are preferably perpendicular to each other;
thermal oxidation: exposing the silicon wafer with the PSG removed in a high-temperature oxidation environment, and plating an oxidation film;
depositing a passivation film: plating a back surface and/or two surfaces of the silicon wafer with an aluminum oxide passive film;
depositing an antireflection passivation film: depositing a silicon nitride film/silicon oxynitride passivation film on the back; depositing a silicon nitride film/silicon oxynitride passivation film on the front surface;
back laser grooving: performing laser grooving on the back silicon nitride/silicon oxynitride film and the aluminum oxide film, wherein the direction of a formed groove line is parallel to the direction of a cutting line and is in the X direction;
screen printing: printing the back electrode and the positive electrode to ensure that the directions of the back side auxiliary grid line and the front side auxiliary grid line formed by printing are X directions;
and (3) sintering: sintering the silicon wafer subjected to screen printing to obtain the SE-PERC solar cell with high conversion efficiency;
quality inspection: the finished product was tested for electrical properties, EL and color and classified.
Example 1
The invention provides a preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece, which comprises the following steps:
(1) S1, preparing a gallium-doped silicon rod, controlling the concentration of a gallium element, ensuring that the resistivity is in the range of 0.3-1.1 omega-cm, and cutting the gallium-doped substrate silicon rod by adopting a diamond wire to form a raw material silicon wafer with cutting lines in the X direction;
(2) S2, pre-cleaning and texturing the silicon wafer by using a groove type texturing machine, and ensuring that cutting lines of the silicon wafer in the texturing basket are vertically arranged;
(3) S3, arranging the cutting line direction of the silicon wafer after texturing to be vertical to the opening direction of a quartz boat in diffusion equipment, and forming a PN junction on the surface of the silicon wafer after the diffusion step;
(4) S4, according to a metalized graph of screen printing, taking a PSG layer formed on the surface of the silicon wafer after diffusion as an impurity source, and performing selective doping treatment by using laser to realize local heavy doping;
(5) S5, removing back knots and peripheral knots of the silicon wafer by using Jiejiawei creat or Rena chain type wet etching equipment, and removing phosphorosilicate glass, wherein the cutting line direction of the silicon wafer is ensured to be parallel to the installation direction of a roller in the wet etching equipment, or the cutting line direction (X direction) on the silicon wafer is ensured to be vertical to the conveying direction (Y direction) of the silicon wafer on the wet etching equipment;
(6) And S6, exposing the silicon wafer without the phosphorosilicate glass in a high-temperature oxidation environment containing oxygen and water to reduce the defects on the surface of the silicon wafer, wherein the silicon wafer is generally operated in a production line of set equipment in the preparation process, so that the cutting line direction of the silicon wafer is ensured to be vertically arranged perpendicular to the hot-oxygen quartz boat in the step in order to reduce the manual sorting work.
(7) And S7, depositing an aluminum oxide passivation film on the back surface of the silicon wafer in an atomic layer mode, and also depositing the aluminum oxide passivation film on the two surfaces of the silicon wafer, wherein the step also ensures that the cutting line direction of the silicon wafer is perpendicular to the aluminum boat for reducing manpower.
(8) S8, depositing a back silicon nitride/silicon oxynitride passivation film in a plate-type or tubular PECVD mode; and depositing the front silicon nitride/silicon oxynitride passivation film in a plate-type or tube-type PECVD (plasma enhanced chemical vapor deposition) mode, wherein when tube-type equipment is used for deposition, the cutting line direction of the silicon wafer needs to be vertically placed in a graphite boat, and when plate-type equipment is used for deposition, the cutting line direction of the silicon wafer needs to be parallel to the running direction of a graphite frame.
(9) And S9, performing laser grooving on the back of the silicon wafer to realize good ohmic contact between the subsequent back aluminum grid line and the silicon, wherein the cutting line direction of the silicon wafer is ensured to be parallel to the laser grooving direction.
(10) And S10, performing screen printing and sintering on the front side and the back side of the silicon wafer, printing an aluminum grid line on a groove opening part on the back side of the silicon wafer, printing a silver grid line on the front side of the silicon wafer, and ensuring that the cutting line pattern direction of the silicon wafer is parallel to the aluminum grid line and the silver grid line.
(11) And S11, sorting, grading and classifying the electrical property, EL and color of the finished product.
Example 2
Different from the embodiment 1, the passivation film and the passivation antireflection film on the back surface of the embodiment are integrally deposited in a plate-type or tubular PECVD mode, and the passivation antireflection film on the front surface is only deposited in a tubular or flat-plate PECVD mode.
The test effect proves that:
setting a comparative example, wherein the comparative example is different from the example 1 in that, referring to fig. 1, in the wet etching stage of the phosphorosilicate glass removing, the conveying direction of a silicon wafer in the wet etching equipment is parallel to the cutting line 1 direction of the silicon wafer, namely the setting direction of a roller 2 of the wet etching equipment is vertical to the cutting line 1 direction; and the direction of a laser image on the silicon wafer, the direction of back laser grooving and the direction of a secondary grid line formed by screen printing are all perpendicular to the direction of the cutting line 1 in the laser doping step.
Referring to fig. 2, in the wet etching stage of the phosphorosilicate glass removing in embodiment 1, the conveying direction of the silicon wafer in the wet etching apparatus is perpendicular to the direction of the cutting line 1 of the silicon wafer, i.e., the setting direction of the roller 2 of the wet etching apparatus is parallel to the direction of the cutting line 1, and the direction of the laser image on the silicon wafer, the direction of the back laser grooving, and the direction of the sub-gate line formed by screen printing are all parallel to the direction of the cutting line 1 during the laser doping step.
Referring to fig. 3, it can be seen from fig. 3 that the conversion efficiency of the comparative example is less than 22.25% in 7 weeks, the conversion efficiency of example 1 is greater than 22.25% in 7 weeks, and the conversion efficiency reaches 22.35% in the third week, which indicates that the conversion efficiency can be improved by about 0.06% on average by using the method described in the present application; the defective proportion of the comparative example is more than 0.37 percent, the defective proportion of the product obtained by the method is less than 0.30 percent, the one-time yield (A rate) is averagely improved by about 0.13 percent, and the conversion efficiency and the yield of the battery piece can be effectively improved by the method provided by the invention on the premise of not increasing the production cost.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A preparation method of a high-efficiency monocrystalline silicon SE-PERC battery piece is characterized by comprising the steps of selecting a raw material silicon chip, texturing, diffusing, laser doping, dephosphorized silicate glass, depositing a passivation film, depositing a passivation antireflection film, performing laser grooving on the back, performing screen printing and sintering;
the raw material silicon wafer is prepared by a wire cutting method, cutting lines on the silicon wafer are set to be in the X direction, the conveying direction of the silicon wafer is controlled to be in the Y direction in the phosphorosilicate glass removing step, and the Y direction and the X direction form an included angle to reduce EL linear blackening of the cell; and the silicon chip is cut by adopting a diamond wire; and controlling the direction of a laser image on the silicon wafer to be X direction during the laser doping step, controlling the direction of slotting to be X direction during the back laser slotting, and controlling the direction of a secondary grid line on the silicon wafer to be X direction during the screen printing.
2. The method of claim 1, wherein the Y direction is 90 ° from the X direction.
3. The preparation method of claim 1, wherein the secondary grid lines comprise aluminum grid lines screen-printed on the back surface of the silicon wafer and fine grid lines screen-printed on the front surface of the silicon wafer.
4. The production method according to claim 1, wherein the raw silicon wafer is a gallium-doped silicon wafer having a resistivity of 0.3 to 1.1 Ω -cm.
5. The production method according to claim 4, wherein the resistivity of the gallium-doped silicon wafer is 0.3 to 0.8 Ω -cm; or the resistivity of the gallium-doped silicon wafer is 0.8-1.1 omega cm.
6. The preparation method according to claim 1, wherein the depositing of the passivation film is depositing a passivation film on the back side of the silicon wafer, or depositing a passivation film ALD on both sides of the silicon wafer; the passivation film is an aluminum oxide passivation film.
7. The method of claim 6, wherein the depositing a passivation antireflection film comprises depositing silicon nitride/silicon oxynitride on the back side and depositing silicon nitride/silicon oxynitride on the front side.
8. The preparation method of claim 1, wherein the manner of depositing the passivation film and the passivation antireflection film is an atomic layer manner or a PECVD manner, and the PECVD manner includes deposition by a plate-type PECVD apparatus or deposition by a tube-type PECVD apparatus.
9. The preparation method of claim 1, wherein after the step of removing phosphorosilicate glass from the silicon wafer is completed, a passivation film and a passivation antireflection film are integrally deposited on the back surface of the silicon wafer in a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the passivation film is aluminum oxide, and the passivation antireflection film is silicon nitride/silicon oxynitride.
10. The method according to any one of claims 6 to 9, wherein a thermal oxidation step is further added after the phosphorosilicate glass is removed and before a passivation film is deposited.
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