CN114678851B - Power management chip protection circuit - Google Patents
Power management chip protection circuit Download PDFInfo
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- CN114678851B CN114678851B CN202210339792.XA CN202210339792A CN114678851B CN 114678851 B CN114678851 B CN 114678851B CN 202210339792 A CN202210339792 A CN 202210339792A CN 114678851 B CN114678851 B CN 114678851B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/041—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using a short-circuiting device
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Abstract
The invention discloses a power management chip protection circuit, which comprises a power supply end, a grounding end, a detection circuit, an input end of an inverting unit connected with the detection circuit, a clamping unit connected with the inverting unit and a power management chip, wherein the clamping unit comprises two switching tubes connected with the inverting unit and a semiconductor device positioned between the two switching tubes, the semiconductor device comprises a first doping region, a first well region positioned on the first doping region, a second well region formed on the first well region, two second doping regions extending from the second well region to the first well region and a third doping region formed on the second well region, the detection circuit is used for detecting surge voltage of the power supply end and outputting the surge voltage to the grid electrodes of the two switching tubes through the inverting unit to start the clamping unit, and the clamping unit releases the surge voltage from the grounding end. The leakage current of the switching tube is limited in a small range, the working safety of the circuit is improved, and the power consumption is reduced.
Description
Technical Field
The invention relates to the technical field of power management chips, in particular to a power management chip protection circuit.
Background
The power management chip is a chip which plays roles of conversion, distribution, detection and other electric energy management responsibilities in an electronic equipment system, and is mainly responsible for identifying the power supply amplitude of a core circuit, generating corresponding short moment waves and pushing a rear-stage circuit to output power. The power management chip is indispensable to the electronic system, and the quality of the performance of the power management chip has a direct influence on the performance of the whole electronic system. Therefore, there is a very strict requirement for the security of the power management chip.
With the rapid development of the chip industry, the CMOS processing technology used by the power core management chip has been gradually miniaturized to the nanometer level, and the gate oxide layer of the transistor is gradually thinner, and the influence of the voltage fluctuation on the gate oxide layer is more serious.
The main sources of voltage fluctuation are surge impact caused by electrostatic discharge, switching and plug plugging, the harmful currents have great threat to a power management chip, and the problem is solved by connecting a protection circuit beside a core circuit in parallel in the prior art. The protection circuit at least comprises a voltage clamping unit, and with the progress of the technology, a protection circuit formed by connecting an RC inverter circuit and the clamping unit in parallel is also available, but the protection circuit still has the defects that the trigger voltage of the clamping unit is still higher, and the leakage current of the whole system is larger, so that the power consumption is increased, and the protection circuit is particularly not beneficial to the use at a power supply end.
Disclosure of Invention
In view of the above, the present invention provides a protection circuit for a power management chip, which utilizes a novel clamping unit to enable a whole system to have a lower trigger voltage and a lower clamping voltage, and simultaneously reduces a leakage current of the whole system, so as to solve the above-mentioned technical problems.
The invention provides a power management chip protection circuit, which comprises a power end, a grounding end, a detection circuit, an input end of an inverting unit connected with the detection circuit, a clamping unit connected with the inverting unit and a power management chip, wherein the detection circuit, the clamping unit and the power management chip are connected between the power end and the grounding end;
the clamping unit comprises two switching tubes connected with the phase inversion unit and a semiconductor device positioned between the two switching tubes, wherein the semiconductor device comprises a first doping region of a first conductivity type, a first well region of a second conductivity type positioned on the first doping region, a second well region of the first conductivity type formed on the first well region, two second doping regions of the first conductivity type extending from the second well region to the first well region, and a third doping region formed on the second well region, the second doping region is connected with the drain electrode of the switching tube, the first doping region is connected with the source electrode of the switching tube, and the grid electrodes of the two switching tubes are connected with the output end of the phase inversion unit;
the detection circuit is used for detecting surge voltage of the power supply end and outputting the surge voltage to the grids of the two switching tubes through the phase inversion unit so as to start the clamping unit, and the clamping unit releases the surge voltage from the grounding end.
As a further improvement of the above technical solution, the detection circuit includes at least one resistor and at least one capacitor, a PMOS transistor connected in parallel to the power supply terminal and the ground terminal, and an NMOS transistor, wherein a source of the PMOS transistor is connected to the power supply terminal, a gate of the PMOS transistor is connected to a gate of the NMOS transistor and located at a connection between the resistor and the capacitor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, and a source of the NMOS transistor is connected to the ground terminal.
As a further improvement of the above technical solution, the inverting unit is a diode, an anode of the diode is connected to the output terminal of the detection circuit, and a cathode of the diode is connected to the clamping unit.
As a further improvement of the above technical solution, the first conductivity type is an N-type, the second conductivity type is a P-type, and the switching tube is an NMOS tube.
As a further improvement of the above technical solution, the inverting unit is an inverter, an input end of the inverter is connected to an output end of the detecting circuit, an output end of the inverter is connected to the clamping unit, and the switching tube is a PMOS tube.
As a further improvement of the above technical solution, the power management chip includes a voltage conversion module and a pulse adjustment module, the voltage conversion module is configured to convert a direct current voltage into an alternating current voltage, or convert an alternating current voltage into a direct current voltage, and the pulse adjustment module is configured to drive an external switch.
As a further improvement of the above technical solution, the doping concentrations of the first well region and the second well region are the same, and the doping concentrations of the first doping region and the third doping region are the same.
Compared with the prior art, the power management chip protection circuit provided by the invention has the following beneficial effects:
by connecting the detection circuit to the power supply end and the grounding end, the surge voltage generated by the circuit can be detected in real time, and when the surge voltage event occurs, the positive voltage is output, so that the inverting unit can quickly respond and invert the output negative voltage. The clamping unit is internally provided with a semiconductor device, and particularly, a P + or N + structure and a grid structure are added on two sides of a PNPN thyristor simultaneously to form a PNPN thyristor structure integrated with an NMOS or a PMOS, so that the clamping unit has extremely low trigger voltage and extremely low clamping voltage, and releases the subsequent large surge voltage to a grounding end, thereby effectively protecting a rear-stage power management chip. The inverting unit is connected between the detection circuit and the clamping unit, so that the leakage current of the switching tube can be limited in a small range, and the working safety of the circuit is improved. When the inverting unit is a diode or an inverter, a smaller trigger voltage is generated, so that the circuit has smaller leakage current, and the power management chip is effectively protected.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic circuit diagram of a protection circuit of a power management chip according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a protection circuit of a power management chip according to another embodiment of the present invention;
FIG. 3 is a comparison graph of transmission line pulse test curves for the inventive structure and the conventional thyristor structure.
The main element symbols are as follows:
10-a power supply terminal; 20-ground terminal; 21-a detection circuit; 22-an inverting unit; 23-a clamping unit; 24-a power management chip; 25-a switching tube; 26-a semiconductor device; 27-a first doped region; 28-a first well region; 29-a second well region; 30-a second doped region; 31-a third doped region; 32-resistance; 33-capacitance; 34-PMOS tube; 35-NMOS tube.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, the present invention provides a power management chip protection circuit, which includes a power terminal 10, a ground terminal 20, a detection circuit 21, an input terminal of an inverting unit 22 connected to the detection circuit 21, a clamping unit 23 connected to the inverting unit 22, and a power management chip 24, wherein the detection circuit 21, the clamping unit 23, and the power management chip 24 are connected between the power terminal 10 and the ground terminal 20;
the clamping unit 23 includes two switching tubes 25 connected to the inverting unit 22, and a semiconductor device 26 located between the two switching tubes 25, where the semiconductor device 26 includes a first doped region 27 of a first conductivity type, a first well region 28 of a second conductivity type located on the first doped region 27, a second well region 29 of the first conductivity type formed on the first well region 28, two second doped regions 30 of the first conductivity type extending from the second well region 29 to the first well region 28, and a third doped region 31 formed on the second well region 29, the second doped region 30 is connected to a drain of the switching tube 25, the first doped region 27 is connected to a source of the switching tube 25, and gates of the two switching tubes 25 are connected to an output terminal of the inverting unit 22;
the detecting circuit 21 is configured to detect a surge voltage of the power source terminal 10, and output the surge voltage to the gates of the two switching tubes 25 through the inverting unit 22 to turn on the clamping unit 23, and the clamping unit 23 releases the surge voltage from the ground terminal 20.
In this embodiment, clamping is a measure for limiting a potential at a certain point to a predetermined potential, and is an overvoltage protection technique, and circuits for generating this measure are called clamping circuits (circuits). The clamp circuit is used for keeping the top or the bottom of the periodically-changed waveform at a certain direct current level, so that the working stability of the whole circuit is improved. A Power Management chip (Power Management Integrated Circuits) is a chip that plays roles in converting, distributing, detecting and other electric energy Management in an electronic equipment system, and is mainly responsible for identifying the Power supply amplitude of a CPU, generating a corresponding short moment wave, and pushing a rear-stage circuit to output Power. Inversion is the phase reversal of an input signal by 180 degrees, and is applied to analog circuits such as audio amplification, clock oscillators, and the like. The detection circuit is widely used to determine the type of any external device connected to the mobile device, and generally, the detection circuit includes a transistor as a switch for controlling the detection process. The semiconductor is generally classified into an intrinsic semiconductor, an N-type semiconductor and a P-type semiconductor, which are undoped, doped with N-type impurities (P, As) and doped with P-type impurities (B, Ga), respectively, and the P-type region is diffused as a P-well region on the N-type substrate and the N-type region is diffused as an N-well region on the P-type substrate.
It should be noted that the two switching tubes have the same conductivity type, the doping concentrations of the first well region and the second well region are the same, and the doping concentrations of the first doping region and the third doping region are the same, so that the voltages at the two ends of the semiconductor device tend to be stable, and the working performance of the semiconductor device is improved. The detection circuit can detect surge voltage between the power supply end and the grounding end, namely, instantly generate larger voltage, the detection circuit can firstly detect the voltage and output a positive voltage, the positive voltage outputs a negative voltage after passing through the phase reversal unit, the grid electrodes and the source and drain electrodes of the two switch tubes are conducted, the two switch tubes serve as the trigger unit to simultaneously act on the left side and the right side of the clamping unit, the clamping unit is enabled to be started in advance, lower trigger voltage and clamping voltage are provided, follow-up large surge voltage is released to the grounding end, and therefore a rear-stage power supply management chip is effectively protected.
It should be understood that, because the inverting unit exists between the detection circuit and the clamping unit, the gate leakage current passing through the two switching tubes is limited within a small range, so that the power management chip protection circuit has a small leakage current, the working efficiency of the whole system can be improved, and the power consumption is also reduced.
Optionally, the detection circuit 21 includes at least one resistor 32 and at least one capacitor 33, a PMOS transistor 34 connected in parallel to the power supply terminal 10 and the ground terminal 20, and an NMOS transistor 35, where a source of the PMOS transistor 34 is connected to the power supply terminal 10, a gate of the PMOS transistor 34 is connected to a gate of the NMOS transistor 35 and located at a connection between the resistor 32 and the capacitor 33, a drain of the PMOS transistor 34 is connected to a drain of the NMOS transistor 35, and a source of the NMOS transistor 35 is connected to the ground terminal 20.
In this embodiment, the PMOS transistor is represented by PMOS1, the NMOS transistor is represented by NMOS1, the PMOS transistor and the NMOS transistor are coupled in parallel between the power terminal and the ground terminal, and the capacitor is used to block the dc signal from passing through and allow the ac signal to pass through, or reduce the passing ability of the low frequency signal and increase the passing ability of the high frequency signal. The parallel connection of the resistor and the capacitor has the effect that a direct current signal or a low-frequency signal is difficult to pass through, and an alternating current signal or a high-frequency signal is easy to pass through. In addition, in the capacitor voltage reduction circuit, in order to provide a discharge path for the capacitor, a discharge resistor is connected in parallel at two ends of the capacitor, so that electric energy stored at two ends of the capacitor is discharged after the capacitor stops working. In the coupling circuit, capacitors are connected in parallel at two ends of the coupling resistor to form a phase advance circuit, so that the integral effect formed by the capacitors can be avoided, the phase is advanced, and the working efficiency of the detection circuit for detecting surge voltage is effectively improved.
It should be noted that the first conductivity type is N-type, the second conductivity type is P-type, the switching tube is NMOS, the PMOS is similar to the NMOS in operation principle, the PMOS is an N-type silicon substrate, wherein the majority carriers are holes, the minority carriers are electrons, the doping type of the source and drain regions is P-type, the PMOS operates under the condition that a negative voltage is applied to the gate relative to the source, that is, negative charge electrons are applied to the gate of the PMOS, and a movable positive charge hole and a depletion layer with fixed positive charge are induced on the substrate, and the number of positive charges induced in the substrate is equal to the number of negative charges on the gate of the PMOS. The PMOS transistor, i.e. PMOS1, and the NMOS transistor, i.e. NMOS1, are coupled in parallel between a VCC power supply terminal and a ground terminal, the source of PMOS1 is connected to the VCC power supply terminal, the gate of PMOS1 is connected to the gate of NMOS1 and then to the anode of diode D1, and the source of NMOS1 is connected to the ground terminal.
It should be understood that the PMOS transistor and the NMOS transistor of the detection circuit can be used as switches in the circuit to control the on/off of the detection circuit, and when the detection circuit detects that the voltage input by the power terminal and the ground terminal exceeds a preset threshold, the detection circuit sends out a protection circuit formed by connecting the inverting unit and the clamping unit in parallel, thereby enhancing the working reliability of the detection circuit to a certain extent.
Optionally, the inverting unit 22 is a diode, an anode of the diode is connected to the output terminal of the detection circuit, and a cathode of the diode is connected to the clamping unit 23.
In this embodiment, the clamping unit is connected in parallel between the VCC power supply terminal and the ground terminal, the main body of the clamping unit has a four-layer structure, which is sequentially P +, NW, PW, and N + from top to bottom, wherein N + regions are respectively disposed on two sides of the NW for connecting to the drain of the NMOS2, the P + of the clamping unit is connected to the VCC power supply terminal, and the lowest layer N + of the clamping unit is connected to the ground terminal. When the inverter cell is a diode, the cathode of the diode D1 is connected to the gates of two NMOS transistors, i.e., NMOS2, the drain of NMOS2 is connected to N + in the clamp cell in NW, and the source of NMOS2 is connected to N + in the clamp cell connected to ground.
It should be noted that, the power management chip is connected in parallel between the VCC power supply terminal and the ground terminal, when the VCC power supply terminal encounters a surge voltage event, the detection circuit composed of the resistor, the capacitor, the PMOS1 and the NMOS1 will detect the voltage first, and then output a positive voltage through the diode D1 to reach the gates of the two NMOS2, the source and drain of the NMOS2 will be turned on, and the NMOS2, as a trigger unit, will act on the left and right sides of the clamp circuit at the same time, so that the clamp circuit is turned on in advance, and therefore has a lower trigger voltage and clamp voltage, and releases a large subsequent voltage to the ground terminal, thereby effectively protecting the power management chip at the subsequent stage. Due to the existence of the diode D1, the reverse direction passing of the gate leakage current from the NMOS2 is not allowed, so that the circuit has smaller leakage current, the efficiency of the whole system can be improved, and the power consumption can be reduced.
More specifically, the structure of the PNPN thyristor is characterized in that N + regions are added on two sides of an NW and a PW of the PNPN thyristor at the same time, two side faces of the PNPN thyristor form two NMOS devices at the same time, the NMOS can be conducted only by applying a small voltage (the minimum voltage can reach 1-3V) on a grid electrode, current can be enabled to flow into a PW of the thyristor through N + and PW junctions along with the conduction of the NMOS, namely a PNP transistor formed by P +/NW/PW is conducted, then an NPN transistor formed by the NW/PW/N + is also conducted, and when the two transistors are conducted at the same time, the thyristor P +/NW/PW/N + enters a positive feedback state, so that the PNPN thyristor has a large negative resistance characteristic, and the clamp voltage drops sharply. Therefore, the trigger voltage of the structure of the invention is determined by the gate threshold voltage of the NMOS, and the two sides of the structure are provided with symmetrical NMOS structures, and the current enters the PW from the two sides simultaneously, so that the current pouring into the PW is obviously increased, and the thyristor P +/NW/PW/N + is easier to be completely switched on in advance. Therefore, the system has extremely low trigger voltage and extremely low clamping voltage, and the protection capability is more comprehensive.
Referring to fig. 2, optionally, the inverting unit 22 is an inverter, an input end of the inverter is connected to an output end of the detecting circuit 21, an output end of the inverter is connected to the clamping unit 23, and the switching tube 25 is a PMOS tube.
In this embodiment, the output terminal of the inverter is connected to the gates of two PMOS2, the drain of PMOS2 is connected to the top P + of the clamp unit, and the source of PMOS2 is connected to the P + of the PW of the clamp unit. The clamping unit is connected between a VCC power supply end and a grounding end in parallel, the main body of the clamping unit is of a four-layer structure and sequentially comprises a P +, an NW, a PW and an N + from top to bottom, wherein P + regions are respectively arranged on two sides of the PW and used for being connected with a source electrode of the PMOS2, the P + of the clamping unit is connected with the VCC power supply end, and the N + of the lowest layer in the clamping unit is connected with the grounding end.
It should be noted that, the power management chip is connected in parallel between the VCC power supply terminal and the ground terminal, when the VCC power supply terminal encounters a surge voltage event, the detection circuit composed of the resistor, the capacitor, the PMOS1 and the NMOS1 will detect the voltage first, and then output a positive voltage, the positive voltage passes through the inverter and then is output as a negative voltage, and reaches the gates of the two PMOS2, the PMOS2 source drain will be turned on, the PMOS2 is used as a trigger unit and acts on the left and right sides of the clamp circuit at the same time, so that the clamp circuit is turned on in advance, and therefore, the lower trigger voltage and clamp voltage are provided, and the subsequent large surge voltage is released to the ground terminal, thereby effectively protecting the power management chip at the later stage. Due to the existence of the inverter, the grid leakage from the PMOS2 can be limited in a smaller range, so that the circuit has smaller leakage current, the efficiency of the whole system can be improved, and the power consumption can be reduced.
More specifically, the structure of the PNPN thyristor is characterized in that P + regions are added on two sides of an NW and a PW of the PNPN thyristor at the same time, two sides of the PNPN thyristor form two PMOS devices at the same time, the PMOS is conducted only by applying a small voltage (the minimum voltage can reach-1V to-3V) on a grid electrode, current can be enabled to pass through the NW and P + junctions along with the conduction of the PMOS, so that the PW of the PNP thyristor is filled with current, namely the PNP transistor formed by the P +/NW/P +/PW is conducted, then the NPN transistor formed by the NW/PW/N + is also conducted, and when the two transistors are conducted at the same time, the PNP thyristor P +/NW/PW/N + enters a positive feedback state, has a large negative resistance characteristic, and the clamping voltage drops sharply. Therefore, the trigger voltage of the structure is determined by the grid threshold voltage of the PMOS, symmetrical PMOS structures are arranged on two sides of the structure, and current enters the PW from two sides simultaneously, so that the current flowing into the PW is remarkably increased, and the thyristor P +/NW/PW/N + is easier to be completely switched on in advance. Therefore, the system has extremely low trigger voltage and extremely low clamping voltage, and the protection capability is more comprehensive.
Fig. 3 is a graph comparing a TLP (transmission line pulse test) curve of the structure of the present invention and a TLP curve of a conventional thyristor structure, where the TLP curve of the structure of the present invention shows that the trigger voltage is only 1.5V, and the trigger voltage of the conventional thyristor structure is still 7.8V; when the TLP pulse current is 20A, the clamp voltage of the structure of the invention is 4V, while the clamp voltage of the conventional thyristor structure is 5.1V. The trigger voltage and the clamping voltage of the structure of the invention are both greatly lower than those of the traditional thyristor structure.
Optionally, the power management chip 24 includes a voltage conversion module for converting a dc voltage into an ac voltage or converting an ac voltage into a dc voltage, and a pulse adjustment module for driving an external switch.
In this embodiment, the voltage conversion module may convert ac voltage into dc voltage, or convert dc voltage into ac voltage to adapt to different circuits, and may convert an analog voltage signal into a digital signal to implement effective management of a power supply, and the pulse adjustment module may periodically input or output a voltage signal to drive the external switch to be turned on or off, thereby improving the operational reliability of the power management chip.
The invention provides a power management chip protection circuit, which can detect surge voltage generated by the circuit in real time by connecting a detection circuit to a power supply end and a grounding end, outputs positive voltage when encountering a surge voltage event to enable an inverting unit to quickly respond to inverting and output negative voltage, and is provided with a semiconductor device in a clamping unit, so that the clamping unit is started in advance to generate lower clamping voltage and releases subsequent large surge voltage to the grounding end, thereby effectively protecting a rear-stage power management chip. The reverse phase unit is connected between the detection circuit and the clamping unit, so that the leakage current of the switch tube can be limited in a small range, and the working safety of the circuit is improved. When the inverting unit is a diode or an inverter, a smaller trigger voltage is generated, so that the circuit has smaller leakage current, and the power management chip is effectively protected.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (10)
1. A power management chip protection circuit is characterized by comprising a power supply end, a grounding end, a detection circuit, an input end of an inverting unit connected with the detection circuit, a clamping unit connected with the inverting unit and a power management chip, wherein the detection circuit, the clamping unit and the power management chip are connected between the power supply end and the grounding end;
the clamping unit comprises two switching tubes connected with the phase inversion unit and a semiconductor device positioned between the two switching tubes, wherein the semiconductor device comprises a first doping region of a first conductivity type, a first well region of a second conductivity type positioned on the first doping region, a second well region of the first conductivity type formed on the first well region, two second doping regions of the first conductivity type extending from the second well region to the first well region, and a third doping region formed on the second well region, the second doping region is connected with the drain electrode of the switching tube, the first doping region is connected with the source electrode of the switching tube, and the grid electrodes of the two switching tubes are connected with the output end of the phase inversion unit;
the detection circuit is used for detecting surge voltage of the power supply end and outputting the surge voltage to the grids of the two switching tubes through the phase inversion unit so as to start the clamping unit, and the clamping unit releases the surge voltage from the grounding end.
2. The power management chip protection circuit of claim 1, wherein the detection circuit comprises at least one resistor and at least one capacitor, a PMOS transistor connected in parallel to the power terminal and the ground terminal, and an NMOS transistor, wherein a source of the PMOS transistor is connected to the power terminal, a gate of the PMOS transistor is connected to a gate of the NMOS transistor and located at a connection between the resistor and the capacitor, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, and a source of the NMOS transistor is connected to the ground terminal.
3. The power management chip protection circuit of claim 1, wherein the inverting unit is a diode, an anode of the diode is connected to the output terminal of the detection circuit, and a cathode of the diode is connected to the clamping unit.
4. The power management chip protection circuit of claim 3, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the switch tube is an NMOS tube.
5. The power management chip protection circuit of claim 1, wherein the inverting unit is an inverter, an input terminal of the inverter is connected to an output terminal of the detection circuit, and an output terminal of the inverter is connected to the clamping unit.
6. The power management chip protection circuit of claim 5, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the switch transistor is a PMOS transistor.
7. The power management chip protection circuit of claim 1, wherein the power management chip comprises a voltage conversion module, and the voltage conversion module is configured to convert a direct current voltage into an alternating current voltage or convert an alternating current voltage into a direct current voltage.
8. The power management chip protection circuit of claim 7, wherein the power management chip further comprises a pulse regulation module, and the pulse regulation module is configured to drive an external switch.
9. The power management chip protection circuit according to claim 1, wherein the first well region and the second well region have the same doping concentration.
10. The power management chip protection circuit of claim 1, wherein the doping concentration of the first doped region and the third doped region is the same.
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| US6912109B1 (en) * | 2000-06-26 | 2005-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power-rail ESD clamp circuits with well-triggered PMOS |
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| CN114678851A (en) | 2022-06-28 |
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