515080 A7 ___—_____ B7 五、發明說明（1 ) <發明之領域> 本發明係關於半導體裝置之E S D ( Electro Static Discharge )保護電路，特別是關於使用Μ〇S F E T之堆 疊構造之E S D，對突波、及外來之過剩電壓之保護電路 〇 <先前之技術> 習知之半導體裝置之保護電路，係於其輸入小片與接 地之間，或輸出小片與接地之間，形成由二極體或電阻之 組合所形成之放電電路，於半導體積體電路之組裝工程或 實裝過程中，藉由將積蓄於封裝之端子上之靜電電荷放電 ，來防止靜電破壞。 另外，對於L S I之高集積化/高速化，尺度化成爲 非常有效之方法，隨著製程之尺度化，從裝置耐壓之觀點 來看，動作電壓也被尺度化。但是，I/O界面電壓，與 裝置相比，電源電壓之尺度化之進行較遲緩，因此，造成 使低動作電壓與高I / 0界面電壓兩立之必要性變高。像 這樣之要求，能夠以不產生製程過負載而予以實現者，已 知者有異電源追跡I / 0之形成技術。 通常，使用輸出緩衝器時，外部電壓比內部動作電壓 高，所以可能產生閘極氧化膜之信賴性之問題，即， T D D B ( Time-Dependent Dielectric Breakdown )或 H C I ( Hot Carder Injection )所代表之信賴性上之問題 ο ___ ____一 4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) --線_ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 五、發明說明（2 ) 爲了避免此問題，以前，係如圖7 ( a )所示，使用 使Μ〇S F E T成爲堆疊構造之防護技術。於圖7 ( a ) ，係爲了簡單起見，只表示N通道Μ〇S F E T之例子。 Ν通道MOSFET Ql、Q2、於外部電源Vext 之小片1與接地之間被串聯連接，Μ〇S F E T之堆疊構 造被形成。內部電源V i n t係被施加於連接於Q 1之閘 極之內部電源端子2。又’被連接於Q 2之閘極之端子 2 a也被施加0V〜V i n t等之電壓。 像這樣，如果使用Μ〇S F E T之堆疊構造， Μ〇S F Ε Τ之閘極•汲極電壓V GD及閘極•源極電壓 V GS可以滿足V GD、V GS < V int之關係，所以，使保 證T D D B信賴性成爲可能，又，汲極•源極電壓V GS將 V ext分壓，使H C I信賴性也可以獲得保障。關於 MOSFET Q 2，使其臨界値電壓爲V th，汲極電壓 被保持於V int - V th，所以可以避免信賴性上之問題。 近年，如圖7 ( a )、圖7 ( b )所示，於使用具備 有外部電源V ext與內部電源V int之異電源方式之半導體 裝置，對於例如經由小片1侵入之突波，表示高突波耐量 之保護電路，係使用具有將MOSFET Ql ，Q2串 聯連接於上述小片1與G N D之間之Μ 0 S F Ε T之堆疊 構造之異電源I / 0之保護電路。 短時間之突波電壓V被施加於小片1時之圖7 ( a ) 之等效電路與問題點，以圖7 ( b )表示。像這樣之外來 突波電壓，係以種種之理由進入小片1，但是，例如於半 ___ _ _____ 一 ~ Fi - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · •線_ 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 五、發明說明（3) 導體裝置之組裝或測試工程及檔案管理系統之實裝工程中 ，於週邊部被附加之電荷，係於經由封裝之端子放電之 E S D之情況產生。 圖7 ( a ) 、（ b )所示之構造，係於小片1被施加 短時間之突波電壓V時，可能產生破壞保護電路之可能性 。良P，如圖7 ( a )所示，Μ〇S F E T Q 1之閘極被 連接於V int，但是電源未被投入之狀態下，係如圖7 ( b )所示，成爲接地電位，由於V mt被等效地連接大容量， 所以，於施加突波電壓V時，Μ 0 S F E T Q 1之閘極 •汲極電壓V GD超過閘極氧化膜之耐壓，於Μ〇S F Ε Τ 之極速恢復特性發揮吸收突波之作用的機能之前， MOSFET Q1就被破壞了。 使用圖7 ( b )表示之等效電路，具體地說明突波電 壓V被施加於小片1時之Μ〇S F E T Q 1之破壞過程 。如果於圖7 ( b )所示之等效電路上施加突波電壓V時 ，於MOSFET Q 1之汲極側之通道表面，發生電子 正孔潰崩，於Q 1之源極•汲極間流通大量電流。被施加 於外部電源小片1之突波電壓V，藉由該放電電流而急速 降低。藉此，Μ〇S F Ε T之堆疊構造所形成之保護電路 表現出良好之極速恢復特性。 但是，如圖7 ( b )之點線圍住之1 〇所示，於 MOSFET Q 1，Q 2所構成之堆疊構造保護電路， 被施加高突波電壓V，所以於Q 1之閘極氧化膜之汲極端 ，施加最大的閘極•汲極間電壓V GD，於該部分有閘極絕 ___- A- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) . 線· 515080 Α7 Β7 五、發明說明（4) 緣膜會破壞之問題點。 另一方面，從以前起就使用將Q 2之汲極直接連接於 小片1之1段Μ 0 S F E T之保護電路試驗，但是，於像 這樣之1段Μ 0 S F Ε Τ之保護電路，Q 2之汲極電壓只 下降Q 1之源極•汲極電壓部分，所以，於Q 2之閘極氧 化膜之汲極端所施加之最大閘極•汲極間電壓V GD會下降 ，可以抑閘極氧化膜之破壞。 圖7 (c)係將由Q1 ，Q2所構成之MOSFET 之堆疊構造保護電路，與只由Q 2所構成之1段 Μ〇S F Ε T之保護電路之極速恢復特性作一比較者。於 圖7 ( c )中，粗點線所表示之堆疊構造之極速恢復電壓 爲V SB，導通狀態之汲極電壓爲V DB。從V SB切換到 V DB之遷移領域之極速恢復曲線爲2段，通常係因爲被稱 作2次破壞之現象所造成者。 相對於此，細實線所示之1段Μ〇S F Ε T之極速恢 復電壓V SB ’及導通狀態之汲極電壓V DB ’，不論哪一 個都比粗點線所示之堆疊構造Μ〇S F Ε T之極速恢復電 壓V SB及〇Ν狀態之汲極電壓V DB爲低。E S D放電等 所產生之突波電壓V如果被施加於小片1，則沿著圖7 ( c )所示之極速恢復特性曲線，保護電路反復地切換’直 到產生如圖7 ( b )所示之不能回復之閘極氧化膜之破壞 爲止，都能產生該半導體積體電路之突波防護之功能。 如先前所述，習知之1段Μ〇S F Ε T之保護電路’ 由於極速恢復電壓V S Β ’比堆疊構造之V S Β低’所以閘 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · _線· 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 五、發明說明（5 ) 極氧化膜破壞1 0之產生被抑制，此爲其優點。但是’另 一方面有一個問題，就是無法使極速恢復電壓v SB ’之値 遠比半導體裝置之信賴性保證所必要之外部電源電壓之最 大規格爲大。以上，係以Μ〇S F E T之堆疊構造作爲 E S D之保護電路之情況做了說明，但是，一般對於外來 突波電壓，使用Μ〇S F Ε Τ之堆疊構造保護電路實’也 有同樣之問題產稱。 <發明所欲解決之問題> 如上所述，習知之堆疊型Μ〇S電晶體保護電路，係 第1之Μ 0 S F Ε Τ之閘極氧化膜於汲極端容易破壞，或 ，習知之1段Μ 0 S F Ε Τ保護電路，無法充分地提供 T D D Β或H C I這樣之半導體裝置的信賴性之保證，此 爲其問題點。 本發明係爲了解決上述之問題點而設計者，以提供可 以保持半導體裝置之T D D Β、H C I信賴性，且可以避 免上述閘極氧化膜破壞之堆疊型Μ 0 S電晶體保護電路爲 目的。 <解決問題之手段> 本發明之堆疊型Μ 0 S電晶體保護電路，係於構成堆 疊構造保護電路之Μ〇S F Ε Τ之閘極•汲極間被施加過 剩電壓，爲了避免閘極氧化膜被壞，於閘極·汲極間，連 接例如箝二極體所形成之箝電路，使過剩電壓緩和者。具 __ -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 五、發明說明（6) 備有像這樣之箝電路之Μ〇S F E T之堆疊構造保護電路 ，係適於作爲由外部電源小片所侵入之外來突波之保護電 路。 又，本發明之堆疊型Μ 0 S電晶體保護電路，其特徵 爲，係爲了避免上述過剩電壓，造成構成堆疊構造保護電 路之Μ 0 S F Ε Τ之閘極氧化膜被破壞，而構成於 Μ〇S F Ε Τ之閘極•汲極間被施加過剩電壓時會〇Ν動 作之二極體及電阻，或M〇S F Ε Τ與電阻等所構成之切 換電路。具備像這樣之切換電路之Μ〇S F Ε Τ之堆疊構 造保護電路，係最適於作爲連接於I / 0小片之由 Μ〇S F Ε Τ所構成之輸出入緩衝器之保護電路。 具體地說，本發明之堆疊型Μ 0 S電晶體保護電路， 其特徵爲：具備有第1、第2之MOS電晶體，係第1之 Μ〇S電晶體之源極及第2 Μ 0 S電經體之汲極彼此連接 者；及箝電路，係具有第1、第2之端子，上述第1端子 連接於上述第1 Μ 0 S電晶體之閘極，上述第2端子連接 於上述第1電晶體之汲極者；及 半導體裝置之小片，係連接於上述第1 Μ 0 S電晶體 之汲極者。上述箝電路係具備，於突波電壓進入上述小片 時，使上述第1、第2端子間之電位差保持於一定之機會g 者。 較理想者，係上述箝電路係由二極體所構成，上述二 極體之陰極形成上述箝電路之第1端子，上述二極體之陽 極形成上述箝電路之第2端子。 __________-9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · --線· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 五、發明說明（7 ) 又，較立想者，係上述箝電路，係由分別屬於隔壁相 鄰之二極體之陽極與陰極彼此連接之複數二極體所構成， 形成上述複數之二極體之一方之終端部之陰極，構成上述 箝電路之第1端子，形成上述複數之二極體另一方之終端 部之陽極，構成上述箝電路之第2端子。 又，本發明一種堆疊型Μ 0 S電晶體保護電路，其特 徵爲：具備有第1、第2之M0S電晶體，係第1之 Μ〇S電晶體之源極及第2 Μ 0 S電經體之汲極彼此連接 者；及切換電路，係具有第1、第2及第3之端子，上述 第1端子連接於上述第1 Μ〇S電晶體之閘極，上述第2 端子連接於上述第1電晶體之汲極者，且第3端子連接於 半導體裝置之內部電源者；及小片，係連接於上述第1 Μ〇S電晶體之汲極者。上述切換電路係具備，於上述半 導體裝置之通常動作中，上述第2端子之電氣被遮斷，突 波電壓進入上述小片時，上述第1、第2之端子間之電位 差保持於一定之機能。更理想者，係上述第2之Μ 0 S電 晶體之源極及閘極，分別接地。 又，較理想者，係上述切換電路係由二極體所構成， 上述二極體之陽極被連接於上述第1之Μ〇S電晶體之閘 極，構成上述切換電路之第1端子，更者，上述二極體之 陰極連接於上述半導體裝置之內部電源，構成上述切換電 路之第3端子。 更者，較理想者，係上述二極體之陰極，經由電阻電 路，被連接於上述半導體裝置之內部電源，構成上述切換 ______- ιη- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ή^τ --線· 經濟部智慧財產局員工消費合作社印製 515080 A7 -B7 五、發明說明（8) 電路之第3端子。 又，較理想者，係上述切換電路係由分別屬於相鄰之 二極體之陽極與陰極彼此被相互連接之複數之二極體所構 成，形成上述複數之二極體之一方之終端部之陰極，被連 接於上述第1 Μ 0 S電晶體之閘極，形成上述切換電路之 第1端子，形成上述複數之二極體之另一方之終端部之陽 極，構成上述切換電路之第2端子，更者，形成上述複數 之二極體一方之終端部之陰極，被連接於上述半導體裝置 之內部電源，形成上述切換電路之第3端子。 更者，較理想者，係上述二極體之陰極，經由電阻電 路，被連接於上述半導體裝置之內部電源，構成上述切換 電路之第3端子。 又，較理想者，係上述複數之二極體之個數η ( η爲 自然數），係以上述半導體裝置之外部電源之電壓爲V ext ，上述內部電源之電壓爲V mt，上述二極體之順方向電壓 爲V F時，η > ( V ext — V mt ) / V F之關係式成立之 方式被選擇者。 又，上述切換電路係由，與導電型之上述第1、第2 之Μ〇S電晶體相反之第3M〇S電晶體所構成，上述第 3 Μ〇S電晶體之源極被連接於上述第1 Μ〇S電晶體之 閘極，形成上述切換電路之第2端子，更者，上述第3之 Μ〇S電晶體之源極，經由電阻被連接於上述第3 Μ〇S 電晶體之閘極，且上述第3 Μ〇S電經體之閘極，被連接 於上述半導體裝置之內部電源，形成上述切換電路之第3 _______ - η - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -X.UO (請先閱讀背面之注意事項再填寫本頁)515080 A7 ___—_____ B7 V. Description of the invention (1) < Field of invention > The present invention relates to an ESD (Electro Static Discharge) protection circuit for a semiconductor device, and particularly to an ESD using a stacked structure of MOSFET. Protection circuits for surges and external excess voltages 0 < Previous technology > Protection circuits for conventional semiconductor devices are formed between the input chip and the ground, or between the output chip and the ground, forming a diode The discharge circuit formed by a combination of resistors or resistors prevents electrostatic damage by discharging the electrostatic charge accumulated on the terminals of the package during the assembly process or mounting process of the semiconductor integrated circuit. In addition, for high integration and high speed of L S I, scaling becomes a very effective method. As the process is scaled, the operating voltage is also scaled from the standpoint of device withstand voltage. However, compared with the device, the scaling of the power supply voltage is slower than that of the device. Therefore, it is necessary to balance the low operating voltage with the high I / 0 interface voltage. Such requirements can be realized without generating process overload, and the known technology has different power source tracking I / 0 formation technology. Generally, when the output buffer is used, the external voltage is higher than the internal operating voltage, so the reliability of the gate oxide film may occur, that is, the reliability represented by TDDB (Time-Dependent Dielectric Breakdown) or HCI (Hot Carder Injection) Questions on sexuality ο ___ ____ 一 4- This paper size is applicable to Chinese National Standard (CNS) A4 (210 χ 297 mm) (Please read the precautions on the back before filling this page) --line _ Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 515080 A7 B7 5. Invention Description (2) In order to avoid this problem, previously, as shown in Figure 7 (a), the use of MOSFET becomes Stacking protection technology. In FIG. 7 (a), for the sake of simplicity, only an example of the N-channel MOS F E T is shown. The N-channel MOSFETs Q1 and Q2 are connected in series between the small chip 1 of the external power source Vext and the ground, and a stacked structure of the MOSFET is formed. The internal power supply Vi n t is applied to the internal power supply terminal 2 connected to the gate of Q 1. Also, a terminal 2 a connected to the gate of Q 2 is also applied with a voltage of 0 V to V i n t or the like. In this way, if a MOSFET stacked structure is used, the gate-drain voltage V GD and the gate-source voltage V GS of MOSSF can satisfy the relationship of V GD, V GS < V int, so This makes it possible to guarantee the reliability of TDDB. In addition, the drain-source voltage V GS divides V ext, so that the reliability of HCI can also be guaranteed. Regarding MOSFET Q 2, the critical threshold voltage is V th and the drain voltage is maintained at V int-V th, so reliability problems can be avoided. In recent years, as shown in FIGS. 7 (a) and 7 (b), a semiconductor device using a different power source system having an external power source V ext and an internal power source V int has a high level of surge intrusion through the chip 1, for example. The surge withstand protection circuit is a protection circuit with a different power supply I / 0 with a stack structure of M 0 SF Ε T that connects MOSFETs Q1 and Q2 in series between the above-mentioned small piece 1 and GND. The equivalent circuit of FIG. 7 (a) and the problem points when the short-time surge voltage V is applied to the chip 1 are shown in FIG. 7 (b). The external surge voltage like this entered the chip 1 for various reasons, but, for example, in the half ___ _ _____ one ~ Fi-This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) ( Please read the precautions on the back before filling in this page) • • Line _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515080 A7 B7 V. Description of the invention (3) Assembly of conductor devices or test engineering and file management system installation In the process, the charge added to the peripheral part is generated by the ESD that is discharged through the terminals of the package. The structure shown in Figs. 7 (a) and (b) is caused by the possibility that the protection circuit may be damaged when the small voltage 1 is applied to the short-term surge voltage V. Good P. As shown in Fig. 7 (a), the gate of MOSFET Q1 is connected to V int, but the power is not turned on. As shown in Fig. 7 (b), it becomes the ground potential. mt is equivalently connected to a large capacity, so when the surge voltage V is applied, the gate-drain voltage V GD of M 0 SFETQ 1 exceeds the withstand voltage of the gate oxide film, and recovers at the extremely fast speed of MOSF ET The MOSFET Q1 is destroyed before the characteristic functions to absorb the surge. Using the equivalent circuit shown in Fig. 7 (b), the destruction process of MOS F E T Q 1 when the surge voltage V is applied to the chip 1 will be specifically described. If a surge voltage V is applied to the equivalent circuit shown in FIG. 7 (b), a positive electron hole collapse occurs on the channel surface of the drain side of MOSFET Q 1, between the source and drain of Q 1 A large amount of current flows. The surge voltage V applied to the external power chip 1 is rapidly reduced by the discharge current. As a result, the protection circuit formed by the stacked structure of MOS F E T exhibits good extremely fast recovery characteristics. However, as shown by 10 surrounded by the dotted line in FIG. 7 (b), the stack structure protection circuit composed of MOSFETs Q 1 and Q 2 is applied with a high surge voltage V, so the gate of Q 1 is oxidized. The drain terminal of the film is applied with the largest gate-drain voltage V GD, and there is a gate insulation in this part ___- A- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ( (Please read the precautions on the back before filling this page). Thread · 515080 Α7 Β7 V. Description of the invention (4) The problem that the membrane will be damaged. On the other hand, a protection circuit test in which the drain of Q 2 is directly connected to the 1-segment M 0 SFET of chip 1 has been tested from the past, but the protection circuit of the 1-segment M 0 SF Ε Τ, Q 2 The drain voltage of Q1 only decreases the source-drain voltage part of Q1, so the maximum gate-to-drain voltage V GD applied at the drain terminal of the gate oxide film of Q2 will decrease, which can suppress the gate Destruction of oxide film. Figure 7 (c) is a comparison of the protection characteristics of the MOSFET stack structure protection circuit composed of Q1 and Q2 with the ultra-fast recovery characteristics of the one-stage MOS F ET protection circuit composed of Q2 only. In Fig. 7 (c), the maximum recovery voltage of the stacked structure indicated by the thick dotted line is V SB, and the drain voltage of the on-state is V DB. The speedy recovery curve of the migration field from V SB to V DB is two segments, usually caused by a phenomenon known as secondary destruction. On the other hand, the one-step MOSF ET fast recovery voltage V SB ′ and the on-state drain voltage V DB ′ shown by the thin solid line are both higher than the stacked structure M shown by the thick dotted line. The fast recovery voltage V SB of SF E T and the drain voltage V DB of the ON state are low. If the surge voltage V generated by the ESD discharge is applied to the chip 1, the protection circuit is repeatedly switched along the extremely fast recovery characteristic curve shown in FIG. 7 (c) until the circuit shown in FIG. 7 (b) is generated. Until the destruction of the non-recoverable gate oxide film, the surge protection function of the semiconductor integrated circuit can be generated. As mentioned earlier, the conventional 1-level MOSF ET protection circuit ', because the extremely fast recovery voltage VS Β' is lower than the VS Β of the stack structure ', so the size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) · _line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 515080 A7 B7 V. Description of the invention (5) The destruction of the polar oxide film 1 0 was caused by Suppression is its advantage. However, on the other hand, there is a problem that the maximum recovery voltage v SB cannot be made larger than the maximum specification of the external power supply voltage necessary for the reliability guarantee of the semiconductor device. In the above, the case where the stack structure of MOS F E T is used as the protection circuit of E S D has been described, but generally, for external surge voltages, the stack structure protection circuit of MOS F ET is used to have the same problem. < Problems to be Solved by the Invention > As mentioned above, the conventional stacked MOS transistor protection circuit is the first gate oxide film of M 0 SF Ε Τ and is easily damaged, or The one-stage M 0 SF ET protection circuit cannot sufficiently provide the reliability guarantee of a semiconductor device such as TDD B or HCI, which is a problem. The present invention is designed to solve the above-mentioned problems, and aims to provide a stacked M 0S transistor protection circuit that can maintain the reliability of T D D B and H C I of a semiconductor device and avoid the destruction of the gate oxide film. < Means for Solving the Problem > The stacked M 0 S transistor protection circuit of the present invention is an excessive voltage applied between the gate and the drain of the MOSSF ET which constitutes the stacked structure protection circuit, in order to avoid the gate The oxide film is damaged, and a clamp circuit formed by, for example, a clamp diode is connected between the gate and the drain to reduce excess voltage. __ -8- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 515080 A7 B7 V. Description of the invention (6) The stacked structure protection circuit of the MOSFET with a clamp circuit like this is suitable as a protection circuit for external surges invaded by small pieces of external power supply. In addition, the stacked M 0 S transistor protection circuit of the present invention is characterized in that the gate oxide film of M 0 SF Ε Τ constituting the stacked structure protection circuit is destroyed in order to avoid the above-mentioned excessive voltage, and is formed in M 〇SF Ε Τ When excess voltage is applied between the gate and the drain, a diode and a resistor that will operate, or a switching circuit composed of MOSF ET and a resistor. A stacking protection circuit of MOS F ET with such a switching circuit is most suitable as a protection circuit for an input / output buffer composed of MOS F ET connected to an I / 0 chip. Specifically, the stacked M 0S transistor protection circuit of the present invention is characterized in that it includes first and second MOS transistors, which are the source of the first MOS transistor and the second MOS transistor. The drain electrodes of the S electric warp body are connected to each other; and the clamp circuit has first and second terminals, the first terminal is connected to the gate of the first M 0 S transistor, and the second terminal is connected to the above The drain of the first transistor and the small piece of the semiconductor device are connected to the drain of the first MOS transistor. The clamp circuit includes a device that keeps the potential difference between the first and second terminals at a certain opportunity g when a surge voltage enters the chip. Preferably, the clamp circuit is composed of a diode, a cathode of the diode forms a first terminal of the clamp circuit, and an anode of the diode forms a second terminal of the clamp circuit. __________- 9- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) 515080 A7 B7 printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economics and Economics V. Description of the Invention (7) Also, the more idealist is the above-mentioned clamp circuit, which is connected to the anode and cathode of the two adjacent diodes next to each other. It is composed of a plurality of diodes, forming a cathode of a terminal portion of one of the plurality of diodes, forming a first terminal of the clamp circuit, forming an anode of a terminal portion of the other plurality of diodes, constituting the above. The second terminal of the clamp circuit. In addition, a stacked M 0S transistor protection circuit according to the present invention is characterized in that it includes first and second MOS transistors, which are the source of the first MOS transistor and the second M 0 S transistor. The drain electrodes of the warp body are connected to each other; and the switching circuit has first, second, and third terminals, the first terminal is connected to the gate of the first MOS transistor, and the second terminal is connected to Those who are the drain of the first transistor and whose third terminal is connected to the internal power supply of the semiconductor device; and small pieces that are connected to the drain of the first MOS transistor. The switching circuit is provided with a function that, during normal operation of the semiconductor device, the second terminal is electrically disconnected and the surge voltage enters the chip, and the potential difference between the first and second terminals is maintained at a constant level. More preferably, the source and gate of the second M 0 S transistor are grounded separately. Further, it is preferable that the switching circuit is composed of a diode, and an anode of the diode is connected to a gate of the first MOS transistor to constitute a first terminal of the switching circuit. The cathode of the diode is connected to an internal power source of the semiconductor device, and constitutes a third terminal of the switching circuit. Furthermore, the ideal one is the cathode of the above diode, which is connected to the internal power supply of the semiconductor device via a resistance circuit to constitute the above-mentioned switching. ______- ιη- This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the notes on the back before filling out this page) 价 ^ τ --line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515080 A7 -B7 V. Description of the invention (8) The first of the circuit 3 terminals. It is also preferable that the above-mentioned switching circuit is constituted by a plurality of diodes in which anodes and cathodes, which respectively belong to adjacent diodes, are connected to each other to form a terminal portion of one of the plurality of diodes. The cathode is connected to the gate of the first MOS transistor, forming the first terminal of the switching circuit, forming the anode of the other terminal portion of the plurality of diodes, and forming the second terminal of the switching circuit. Furthermore, a cathode forming a terminal portion of the plurality of diodes is connected to an internal power source of the semiconductor device to form a third terminal of the switching circuit. More preferably, the cathode of the diode is connected to an internal power source of the semiconductor device via a resistance circuit to constitute a third terminal of the switching circuit. Further, it is preferable that it is the number η of the plural diodes (η is a natural number), and the voltage of the external power source of the semiconductor device is V ext, the voltage of the internal power source is V mt, and the diode When the forward voltage of the body is VF, the method in which η > (V ext — V mt) / VF is established is selected. The switching circuit is composed of a 3MOS transistor which is opposite to the conductive type of the first and second MOS transistors, and the source of the third MOS transistor is connected to the above. The gate of the first MOS transistor forms the second terminal of the switching circuit. Furthermore, the source of the third MOS transistor is connected to the third MOS transistor via a resistor. The gate, and the gate of the 3 MOS electrical warp body is connected to the internal power supply of the semiconductor device to form the third _______-η-This paper standard applies to China National Standard (CNS) A4 (210 X 297 mm) -X.UO (Please read the notes on the back before filling this page)
515080 A7 B7 五、發明說明（9 ) 端子。 (請先閱讀背面之注咅？事項再填寫本頁) 又，較理想者，係上述第3 Μ〇S電晶體之臨界値 V th，係以上述內部電源之電壓爲V int時，V th>V ext 一 V int之關係成立之方式被選擇者。 又，本發明之堆疊型Μ 0 S電晶體保護電路，係具備 有：第1導電型之第1、第2M0S電晶體，及第2導電 型之第3、第4之M〇S電晶體，及第1、第2之二極體 ，及第1、第2之電阻，及輸出入小片，及第1、第2、 經濟部智慧財產局員工消費合作社印製515080 A7 B7 5. Description of the invention (9) Terminal. (Please read the note on the back? Matters before filling out this page) Also, ideally, it is the critical value of the 3 MOS transistor (V th), and when the voltage of the internal power supply is V int, V th > V ext-The way in which the relationship of V int is established is selected. In addition, the stacked M 0S transistor protection circuit of the present invention includes: the first and second MOS transistors of the first conductivity type, and the third and fourth MOS transistors of the second conductivity type, And the first and second diodes, and the first and second resistors, and the input and output chips, and the first, second, and two employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the consumer cooperative
第3之電源之保護電路；其特徵爲：上述第1之MO S電 晶體之源極與上述第2之Μ〇S電晶體之汲極互相連接； 述第3之Μ〇S電晶體之源極與上述第4之Μ〇S電晶體 之汲極，彼此互相連接；上述第1之Μ〇S電晶體之汲極 與上述第3之Μ 0 S電晶體之汲極被連接於上述輸出入小 片；上述第1之二極體之陰極，係連接於上述第1之 Μ〇S電晶體之閘極，更者，上述第1之二極體之陰極， 經由地1電阻被連接於上述第1電源；上述第1之二極體 之陽極，係被連接於上述輸出入小片；上述第1之二極體 之陰極，係連接於上述第1之Μ 0 S電晶體之閘極，更者 ，上述第1之二極體之陰極，經由地1電阻被連接於上述 第1電源；上述第1之二極體之陽極，係被連接於上述輸 出入小片；上述第2之二極體之陽極，係被連接於上述第 3之Μ 0 S電晶體之閘極，更者，上述第2二極體之陽極 係經由第2電阻被連接於上述第2電源；上述第2二極體 之陰極，係被連接於上述輸出入小片；上述第4之Μ〇S ____ 19-_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515080 A7 B7 五、發明說明（10) 電晶體之源極，係被連接於上述第3電源；上述第2之 Μ〇S電晶體之源極，係被接地而形成者。 <實施例> 以下，參照圖示詳細說明本發明之實施型態。 圖1 ( a )係表示地1實施型態之堆疊型Μ 〇 S電晶 體保護電路之構成之圖。該保護電路，係例如針對從外部 電源小片所進入之外來突波，保護半導體裝置之內部電路 者，係由供給外部電源V ext之小片1，及將第1、地2 MOSFET Ql、Q2串聯連接之MOSFET之堆 疊構造，及箝電路3所構成。 此處，箝電路3係具有，連接於圖1 9 ( a )所不之 堆疊型Μ〇S電晶體保護電路之節點A之第1端子，及連 接於節點B之第2端子之2端子電路；具備有不論其電流 値爲多少，而端子間電壓V AB爲一定之機能；藉由連接箱 電路3，可以使Μ〇S F E T Q 1之閘極•汲極間電壓 V GB，不會超過於汲極端之絕緣膜產生無法恢復之破壞之 電壓Β V GDm。 具體地說，箝電路3係如圖1 ( b )之點線圍住之 3 a所示，可以使用二極體之順方向電壓V p構成。由於 只要將複數的二極體D i ( i = 1〜η，η爲自然數）予 以串聯連接，則可以使V AB = η V F，所以，只要藉由將 二極體之個數η最佳化，即可以不損及通常動作時之半導 體裝置之T D D Β、H C I信賴性保證所需之機能，而防 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · --線· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 五、發明說明（11) 止於Μ〇S F Ε τ之汲極端產生閘極絕緣膜之無法恢復之 破壞。 又，例如假設M〇SFEET Q2爲正常切斷型， 則對於半導體積體電路之通常動作，可以使保護電路成爲 〇F F狀態，所以，Μ〇S F Ε T之堆疊型構造保護電路 ，可以不影響通常動作’即可以提供表示最適於半導體裝 置之信賴性保證之極速恢復電壓V S Β之値之保護電路。 其次，使用圖3 ( c )對於堆疊型Μ 0 S電晶體保護 電路之動作作^"更詳細說明。圖3 ( c )之係貫線’係表 示圖3 ( a )、圖3 ( b )、之節點Β之突波吸收波形。 又，圖3 ( c )之粗點線係表示圖3 ( a )、圖3 ( b ) 之節點A、之突波吸收形。 如圖3 ( c )所不’節點B之極速恢復電壓V S Β B與 節點A之極速恢復電壓V SBA之差，及Q1、Q2爲〇N 狀態時之節點B之電壓V DBB與節點A之電壓V DBA之差 ，係相當於圖3 ( a )之箝電路4之端子電壓V AB，或圖 3 (b)之被串聯連接之箝二極體Di之箝電壓nVF之 値。像這樣，即使於小片1被施加高突波電壓V SBB，節 點A之電壓會從節點B之電壓被箝住成爲V AB或η V F位 準移位之電壓，因此，Q 1之閘極氧化膜之破壞被防止。 其次，使用圖2 ( a )，說明第2實施型態之堆疊型 Μ〇S電晶體保護電路。第2實施型態之保護電路，其本 身爲可以發揮作爲連接半導體裝置之I/0小片之輸出入 緩衝器之機能之電路，又，同時也具備有保護半導體裝置 __________一___ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 言 (請先閱讀背面之注意事項再填寫本頁)The protection circuit of the third power source; characterized in that: the source of the first MOS transistor and the drain of the second MOS transistor are connected to each other; the source of the third MOS transistor And the drain of the fourth MOS transistor are connected to each other; the drain of the first MOS transistor and the drain of the third MOS transistor are connected to the input / output. The small piece; the cathode of the first diode is connected to the gate of the first MOS transistor, and the cathode of the first diode is connected to the first resistor via the ground 1 resistor. 1 power supply; the anode of the first diode is connected to the input and output chip; the cathode of the first diode is connected to the gate of the first M 0 S transistor, or The cathode of the first diode is connected to the first power source through the ground 1 resistor; the anode of the first diode is connected to the input / output chip; the second diode is connected to the first diode. The anode is connected to the gate of the third M 0 S transistor, and the anode of the second diode is passed through the second The resistor is connected to the above-mentioned second power source; the cathode of the above-mentioned second diode is connected to the above-mentioned input and output chip; the above-mentioned No. 4 MOS ____ 19-_ This paper standard is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 515080 A7 B7 V. Description of the invention (10) The source of the transistor is connected to the third power source; the source of the second MOS transistor is grounded. By. < Example > Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Fig. 1 (a) is a diagram showing the structure of a stacked MOS electrical crystal protection circuit in the implementation mode of ground 1. This protection circuit, for example, protects the internal circuit of a semiconductor device against external surges entering from a small chip of an external power supply, and connects the small chip 1 of the external power supply V ext and the first and second MOSFETs Q1 and Q2 in series. The stacked structure of the MOSFET and the clamp circuit 3. Here, the clamp circuit 3 has a first terminal connected to the node A of the stacked MOS transistor protection circuit shown in Fig. 19 (a), and a two terminal circuit connected to the second terminal of the node B. ; It has the function that the voltage between terminals V AB is constant regardless of the current 値; By connecting the circuit 3, the gate-drain voltage V GB of MOSFETQ 1 can not exceed the drain The extreme insulating film generates an irrecoverable destruction voltage Β V GDm. Specifically, the clamp circuit 3 is shown as 3 a surrounded by a dotted line in FIG. 1 (b), and can be formed using a forward voltage V p of the diode. As long as the complex diodes Di (i = 1 to η, η is a natural number) are connected in series, V AB = η VF, so as long as the number of diodes η is optimal It can prevent the TDD Β and HCI reliability of the semiconductor device during normal operation from impairing the required functions, and prevent the 13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page.) ·-· Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumers' Cooperatives of the Ministry of Economic Affairs's Intellectual Property Bureau printed by 515080 A7 B7 V. Invention Description (11) Ends at The drain terminal of MOSF E τ causes irrecoverable damage to the gate insulating film. For example, if the MOSFEET Q2 is a normal cut-off type, the normal operation of the semiconductor integrated circuit can make the protection circuit into the 0FF state. Therefore, the stacking structure protection circuit of the MOSF ET can not be affected. The "normal operation" can provide a protection circuit representing the extremely fast recovery voltage VS Β of the reliability guarantee of the semiconductor device. Next, the operation of the stacked M 0 S transistor protection circuit will be described in more detail using FIG. 3 (c). The line “c” of FIG. 3 (c) represents the surge absorption waveform of the node B in FIG. 3 (a), FIG. 3 (b), and FIG. The thick dotted lines in FIG. 3 (c) indicate the surge absorption shapes of the nodes A and 3 (a) and FIG. 3 (b). As shown in Figure 3 (c), the difference between the extremely fast recovery voltage VS B of node B and the extremely fast recovery voltage V SBA of node A, and the voltage V of node B V DBB and the voltage of node A when Q1 and Q2 are ON. The difference between the voltages V DBA is equivalent to the terminal voltage V AB of the clamp circuit 4 in FIG. 3 (a), or the clamp voltage nVF of the clamp diode Di connected in series in FIG. 3 (b). In this way, even if a high surge voltage V SBB is applied to the chip 1, the voltage of the node A will be clamped from the voltage of the node B to a voltage shifted to the level of V AB or η VF. Therefore, the gate of Q 1 is oxidized. The destruction of the film is prevented. Next, a stacked MOS transistor protection circuit according to the second embodiment will be described using FIG. 2 (a). The protection circuit of the second embodiment is a circuit that can function as an input / output buffer of an I / 0 chip connected to a semiconductor device, and also has a protective semiconductor device. ______________ This paper Standards apply to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page)
515080 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（12) 之內部電路，不受I /〇小片進來之外來突波之影響之機 會b 。 圖2 ( a )所示知堆疊型Μ〇S電晶體保護電路，係 由將第1、第2之MOSFET Ql、Q2予以串聯連 接之M〇S F Ε Τ之堆疊構造，及半導體裝置之I /〇小 片4，及切換電路5所構成。 堆疊型MOSFET Ql、Q2，係連接於I/O 小片4之輸出入緩衝器電路，於Μ〇S F E T Q 1之閘 極·汲極間，連接有決定緩衝器電路之輸出阻抗之電阻電 路，及含有給予閘極偏壓等之內部電源V mt之供給端子之 切換電路。 此處，切換電路5係具備第1、第2、第3、之端子 之3端子電路，其第1、第2端子，分別與堆疊型M〇S 電晶體保護電路之節點A與B相連接，內部電源V mt之供 給端子與弟3端子連接，第1、第2端子間連接切換元件 0 其次，針對切換電路5之動作作一說明。堆疊型 MOSFET Ql、Q2作爲連接I/O小片4之輸出 入緩衝器電路而進行通常作動時，切換元件成爲Ο F F狀 態，輸出緩衝器電路之動作所必要之Μ〇S F E T Q 1 閘極偏壓電壓V G，係由連接於節點Α之第1之端子所供 給。此處，鬧極偏壓電壓V G，係被輸入到第3端子之內 部電源電壓V int，經由包含電阻電路之切換電路5從第1 端子被輸出之電壓。 --- - lfi-__ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) . -丨線· 515080 A7 B7 五、發明說明（13) 堆疊型Μ〇S F E T Q 1、Q 2吸收從I /〇小片 4進入之外來突波電壓時’切換元件成爲〇 ν狀態。不論 從此Ο Ν狀態之第2端子所流入之電流之値爲多少，連接 節點Β之第2端子之電壓，與連接節點Α之第1端子之電 壓之差V AB成爲一定之方式下，切換電路作動作。 像這樣’如果連接動作之切換電路5，於施加突波電 壓時’可以使Μ〇S F E T Q 1之閘極•汲極間電壓 V GB (與V ΑΒ相等），不會超越使汲極端之閘極絕緣膜 產生無法恢復之破壞之電壓Β V GDm。 又，通常動作時，切換電路5從Μ〇S F E T Q 1 之汲極（節點Β )被切離，於閘極（節點A )，被供給通 常動作時之偏壓電壓V G，係經由切換電路5從內部電源 V int被供給，所以第2實施型態之堆疊型Μ 0 S電晶體保 護電路可以具備有，可以發揮作爲連接於I / 0小片4之 輸出緩衝器之機能，同時也具備有保護半導體積體電路之 內部電路，不受從I / 0小片4進入之外來突波之影響。 其次，對於第2實施型態之第1具體例，以使用二極 體與電阻構成切換電路5之堆疊型Μ 0 S電晶體保護電路 ，作一說明。 圖2 ( b )係表示使用二極體與電阻構成點線包圍之 5 a之切換電路之堆疊型Μ〇S電晶體保護電路之圖。此 保護電路係，由半導體裝置之I / 〇小片4 ’及將第1、 .第2M0SFET Ql、Q2予以串聯連接枝堆疊型 Μ〇S F Ε Τ，及供給半導體裝置之內部電源V int之內部 ________- 1Λ- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · 線· 經濟部智慧財產局員工消費合作社印製 515080 A7 B7 __ 五、發明說明（Μ) 電源端子，及i個（i = l〜η，η爲自然數）被串聯連 接之二極體D i ，及電阻R所構成。又，I /〇小片4係 從外部被供給電源電壓V ext。 二極體D i之個數n，係可以半導體裝置之外部電源電 壓V ext與內部電源V int，以下式求得。 η > ( V ext - V int ) / V F ( 1 ) 此處，V F爲二極體之順方向電壓。 ‘ 二極體之個數η係以滿足式（1 )之方式決定，於半 導體裝置之通常動作中，於節點Β被施加V ext，即使於節 點A被施加比V ext低之V int，也可以防止外部電源電流 流出到被串聯連接之二極體D i ( i二1〜η )。 所以，例如如果V ext - V int爲0 · 5 V左右，則只 要連接1個二極體即可，但是，如果是連接1 V以上者， 則必需連接2個以上之二極體。 於具備單數或複數之二極體D i之M〇S F E T之堆 疊型保護電路中，如果於其小片4，被施加比V ext高之突 波電壓V，上述二極體D 1之阻抗與電阻R之阻抗相比非 常小，所以，節點B與節點A之間之電位差V AB通常與 η V F相等，可以防止Μ〇S F E T Q 1之汲極端之閘 極氧化膜之破壞。 對於半導體裝置之通常動作，由式（1 ) Μ〇S F E T Q 1之閘極•汲極間電壓V GD比η V Ρ小 ___- 17- ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂： ••線_ 經濟部智慧財產局員工消費合作社印製 515080 A7 ___ B7 五、發明說明（is) ，所以連接於節點B之二極體D i之串聯連接電路，以作 爲〇F F狀態被切離。又，於Μ〇S F E T Q 1之閘極 ，被施加作爲輸出緩衝器作動所必要之偏壓電壓V G，係 經由電阻R從V lnt (這時爲V G = V mt )被供給。 所以，Μ〇S F E T之堆疊保護電路，可以提供對於 作爲輸出緩衝器之通常動作不會有任何影響，而對半導體 裝置之信賴性保證表示適切之極速回復電壓値之堆疊型 Μ〇S電晶體保護電路。又，電阻R，係於外部電源小片 4被施加局突波電壓V ’經由一極體D i大電流流入內部 電源端子時，發揮保護半導體裝置之內部電路之功效。 其次，就第2實施狀態之第2具體例子，以使用 M〇S F E T及電阻構成切換電路5之堆疊型MO S電晶 體保護電路作一說明。 圖2 (c)係表示使用P通道MOSFET及電阻， 構成點線所圍住之切換電路5之第2實施型態之第2具體 例子之圖。該保護電路，係由半導體裝置之I /〇小片4 ，及將第1、第2之MOSFET Ql、Q2予以串聯 連接之堆疊M〇 S F E T，及供給半導體裝置之內部電源 V int之內部電端子，及切換動作之P通道m〇S F E T Q 3，及電阻R所構成。又I /〇小片4被供給外部電源 V ext 〇 作切換動作之P通道Μ 0 S F E T Q 3之臨界値 V th，係由外部電源V ext與內部電源V int所構成，以下 式之關係式求出。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂·· 線· 經濟部智慧財產局員工消費合作社印製 515080 Α7 Β7 五、發明說明（16) V th > V ext - V int ( 2 ) 作切換動作之P通道Μ〇S F E T Q 3之臨界値電 壓V th，如果以滿足（2 )之方式被決定，則於半導體裝 置之通常動作中，於節點B被施加V ext，於節點A被施加 比V ext低之V int，由於P通道Μ〇S F E 丁 Q 3成爲 〇 F F狀態，所以，可以防止外部電源電流流出到Ρ通道 MOSFET Q3。 於具備Ρ通道MOSFET Q3之堆疊型MOS電 晶體保護電路中，如果於I / 〇小片4被施加比V ext高之 短時間之突波電壓V，則如先前圖7 ( b )所說明者，由 於內部電源端子V int被經由大的等效電容C而被接地，所 以，P通道Μ 0 S F E T Q 3成爲〇Ν狀態。這時，節 點Α與節點Β之間之電位差V ΑΒ係以下式被給予。 V AB = (V ext - V int)* R ON/(R ON+R) (3) 經濟部智慧財產局員工消費合作社印製 此處，RON (RON <R)爲 P 通道 MOSFET Q 3之Ο N電阻。藉由使R ON成爲與電阻之阻抗値等效， 而被施加於端子B之突波電壓V ext，由於被分壓，所以 Q 1、Q 3之閘極氧化膜被保護。於I / ◦小片4被施加 突波電壓間，節點B與節點A之間之電位差V AB成爲與$ (3 )之値相等，所以只要成爲 1Q- (社叫先閱讀背面之注音？事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515080 A7 ____ B7___ 五、發明說明（I7) V AB < V ext — V int ( 4 ) (請先閱讀背面之注音？事項再填寫本頁) 則可以防止Μ〇S F E T Q 1之汲極端之閘極氧化 膜之破壞。 對於半導體裝置之通常動作，藉由式（2 )，連接於 節點B之P通道MOSFET Q3作爲OFF狀態而被 切離。又，於Μ〇S F E T Q 1之閘極處，作爲輸出緩 衝器動作所必要之偏壓電壓V G，經由電阻R，從V int ( 這時爲V G = V int )被供給。 經濟部智慧財產局員工消費合作社印製 所以，圖2 ( c )所示之Μ〇S F E T之堆疊構造保 護電路，能夠不影響作爲輸出緩衝器之通常動作，而提供 可以使半導體裝置之信賴性保證與E S D耐性兩立之堆疊 型Μ 0 S電晶體保護電路。又，電阻R，係當從對外部電 源小片施加高的突波電壓V，經由Ρ通道Μ〇S F Ε Τ Q 3，大電流流入內部電源端子時，發揮保護內部電路之 功效。圖2 ( a )、圖2 ( b )及圖2 ( c )所示之堆疊 型Μ 0 S電晶體保護電路突波吸收波形，係與先前之圖1 (c )所示知突波吸收波形相同。 像這樣，即使於I /〇小片4被施加高突波電壓，由 於節點Α之電位追隨節點Β之電位，節點Β與節點Α之電 位差V AB經常保持一定，所以，q 1之閘極氧化膜之破壞 被防止。 其次，使用圖3 ( a )、圖3 ( b )說明第3實施型 態之堆疊型Μ〇S電晶體保護電路之構造。圖3 ( a )、 _____-20-_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公愛） 515080 A7 B7____ 五、發明說明（18) 圖3 ( b )係表示以箝二極體與電阻R所形成之領域之剖 面構造及平面圖作一例子。又，圖3 ( a )係圖3 ( b ) (請先閱讀背面之注音？事項再填寫本頁) 之A - A剖面圖。於N阱上形成1個P N接合二極體之情 況作一說明。 如圖3 ( a )所示，於P型矽基版1 1上形成構成電 組R之主體之N阱1 2，於其一方設有P型擴散層1 3， 藉此，連接於電阻R之一方之電極之P N接合所形成之二 極體被形成。又，以包圍二極體之方式，形成N型擴散層 1 4。該N型擴散層1 4係將電阻R與二極體之陰極連接 之一方之有電阻之接觸，具有使電阻R之値精確地接近設 計値之效果。 經濟部智慧財產局員工消費合作社印製 又，於N阱1 2設N型擴散層1 5，形成電阻R之他 方之有電阻之接觸。更者，爲了提高施加有高突波電壓之 N阱1 2與P型矽基版1 1之間之P N接合分離特性，以 將該N阱1 2圍著之方式形成切斷通道用之P型擴散層（ 保護層）1 6。藉由該P型擴散層1 6，於P型矽基版之 上面很容易擴散之N型反轉層被遮斷，可以提高電壓之N 阱1 2之分離特性。 此處，1 7爲設於P型擴散層1 6之保護層之電極， 1 8係圖2 ( b )之節點B之電極，1 9係節點A之電極 ，2 0係連接內部電源V 之電極。圖3 ( b 〇 )表示著 這些構造之平面圖。又，1 1 a係覆蓋矽基版1 1之表面 之絕緣膜。 其次，使用圖4說明，半導體裝置之輸出入部之第4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -91 - 515080 Α7 __ Β7 五、發明說明（l9) (請先閱讀背面之注咅？事項再填寫本頁) 實施型態之堆疊型Μ 0 S電晶體保護電路之具體之適用例 。於第4之實施型態，就半導體裝置之I / 〇小片與內部 電路之間所連接之本發明之保護電路之種種之組合作一說 明。 於圖4中，點線所爲著的2 1之實線部分所表示之輸 出入電路，係圖1 ( b )所說明過之具備箝二極體D之突 波保護電路。點線所圍著的2 2所示之輸出電路係由 MOSFET Ql’ Q2’ 、二極體D’及電阻R’所 構成之具有輸出緩衝機能之保護電路。又，6 a係表示前 段之輸出緩衝器。 點線所圍著的2 3所表示之內部電路，係表示I /〇 小片及內部電路之連接端子8，經由操作放大器被連接之 例子。該操作放大器6，爲了防止從I / 〇小片來的突波 之侵入，所以於一方之輸入端子配置保護電阻R ” ，於另 一方之輸入端子被施加參考電壓V ref。 例如，對於連接於端子8之內部電路，藉由組合對於 輸入電路2 1之實線部所示之E S D等之突波保護電路， 而可以達成對於內部電路之良好之突波防護機能。 經濟部智慧財產局員工消費合作社印製 這時，如輸入電路2 1之點線所示，如果連接電阻R 與內部電源端子V int，則輸入電路2 1可以作爲具備突波 防護機能之輸入緩衝器使用。又，於作爲輸入緩衝器動作 之輸入電路2 1及作爲輸出緩衝器動作之輸出電路2 2中 ，將電阻 R、R’與內部電源端子V int共通化’使兼具有連接 ___-22- ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公θ 515080 A7 ______B7____ 五、發明說明（20) (請先閱讀背面之注音？事項再填寫本頁} 於I / 0小片之輸出入緩衝器之機能，及對於從I /〇小 片進入之E S D等之突波保護機能也可。又，於圖4中， 表示二極體D、D ’爲單數之情況，但是，二極體D、 D ’爲複數也可以同樣地組合。 其次，使用圖5，對於於堆疊型Μ 0 S電晶體保護電 路之MOSFET Ql、Q2之構成上之問題，作一說 明。Μ〇S F E T Q 1及Q 2由於必需吸收很大之突波 電流，所以，數1 0 0 // m之閘極寬度係必須要的，但是 ’一方面，如果使閘極寬度變大，則從寄生電阻成分等之 元件定數之不均依性，產生部分之閘極破壞，而無法獲得 良好之突波防護特性。 經濟部智慧財產局員工消費合作社印製 爲了避免此問題，如圖5所示，將Q 1、Q 2分割成 閘極寬度1 0 //m左右之多數之並聯連接之M〇S F E 丁 。如果這樣，則經由二極體D從I /〇小片進入節點A之 突波電流，分散於由閘極寬度小之多數之Μ〇S F E T所 形成之Q 1，均勻的流通，所以，可以改善Q 1本身之突 波耐量。又，這時，Q 1及Q 2之節點Ν係作爲共通節點 彼此相互連接。 其次，使用圖6說明第5實施型態之互補型 Μ〇S F Ε Τ電晶體保護電路之構成。例如，使用內部電 源V int與接地電位G N D所形成之C Μ 0 S型半導體裝置 中，如果要應用本發明之突波保護電路，則基本上，只要 將第1到第4實施型態所說明之Ν通道M〇s F Ε Τ側之 突波防護電路，及將其反轉之P通道側之突波防護電路以 -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515080 A7 B7 五、發明說明（21) 共通汲極連接即可。 (請先閱讀背面之注音5事項再填寫本頁) 圖6係表示互補型Μ ◦ S電晶體保護電路之構成之例 子之圖。圖6所示之保護電路，係由Ν通道M〇S F Ε Τ Q1、Q2，及 Ρ 通道MOSFET Q3、Q4，及二 極體D 1、D 2，及電阻R 1、R 2，及外部電源V ext， 及內部電源V i n 11、V i n 12所構成。 圖6所示之保護電路，舉一個例子，如圖之點線所示 ，Q 1、Q 3之閘極偏壓以V inti、V int2及電阻R 1、 R 2被給予。像這樣，可以以同一電路形式構成E S D保 護電路（無點線部分時）及輸出緩衝電路（有點線部分時 )。一方面，對只限於E S D保護電路之目的者’ Q 1、 Q之閘極端子，只要爲不與V inti、V int2連接之電路形 式（無點線部分時）即足夠。 又，圖6所示之保護電路作爲互補型輸出緩衝器使用 時，經由2 4，2 5，於Q 2、Q 4之閘極被輸入互補信 號，從Q 1、Q 3之共通汲極所連接之I / 〇小片輸出信 號。 經濟部智慧財產局員工消費合作社印製 其次，將圖6所示之保護電路作之動作作一說明。 具備單數或複數之二極體D 1，D 2之互補型Μ〇S電晶 體保護電路中，如果於I / 0小片被施加正的突波電壓， 則藉由Ν通道Μ〇S F E T Q 1、Q 2之極速回復特性 ，突波電壓被吸收，藉由二極體D 1，可以防止Q 1之汲 極端之閘極氧化膜之破壞。 又，於I / 0小片被施加負的突波電壓時，藉由Ρ通 ____-24-_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515080 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（22) 道MOSFET Q3、Q4極速回復特性，突波電壓被 吸收，藉由二極體D 2，Q 3之汲極端之閘極氧化膜之破 壞被防止。 又，二極體 D 1，D 2 係藉由 V ext、V inti、V int2 以複數段被構成之情況時。這時，二極體D 1、D 2之段 數 η 1、η 2 係需要滿足 η 1 >( V ext - V inti )/ V F 、η 2 > ( V int2 — 0 ) / V F。 對於互補型半導體裝置之通常動作，二極體D 1、 D 2係從Q 1、Q 2之閘極被切離，又，於Q 1、Q 3之 閘極，從V inti、V int2被供給作爲緩衝器作動所必要之 偏壓，所以，圖6所示之互補型Μ〇S電晶體保護電路， 係不會對作爲緩衝器之通常動作有任何影響，可以使互補 型半導體裝置之T D D Β、H C I信賴性保證與E S D耐 性兩立。 又，電阻R1、R2具有使二極體D1、D2之箝特 性安定化，防止過大電流，防止D 1、D 2之破壞之效果 。又’於I /〇小片被施加高突波電壓，經由電晶體D 1 、D 2，大電流流入內部電源v inti、v int2時，可以發 揮保護內部電路之功能。 又’本發明並不限定於上述之實施之型態。例如，第 1到第5之實施之型態中，可以用由複數之電阻所構成之 電阻電路，或阻抗元件，以代替保護電阻r。又，如第2 實施型態所述，例如可以用由Μ 0 S F E T所構成之切換 元件，代替二極體。 —^—.--------— (請先閱讀背面之注意事項再填寫本頁) 訂· --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) 二25 - 515080 A7 B7 五、發明說明（23) 又，如第4實施型態所說明者，於第1到第5之實施 型態，必部只限定外部電源小片或I /〇小片，一般只要 是有外來突波進入之虞之部分，都可以應用。其他只要是 不脫離本發明之範圍，實施例可以做種種之變形來實施。 <效果> 如上所述，藉由本發明之堆疊型Μ 0 S電晶體保護電 路，藉由於以前容易於閘極氧化膜產生破壞之第1 Μ 0 S F Ε Τ之閘極•汲極間，連接二極體或 Μ〇S F Ε Τ開關，使提供對於半導體電路之信賴性保證 表示適切之極速回復電壓之値，且可以避免閘極氧化膜之 破壞之保護電路成爲可能。 又，依據本發明之保護電路，於半導體積體電路之通 常動作時，部會產生保護電路之電流被遮斷，閘極氧化膜 被施加一定値以上之電壓之虞，所以，不會產生HC I或 T D D Β等之信賴性上之問題。 <圖示簡單說明> 圖1係表示第1實施型態之堆疊型Μ 0 S電晶體保護 電路之構成及特性之圖。 (a )係表示第1之實施型態之保護電路之基本構成 之圖。 (b )係表示使用二極體之保護電路之構成之圖。 (c )係表示保護電路之突波吸收波型之圖。 _ -26 -_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---*------------— (請先閱讀背面之注意事項再填寫本頁) --線· 經濟部智慧財產局員工消費合作社印製 5J.5080 Α7 Β7 五、發明說明（24) 圖2係表示第2實施型態之堆疊型Μ〇S電晶體保護 電路之構成及特性之圖。 (請先閱讀背面之注意事項再填寫本頁) (a )係表示第2之實施型態之保護電路之基本構成 之圖。 (b )係表示使用二極體及電阻之保護電路之構成之 圖。 (c )係表示使用μ〇S電晶體及電阻之保護電路之 圖。 圖3係表示第3實施型態之堆疊型Μ〇S電晶體保護 電路之構造之圖。 (a )係表示切換（箝）元件部之構成之圖。 (b )係表示切換（箝）元件部之構成之圖。 圖4係表示第4實施型態之Μ〇S電晶體保護電路之 應用例子之圖。 圖5係表示第4實施型態之堆疊型Μ〇S電晶體保護 電路之MOS電晶體Q1、Q2之構成圖。 經濟部智慧財產局員工消費合作社印製 圖6係表示第5實施型態之互補型Μ 0 S電晶體保護 電路之構成圖。 圖7係表示習知之堆疊型μ〇S電晶體保護電路之構 成與等效電路及特性之圖。 (a )係表示通動作之電路構成之圖。 (b )係表示突波電壓施加時之等效電路之圖。 (c )係表示比較堆疊構造與i段構造之μ〇s電晶 體保護電路之極速恢復特性之圖。 27 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515080 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（25) <符號說明> 1 外部電源小片 2、2 a 內部電源端子 3 箝電路 3 a 二極體箝電路 4 I /〇小片 5 切換電路 5 a 由二極體與電阻所構成之切換電路 5 b 又Μ 0 S F E T與電阻所構成之切換電路 6 操作放大器 7 參 考 電 壓 端 子 8 內 部 電 路 連 接 端 子 1 〇 閘 極 氧 化 膜 破 壞部 1 1 P 型 矽 基 版 1 1 a 絕 緣 膜 1 2 N 阱 13、16 Ρ型擴散層 1 4、1 5 Ν型擴散層 17 保護層 18 電極Β515080 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. The internal circuit of the invention description (12) is not affected by the surge from the incoming I / 〇 chip b. The stacked MOS transistor protection circuit shown in Fig. 2 (a) is a stacked structure of MOSF ET which has the first and second MOSFETs Q1 and Q2 connected in series, and the I / 〇 constituted by a small piece 4 and a switching circuit 5. Stacked MOSFETs Q1 and Q2 are connected to the I / O chip 4 output I / O buffer circuit. Between the gate and the drain of MOSFET Q1, a resistance circuit that determines the output impedance of the buffer circuit is connected, and A switching circuit for a supply terminal of an internal power supply V mt to which a gate bias is applied. Here, the switching circuit 5 is a 3-terminal circuit having first, second, third, and third terminals. The first and second terminals are connected to nodes A and B of the stacked MOS transistor protection circuit, respectively. The supply terminal of the internal power supply V mt is connected to the 3 terminal, and the switching element 0 is connected between the first and second terminals. Next, the operation of the switching circuit 5 will be described. When the stacked MOSFETs Q1 and Q2 are normally operated as the input / output buffer circuit connected to the I / O chip 4, the switching element is in the 0 FF state, and the MOSFETQ 1 gate bias voltage is necessary for the operation of the output buffer circuit. VG is supplied from the first terminal connected to node A. Here, the alarm bias voltage V G is a voltage that is input to the internal power supply voltage V int of the third terminal and is output from the first terminal via a switching circuit 5 including a resistance circuit. ----lfi -__ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page).-丨 515080 A7 B7 V. Invention Explanation (13) When the stacked MOSFETs Q1 and Q2 absorb external surge voltage from the I / 〇 chip 4 and the switching element is in the νν state. Regardless of the magnitude of the current flowing from the second terminal of the 0 Ν state, the voltage difference between the voltage of the second terminal of the connection node B and the voltage of the first terminal of the connection node V AB becomes a certain way, the switching circuit Take action. In this way, if the switching circuit 5 that is in operation is connected, when a surge voltage is applied, the gate-drain voltage V GB of MOSFETQ 1 (equivalent to V ΑΒ) will not exceed the gate that makes the drain terminal The insulating film generates an irrecoverable and destroyed voltage β V GDm. During normal operation, the switching circuit 5 is cut off from the drain (node B) of MOSFET Q1, and the gate (node A) is supplied with the bias voltage VG during normal operation. The internal power supply V int is supplied, so the stacked M 0 S transistor protection circuit of the second embodiment can be provided, which can function as an output buffer connected to the I / 0 chip 4 and also has a protective semiconductor. The internal circuit of the integrated circuit is not affected by surges from outside the I / 0 chip 4. Next, for the first specific example of the second embodiment, a description will be given of a stacked M 0 S transistor protection circuit that uses a diode and a resistor to form the switching circuit 5. Figure 2 (b) is a diagram showing a stacked MOS transistor protection circuit using a 5a switching circuit surrounded by a diode and a resistor to form a dotted line. This protection circuit is composed of an I / 0 chip 4 ′ of a semiconductor device and the first and second MOSFETs Q1 and Q2 connected in series to a branch stacking MOSSF ET, and an internal power supply V int supplied to the semiconductor device. _______- 1Λ- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) · Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 515080 A7 B7 __ 5. Description of the invention (M) Power terminals, and i (i = l ~ η, η is a natural number) are connected in series by a diode D i and a resistor R. The I / 〇 chip 4 is supplied with a power supply voltage V ext from the outside. The number n of the diodes Di can be obtained from the external power supply voltage V ext and the internal power supply V int of the semiconductor device by the following formula. η > (V ext-V int) / V F (1) Here, V F is the forward voltage of the diode. 'The number of diodes η is determined in such a way as to satisfy formula (1). In the normal operation of a semiconductor device, V ext is applied to node B, and even if V int lower than V ext is applied to node A, It is possible to prevent the external power supply current from flowing to the diodes Di (i 2 to η) connected in series. Therefore, for example, if V ext-V int is about 0 · 5 V, only one diode can be connected, but if it is more than 1 V, two or more diodes must be connected. In a MOSFET with a singular or plural diode D i in a stacked protection circuit, if a surge voltage V higher than V ext is applied to the die 4, the impedance and resistance of the diode D 1 The impedance of R is very small, so the potential difference V AB between node B and node A is usually equal to η VF, which can prevent the gate oxide film on the drain terminal of MOSFETQ 1 from being damaged. For the normal operation of a semiconductor device, the gate-drain voltage V GD of MOSFETQ 1 is smaller than η V ρ by the formula (1) ___- 17- ^ The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Order: •• _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515080 A7 ___ B7 V. Description of the invention (is), so it is connected to the node The series connection circuit of the diode B i of B is cut off as an OFF state. A bias voltage V G necessary for operating as an output buffer is applied to the gate of MOS F E T Q 1 and is supplied from V lnt (in this case, V G = V mt) via a resistor R. Therefore, the stacked protection circuit of MOSFET can provide stacked MOS transistor protection that does not have any effect on the normal operation as an output buffer, and represents the appropriate fast recovery voltage for the reliability guarantee of semiconductor devices. Circuit. In addition, the resistor R is used to protect the internal circuit of the semiconductor device when a large surge current V 'is applied to the external power chip 4 and flows into the internal power terminal through a polar body Di. Next, as a second specific example of the second implementation state, a description will be given of a stacked MOS transistor protection circuit that uses the MOSFET and resistor to form the switching circuit 5. Fig. 2 (c) is a diagram showing a second specific example of the second embodiment of the switching circuit 5 surrounded by a dotted line using a P-channel MOSFET and a resistor. The protection circuit is composed of an I / 0 chip 4 of a semiconductor device, a stacked MOSFET in which the first and second MOSFETs Q1 and Q2 are connected in series, and an internal electrical terminal for supplying an internal power source V int of the semiconductor device. And the switching operation of the P channel MOSFETQ 3, and the resistor R. The I / 〇 chip 4 is supplied with an external power source V ext 〇 The threshold 値 V th of the P channel M 0 SFETQ 3 for switching operation is composed of the external power source V ext and the internal power source V int, which can be obtained by the relationship of the following formula . This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) Order · · Line · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 515080 Α7 Β7 V. Description of the invention (16) V th > V ext-V int (2) The threshold voltage V th of the P-channel MOSFETQ 3 for switching operation, if determined in a manner satisfying (2), it is determined in the semiconductor In the normal operation of the device, V ext is applied to node B and V int lower than V ext is applied to node A. Since P channel MOSFE DQ 3 becomes FF state, external power current can be prevented from flowing to P-channel MOSFET Q3. In a stacked MOS transistor protection circuit with a P-channel MOSFET Q3, if a surge voltage V higher than V ext is applied to the I / 〇 chip 4 for a short time, as described in FIG. 7 (b), Since the internal power supply terminal V int is grounded via the large equivalent capacitance C, the P channel M 0 SFETQ 3 is in the ON state. At this time, the potential difference V AB between the node A and the node B is given by the following formula. V AB = (V ext-V int) * R ON / (R ON + R) (3) Printed here by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, RON (RON < R) is the P-channel MOSFET Q 3 Ο N resistance. By making R ON equivalent to the resistance 値 of the resistor, the surge voltage V ext applied to the terminal B is divided, so that the gate oxide films of Q 1 and Q 3 are protected. When a surge voltage is applied to I / ◦ sheet 4, the potential difference V AB between node B and node A becomes equal to 値 of $ (3), so as long as it becomes 1Q- (the company first read the note on the back? Matters then (Fill in this page) The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 515080 A7 ____ B7___ V. Description of Invention (I7) V AB < V ext — V int (4) (Please read first Note on the back? Matters need to be filled out on this page) to prevent damage to the gate oxide film of the MOSFETQ 1 drain terminal. For the normal operation of the semiconductor device, the P-channel MOSFET Q3 connected to the node B is cut off by the formula (2) as the OFF state. In addition, at the gate of MOS F E T Q 1, a bias voltage V G necessary for operation as an output buffer is supplied from V int (in this case, V G = V int) via a resistor R. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, the stacked structure protection circuit of the MOSFET shown in Figure 2 (c) can provide reliability guarantee for semiconductor devices without affecting the normal operation as an output buffer. Stacked M 0 S transistor protection circuit with ESD resistance. The resistor R is used to protect the internal circuit when a large surge voltage V is applied from the external power chip and a large current flows into the internal power terminal via the P channel MOS F E T Q 3. The surge absorption waveforms of the stacked M 0S transistor protection circuit shown in Fig. 2 (a), Fig. 2 (b), and Fig. 2 (c) are the same as the known surge absorption waveforms shown in Fig. 1 (c). the same. In this way, even if a high surge voltage is applied to the I / 0 chip 4, since the potential of the node A follows the potential of the node B, the potential difference V AB between the node B and the node A is always kept constant. Therefore, the gate oxide film of q 1 Its destruction is prevented. Next, the structure of the stacked MOS transistor protection circuit according to the third embodiment will be described with reference to Figs. 3 (a) and 3 (b). Figure 3 (a), _____- 20-_ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 515080 A7 B7____ V. Description of the invention (18) Figure 3 (b) is shown in Figure 2 The cross-sectional structure and plan view of the area formed by the polar body and the resistor R are taken as an example. In addition, Figure 3 (a) is the A-A section of Figure 3 (b) (please read the note on the back? Matters before filling out this page). A description will be given of a case where a P N junction diode is formed on the N well. As shown in FIG. 3 (a), an N-well 12 is formed on the P-type silicon substrate 11 to form the main body of the electric group R, and a P-type diffusion layer 13 is provided on one side thereof, thereby being connected to the resistor R. A diode formed by PN junction of one of the electrodes is formed. An N-type diffusion layer 14 is formed so as to surround the diode. The N-type diffusion layer 14 has a resistance contact between one of the resistors R and the cathode of the diode, and has the effect of accurately bringing the resistance R to the design value. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Furthermore, an N-type diffusion layer 15 is provided on the N well 12 to form a resistive contact with the other resistance R. Furthermore, in order to improve the PN junction separation characteristics between the N-well 12 and the P-type silicon base plate 11 to which a high surge voltage is applied, a P for cutting off the channel is formed so as to surround the N-well 12. Type diffusion layer (protective layer) 1 6. With the P-type diffusion layer 16, the N-type inversion layer that is easily diffused on the P-type silicon substrate is blocked, and the separation characteristics of the voltage N-well 12 can be improved. Here, 17 is the electrode of the protective layer provided on the P-type diffusion layer 16, 18 is the electrode of node B of FIG. 2 (b), 19 is the electrode of node A, and 20 is the electrode connected to the internal power source V electrode. Fig. 3 (b0) shows a plan view of these structures. In addition, 1 1 a is an insulating film covering the surface of the silicon base plate 1 1. Next, use Figure 4 to explain that the fourth paper size of the input / output section of the semiconductor device applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -91-515080 Α7 __ Β7 V. Description of the Invention (l9) (Please First read the note on the back? Matters and then fill out this page) Specific application examples of the implementation of the stacked M 0 S transistor protection circuit. In the fourth implementation mode, a description will be given of various types of cooperation of the protection circuit of the present invention connected between the I / O chip of the semiconductor device and the internal circuit. In FIG. 4, the output and input circuits indicated by the solid lines of 21 indicated by the dotted lines are surge protection circuits provided with clamp diode D as described in FIG. 1 (b). The output circuit shown by 22 surrounded by the dotted line is a protection circuit with output buffer function composed of MOSFET Q1 'Q2', diode D ', and resistor R'. 6a indicates the output buffer at the previous stage. The internal circuit indicated by 2 3 surrounded by the dotted line is an example in which the I / 〇 chip and the connection terminal 8 of the internal circuit are connected via an operational amplifier. In order to prevent the surge from the I / 〇 chip, the operational amplifier 6 is provided with a protection resistor R "on one input terminal, and a reference voltage V ref is applied to the other input terminal. For example, for the connection to the terminal The internal circuit of 8 can achieve a good surge protection function for the internal circuit by combining surge protection circuits such as ESD shown in the solid line section of the input circuit 21. 1 Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs At this time, as indicated by the dotted line of the input circuit 21, if the resistor R and the internal power terminal V int are connected, the input circuit 21 can be used as an input buffer with surge protection. It can also be used as an input buffer. In the input circuit 21 and the output circuit 2 2 functioning as output buffers, the resistors R and R 'are integrated with the internal power supply terminal V int so as to have both connections ___- 22- ^ Paper size applies to China National Standard (CNS) A4 Specification (210 X 297 Male θ 515080 A7 ______B7____ V. Description of Invention (20) (Please read the note on the back? Matters before filling out this page}) I / 0 small The functions of the input and output buffers and the surge protection function for ESD etc. entering from the I / 0 chip are also possible. In addition, FIG. 4 shows a case where the diodes D and D 'are singular. The polar bodies D and D 'can be plurally combined in the same way. Next, using FIG. 5, the problem of the structure of the MOSFETs Q1 and Q2 of the stacked M0S transistor protection circuit will be described. MOSFETQ 1 And Q 2 must absorb a large surge current, so a gate width of 1 0 0 // m is necessary, but 'on the one hand, if the gate width is made larger, the parasitic resistance components, etc. The non-uniform dependence of the fixed number of components has caused some gate destruction and can not obtain good surge protection characteristics. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to avoid this problem, as shown in Figure 5, 1. Q 2 is divided into a large number of parallel connected M0SFE Ds with a gate width of 1 0 // m. If so, the surge current from the I / 〇 chip to node A via diode D is dispersed in Q formed by a majority of MOSFETs with a small gate width 1. Uniform circulation. Therefore, the surge resistance of Q 1 itself can be improved. At this time, the nodes N of Q 1 and Q 2 are connected to each other as a common node. Next, the fifth embodiment will be described using FIG. 6. Complementary MOSF ET transistor protection circuit configuration. For example, in a C M 0 S type semiconductor device formed using an internal power supply V int and a ground potential GND, if the surge protection circuit of the present invention is to be applied, it is basically In the above, as long as the surge protection circuit on the N channel Mos F E T side described in the first to fourth implementation modes, and the surge protection circuit on the P channel side which is reversed, The dimensions are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 515080 A7 B7 V. Description of the invention (21) Common drain connection is sufficient. (Please read the note 5 on the back before filling out this page.) Figure 6 is a diagram showing an example of the structure of a complementary M ◦ S transistor protection circuit. The protection circuit shown in FIG. 6 is composed of N-channel MOSF ET Q1, Q2, and P-channel MOSFETs Q3, Q4, and diodes D1, D2, and resistors R1, R2, and an external power supply. V ext and the internal power supply V in 11, V in 12. The protection circuit shown in FIG. 6 is an example. As shown by the dotted line, the gate bias voltages of Q 1 and Q 3 are given by V inti and V int 2 and resistors R 1 and R 2. In this way, the E S D protection circuit (when there is no dotted line portion) and the output buffer circuit (when there is a dotted line portion) can be configured in the same circuit form. On the one hand, the gate terminals of Q1, Q, which are limited to the purpose of the ESD protection circuit, are sufficient as long as they are in the form of a circuit that is not connected to V inti, V int2 (when there is no dotted line). In addition, when the protection circuit shown in FIG. 6 is used as a complementary output buffer, complementary signals are input to the gates of Q 2 and Q 4 through 2 4 and 25, and the common drains of Q 1 and Q 3 are input. Connected I / 〇 chip output signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, the operation of the protection circuit shown in FIG. 6 will be described. In a complementary MOS transistor protection circuit with singular or plural diodes D 1 and D 2, if a positive surge voltage is applied to the I / 0 chip, the N channel MOSFET Q 1, Q The extremely fast recovery characteristics of 2 and the surge voltage are absorbed. With the diode D 1, the gate oxide film on the drain terminal of Q 1 can be prevented from being damaged. In addition, when a negative surge voltage is applied to the I / 0 chip, the P _____- 24-_ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515080 Α7 Β7 Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative V. Invention description (22) MOSFET Q3, Q4 extremely fast recovery characteristics, the surge voltage is absorbed, and the gate oxide film is destroyed by the diode D 2 and Q 3 extremes Be prevented. When the diodes D 1 and D 2 are configured in a plural number by V ext, V inti, and V int 2. At this time, the number of segments η 1 and η 2 of the diodes D 1 and D 2 must satisfy η 1 > (V ext-V inti) / V F, η 2 > (V int2 — 0) / V F. For the normal operation of the complementary semiconductor device, the diodes D 1 and D 2 are cut off from the gates of Q 1 and Q 2, and the gates of Q 1 and Q 3 are cut from V inti and V int 2. The bias voltage necessary for operating as a buffer is provided. Therefore, the complementary MOS transistor protection circuit shown in FIG. 6 does not have any influence on the normal operation of the buffer, and can enable the TDD of the complementary semiconductor device. Β, HCI reliability guarantee and ESD tolerance are mutually exclusive. In addition, the resistors R1 and R2 have the effects of stabilizing the clamp characteristics of the diodes D1 and D2, preventing excessive current, and preventing the destruction of D1 and D2. In addition, when a high surge voltage is applied to the I / 〇 chip and a large current flows into the internal power sources v inti and v int2 through the transistors D 1 and D 2, the function of protecting the internal circuit can be performed. The present invention is not limited to the above-mentioned embodiment. For example, in the first to fifth implementations, a resistor circuit composed of a plurality of resistors or an impedance element may be used instead of the protection resistor r. In addition, as described in the second embodiment, for example, a switching element composed of M 0 S F E T may be used instead of the diode. — ^ —.--------— (Please read the notes on the back before filling in this page) Order · --line · This paper size applies to China National Standard (CNS) A4 (210 X 297mm f ) II 25-515080 A7 B7 V. Description of the invention (23) In addition, as explained in the fourth embodiment, in the first to fifth embodiments, the necessary parts are limited to external power chips or I / 〇 chips. Generally, it can be applied as long as it is a part that is subject to external surges. As long as the other embodiments do not depart from the scope of the present invention, the embodiments can be implemented in various modifications. < Effect > As described above, with the stacked M 0 S transistor protection circuit of the present invention, the gate and drain between the 1 M 0 SF Ε Τ due to the gate oxide film that was easily damaged before was easily generated. By connecting a diode or a MOSF ET switch, it is possible to provide a protection circuit that provides adequate guarantee of the reliability of the semiconductor circuit, expresses the appropriate high-speed recovery voltage, and prevents damage to the gate oxide film. In addition, according to the protection circuit of the present invention, during the normal operation of the semiconductor integrated circuit, the current of the protection circuit is interrupted, and the gate oxide film may be applied with a voltage higher than a certain threshold. Therefore, HC will not be generated. Reliability issues such as I or TDD Β. < Brief description of the diagram > Fig. 1 is a diagram showing the structure and characteristics of the stacked M 0 S transistor protection circuit of the first embodiment. (a) is a diagram showing the basic structure of the protection circuit of the first embodiment. (b) is a diagram showing the configuration of a protection circuit using a diode. (c) is a diagram showing a surge absorption waveform of a protection circuit. _ -26 -_ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --- * ------------— (Please read the precautions on the back before (Fill in this page)-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5J.5080 Α7 Β7 V. Description of the invention (24) Figure 2 shows the second embodiment of the stacked MOS transistor protection circuit. Diagram of composition and characteristics. (Please read the precautions on the back before filling this page) (a) is a diagram showing the basic structure of the protection circuit of the second implementation type. (b) is a diagram showing the structure of a protection circuit using a diode and a resistor. (c) is a diagram showing a protection circuit using a μS transistor and a resistor. Fig. 3 is a diagram showing the structure of a stacked MOS transistor protection circuit according to a third embodiment. (a) is a figure which shows the structure of a switching (clamp) element part. (b) is a figure which shows the structure of a switching (clamp) element part. Fig. 4 is a diagram showing an application example of the MOS transistor protection circuit of the fourth embodiment. Fig. 5 is a diagram showing the structure of MOS transistors Q1 and Q2 of a stacked MOS transistor protection circuit of a fourth embodiment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 6 is a block diagram of a complementary M 0 S transistor protection circuit showing the fifth implementation type. Fig. 7 is a diagram showing the structure and equivalent circuit and characteristics of a conventional stacked-type transistor protection circuit. (a) is a diagram showing a circuit configuration of a communication operation. (b) is a diagram showing an equivalent circuit when a surge voltage is applied. (c) is a graph comparing the ultra-fast recovery characteristics of a μs electric crystal protection circuit with a stacked structure and an i-stage structure. 27 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 515080 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (25) < Symbol description > 1 External power supply chip 2, 2 a Internal power supply terminal 3 Clamp circuit 3 a Diode clamp circuit 4 I / 〇 chip 5 Switching circuit 5 a Switching circuit composed of diode and resistor 5 b Switching composed of M 0 SFET and resistor Circuit 6 Operational amplifier 7 Reference voltage terminal 8 Internal circuit connection terminal 1 〇Gate oxide film destruction part 1 1 P-type silicon base plate 1 1 a Insulating film 1 2 N Well 13, 16 P-type diffusion layer 1 4, 1 5 Ν Type diffusion layer 17 Protective layer 18 Electrode B
19 電極A 2〇 電極A ’ 2 1 輸入電路 _-28- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---*---4-----I---------訂---------線--^__w (請先閱讀背面之注意事項再填寫本頁) 5J.5080 A7 _B7 五、發明說明（26) 2 2 輸出電路 2 3 內部電路 2 4、2 5 互補信號輸入端子 —^—IL—--------------tr---------^ I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 卜紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 2919 Electrode A 2〇 Electrode A '2 1 Input Circuit_-28- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --- * --- 4 ----- I- -------- Order --------- line-^ __ w (Please read the notes on the back before filling this page) 5J.5080 A7 _B7 V. Description of the invention (26) 2 2 Output circuit 2 3 Internal circuit 2 4, 2 5 Complementary signal input terminal — ^ — IL —-------------- tr --------- ^ I (Please read first Note on the back, please fill out this page again) The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 29