CN114664931A - Trench gate semiconductor device and preparation method thereof - Google Patents
Trench gate semiconductor device and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000012216 screening Methods 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000002513 implantation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The present disclosure relates to a trench gate semiconductor device and a method of manufacturing the same. The trench gate semiconductor device sequentially comprises a drain metal region (122), a substrate region (101) of a first conduction type, an epitaxial region (102) of the first conduction type, an active region (100) and a source metal region (121) from bottom to top, wherein the active region (100) comprises a shielding region (107) of a second conduction type located at the bottom of a trench (106), and a channel is arranged in the shielding region (107) of the second conduction type. The channel is also formed in the second conduction type shielding region at the bottom of the groove gate semiconductor device, so that a conduction channel can be increased, and the channel density of the device is improved, so that the on-resistance of the groove gate semiconductor device is effectively reduced, and meanwhile, the channel in the shielding region is prepared by adopting a self-alignment process, so that the length of the channel is accurately controlled.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a trench gate semiconductor device and a method for manufacturing the same.
Background
Trench gate semiconductor devices are becoming the direction of future development due to their smaller on-resistance. However, taking SiC MOSFETs as an example, SiC materials can withstand higher electric field strengths and between SiC and its gate dielectric materialThe ratio of dielectric constant is relatively high (e.g., compared to the commonly used gate dielectric material SiO)2About 2.5) and therefore the electric field strength in the gate dielectric is generally greater when the SiC MOSFET device is subjected to withstand voltages.
In the related art, the trench gate semiconductor device can effectively shield an electric field by forming a P-type (or N-type) shielding region at the bottom of the trench to reduce the electric field strength in the gate dielectric, thereby improving the long-term reliability of the product. However, the introduced P-type (or N-type) shielding region and the P-type (or N-type) base region together form a Junction Field-Effect Transistor (JFET) structure, thereby increasing the on-resistance of the device.
Disclosure of Invention
The invention aims to provide a simple and high-reliability trench gate semiconductor device and a preparation method thereof.
In order to achieve the above object, the present disclosure provides a trench gate semiconductor device, which sequentially includes, from bottom to top, a drain metal region, a substrate region of a first conductivity type, an epitaxial region of the first conductivity type, an active region, and a source metal region, wherein the active region includes a shielding region of a second conductivity type located at the bottom of a trench, and a channel is provided in the shielding region of the second conductivity type.
Optionally, the active region includes a first source region of the first conductivity type, a first contact region of the second conductivity type, a well region of the second conductivity type, an insulated gate dielectric layer, and a gate.
The well region of the second conductivity type is formed on the epitaxial region of the first conductivity type, the insulated gate dielectric layer is positioned on the inner wall of the groove, the insulated gate dielectric layer is respectively contacted with the first source region of the first conductivity type and the well region of the second conductivity type, on the inner wall of the groove, the grid electrode covers the insulated gate dielectric layer, the first contact region of the second conductivity type is formed on the well region of the second conductivity type, and the first source region of the first conductivity type is formed on the well region of the second conductivity type.
The active region further comprises a second source region of the first conductivity type and a second contact region of the second conductivity type, which are arranged at the bottom of the trench and used for forming a channel in the shielding region of the second conductivity type, wherein the second source region of the first conductivity type is positioned between the insulated gate dielectric layer and the shielding region of the second conductivity type, so that the insulated gate dielectric layer is partially contacted with the shielding region of the second conductivity type.
Optionally, the trench in the shielding region of the second conductivity type is prepared by a self-aligned process.
Optionally, the doping concentration of the shielding region of the second conductivity type is 1014cm-3～1019cm-3。
Optionally, the length of the channel is greater than 0.1 μm.
The present disclosure also provides a method for manufacturing a trench gate semiconductor device, the method including:
forming an epitaxial region of the first conductivity type on the substrate region of the first conductivity type;
forming an active region on the epitaxial region of the first conductivity type, wherein the active region comprises a shielding region of a second conductivity type at the bottom of the trench, and a channel is arranged in the shielding region of the second conductivity type;
forming a source metal region on the active region;
a drain metal region is formed under the substrate region of the first conductivity type.
Optionally, forming an active region on the epitaxial region of the first conductivity type includes:
sequentially forming a well region of a second conductive type and a first source region of a first conductive type on the epitaxial region of the first conductive type;
depositing a first mask on the first source region of the first conductive type, and etching to form the groove;
forming a shielding region of the second conductivity type in the trench, followed by depositing a second mask covering the bottom and inner walls of the trench;
etching the second mask to form a side wall, then forming a second source region of the first conductive type at the bottom of the trench, preparing a channel in the shielding region of the second conductive type by a self-aligned process, and then removing the first mask and the side wall;
forming an insulated gate dielectric layer covering the bottom and the inner wall of the groove;
forming a grid on the inner wall of the groove;
depositing a first insulating medium isolation layer, wherein the first insulating medium isolation layer completely fills the groove;
polishing to expose the source region of the first conductivity type;
depositing a second insulating medium isolation layer and a third mask in sequence, and etching to remove the exposed first source region of the first conductive type to form a first contact hole part and remove the exposed second source region of the first conductive type to form a second contact hole part;
a first contact region of a second conductivity type is formed at the first contact hole portion, and a second contact region of the second conductivity type is formed at the second contact hole portion.
Optionally, forming a gate on an inner wall of the trench includes:
depositing polycrystalline silicon on the bottom and the inner wall of the groove;
and etching the polysilicon to remove the polysilicon at the bottom of the groove and form the grid on the inner wall of the groove.
Optionally, the doping concentration of the shielding region of the second conductivity type is 1014cm-3～1019cm-3。
Optionally, the length of the channel is greater than 0.1 μm.
According to the technical scheme, the channel is also formed in the shielding region of the second conduction type at the bottom of the groove gate semiconductor device, so that a conduction channel can be increased, the channel density of the device is improved, and the on-resistance of the groove gate semiconductor device is effectively reduced.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic structural diagram of a trench-gate semiconductor device according to an exemplary embodiment;
fig. 2 is a schematic structural diagram of a trench-gate semiconductor device according to another exemplary embodiment;
FIG. 3 is a flowchart of a method for fabricating a trench-gate semiconductor device provided by an exemplary embodiment;
fig. 4 a-4 p are schematic diagrams of a process for fabricating a trench-gate semiconductor device according to an example embodiment.
Description of the reference numerals
100 active region 112 insulated gate dielectric layer
101 a substrate region 113 gate of a first conductivity type
102 epitaxial region 114 of a first conductivity type and a first insulating dielectric isolation layer
103 well region 115 of the second conductivity type, a second insulating dielectric isolation layer
104 first source regions 116 of a first conductivity type third mask
105 first mask 117 first contact hole portion
106 groove 118 second contact hole portion
107 shield region 119 of the second conductivity type a first contact region of the second conductivity type
108 second mask 120 second contact regions of the second conductivity type
109 sidewalls 121 source metal regions
110 implantation window 122 drain metal region
111 second source region of the first conductivity type
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
As described above, in the trench gate semiconductor device, the P-type (or N-type) shielding region is formed at the bottom of the trench, so that an electric field can be effectively shielded to reduce the intensity of the electric field in the gate dielectric, thereby improving the long-term reliability of the product. However, the introduced P-type (or N-type) shielding region and the P-type (or N-type) base region form a JFET structure, so that the on-resistance of the device is increased. The inventors contemplate that the channel density of the device may be increased by providing a channel in the P-type (or N-type) shield region, thereby reducing the on-resistance of the device.
In the present disclosure, the use of directional terms such as "upper and lower" generally refers to the direction of a semiconductor device during its manufacture, unless otherwise specified.
Fig. 1 is a schematic structural diagram of a trench gate semiconductor device according to an exemplary embodiment. As shown in fig. 1, the trench-gate semiconductor device may include, from bottom to top, a drain metal region 122, a substrate region 101 of a first conductivity type, an epitaxial region 102 of the first conductivity type, an active region 100, and a source metal region 121 in that order. Wherein the active region 100 includes a shielding region 107 of the second conductivity type at the bottom of the trench, and a channel is disposed in the shielding region 107 of the second conductivity type.
Generally, the channel of the trench gate semiconductor device is not arranged in the bottom of the trench, and through the technical scheme, the channel is also formed in the shielding region of the second conduction type at the bottom of the trench gate semiconductor device, so that a conduction channel can be increased, the channel density of the device is improved, and the on-resistance of the trench gate semiconductor device is effectively reduced.
It will be understood by those skilled in the art that the first and second conductivity types may be P-type and N-type, respectively, or may also be N-type and P-type, respectively.
Fig. 2 is a schematic structural diagram of a trench-gate semiconductor device according to another exemplary embodiment. As shown in fig. 2, the active region 100 may include a first source region 104 of the first conductivity type, a first contact region 119 of the second conductivity type, a well region 103 of the second conductivity type, an insulating gate dielectric layer 112, and a gate electrode 113.
Specifically, the first source region 104 of the first conductivity type and the first contact region 119 of the second conductivity type are both formed on the well region 103 of the second conductivity type. The well region 103 of the second conductive type is formed on the epitaxial region 102 of the first conductive type, and the first source region 104 of the first conductive type and the first contact region 119 of the second conductive type may be contacted or not contacted. A first contact region 119 of the second conductivity type is formed on the well region 103 of the second conductivity type. A first source region 104 of the first conductivity type is formed on the well region 103 of the second conductivity type.
In one unit cell shown in fig. 2, a first contact region 119 of the second conductivity type is formed on an outer edge of the well region 103 of the second conductivity type. It will be understood by those skilled in the art that in an actual device, the unit cells are repeatedly arranged laterally, and thus, the first contact region 119 of the second conductive type is formed in the middle of the well region 103 of the second conductive type.
The insulated gate dielectric layer 112 is located on the inner wall of the trench, the insulated gate dielectric layer 112 is in contact with the first source region 104 of the first conductivity type and the well region 103 of the second conductivity type, respectively, and the gate 113 covers the insulated gate dielectric layer 112 on the inner wall of the trench 106.
In addition, the active region 100 may further include a second source region 111 of the first conductivity type and a second contact region 120 of the second conductivity type disposed at the bottom of the trench for forming a channel in the shield region 107 of the second conductivity type. Wherein the second source region 111 of the first conductivity type is located between the insulated gate dielectric layer 112 and the shielding region 107 of the second conductivity type, such that the insulated gate dielectric layer 112 is partially in contact with the shielding region 107 of the second conductivity type.
In this way, a new channel at the bottom of the trench-gate semiconductor device can be formed by the second source region 111 of the first conductivity type, the insulated gate dielectric layer 112 and the shield region 107 of the second conductivity type.
In fig. 2, the trench gate semiconductor device may further include a first insulating dielectric isolation layer 114 and a second insulating dielectric isolation layer 115. First insulating dielectric spacers 114 flank the trench for isolating the source metal region 121 from the gate 113 from the sidewall ends. The second insulating dielectric isolation layer 115 serves to isolate the source metal region 121 from the gate electrode 113 from the upper end.
In another embodiment, the trench in the shielding region 107 of the second conductivity type is prepared by a self-aligned process, which can effectively avoid the problem of trench length fluctuation caused by photolithography offset, thereby greatly reducing the trench length to save the cell size, avoiding the waste of wafer area, and avoiding device performance fluctuation caused by the trench length fluctuation, such as on-resistance fluctuation, threshold fluctuation, and short-circuit capability fluctuation.
Generally, an increase in channel density increases the short circuit current of the device. In this regard, the saturation current of the channel can be reduced. Therefore, it is possible to reasonably increase the length of the second conductive-type screening-region channel (for example, more than 0.1 μm), or increase the doping concentration of the channel surface to increase the threshold voltage, thereby reducing the saturation current of the second conductive-type screening-region channel so that the short-circuit current of the device is reduced.
To achieve an effective shielding effect, the shielding region of the second conductivity type may have a higher doping concentration (e.g. 10)14cm-3～1019cm-3) This also contributes to reducing the short-circuit current of the device. The self-alignment process is adopted, so that not only can the length of the channel be accurately controlled, but also the length of the channel in the shielding region can be reasonably adjusted, and therefore the saturation current can be adjusted.
The present disclosure also provides a method of manufacturing a trench gate semiconductor device. Fig. 3 is a flowchart of a method for manufacturing a trench-gate semiconductor device according to an exemplary embodiment. As shown in fig. 3, the method may include the following steps.
In step S301, an epitaxial region 102 of the first conductivity type is formed on a substrate region 101 of the first conductivity type.
Step S302, an active region 100 is formed on the epitaxial region 102 of the first conductivity type, wherein the active region 100 includes a shielding region 107 of the second conductivity type located at the bottom of the trench 106, and a channel is disposed in the shielding region 107 of the second conductivity type.
In step S303, a source metal region 121 is formed on the active region 100.
In step S304, a drain metal region 122 is formed under the substrate region 101 of the first conductivity type.
According to the technical scheme, the channel is also formed in the shielding region of the second conduction type at the bottom of the groove gate semiconductor device, so that a conduction channel can be increased, the channel density of the device is improved, and the on-resistance of the groove gate semiconductor device is effectively reduced.
Fig. 4 a-4 p are schematic diagrams of a process for fabricating a trench-gate semiconductor device according to an example embodiment. In this embodiment, the following steps may be included:
1. a wafer is provided that is adapted to the parameters of the substrate 101 (e.g., SiC) of the substrate region of the first conductivity type and the epitaxial region 102 of the first conductivity type, as shown in fig. 4 a. The parameters of the epitaxial region 102 of the first conductivity type are related to the voltage withstand requirements of the device. Generally, the higher the withstand voltage requirement, the lower the doping concentration of the epitaxial region 102 of the first conductivity type, and the thicker the thickness. The doping concentration of the epitaxial region 102 of the first conductivity type may be at 1013cm-3～1017cm-3The thickness may be greater than 6 μm.
2. The well region 103 of the second conductivity type is formed by implantation as shown in fig. 4 b. The concentration of the well region 103 of the second conductivity type may be 1014cm-3～1018cm-3The thickness may be greater than 0.5 μm.
3. A first source region 104 of the first conductivity type is formed by implantation as shown in fig. 4 c. The concentration of the first source region 104 of the first conductivity type may be at 1018cm-3～1021cm-3The thickness may be greater than or equal to 0.2 μm.
4. A first mask 105 is formed by photolithography and dry etching, and a trench 106 is formed in the epitaxial region 102 of the first conductivity type by dry etching, the bottom of the trench 106 exceeding the well region 103, as shown in fig. 4 d. The first mask 105 may be silicon dioxide or silicon nitride and may have a thickness of 0.1 μm to 3 μm. The trench 106 may be greater than 0.5 μm deep and greater than 0.5 μm wide.
5. A screening region 107 of the second conductivity type is formed at the bottom of the trench 106 by implantation, as shown in fig. 4 e. The doping concentration of the shielding region 107 of the second conductivity type may be higher than the well region 103 of the second conductivity type and may be at 1014cm-3～1019cm-3The thickness may be greater than 0.5 μm. The surface concentration can be adjusted to adjust the threshold voltage of the channel here, thereby adjusting the saturation current.
6. A second mask 108 is deposited covering the substrate surface, as well as the bottom and inner walls of the trench 106, as shown in fig. 4 f. The second mask 108 may be silicon dioxide or silicon nitride and may be thicker than 0.1 μm.
7. The second mask 108 is dry etched to form sidewalls 109 and implantation windows 110, and then second source regions 111 of the first conductivity type are formed in the implantation windows 110 by implantation, as shown in fig. 4g, followed by removal of the sidewalls 109 and the first mask 105. I.e. a self-aligned process is used to prepare the trenches in the screening region 107 of the second conductivity type. The width of the sidewalls 109 determines the length of the channel, which may be greater than 0.1 μm. The concentration of the first conductive type second source region 111 may be at 1018cm-3～1021cm-3The thickness may be greater than or equal to 0.2 μm. The width of the sidewalls 109 can be adjusted to adjust the length of the channel therein, thereby adjusting the saturation current.
8. An insulated gate dielectric layer 112 is formed on the second source region 111 of the first conductivity type, the shielding region 107 of the second conductivity type, the inner wall of the trench 106 and the first source region 104 of the first conductivity type, but does not fill the trench, as shown in fig. 4 h. The insulated gate dielectric layer 112 may be silicon dioxide, and the forming method may be thermal oxidation, or chemical vapor deposition or atomic layer deposition, and the thickness may be greater than 0.01 μm.
9. And depositing a polysilicon layer to cover the surface, the bottom and the inner wall of the insulated gate dielectric layer 112, but not to fill the trench, as shown in fig. 4 i. The polysilicon is typically heavily doped and may have a sheet resistance of less than 100 ohms per square.
10. The polysilicon layer is etched to remove the polysilicon above the first source region 104 of the first conductivity type and at the bottom of the trench to form a gate 113, as shown in fig. 4 j. The width of the gate 113 should completely cover the length of the channel in the shielding region 107 of the second conductivity type, and the length of the channel in the shielding region 107 of the second conductivity type may be greater than 0.1 μm.
11. A first insulating dielectric isolation layer 114 is deposited as shown in fig. 4 k. The first insulating dielectric isolation layer 114 may be silicon dioxide or silicon nitride. The first insulating dielectric isolation layer 114 needs to completely fill the trench.
12. The insulating gate dielectric layer 112, the polysilicon layer, and the first insulating dielectric isolation layer 114 are removed and planarized as shown in fig. 4 l. The method may employ chemical mechanical polishing.
13. A second insulating dielectric isolation layer 115 is deposited as shown in fig. 4 m. The second insulating dielectric isolation layer 115 may be silicon dioxide or silicon nitride and may have a thickness of 0.1 μm to 3 μm.
14. A mask is deposited and a third mask 116 is formed by photolithography and dry etching, then the second insulating dielectric isolation layer 115 and the first insulating dielectric isolation layer 114 are dry etched and etching is continued to remove the exposed first source region 104 of the first conductivity type, forming a first contact hole portion 117, removing the exposed second source region 111 of the first conductivity type, forming a second contact hole portion 118. A first contact region 119 of the second conductivity type is then formed by implantation in the first contact hole portion 117 and a second contact region 120 of the second conductivity type is implanted in the second contact hole portion 118, as shown in fig. 4 n. The third mask 116 may typically be silicon dioxide or silicon nitride and may be 0.1 μm to 3 μm thick. The concentration of the first contact region 119 of the second conductivity type and the second contact region 120 of the second conductivity type may be at 1018cm-3～1021cm-3The thickness may be greater than 0.2 μm. The widths of the first contact hole portion 117 and the second contact hole portion 118 may be greater than 0.1 μm.
15. A source metal region 121 of the front side is deposited over the second insulating dielectric isolation layer 115 and the first contact region 119 of the second conductivity type and fills the trench as shown in fig. 4 o. The source metal region 121 may be aluminum and have a thickness of about 4 μm.
16. A back side drain metal region 122 is deposited as shown in fig. 4 p. The drain metal region 122 may be aluminum and may have a thickness of about 4 μm.
In an embodiment, on the basis of fig. 3, forming the active region 100 on the epitaxial region 102 of the first conductivity type (step S302) may include the steps of:
sequentially forming a well region 103 of a second conductivity type and a first source region 104 of a first conductivity type on the epitaxial region 102 of the first conductivity type;
depositing a first mask 105 on the first source region 104 of the first conductivity type, and etching to form a trench 106;
forming a screening region 107 of the second conductivity type in the trench 106, followed by depositing a second mask 108, the second mask 108 covering the bottom and the inner walls of the trench 106;
etching the second mask 108 to form sidewalls 109, and then forming second source regions 111 of the first conductivity type at the bottom of the trenches 106, preparing trenches in the screening regions 107 of the second conductivity type in a self-aligned process, and subsequently removing the first mask 105 and the sidewalls 109;
forming an insulated gate dielectric layer 112 covering the bottom and the inner wall of the groove;
forming a gate 113 on the inner wall of the trench 106;
depositing a first insulating medium isolation layer 114, wherein the first insulating medium isolation layer 114 completely fills the trench 106;
polishing is performed to expose the source region 104 of the first conductivity type;
depositing a second insulating dielectric isolation layer 115 and a third mask 116 in sequence and etching to remove the exposed first source region 104 of the first conductivity type to form first contact hole portions 117 and to remove the exposed second source region 111 of the first conductivity type to form second contact hole portions 118;
a first contact region 119 of the second conductivity type is formed at the first contact hole portion 117, and a second contact region 120 of the second conductivity type is formed at the second contact hole portion 118.
The step of forming the gate electrode 113 on the inner wall of the trench may include: depositing polysilicon on the bottom and inner wall of the trench 106; the polysilicon is etched to remove the polysilicon at the bottom of the trench 106 and form a gate 113 on the inner wall of the trench 106.
Through the technical scheme, the channel is also formed in the shielding region of the second conduction type at the bottom of the groove gate semiconductor device, so that the conduction channel can be increased, the channel density of the device is improved, and the on-resistance of the groove gate semiconductor device is effectively reduced.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (10)
1. The trench gate semiconductor device is characterized by sequentially comprising a drain metal region (122), a substrate region (101) of a first conductivity type, an epitaxial region (102) of the first conductivity type, an active region (100) and a source metal region (121) from bottom to top, wherein the active region (100) comprises a shielding region (107) of a second conductivity type positioned at the bottom of a trench (106), and a channel is arranged in the shielding region (107) of the second conductivity type.
2. The trench-gate semiconductor device according to claim 1, wherein the active region (100) comprises a first source region (104) of a first conductivity type, a first contact region (119) of a second conductivity type, a well region (103) of a second conductivity type, an insulated gate dielectric layer (112) and a gate electrode (113), wherein the well region (103) of the second conductivity type is formed on the epitaxial region (102) of the first conductivity type, the insulated gate dielectric layer (112) is located on an inner wall of the trench (106), the insulated gate dielectric layer (112) is in contact with the first source region (104) of the first conductivity type and the well region (103) of the second conductivity type, respectively, the gate electrode (113) covers the insulated gate dielectric layer (112) on the inner wall of the trench (106), the first contact region (119) of the second conductivity type is formed on the well region (103) of the second conductivity type, a first source region (104) of the first conductivity type is formed on the well region (103) of the second conductivity type,
the active region (100) further comprises a second source region (111) of the first conductivity type and a second contact region (120) of the second conductivity type arranged at the bottom of the trench (106) for forming a channel in the shielding region (107) of the second conductivity type, wherein the second source region (111) of the first conductivity type is located between the insulating gate dielectric layer (112) and the shielding region (107) of the second conductivity type such that the insulating gate dielectric layer (112) is partially in contact with the shielding region (107) of the second conductivity type.
3. The trench-gate semiconductor device according to claim 1, wherein the channel in the screening region (107) of the second conductivity type is prepared using a self-aligned process.
4. The trench-gate semiconductor device according to claim 1, wherein the screening region (107) of the second conductivity type has a doping concentration of 1014cm-3～1019cm-3。
5. The trench-gate semiconductor device of claim 1, wherein the length of the channel is greater than 0.1 μm.
6. A method of manufacturing a trench-gate semiconductor device, the method comprising:
forming an epitaxial region (102) of a first conductivity type on a substrate region (101) of the first conductivity type;
forming an active region (100) on the epitaxial region (102) of the first conductivity type, wherein the active region (100) comprises a screening region (107) of the second conductivity type at the bottom of a trench (106), a trench being provided in the screening region (107) of the second conductivity type;
forming a source metal region (121) on the active region (100);
a drain metal region (122) is formed under the substrate region (101) of the first conductivity type.
7. The method of claim 6, wherein forming an active region (100) on the epitaxial region (102) of the first conductivity type comprises:
forming a well region (103) of a second conductivity type and a first source region (104) of a first conductivity type in sequence on the epitaxial region (102) of the first conductivity type;
depositing a first mask (105) on a first source region (104) of the first conductivity type and etching to form the trench (106);
-forming a screening region (107) of said second conductivity type in said trench (106), followed by depositing a second mask (108), said second mask (108) covering the bottom and inner walls of said trench (106);
-etching said second mask (108) to form sidewalls (109), followed by forming second source regions (111) of the first conductivity type at the bottom of said trenches (106), preparing trenches in said screening regions (107) of the second conductivity type in a self-aligned process, followed by removing said first mask (105) and said sidewalls (109);
forming an insulated gate dielectric layer (112) covering the bottom and the inner wall of the groove (106);
forming a gate (113) on the inner wall of the trench (106);
depositing a first insulating medium isolation layer (114), wherein the first insulating medium isolation layer (114) completely fills the groove (106);
polishing to expose the source region (104) of the first conductivity type;
sequentially depositing a second insulating dielectric isolation layer (115) and a third mask (116) and etching to remove the exposed first source region (104) of the first conductivity type to form a first contact hole portion (117) and to remove the exposed second source region (111) of the first conductivity type to form a second contact hole portion (118);
a first contact region (119) of a second conductivity type is formed at the first contact hole portion (117) and a second contact region (120) of the second conductivity type is formed at the second contact hole portion (118).
8. The method of claim 7, wherein forming a gate (113) on an inner wall of the trench (106) comprises:
depositing polysilicon on the bottom and inner wall of the trench (106);
and etching the polysilicon to remove the polysilicon at the bottom of the trench (106), and forming the gate (113) on the inner wall of the trench (106).
9. Method according to claim 6, characterized in that the screening region (107) of the second conductivity type has a doping concentration of 1014cm-3～1019cm-3。
10. The method of claim 6, wherein the length of the channel is greater than 0.1 μm.
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