CN116666444A - SGT device and method of making same - Google Patents

SGT device and method of making same Download PDF

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Publication number
CN116666444A
CN116666444A CN202310736657.3A CN202310736657A CN116666444A CN 116666444 A CN116666444 A CN 116666444A CN 202310736657 A CN202310736657 A CN 202310736657A CN 116666444 A CN116666444 A CN 116666444A
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layer
forming
epitaxial
layers
substrate
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李敦然
彭运文
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Suzhou Huatai Electronics Co Ltd
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Suzhou Huatai Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a preparation method of an SGT device and the SGT device. The method comprises the following steps: firstly, providing a substrate comprising a substrate, a first epitaxial layer and a preparation oxide layer which are sequentially laminated; then, removing part of the preliminary oxide layers, forming first oxide layers arranged at intervals by the rest of the preliminary oxide layers, and forming a plurality of first grooves arranged at intervals between the adjacent first oxide layers, wherein part of the first epitaxial layers are exposed by the first grooves; then, forming a second epitaxial layer in each first groove; then, removing part of the second epitaxial layer and part of the first epitaxial layer at the bottom of the second epitaxial layer to obtain a plurality of second grooves which are arranged at intervals, wherein part of the side wall of each second groove exposes part of the first oxide layer; finally, a gate structure is formed in at least each of the second trenches to obtain an SGT device. The first oxide layer depletes the second epitaxial layer during operation of the SGT, thereby reducing parasitic capacitance of the SGT device and ensuring better performance of the SGT device.

Description

SGT device and method of making same
Technical Field
The application relates to the field of semiconductors, in particular to a preparation method of an SGT device and the SGT device.
Background
The Drain terminal Drain and Source terminal Source of the existing LDMOS (Laterally Diffused Metal Oxide Semiconductor ) are all routed by multilayer metal layers, parasitic capacitance exists between the metal wires of the Drain terminal and the field plate as well as between the metal wires of the Source terminal, and compared with the existing LDMOS device, the existing SGT (Shield Gate Trench, shielded gate trench) device has the advantage of better circuit parameters.
However, current SGT devices also suffer from the following problems: first, because the horizontal spacing of the cells of the vertical SGT device is smaller, the SGT has poor heat dissipation capacity; second, because the medium between the SGT device cells is heavily doped silicon of the channel or drift region, the SGT device is hard to run out, and parasitic capacitance exists in the depletion layer, which ultimately affects the performance of the SGT device.
Disclosure of Invention
The application mainly aims to provide a preparation method of an SGT device and the SGT device, so as to solve the problem that the SGT device in the prior art is poor in performance due to parasitic capacitance.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of manufacturing an SGT device, the method including: providing a substrate, wherein the substrate comprises a substrate, a first epitaxial layer and a preparation oxide layer which are sequentially laminated; removing part of the preparation oxidation layer to form a plurality of first grooves which are arranged at intervals, wherein part of the first epitaxial layer is exposed by the first grooves, and the rest of the preparation oxidation layer forms a first oxidation layer; forming a second epitaxial layer in each first groove; removing part of the second epitaxial layer and part of the first epitaxial layer to form a plurality of second grooves which are arranged at intervals, wherein part of the first oxide layer is exposed by the side wall of each second groove, part of the first epitaxial layer is exposed by the bottom of each second groove, the rest of the first epitaxial layer forms a first target epitaxial layer, and the rest of the second epitaxial layer forms a second target epitaxial layer; a gate structure is formed in at least each of the second trenches to obtain an SGT device.
Optionally, a portion of the plurality of second epitaxial layers is a first sub-epitaxial layer, a portion of the plurality of second epitaxial layers is a second sub-epitaxial layer, the plurality of second sub-epitaxial layers are located on two sides of the plurality of first sub-epitaxial layers, and a portion of the second epitaxial layers and a portion of the first epitaxial layers are removed to form a plurality of second trenches disposed at intervals, including: and removing part of the second sub-epitaxial layer and part of the first epitaxial layer to form a plurality of second grooves which are arranged at intervals.
Optionally, forming a gate structure at least in each of the second trenches includes: forming a shielding gate oxide layer on the bottom and part of the side wall surface of the second groove, forming a first gate in the rest part of the second groove, wherein the thickness of the first gate is smaller than the depth of the second groove, and forming a third groove by the second groove with the first gate; forming a gate oxide layer on the side wall of the third groove, and forming a second oxide layer and a second gate which are stacked on the surface, far away from the substrate, of the first gate, wherein the shielding gate oxide layer, the first gate, the second oxide layer and the second gate form the gate structure; forming a plurality of body regions and a plurality of source regions in a part of the second target epitaxial layer, wherein each source region is positioned in the corresponding body region; and forming a plurality of extraction structures, wherein each extraction structure is used for extracting each source region, and the extraction structures are in one-to-one correspondence with the source regions.
Optionally, forming a shielding gate oxide layer on the bottom and part of the sidewall surface of the second trench, and forming a first gate in the remaining part of the second trench, including: forming a preliminary shielding gate oxide layer on the exposed surface of the second trench, the surface of the first oxide layer away from the substrate, and the surface of the second target epitaxial layer away from the substrate; forming the first grid electrode in the rest part of the second grooves, and forming the third grooves by the rest part of the second grooves; and removing part of the preparation shielding gate oxide layer, exposing part of the first oxide layer and part of the second target epitaxial layer by the side wall of the third groove, exposing the surface of the first oxide layer, which is far away from the substrate, and the surface of the second target epitaxial layer, which is far away from the substrate, and forming the shielding gate oxide layer by the rest of the preparation shielding gate oxide layer.
Optionally, forming a gate oxide layer on a sidewall of the third trench, and forming a stacked second oxide layer and a second gate on a surface of the first gate remote from the substrate, including: forming a preliminary gate oxide layer on the exposed surface of the third trench, the surface of the first oxide layer away from the substrate, and the surface of the second target epitaxial layer away from the substrate; forming the second grid electrode in the rest third grooves; and removing part of the preliminary gate oxide layer, so that the surface of the first oxide layer, which is far away from the substrate, and the surface of the second target epitaxial layer, which is far away from the substrate, are exposed, and the rest of the preliminary gate oxide layer forms the gate oxide layer and the second oxide layer.
Optionally, forming a plurality of body regions and a plurality of source regions in a portion of the second target epitaxial layer includes: performing ion implantation on each second sub-epitaxial layer to enable part of the second sub-epitaxial layers to form the body region; and carrying out ion implantation on part of the body region to obtain the source region.
Optionally, forming a plurality of extraction structures includes: forming a first preparation medium layer on the surface of the second grid electrode, which is far away from the substrate, the surface of the first oxide layer, which is far away from the substrate, and the surface of the second target epitaxial layer, which is far away from the substrate; removing part of the first preparation medium layer, part of the source region and part of the body region to form a plurality of fourth grooves, wherein each fourth groove penetrates through the first preparation medium layer, the source region and the body region, and the rest of the first preparation medium layer forms a first medium layer; forming a first connection layer in each fourth groove; forming a plurality of first metal layers, a plurality of second connection layers and a plurality of second metal layers, wherein each first metal layer is located on one side, away from the substrate, of a corresponding first connection layer, each first metal layer is in contact with a corresponding first connection layer, each second connection layer is located on a part of the surface, away from the first connection layer, of a corresponding first metal layer, each second metal layer is located on one side, away from the first metal layer, of a corresponding second connection layer, each second metal layer is in contact with a corresponding second connection layer, and the first connection layer, the first metal layer, the second connection layer and the second metal layer form the extraction structure.
Optionally, forming a plurality of first metal layers, a plurality of second connection layers, and a plurality of second metal layers includes: forming a first preparation metal layer on the first dielectric layer and the surface of the first connection layer, which is far away from the substrate; removing part of the first preparation metal layer, forming a plurality of first metal layers by the rest of the first preparation metal layers, wherein each first metal layer covers part of the surface of the first dielectric layer, which is far away from the substrate, and each first metal layer covers the surface of the corresponding first connection layer, which is far away from the substrate; forming a second preparation medium layer on the first metal layer and the exposed surface of the first medium layer; removing part of the second preparation medium layer to form a plurality of fifth grooves, wherein each fifth groove exposes a corresponding part of the first metal layer, and the rest of the second preparation medium layer forms a second medium layer; forming a second connection layer in each fifth groove, forming a second preparation metal layer on the surfaces of the second connection layer and the second medium layer, which are far away from the substrate, removing part of the second preparation metal layer, obtaining a plurality of second metal layers by the rest of the second preparation metal layer, wherein each second metal layer covers part of the surface of the second medium layer, which is far away from the substrate, and each second metal layer covers the surface of the second connection layer, which is far away from the substrate.
Optionally, the material of the first oxide layer includes silicon dioxide.
According to another aspect of the present application, there is provided an SGT device including a substrate, a first target epitaxial layer, a plurality of first oxide layers, a plurality of second target epitaxial layers, and a plurality of gate structures, wherein the first target epitaxial layer is located on a surface of the substrate; the first oxide layers are arranged at intervals, the second target epitaxial layer is positioned between two adjacent first oxide layers, and a plurality of second grooves are formed between the first oxide layers and the second target epitaxial layer; the gate structures are respectively located in the second trenches, and two sides of the gate structures are respectively contacted with the first oxide layer and the second target epitaxial layer.
In the technical scheme of the application, in the preparation method of the SGT device, firstly, a substrate comprising a substrate, a first epitaxial layer and a preparation oxide layer which are sequentially laminated is provided; then, removing part of the preparation oxide layer, forming first oxide layers arranged at intervals by the rest preparation oxide layers, and forming a plurality of first grooves arranged at intervals between the adjacent first oxide layers, wherein part of the first epitaxial layers are exposed by the first grooves; then, forming a second epitaxial layer in each first groove; then, removing part of the second epitaxial layer and part of the first epitaxial layer at the bottom of the second epitaxial layer to obtain a plurality of second grooves which are arranged at intervals, wherein part of the side wall of each second groove exposes part of the first oxide layer, part of the first epitaxial layer is exposed at the bottom of each second groove, the rest of the first epitaxial layer forms a first target epitaxial layer, and the rest of the second epitaxial layer forms a second target epitaxial layer; finally, a gate structure is formed in at least each of the second trenches to obtain an SGT device. Compared with the prior art, the SGT device has the problem of poor performance caused by parasitic capacitance, the preparation method of the SGT device of the application has the advantages that the substrate comprises the substrate, the first epitaxial layers and the preparation oxide layers which are stacked, the first grooves are formed among the preparation oxide layers at intervals, the second epitaxial layers are formed in the first grooves, the first oxide layers are arranged among the second epitaxial layers, namely, the isolation of the second epitaxial layers through the first oxide layers is realized, the resistance of the SGT device can be improved through the first oxide layers at intervals, namely, a high-resistance region can be formed, and the high-resistance region can exhaust the second epitaxial layers when the SGT works, so that the parasitic capacitance of the SGT device is reduced, the problem that the parasitic capacitance of the SGT device in the prior art is difficult to exhaust when the epitaxial layers work due to the fact that the oxide layers are not arranged is avoided, the problem that the parasitic capacitance of the SGT device in the prior art is poor in performance caused by the fact that the parasitic capacitance of the SGT device is poor is guaranteed is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
FIG. 1 shows a schematic flow diagram of a method of fabricating an SGT device according to an embodiment of the present application;
FIG. 2 shows a schematic structural view of a substrate according to one embodiment of the application;
FIG. 3 shows a schematic diagram of a structure obtained after forming a first trench according to an embodiment of the present application;
fig. 4 shows a schematic structural diagram obtained after forming a second epitaxial layer according to one embodiment of the present application;
FIG. 5 shows a schematic diagram of a structure obtained after forming a second trench according to an embodiment of the present application;
fig. 6 shows a schematic structural diagram obtained after forming a preliminary shield gate oxide layer according to an embodiment of the present application;
fig. 7 shows a schematic structural diagram obtained after forming a first gate according to an embodiment of the present application;
fig. 8 shows a schematic structural diagram obtained after forming a shield gate oxide layer according to an embodiment of the present application;
fig. 9 shows a schematic structural diagram obtained after forming a pre-gate oxide layer according to an embodiment of the present application;
Fig. 10 shows a schematic structural diagram obtained after forming a second gate according to an embodiment of the present application;
fig. 11 shows a schematic structural diagram obtained after forming a gate oxide layer and a second oxide layer according to an embodiment of the present application;
FIG. 12 shows a schematic structure obtained after formation of body and source regions according to an embodiment of the present application;
FIG. 13 is a schematic diagram showing a structure obtained after forming a first preliminary dielectric layer according to an embodiment of the present application;
fig. 14 shows a schematic structural view obtained after forming a fourth trench according to an embodiment of the present application;
fig. 15 shows a schematic structural view obtained after forming a first connection layer according to an embodiment of the present application;
fig. 16 shows a schematic structural view obtained after forming a first preliminary metal layer according to an embodiment of the present application;
FIG. 17 shows a schematic diagram of a structure obtained after forming a first metal layer according to an embodiment of the present application;
FIG. 18 shows a schematic diagram of a structure obtained after forming a second preliminary dielectric layer according to an embodiment of the present application;
fig. 19 shows a schematic structural view obtained after forming a fifth trench according to an embodiment of the present application;
Fig. 20 shows a schematic structural diagram obtained after forming a second preliminary metal layer according to an embodiment of the present application;
FIG. 21 illustrates a schematic diagram of an SGT device according to an embodiment of the present application;
FIG. 22 illustrates a schematic diagram of an SGT device according to another embodiment of the present application;
FIG. 23 shows a schematic structural diagram of an SGT device according to yet another embodiment of the present application;
FIG. 24 illustrates a schematic top-down structure of an SGT device according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a substrate; 20. a first trench; 30. a second epitaxial layer; 40. a second trench; 50. a second target epitaxial layer; 60. a shielding gate oxide layer; 70. a first gate; 80. a third trench; 90. a gate oxide layer; 100. a second oxide layer; 101. a substrate; 102. a first epitaxial layer; 103. preparing an oxide layer; 104. a first oxide layer; 105. a first target epitaxial layer; 110. a second gate; 120. a body region; 130. a source region; 140. preparing a shielding gate oxide layer; 150. preparing a gate oxide layer; 160. a first preliminary dielectric layer; 170. a fourth trench; 180. a first dielectric layer; 190. a first connection layer; 200. a first metal layer; 210. a second connection layer; 220. a second metal layer; 230. a first preliminary metal layer; 240. a second preliminary dielectric layer; 250. a fifth groove; 260. a second dielectric layer; 270. a second preliminary metal layer; 280. a third connection layer; 290. a third metal layer; 300. a fourth connection layer; 301. a first sub-epitaxial layer; 302. a second sub-epitaxial layer; 310. a fourth metal layer; 320. a fifth connection layer; 330. a fifth metal layer; 340. a sixth connection layer; 350. and a sixth metal layer.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the SGT device in the prior art has poor performance due to parasitic capacitance, and in order to solve the above problems, embodiments of the present application provide a preparation method of an SGT device and an SGT device.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
FIG. 1 is a flow chart of a method of fabricating an SGT device according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, as shown in fig. 2, providing a base 10, wherein the base 10 includes a substrate 101, a first epitaxial layer 102, and a preliminary oxide layer 103 stacked in this order;
specifically, the thickness of the preliminary oxide layer ranges from 1 micron to 2 microns, and the doping types of the substrate and the first epitaxial layer are the same.
Step S102, as shown in fig. 2 to 3, removing a portion of the preliminary oxide layer 103 to form a plurality of first trenches 20 disposed at intervals, where the first trenches 20 expose a portion of the first epitaxial layer 102, and the remaining preliminary oxide layer 103 forms a first oxide layer 104;
specifically, the width of the bottom of the first groove ranges from 1 micron to 2 microns, the length of the bottom of the first groove ranges from 100 microns to 400 microns, the depth of the first groove ranges from 1 micron to 2 microns, and the sizes of the plurality of first grooves can be different.
Step S103, as shown in fig. 3 to 4, forming a second epitaxial layer 30 in each of the first trenches 20;
specifically, the second epitaxial layer is grown by selective epitaxy.
Step S104, as shown in fig. 4 to 5, removing a portion of the second epitaxial layer 30 and a portion of the first epitaxial layer 102 to form a plurality of second trenches 40 disposed at intervals, wherein a sidewall of each of the second trenches 40 exposes a portion of the first oxide layer 104, a bottom of each of the second trenches 40 exposes a portion of the first epitaxial layer 102, the remaining first epitaxial layer 102 forms a first target epitaxial layer 105, and the remaining second epitaxial layer 30 forms a second target epitaxial layer 50;
specifically, a portion of the sidewall of each second trench exposes the second epitaxial layer, and a portion of the sidewall of each second trench exposes the first oxide layer, i.e., one side of the second trench is the first oxide layer, and the other side of the second trench is the remaining second epitaxial layer.
In step S105, a gate structure is formed at least in each of the second trenches, so as to obtain an SGT device, and a structure as shown in fig. 21 is obtained.
In the above-mentioned SGT device preparation method, first, provide the substrate comprising substrate, first epitaxial layer and preparation oxide layer that stacks sequentially; then, removing part of the preparation oxidation layer, forming first oxidation layers arranged at intervals by the rest preparation oxidation layers, and forming a plurality of first grooves arranged at intervals between the adjacent first oxidation layers, wherein part of the first epitaxial layers are exposed by the first grooves; then, forming a second epitaxial layer in each first groove; then, removing part of the second epitaxial layer and part of the first epitaxial layer at the bottom of the second epitaxial layer to obtain a plurality of second grooves which are arranged at intervals, wherein part of the side wall of each second groove exposes part of the first oxide layer, part of the first epitaxial layer is exposed at the bottom of each second groove, the rest of the first epitaxial layer forms a first target epitaxial layer, and the rest of the second epitaxial layer forms a second target epitaxial layer; finally, a gate structure is formed in at least each of the second trenches to obtain an SGT device. Compared with the prior art, the preparation method of the SGT device has the problem of poor performance caused by parasitic capacitance, because the substrate comprises the substrate, the first epitaxial layers and the preparation oxide layers which are stacked, and the first trenches which are arranged at intervals are formed among the preparation oxide layers, and the second epitaxial layers are formed in the first trenches, the first oxide layers exist among the second epitaxial layers, namely the isolation of the second epitaxial layers through the first oxide layers is realized, the resistance of the SGT device can be improved through the first oxide layers at intervals, namely a high-resistance region can be formed, and the second epitaxial layers can be exhausted when the SGT works, so that the parasitic capacitance of the SGT device is reduced, the problem that the parasitic capacitance of the SGT device in the prior art is difficult to exhaust when the epitaxial layers work due to the fact that the oxide layers are not arranged is avoided, and the parasitic capacitance of the SGT device in the prior art is poor in performance caused by the fact that the parasitic capacitance of the SGT device exists is guaranteed.
In the implementation process, because the medium between the cells of the SGT device in the prior art is the heavily doped Si of the channel or the drift region, namely the epitaxial layer, the SGT device in the prior art is difficult to deplete in operation, so that the depletion layer capacitor exists, and the problem of influencing the device performance is solved.
In addition, compared to LDMOS devices in the prior art, the existing SGT device has better circuit parameters, for example, a 12V LDMOS typically has an rdson×coss value of 1.75 and an SGT of 0.56, where rdson×coss represents the energy required for switching the switch when the voltage from the drain to the source is 1V when the device is in operation, rdson represents the on-resistance, coss represents the output capacitance, and thus rdson×coss can be used to evaluate the power consumption and heat that the device needs to handle when operating up to voltage/frequency. However, since the horizontal spacing between the cells of the SGT device in the prior art is smaller, the heat dissipation capability of the SGT device in the prior art is poor, and since the first oxide layers are disposed between the second epitaxial layers, the distance between the gate structures formed in the second epitaxial layers is longer, thereby ensuring that the spacing between the cells in the SGT device is larger, thereby ensuring that the heat dissipation capability of the SGT device is stronger, and solving the problem of the poor heat dissipation capability of the SGT device in the prior art.
In the specific implementation process, as shown in fig. 4, a portion of the plurality of second epitaxial layers 30 is a first sub-epitaxial layer 301, a portion of the plurality of second epitaxial layers 30 is a second sub-epitaxial layer 302, the plurality of second sub-epitaxial layers 302 are located at two sides of the plurality of first sub-epitaxial layers 301, and a portion of the second epitaxial layers and a portion of the first epitaxial layers are removed to form a plurality of second trenches disposed at intervals, including: as shown in fig. 4 to 5, a portion of the second sub-epitaxial layer 302 and a portion of the first epitaxial layer 102 are removed, so as to form a plurality of second trenches 40 disposed at intervals. Because the parts of the second epitaxial layers are the first sub-epitaxial layers, the parts of the second epitaxial layers are the second sub-epitaxial layers, and the second grooves are obtained by removing part of the second sub-epitaxial layers and part of the first epitaxial layers at the bottom, the second sub-epitaxial layers are positioned on two sides of the first sub-epitaxial layers, so that the first sub-epitaxial layers are arranged among the groove gates formed in the second grooves, the SGT device is ensured to comprise a plurality of cells, the spacing among the cells is ensured to be larger, and the heat dissipation capacity of the SGT is ensured to be stronger.
In some embodiments, forming a gate structure in at least each of the second trenches includes: as shown in fig. 5 to 8, a shield gate oxide layer 60 is formed on the bottom and part of the sidewall surface of the second trench 40, and a first gate 70 is formed in the remaining part of the second trench 40, wherein the thickness of the first gate 70 is smaller than the depth of the second trench 40, and the second trench 40 with the first gate 70 formed therein forms a third trench 80; as shown in fig. 8 to 11, a gate oxide layer 90 is formed on a sidewall of the third trench 80, a second oxide layer 100 and a second gate 110 are formed on a surface of the first gate 70 away from the substrate 101, and the shield gate oxide layer 60, the gate oxide layer 90, the first gate 70, the second oxide layer 100 and the second gate 110 form the gate structure; as shown in fig. 11 to 12, a plurality of body regions 120 and a plurality of source regions 130 are formed in a portion of the second target epitaxial layer 50, and each of the source regions 130 is located in a corresponding one of the body regions 120; and forming a plurality of extraction structures, wherein each extraction structure is used for extracting each source region, and the extraction structures are in one-to-one correspondence with the source regions. By forming the shielded gate oxide layer, the first gate electrode, the second oxide layer, and the second gate electrode in the second trench, it is ensured that the SGT device having a trench gate can be obtained, and further, because the body region and the source region are formed in the second target epitaxial layer, it is ensured that the SGT device can realize its performance.
In the implementation process, the first grid electrode is a shielding grid.
Specifically, shielding gates (Shielding gates) in the SGT are used to control the relationship between transistor source and drain currents. The shielding gate in the SGT plays two important roles of loop barrier protection and a signal transmission gain adjusting device.
In order to further ensure better performance of the SGT device, forming a shield gate oxide layer on a bottom portion and a portion of a sidewall surface of the second trench, and forming a first gate in a remaining portion of the second trench, including: as shown in fig. 6, a preliminary shield gate oxide layer 140 is formed on the exposed surface of the second trench 40, the surface of the first oxide layer 104 away from the substrate 101, and the surface of the second target epitaxial layer 50 away from the substrate 101; as shown in fig. 6 to 7, the first gate electrode 70 is formed in the remaining portion of the second trench 40, and the third trench 80 is formed in the remaining portion of the second trench 40; as shown in fig. 7 to 8, a portion of the preliminary shielding gate oxide layer 140 is removed, a portion of the first oxide layer 104 and a portion of the second target epitaxial layer 50 are exposed by the sidewall of the third trench 80, and a surface of the first oxide layer 104 remote from the substrate 101 and a surface of the second target epitaxial layer 50 remote from the substrate 101 are exposed, so that the remaining preliminary shielding gate oxide layer 140 forms the shielding gate oxide layer 60. The first grid electrode is formed in the second groove of the rest part, and finally the shielding grid electrode layer is obtained by removing part of the first grid electrode layer, so that the shielding grid electrode oxide layer and the first grid electrode are formed at the bottom of the second groove, the shielding grid electrode oxide layer and the shielding grid electrode are obtained, an electric field between source and drain ends in the SGT device can be blocked through the shielding grid electrode oxide layer and the shielding grid electrode, the SGT device can be protected through the shielding grid electrode oxide layer and the shielding grid electrode, and better performance of the SGT device is further guaranteed.
In addition, the shielding grid is a high-resistance area, and the application further ensures that the SGT device can form the high-resistance area by forming the oxide layer among a plurality of shielding grids, thereby ensuring that the second epitaxial layer is completely consumed when the SGT device works, ensuring that the parasitic capacitance of the SGT is smaller, and further ensuring that the performance of the SGT device is better.
In some embodiments, forming a gate oxide layer on a sidewall of the third trench, and forming a stacked second oxide layer and a second gate on a surface of the first gate remote from the substrate, includes: as shown in fig. 8 to 9, a pre-gate oxide layer 150 is formed on the exposed surface of the third trench 80, the surface of the first oxide layer 104 away from the substrate 101, and the surface of the second target epitaxial layer 50 away from the substrate 101; as shown in fig. 9 to 10, the second gate 110 is formed in the remaining third trench 80; as shown in fig. 10 to 11, a portion of the preliminary gate oxide layer 150 is removed so that the surface of the first oxide layer 104 remote from the substrate 101 and the surface of the second target epitaxial layer 50 remote from the substrate 101 are exposed, and the remaining preliminary gate oxide layer 150 forms the gate oxide layer 90 and the second oxide layer 100. The first grid electrode and the second grid electrode are isolated through the second oxide layer, namely the shielding grid electrode and the second grid electrode are isolated through the second oxide layer, on one hand, the effect of the first grid electrode on the shielding grid electrode can be guaranteed, namely the shielding grid electrode is used for blocking an electric field between the source end and the drain end of the SGT device, the SGT device is protected through the shielding grid electrode, on the other hand, the effect of the grid electrode of the SGT device is achieved through the second grid electrode, namely the effect of a control current is controlled, and on the other hand, the better performance of the SGT is further guaranteed.
In a specific implementation process, forming a plurality of body regions and a plurality of source regions in a portion of the second target epitaxial layer includes: performing ion implantation on each second sub-epitaxial layer to form part of the second sub-epitaxial layers into the body region; and carrying out ion implantation on part of the body region to obtain the source region.
In addition, a thermal annealing process is required after the ion implantation to obtain the body region and the source region.
In some embodiments, forming a plurality of extraction structures includes: as shown in fig. 13, a first preliminary dielectric layer 160 is formed on a surface of the second gate 110 away from the substrate 101, a surface of the first oxide layer 104 away from the substrate 101, and a surface of the second target epitaxial layer 50 away from the substrate 101; as shown in fig. 13 to 14, a part of the first preliminary dielectric layer 160, a part of the source region 130, and a part of the body region 120 are removed to form a plurality of fourth trenches 170, each of the fourth trenches 170 penetrates the first preliminary dielectric layer 160, the source region 130, and the body region 120, and the remaining first preliminary dielectric layer 160 forms a first dielectric layer 180; as shown in fig. 14 to 15, a first connection layer 190 is formed in each of the fourth trenches 170; as shown in fig. 15 to 21, a plurality of first metal layers 200, a plurality of second connection layers 210, and a plurality of second metal layers 220 are formed, wherein each of the first metal layers 200 is located on a side of the corresponding first connection layer 190 away from the substrate 101, each of the first metal layers 200 is in contact with the corresponding first connection layer 190, each of the second connection layers 210 is located on a portion of the corresponding first metal layer 200 away from the first connection layer 190, each of the second metal layers 220 is located on a side of the corresponding second connection layer 210 away from the first metal layer 200, each of the second metal layers 220 is in contact with the corresponding second connection layer 210, and the first connection layer 190, the first connection layer 200, the second connection layer 210, and the second metal layers 220 constitute the lead-out structure. Through forming above-mentioned first tie layer, above-mentioned first metal level, above-mentioned second tie layer and above-mentioned second metal level, and above-mentioned first tie layer, above-mentioned first metal level, above-mentioned second tie layer and above-mentioned second metal level contact in proper order and set up, above-mentioned first tie layer all contacts with above-mentioned source region and above-mentioned body region for can draw forth above-mentioned source region through the extraction structure that above-mentioned first tie layer, above-mentioned first metal level, above-mentioned second tie layer and above-mentioned second metal level constitute, make the external world can connect above-mentioned source region through above-mentioned extraction structure, realize ohmic contact.
In the implementation process, the materials of the first connection layer and the second connection layer include tungsten, and of course, the materials of the first connection layer and the second connection layer are not limited to tungsten, and other metals with better conductivity can be selected, and the materials are specifically determined according to practical situations.
In a specific implementation process, forming a plurality of first metal layers, a plurality of second connection layers and a plurality of second metal layers, including: as shown in fig. 16, a first preliminary metal layer 230 is formed on the surface of the first dielectric layer 180 and the first connection layer 190 away from the substrate 101; as shown in fig. 16 to 17, a portion of the first preliminary metal layer 230 is removed, the remaining first preliminary metal layer 230 forms a plurality of first metal layers 200, each of the first metal layers 200 covers a portion of the surface of the first dielectric layer 180 remote from the substrate 101, and each of the first metal layers 200 covers a surface of the corresponding first connection layer 190 remote from the substrate 101; as shown in fig. 18, a second preliminary dielectric layer 240 is formed on the exposed surfaces of the first metal layer 200 and the first dielectric layer 180; as shown in fig. 18 to 19, a portion of the second preliminary dielectric layer 240 is removed to form a plurality of fifth trenches 250, each of the fifth trenches 250 exposes a corresponding portion of the first metal layer 200, and the remaining second preliminary dielectric layer 240 forms a second dielectric layer 260; as shown in fig. 19 to 20, the second connection layer 210 is formed in each of the fifth trenches 250, and a second preliminary metal layer 270 is formed on the surface of the second connection layer 210 and the second dielectric layer 260 remote from the substrate 101, and as shown in fig. 20 to 21, a portion of the second preliminary metal layer 270 is removed, the remaining second preliminary metal layer 270 results in a plurality of the second metal layers 220, each of the second metal layers 220 covers a portion of the surface of the second dielectric layer 260 remote from the substrate 101, and each of the second metal layers 220 covers a surface of the second connection layer 210 remote from the substrate 101. The first metal layer is obtained by forming the first preparation metal layer and removing part of the first preparation metal layer by etching, so that the first metal layer can be obtained by a simpler process, and similarly, the second grooves are obtained by forming the second preparation medium layer and removing part of the second preparation medium layer, so that contact holes can be obtained by forming a second connecting layer in the second grooves, contact between the second connecting layer and the first metal layer is realized, the second connecting layer can be obtained by a simpler manufacturing process, the second metal layer can be obtained by the same manufacturing process as the first metal layer, and the process for forming the extraction structure of the source region is simpler.
In the implementation process, the SGT device has the following advantages: firstly, lengthening the interval between two SGT unit cells or a plurality of SGT unit cell arrays of the SGT device, forming the first oxide layer high-resistance region, and ensuring that the parasitic capacitance of the SGT device is smaller; then, the above-mentioned: the SGT device realizes the high isolation SGT device technology which is compatible with the traditional SGT technology, and no extra technology is required to be introduced into the SGT device channel in the preparation process, so that the process complexity in the preparation process of the SGT device is low, and the stability of the preparation process of the SGT device is good; finally, in the preparation process of the SGT device, the special process for realizing the high barrier SGT device is less, and the preparation cost of the SGT device is lower.
In some embodiments, the material of the first oxide layer includes silicon dioxide.
In addition, the materials of the first grid electrode and the second grid electrode comprise polysilicon. The doping type of the substrate, the first epitaxial layer and the second epitaxial layer comprises an N type.
There is further provided, in accordance with an embodiment of the present application, an SGT device, as shown in fig. 21, comprising a substrate 101, a first target epitaxial layer 105, a plurality of first oxide layers 104, a plurality of second target epitaxial layers 50, and a plurality of gate structures, wherein the first target epitaxial layer 105 is located on a surface of the substrate 101; the first oxide layers 104 are spaced apart, the second target epitaxial layer 50 is located between two adjacent first oxide layers 104, and a plurality of second trenches (not shown) are formed between the first oxide layers 104 and the second target epitaxial layers 50; the gate structures are respectively located in the second trenches (not shown), and both sides of the gate structures are respectively in contact with the first oxide layer 104 and the second target epitaxial layer 50.
The SGT device includes a substrate, a first target epitaxial layer, a plurality of first oxide layers, a plurality of second target epitaxial layers, and a plurality of gate structures, wherein the first target epitaxial layer is located on a surface of the substrate; the first oxide layers are arranged at intervals, the second target epitaxial layer is positioned between two adjacent first oxide layers, and a plurality of second grooves are formed between the first oxide layers and the second target epitaxial layers; the gate structures are respectively located in the second trenches. Compared with the SGT device in the prior art, the SGT device has the problem of poor performance due to parasitic capacitance, the first oxide layers are arranged at intervals, the second target epitaxial layer is positioned between two adjacent first oxide layers, the grid structure is positioned between the first oxide layers and the second target epitaxial layer, the first oxide layers are ensured to exist among the second epitaxial layers, namely, the isolation of the second epitaxial layers through the first oxide layers is realized, the resistance of the SGT device can be improved through the first oxide layers at intervals, namely, a high-resistance region is formed, and the high-resistance region can deplete the second epitaxial layer when the SGT works, so that the parasitic capacitance of the SGT device is reduced, the problem that the SGT device in the prior art is difficult to deplete the epitaxial layer when the SGT device works due to the fact that the oxide layers are not arranged is solved, the problem of poor performance due to the parasitic capacitance of the SGT device in the prior art is solved, and the high-resistance performance of the SGT device is ensured.
In the implementation, fig. 21 is a schematic cross-sectional view of a cell region of the SGT device according to the present application, that is, including an extraction structure of the source region 130, fig. 22 is a schematic cross-sectional view of an extraction structure of the second gate 110 of the SGT device, fig. 23 is a schematic cross-sectional view of an extraction structure of the first gate 70 of the SGT device, that is, a schematic cross-sectional view of a shielding gate of the SGT device, and fig. 21, 22, and 23 correspond to different positions of the SGT device. Fig. 24 is a schematic plan view of the SGT device, that is, a schematic plan view of a metal structure in the SGT device, and fig. 24 includes positional relationships of corresponding metal structures in different cross sections corresponding to fig. 21, 22, and 23, as shown in fig. 24.
Specifically, as shown in fig. 22, the second gate electrode 110 is led out through the third connection layer 280, the third metal layer 290, the fourth connection layer 300, and the fourth metal layer 310, which are sequentially in contact with each other, wherein the third connection layer 280 is in contact with the second gate electrode 110, the third metal layer 290 is in contact with the third connection layer 280 and the fourth connection layer 300, respectively, and is finally led out through the fourth metal layer 310. As shown in fig. 23, the first gate electrode 70 is led out through the fifth connection layer 320, the fifth metal layer 330, the sixth connection layer 340, and the sixth metal layer 350 which are sequentially in contact with each other, wherein a contact hole corresponding to the fifth connection layer 320 penetrates through a dielectric layer into the first gate electrode 70, the fifth metal layer 330 is in contact with the fifth connection layer 320 and the sixth connection layer 340, and is finally led out through the sixth metal layer 350. Of course, the fifth connection layer, the third connection layer, and the first connection layer are simultaneously prepared, and similarly, the fifth metal layer, the third metal layer, and the first metal layer are simultaneously prepared, and the sixth connection layer, the fourth connection layer, and the second connection layer are simultaneously prepared, and the sixth metal layer, the fourth metal layer, and the second metal layer are simultaneously prepared.
In the embodiments of the present application, the descriptions of the embodiments are emphasized, and for a part of the detailed description of some embodiment, reference may be made to the related descriptions of other embodiments.
From the above description, it can be seen that the following technical effects are achieved by the embodiments of the present application:
1) In the method for manufacturing the SGT device of the present application, first, a substrate including a substrate, a first epitaxial layer and a preliminary oxide layer laminated in this order is provided; then, removing part of the preparation oxidation layer, forming first oxidation layers arranged at intervals by the rest preparation oxidation layers, and forming a plurality of first grooves arranged at intervals between the adjacent first oxidation layers, wherein part of the first epitaxial layers are exposed by the first grooves; then, forming a second epitaxial layer in each first groove; then, removing part of the second epitaxial layer and part of the first epitaxial layer at the bottom of the second epitaxial layer to obtain a plurality of second grooves which are arranged at intervals, wherein part of the side wall of each second groove exposes part of the first oxide layer, part of the first epitaxial layer is exposed at the bottom of each second groove, the rest of the first epitaxial layer forms a first target epitaxial layer, and the rest of the second epitaxial layer forms a second target epitaxial layer; finally, a gate structure is formed in at least each of the second trenches to obtain an SGT device. Compared with the prior art, the preparation method of the SGT device has the problem of poor performance caused by parasitic capacitance, because the substrate comprises the substrate, the first epitaxial layers and the preparation oxide layers which are stacked, and the first trenches which are arranged at intervals are formed among the preparation oxide layers, and the second epitaxial layers are formed in the first trenches, the first oxide layers exist among the second epitaxial layers, namely the isolation of the second epitaxial layers through the first oxide layers is realized, the resistance of the SGT device can be improved through the first oxide layers at intervals, namely a high-resistance region can be formed, and the second epitaxial layers can be exhausted when the SGT works, so that the parasitic capacitance of the SGT device is reduced, the problem that the parasitic capacitance of the SGT device in the prior art is difficult to exhaust when the epitaxial layers work due to the fact that the oxide layers are not arranged is avoided, and the parasitic capacitance of the SGT device in the prior art is poor in performance caused by the fact that the parasitic capacitance of the SGT device exists is guaranteed.
2) The SGT device of the present application includes a substrate, a first target epitaxial layer, a plurality of first oxide layers, a plurality of second target epitaxial layers, and a plurality of gate structures, wherein the first target epitaxial layer is located on a surface of the substrate; the first oxide layers are arranged at intervals, the second target epitaxial layer is positioned between two adjacent first oxide layers, and a plurality of second grooves are formed between the first oxide layers and the second target epitaxial layers; the gate structures are respectively located in the second trenches. Compared with the SGT device in the prior art, the SGT device has the problem of poor performance due to parasitic capacitance, the first oxide layers are arranged at intervals, the second target epitaxial layer is positioned between two adjacent first oxide layers, the grid structure is positioned between the first oxide layers and the second target epitaxial layer, the first oxide layers are ensured to exist among the second epitaxial layers, namely, the isolation of the second epitaxial layers through the first oxide layers is realized, the resistance of the SGT device can be improved through the first oxide layers at intervals, namely, a high-resistance region is formed, and the high-resistance region can deplete the second epitaxial layer when the SGT works, so that the parasitic capacitance of the SGT device is reduced, the problem that the SGT device in the prior art is difficult to deplete the epitaxial layer when the SGT device works due to the fact that the oxide layers are not arranged is solved, the problem of poor performance due to the parasitic capacitance of the SGT device in the prior art is solved, and the high-resistance performance of the SGT device is ensured.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of making an SGT device, said method comprising:
providing a substrate, wherein the substrate comprises a substrate, a first epitaxial layer and a preparation oxide layer which are sequentially laminated;
removing part of the preparation oxidation layer to form a plurality of first grooves which are arranged at intervals, wherein part of the first epitaxial layer is exposed by the first grooves, and the rest of the preparation oxidation layer forms a first oxidation layer;
forming a second epitaxial layer in each first groove;
removing part of the second epitaxial layer and part of the first epitaxial layer to form a plurality of second grooves which are arranged at intervals, wherein part of the first oxide layer is exposed by the side wall of each second groove, part of the first epitaxial layer is exposed by the bottom of each second groove, the rest of the first epitaxial layer forms a first target epitaxial layer, and the rest of the second epitaxial layer forms a second target epitaxial layer;
A gate structure is formed in at least each of the second trenches to obtain an SGT device.
2. The method of claim 1, wherein portions of the plurality of second epitaxial layers are first sub-epitaxial layers, portions of the plurality of second epitaxial layers are second sub-epitaxial layers, the plurality of second sub-epitaxial layers are located on both sides of the plurality of first sub-epitaxial layers, removing portions of the second epitaxial layers and portions of the first epitaxial layers to form a plurality of spaced apart second trenches, comprising:
and removing part of the second sub-epitaxial layer and part of the first epitaxial layer to form a plurality of second grooves which are arranged at intervals.
3. The method of claim 2, wherein forming a gate structure in at least each of the second trenches comprises:
forming a shielding gate oxide layer on the bottom and part of the side wall surface of the second groove, forming a first gate in the rest part of the second groove, wherein the thickness of the first gate is smaller than the depth of the second groove, and forming a third groove by the second groove with the first gate;
forming a gate oxide layer on the side wall of the third groove, and forming a second oxide layer and a second gate which are stacked on the surface, far away from the substrate, of the first gate, wherein the shielding gate oxide layer, the first gate, the second oxide layer and the second gate form the gate structure;
Forming a plurality of body regions and a plurality of source regions in a part of the second target epitaxial layer, wherein each source region is positioned in the corresponding body region;
and forming a plurality of extraction structures, wherein each extraction structure is used for extracting each source region, and the extraction structures are in one-to-one correspondence with the source regions.
4. The method of claim 3, wherein forming a shield gate oxide layer on a bottom and a portion of sidewall surfaces of the second trench and forming a first gate within a remaining portion of the second trench comprises:
forming a preliminary shielding gate oxide layer on the exposed surface of the second trench, the surface of the first oxide layer away from the substrate, and the surface of the second target epitaxial layer away from the substrate;
forming the first grid electrode in the rest part of the second grooves, and forming the third grooves by the rest part of the second grooves;
and removing part of the preparation shielding gate oxide layer, exposing part of the first oxide layer and part of the second target epitaxial layer by the side wall of the third groove, exposing the surface of the first oxide layer, which is far away from the substrate, and the surface of the second target epitaxial layer, which is far away from the substrate, and forming the shielding gate oxide layer by the rest of the preparation shielding gate oxide layer.
5. The method of claim 3, wherein forming a gate oxide layer on sidewalls of the third trench and forming a stacked second oxide layer and second gate on a surface of the first gate remote from the substrate comprises:
forming a preliminary gate oxide layer on the exposed surface of the third trench, the surface of the first oxide layer away from the substrate, and the surface of the second target epitaxial layer away from the substrate;
forming the second grid electrode in the rest third grooves;
and removing part of the preliminary gate oxide layer, so that the surface of the first oxide layer, which is far away from the substrate, and the surface of the second target epitaxial layer, which is far away from the substrate, are exposed, and the rest of the preliminary gate oxide layer forms the gate oxide layer and the second oxide layer.
6. The method of claim 3, wherein forming a plurality of body regions and a plurality of source regions in a portion of the second target epitaxial layer comprises:
performing ion implantation on each second sub-epitaxial layer to enable part of the second sub-epitaxial layers to form the body region;
and carrying out ion implantation on part of the body region to obtain the source region.
7. A method according to claim 3, wherein forming a plurality of extraction structures comprises:
forming a first preparation medium layer on the surface of the second grid electrode, which is far away from the substrate, the surface of the first oxide layer, which is far away from the substrate, and the surface of the second target epitaxial layer, which is far away from the substrate;
removing part of the first preparation medium layer, part of the source region and part of the body region to form a plurality of fourth grooves, wherein each fourth groove penetrates through the first preparation medium layer, the source region and the body region, and the rest of the first preparation medium layer forms a first medium layer;
forming a first connection layer in each fourth groove;
forming a plurality of first metal layers, a plurality of second connection layers and a plurality of second metal layers, wherein each first metal layer is located on one side, away from the substrate, of a corresponding first connection layer, each first metal layer is in contact with a corresponding first connection layer, each second connection layer is located on a part of the surface, away from the first connection layer, of a corresponding first metal layer, each second metal layer is located on one side, away from the first metal layer, of a corresponding second connection layer, each second metal layer is in contact with a corresponding second connection layer, and the first connection layer, the first metal layer, the second connection layer and the second metal layer form the extraction structure.
8. The method of claim 7, wherein forming a plurality of first metal layers, a plurality of second connection layers, and a plurality of second metal layers comprises:
forming a first preparation metal layer on the first dielectric layer and the surface of the first connection layer, which is far away from the substrate;
removing part of the first preparation metal layer, forming a plurality of first metal layers by the rest of the first preparation metal layers, wherein each first metal layer covers part of the surface of the first dielectric layer, which is far away from the substrate, and each first metal layer covers the surface of the corresponding first connection layer, which is far away from the substrate;
forming a second preparation medium layer on the first metal layer and the exposed surface of the first medium layer;
removing part of the second preparation medium layer to form a plurality of fifth grooves, wherein each fifth groove exposes a corresponding part of the first metal layer, and the rest of the second preparation medium layer forms a second medium layer;
forming a second connection layer in each fifth groove, forming a second preparation metal layer on the surfaces of the second connection layer and the second medium layer, which are far away from the substrate, removing part of the second preparation metal layer, obtaining a plurality of second metal layers by the rest of the second preparation metal layer, wherein each second metal layer covers part of the surface of the second medium layer, which is far away from the substrate, and each second metal layer covers the surface of the second connection layer, which is far away from the substrate.
9. The method of any one of claims 1 to 8, wherein the material of the first oxide layer comprises silicon dioxide.
10. An SGT device, said SGT device comprising:
a substrate;
a first target epitaxial layer on a surface of the substrate;
the semiconductor device comprises a plurality of first oxide layers and a plurality of second target epitaxial layers, wherein the first oxide layers are arranged at intervals, the second target epitaxial layers are positioned between two adjacent first oxide layers, and a plurality of second grooves are formed between the first oxide layers and the second target epitaxial layers;
and the grid structures are respectively positioned in the second trenches, and two sides of the grid structures are respectively contacted with the first oxide layer and the second target epitaxial layer.
CN202310736657.3A 2023-06-20 2023-06-20 SGT device and method of making same Pending CN116666444A (en)

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