CN114664219A - Display control module, method and display device - Google Patents
Display control module, method and display device Download PDFInfo
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- CN114664219A CN114664219A CN202210312809.2A CN202210312809A CN114664219A CN 114664219 A CN114664219 A CN 114664219A CN 202210312809 A CN202210312809 A CN 202210312809A CN 114664219 A CN114664219 A CN 114664219A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- General Physics & Mathematics (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a display control module, a display control method and a display device. The display control module comprises a gating control signal generating circuit and a first switch circuit; the gating control signal generating circuit controls to provide a first gating control signal and controls to provide a second gating control signal; the first switch circuit controls the source driver to provide the data voltage to the data line or controls the first direct current voltage end to provide the first direct current voltage to the data line under the control of the first strobe control signal and the second strobe control signal. The display control module, the display control method and the display device can well maintain the potential of the first node by reducing electric leakage when the image signal to be displayed is unchanged, and ensure excellent display quality picture.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display control module, a display control method and a display device.
Background
When the image signal to be displayed in the display device is unchanged or substantially unchanged, the pixels can be driven at a low speed to reduce the power consumption of the display device. But may suffer from a problem of image quality degradation. In the low-speed driving mode, for example, the potential of the gate of the driving transistor may leak due to the transistor electrically connected to the gate, thereby causing a flicker phenomenon to be felt by a user,
disclosure of Invention
It is a primary object of the present invention to provide a display control module, a display control method, and a display device, which solve the problem that the potential of a first node (the first node is a node electrically connected to the gate of the driving transistor) cannot be maintained well by reducing the leakage current when the image signal to be displayed is unchanged.
In order to achieve the above object, an embodiment of the present invention provides a display control module, which is applied to a display device, where the display device includes a display panel, where the display panel includes a plurality of data lines; the display control module comprises a gating control signal generating circuit and a first switch circuit;
the gating control signal generating circuit is respectively electrically connected with a first control end, a first clock signal end, a second clock signal end, a first voltage end, a first gating control end and a second gating control end, and is used for controlling the first gating control end to provide a first gating control signal and controlling the second gating control end to provide a second gating control signal under the control of a first control signal provided by the first control end, a first clock signal provided by the first clock signal end and a second clock signal provided by the second clock signal end;
the first switch circuit is electrically connected with the first gating control end, the second gating control end, the first direct current voltage end, the source driver and the data line respectively, and is used for controlling the source driver to provide data voltage for the data line under the control of the first gating control signal and the second gating control signal, or controlling the first direct current voltage end to provide the first direct current voltage for the data line.
Optionally, the display panel further includes a plurality of reference voltage lines; the display control module further comprises a second switch circuit;
the second switch circuit is electrically connected to the first gate control terminal, the second dc voltage terminal, the source driver, and the reference voltage line, respectively, and is configured to control the source driver to provide the reference voltage line with the reference voltage under the control of the first gate control signal and the second gate control signal, or the second dc voltage terminal to provide the reference voltage line with the second dc voltage.
Optionally, the gate control signal generating circuit includes a first generating circuit and a second generating circuit;
the first generating circuit is respectively electrically connected with the first control end, the first clock signal end, the second clock signal end, the first gating control end and the first voltage end, and is used for controlling the communication between the first gating control end and the first clock signal end under the control of the first control signal and controlling the communication between the first gating control end and the first voltage end under the control of the second clock signal provided by the second clock signal end;
the second generating circuit is respectively electrically connected with the first control end, the first clock signal end, the second gating control end and the first voltage end, and is used for controlling the communication between the second gating control end and the second clock signal end under the control of the first control signal and controlling the communication between the second gating control end and the first voltage end under the control of the first clock signal provided by the first clock signal end.
Optionally, the first generating circuit includes a first transistor, a second transistor, and a first capacitor;
a control electrode of the first transistor is electrically connected with the first control end, a first electrode of the first transistor is electrically connected with the first clock signal end, and a second electrode of the first transistor is electrically connected with the first gating control end;
a control electrode of the second transistor is electrically connected with the second clock signal end, a first electrode of the second transistor is electrically connected with the first gating control end, and a second electrode of the second transistor is electrically connected with the first voltage end;
the first end of the first capacitor is electrically connected with the first control end, and the second end of the first capacitor is electrically connected with the first gating control end;
the second generation circuit comprises a third transistor, a fourth transistor and a second capacitor;
a control electrode of the third transistor is electrically connected with the first control end, a first electrode of the third transistor is electrically connected with the second gating control end, and a second electrode of the third transistor is electrically connected with the second clock signal end;
a control electrode of the fourth transistor is electrically connected with the first clock signal end, a first electrode of the fourth transistor is electrically connected with the first voltage end, and a second electrode of the fourth transistor is electrically connected with the second gating control end;
the first end of the second capacitor is electrically connected with the first control end, and the second end of the second capacitor is electrically connected with the second gating control end.
Optionally, the first switch circuit includes a first switch unit circuit and a second switch unit circuit, the display device includes N data lines, and N is a positive integer; the first switching unit circuit includes N first switching transistors, and the second switching unit circuit includes N second switching transistors; n is a positive integer less than or equal to N;
a control electrode of the nth first switching transistor is electrically connected with the first gating control end, a first electrode of the nth first switching transistor is electrically connected with the nth data line, and a second electrode of the nth first switching transistor is electrically connected with the source electrode driver;
the control electrode of the nth second switching transistor is electrically connected with the second gating control end, the first electrode of the nth second switching transistor is electrically connected with the nth data line, and the second electrode of the nth second switching transistor is electrically connected with the first direct current voltage end.
Optionally, the N first switch transistors and the N second switch transistors are both N-type transistors, or the N first switch transistors and the N second switch transistors are both p-type transistors.
Optionally, the second switch circuit includes a third switch unit circuit and a fourth switch unit circuit, the display device includes P reference voltage lines, P is a positive integer; the third switching unit circuit comprises P third switching transistors, and the fourth switching unit circuit comprises P fourth switching transistors; p is a positive integer less than or equal to P;
a control electrode of a p-th third switching transistor is electrically connected with the first gating control end, a first electrode of the p-th third switching transistor is electrically connected with a p-th reference voltage line, and a second electrode of the p-th third switching transistor is electrically connected with the source driver;
and the control electrode of the p-th fourth switching transistor is electrically connected with the second gating control end, the first electrode of the p-th fourth switching transistor is electrically connected with a p-th reference voltage line, and the second electrode of the p-th fourth switching transistor is electrically connected with the second direct-current voltage end.
Optionally, the P third switching transistors and the P fourth switching transistors are both n-type transistors, or the P third switching transistors and the P fourth switching transistors are both P-type transistors.
Optionally, the system further comprises a direct current module;
the direct current module is respectively electrically connected with the first direct current voltage end and the second direct current voltage end and is used for providing first direct current voltage for the first direct current voltage end and providing second direct current voltage for the second direct current voltage end.
An embodiment of the present invention further provides a display control method, which is applied to the display control module described above, where the display control method includes:
the source driver receives an image signal to be displayed, and judges whether the image signal to be displayed changes or not when a display period starts;
when the image signal to be displayed does not change, detecting that the display control module enters a low-speed driving mode, and setting the display period to comprise a refresh frame and at least one retention frame which are successively set;
in the refresh frame, controlling a first control signal, a first clock signal and a second clock signal to enable the gating control signal generating circuit to provide a first gating control signal and a first second gating control signal, and controlling a source driver to provide corresponding data voltages to the data lines by a first switch circuit under the control of the first gating control signal and the first second gating control signal;
and in the holding frame, the first control signal, the first clock signal and the second clock signal are controlled to enable the gating control signal generating circuit to provide a second first gating control signal and a second gating control signal, and the first switch circuit controls the first direct-current voltage end to provide the first direct-current voltage for the data line under the control of the second first gating control signal and the second gating control signal.
Optionally, the display panel further includes a plurality of reference voltage lines; the display control module further comprises a second switch circuit; the display control method further includes:
the second switching circuit controls the supply of the reference voltage to the reference voltage line by the source driver under the control of the first gate control signal and the first second gate control signal in the refresh frame;
in the hold frame, the second switch circuit controls the supply of the second dc voltage from the second dc voltage terminal to the reference voltage line under the control of the second first gate control signal and the second gate control signal.
Optionally, the display control method according to at least one embodiment of the present invention further includes:
when the image signal to be displayed changes, in the display period, the gate control signal generation circuit provides a first gate control signal and a first second gate control signal by controlling a first control signal, a first clock signal and a second clock signal, the first switch circuit controls the source driver to provide corresponding data voltages to the plurality of data lines respectively under the control of the first gate control signal and the first second gate control signal, and the second switch circuit controls the source driver to provide reference voltages to the plurality of reference voltage lines respectively under the control of the first gate control signal and the first second gate control signal.
The embodiment of the invention also provides a display device which comprises the display control module.
The display control module, the display control method and the display device can well maintain the potential of the first node by reducing electric leakage when the image signal to be displayed is unchanged, and ensure excellent display quality picture.
Drawings
FIG. 1 is a block diagram of a display control module according to at least one embodiment of the present disclosure;
FIG. 2 is a block diagram of a display control module according to at least one embodiment of the present disclosure;
FIG. 3 is a circuit diagram of at least one embodiment of the pixel circuit in the mth row and nth column of the display device according to the present invention;
FIG. 4 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 3 in a normal driving mode;
FIG. 5 is a block diagram of at least one embodiment of a gate control signal generation circuit in the display control module according to the present invention;
FIG. 6 is a circuit diagram of at least one embodiment of a gate control signal generation circuit in a display control module according to the present invention;
FIG. 7 is a circuit diagram of a display control module according to at least one embodiment of the invention;
FIG. 8 is a timing diagram illustrating operation of a display control module according to at least one embodiment of the present disclosure;
FIG. 9 is a circuit diagram of a display control module according to at least one embodiment of the invention;
FIG. 10 is a circuit diagram of a display control module according to at least one embodiment of the invention;
FIG. 11 is a circuit diagram of a display control module according to at least one embodiment of the present disclosure;
fig. 12 is a flowchart of a display control method according to at least one embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.
The display control module is applied to a display device, the display device comprises a display panel P0, and the display panel P0 comprises a plurality of data lines; as shown in fig. 1, the display control module may include a gate control signal generation circuit 11 and a first switching circuit 12;
the gate control signal generating circuit 11 is respectively electrically connected to a first control end COE, a first clock signal end CKA, a second clock signal end CKB, a first voltage end V1, a first gate control end SELA, and a second gate control end SELB, and is configured to control the first gate control end SELA to provide a first gate control signal and control the second gate control end SELA to provide a second gate control signal under the control of a first control signal provided by the first control end COE, a first clock signal provided by the first clock signal end CKA, and a second clock signal provided by the second clock signal end CKB;
the first switch circuit 12 respectively with the first gate control terminal SELA, the second gate control terminal SELB, the first direct current voltage terminal VZ1, the source driver S1 and the data line is electrically connected, is used for under the control of the first gate control signal and the second gate control signal, the control is by the source driver S1 to the data line provides the data voltage, or, by the first direct current voltage terminal VZ1 to the data line provides the first direct current voltage VDC 1.
In the embodiment of the display control module shown in fig. 1, the reference numeral D1 is a first data line, the reference numeral D2 is a second data line, the reference numeral DN is an nth data line, and N is a positive integer.
In a specific implementation, the display device may include M rows and N columns of pixel circuits, the same column of pixel circuits is electrically connected to the corresponding data lines, and M and N are positive integers.
In at least one embodiment of the present invention, the first voltage terminal V1 can be a low voltage terminal, but is not limited thereto.
When the embodiment of the display control module shown in fig. 1 of the present invention is in operation, the source driver S1 receives the image signal to be displayed, and at the beginning of each display period, determines whether the image signal to be displayed changes;
when the image signal to be displayed does not change, the first control signal, the first clock signal and the second clock signal are controlled, so that the gate control signal generating circuit 11 provides the first gate control signal and the first second gate control signal, and the first switch circuit 12 controls the first direct-current voltage end VZ1 to provide the first direct-current voltage VDC1 to the data line under the control of the first gate control signal and the first second gate control signal.
When the embodiment of the display control module shown in fig. 1 of the present invention is in operation, when the source driver S1 determines that the image signal to be displayed does not change, the low-speed driving mode is entered, that is, the display screen does not change substantially, the data voltage does not need to be updated, but the light-emitting state needs to be maintained, the gate control signal generating circuit 11 controls the first switch circuit 12, so that the first dc voltage end VZ1 provides the first dc voltage VDC1 to the data line, so that the difference between the potential of the source of the data writing transistor and the potential of the drain of the data writing transistor is not large, the leakage effect of the data writing transistor on the first node (the first node is the node with the gate of the driving transistor) is reduced, and the display image quality is improved.
Optionally, the voltage value of the first direct current voltage VDC1 may be greater than or equal to 0V and less than or equal to 16V, but is not limited thereto.
In at least one embodiment of the present invention, the display panel further includes a plurality of reference voltage lines; the display control module may further include a second switching circuit;
the second switch circuit is electrically connected to the first gate control terminal, the second dc voltage terminal, the source driver, and the reference voltage line, respectively, and is configured to control the source driver to provide the reference voltage line with the reference voltage under the control of the first gate control signal and the second gate control signal, or the second dc voltage terminal to provide the reference voltage line with the second dc voltage.
In a specific implementation, the display control device module may further include a second switch circuit, and when the image signal to be displayed does not change, the second switch circuit controls the second dc voltage end to provide the second dc voltage to the reference voltage line under the control of the first gate control signal and the first second gate control signal.
As shown in fig. 2, the display control module may further include a second switching circuit 21; the second switch circuit 21 is electrically connected to the gate control signal generation circuit 11;
the gating control signal generating circuit 11 is electrically connected to a first control terminal COE, a first clock signal terminal CKA, a second clock signal terminal CKB, a first voltage terminal V1, a first gating control terminal SELA, and a second gating control terminal SELB, respectively, and is configured to control the first gating control terminal SELA to provide a first gating control signal and control the second gating control terminal SELA to provide a second gating control signal under the control of a first control signal provided by the first control terminal COE, a first clock signal provided by the first clock signal terminal CKA, and a second clock signal provided by the second clock signal terminal CKB;
the second switch circuit 21 is electrically connected to the first gate control terminal SELA, the second gate control terminal SELB, the second dc voltage terminal VZ2, the source driver S1, and the reference voltage line, respectively, and is configured to control the source driver S1 to supply the reference voltage line with the reference voltage Vref or the second dc voltage terminal VZ2 to supply the reference voltage line with the second dc voltage Vref _ h under the control of the first gate control signal and the second gate control signal.
In fig. 2, reference numeral P0 denotes a display panel, reference numeral R1 denotes a first reference voltage line, reference numeral R2 denotes a second reference voltage line, reference numeral RP denotes a pth reference voltage line, and P is a positive integer.
In a specific implementation, the display device may include M rows and N columns of pixel circuits, the same column of pixel circuits being electrically connected to corresponding reference voltage lines, M and N being positive integers.
When the embodiment of the display control module shown in fig. 2 of the present invention is in operation, the source driver S1 receives the image signal to be displayed, and at the beginning of each display period, determines whether the image signal to be displayed changes;
when the image signal to be displayed does not change, the second switch circuit 21 controls the second dc voltage terminal VZ2 to supply the second dc voltage Vref _ h to the reference voltage line under the control of the first gate control signal and the first second gate control signal.
In fig. 2, reference numeral R1 is a first reference voltage line, reference numeral R2 is a second reference voltage line, and reference numeral RP is a pth reference voltage line.
When the embodiment of the display control module shown in fig. 2 of the present invention is in operation, when the source driver S1 determines that the image signal to be displayed does not change, the low-speed driving mode is entered, that is, the display screen does not change substantially, the data voltage does not need to be updated, but the light-emitting state needs to be maintained, the gate control signal generating circuit 11 controls the second switch circuit 21, so that the second dc voltage Vref _ h is provided from the second dc voltage terminal VZ2 to the reference voltage line, so that the difference between the potential of the source of the compensation control transistor and the potential of the drain of the data writing transistor is not large, the leakage effect of the compensation control transistor on the first node (the first node is the node with the gate of the driving transistor) is reduced, and the display image quality is improved.
Optionally, the voltage value of the second dc voltage Vref _ h may be greater than or equal to 0V and less than or equal to 16V, but is not limited thereto.
The gate control signal generating circuit included in the embodiment of the display control module shown in fig. 1 may be the same gate control signal generating circuit as the gate control signal generating circuit included in the embodiment of the display control module shown in fig. 2, or the gate control signal generating circuit included in the embodiment of the display control module shown in fig. 1 may be a different gate control signal generating circuit from the gate control signal generating circuit included in the embodiment of the display control module shown in fig. 2.
In at least one embodiment of the present invention, as shown in fig. 3, the pixel circuit in the mth row and nth column in the display device may include a driving transistor T0, a data writing transistor T1, a compensation control transistor T2, a storage capacitor Cst, a light emission control transistor T3, a reset transistor T4, and an organic light emitting diode O1;
a gate of the T1 is electrically connected to the first scan line G1, a source of the T1 is electrically connected to the nth data line Dn, and a drain of the T1 is electrically connected to the first node N1; the first node N1 is electrically connected with the gate of T0;
the gate of the T2 is electrically connected to the second scan line G2, the source of the T2 is electrically connected to the p-th reference voltage line Rp, and the drain of the T2 is electrically connected to the first node N1;
a gate of the T3 is electrically connected to the emission control line EM, a source of the T3 is electrically connected to the high voltage line VDD, and a drain of the T3 is electrically connected to a drain of the T0;
the grid electrode of T4 is electrically connected with the third scanning line G3, the source electrode of T4 is electrically connected with the sensing line Sense, and the drain electrode of T4 is electrically connected with the source electrode of T0;
the source of T0 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to a low voltage line VSS;
the first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the source of T0.
In at least one embodiment of the present invention, M and N are positive integers, M is less than or equal to M, N is less than or equal to N, and p is a positive integer.
In the related art, when at least one embodiment of the pixel circuit shown in fig. 3 operates, if the potential of the first node N1 is lowered due to the leakage current of T1 and T2 during the low-speed driving period, the display quality is degraded. Therefore, the display control module according to the embodiment of the invention can reduce the leakage current of T1 and the leakage current of T2 during the low-speed driving period, and ensure that the display picture quality is excellent.
FIG. 4 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 3 in a normal driving mode.
Optionally, as shown in fig. 5, at least one embodiment of the gate control signal generating circuit may include a first generating circuit 41 and a second generating circuit 42;
the first generating circuit 41 is electrically connected to the first control terminal COE, the first clock signal terminal CKA, the second clock signal terminal CKB, the first gating control terminal SELA, and the first voltage terminal V1, respectively, and is configured to control the communication between the first gating control terminal SELA and the first clock signal terminal CKA under the control of the first control signal, and control the communication between the first gating control terminal SELA and the first voltage terminal V1 under the control of the second clock signal provided by the second clock signal terminal CKB;
the second generating circuit 42 is electrically connected to the first control terminal COE, the first clock signal terminal CKA, the second clock signal terminal CKB, the second gating control terminal SELB, and the first voltage terminal V1, and is configured to control the communication between the second gating control terminal SELB and the second clock signal terminal CKB under the control of the first control signal, and control the communication between the second gating control terminal SELB and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal CKA.
In a specific implementation, the gate control signal generating circuit may include a first generating circuit 41 and a second generating circuit 42, where the first generating circuit 41 controls the first gate control signal provided by the first gate control terminal SELA under the control of the first control signal and the second clock signal, and the second generating circuit 42 controls the second gate control signal provided by the second gate control terminal SELB under the control of the first control signal and the first clock signal.
Optionally, the first generating circuit includes a first transistor, a second transistor, and a first capacitor;
a control electrode of the first transistor is electrically connected with the first control end, a first electrode of the first transistor is electrically connected with the first clock signal end, and a second electrode of the first transistor is electrically connected with the first gating control end;
a control electrode of the second transistor is electrically connected with the second clock signal end, a first electrode of the second transistor is electrically connected with the first gating control end, and a second electrode of the second transistor is electrically connected with the first voltage end;
the first end of the first capacitor is electrically connected with the first control end, and the second end of the first capacitor is electrically connected with the first gating control end;
the second generation circuit comprises a third transistor, a fourth transistor and a second capacitor;
a control electrode of the third transistor is electrically connected with the first control end, a first electrode of the third transistor is electrically connected with the second gating control end, and a second electrode of the third transistor is electrically connected with the second clock signal end;
a control electrode of the fourth transistor is electrically connected with the first clock signal end, a first electrode of the fourth transistor is electrically connected with the first voltage end, and a second electrode of the fourth transistor is electrically connected with the second gating control end;
the first end of the second capacitor is electrically connected with the first control end, and the second end of the second capacitor is electrically connected with the second gating control end.
As shown in fig. 6, on the basis of at least one embodiment of the gate control signal generating circuit shown in fig. 5, the first generating circuit 41 includes a first transistor T1, a second transistor T2, and a first capacitor C1;
the gate of the first transistor T1 is electrically connected to the first control terminal COE, the source of the first transistor T1 is electrically connected to the first clock signal terminal CKA, and the drain of the first transistor T1 is electrically connected to the first gate control terminal SELA;
a gate of the second transistor T2 is electrically connected to the second clock signal terminal CKB, a source of the second transistor T2 is electrically connected to the first gate control terminal SELA, and a drain of the second transistor T2 is electrically connected to a low voltage terminal; the low voltage end is used for providing a low voltage VGL;
a first end of the first capacitor C1 is electrically connected to the first control terminal COE, and a second end of the first capacitor C1 is electrically connected to the first gate control terminal SELA;
the second generating circuit 42 includes a third transistor T3, a fourth transistor T4, and a second capacitor C2;
a gate of the third transistor T3 is electrically connected to the first control terminal COE, a source of the third transistor T3 is electrically connected to the second gate control terminal SELB, and a drain of the third transistor T3 is electrically connected to the second clock signal terminal CKB;
a gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKA, a source of the fourth transistor T4 is electrically connected to the low voltage terminal, and a drain of the fourth transistor T4 is electrically connected to the second gate control terminal SELB;
a first end of the second capacitor C2 is electrically connected to the first control terminal COE, and a second end of the second capacitor C2 is electrically connected to the second gate control terminal SELB.
In at least one embodiment of the gate control signal generating circuit shown in fig. 6, lossless output can be realized through signal collocation, so as to enhance the driving capability of the gate thin film transistor. In specific implementation, the high voltage value of the first control signal output by the COE may be set to be greater than the high voltage value of the first clock signal provided by the first clock signal terminal CKA, and the high voltage value of the first control signal output by the COE may be set to be greater than the high voltage value of the second clock signal provided by the second clock signal terminal CKB, so that the high voltage value of the first gate control signal provided by the first gate control terminal SELA and the high voltage value of the second gate control signal provided by the second gate control terminal SELB are higher, and the driving capability can be enhanced.
In at least one embodiment of the gate control signal generating circuit shown in fig. 6, T1, T2, T3, and T4 may be n-type thin film transistors, but are not limited thereto.
At least one embodiment of the gate control signal generation circuit shown in figure 6 is operative,
in a refresh frame, the COE provides a high voltage signal, the CKA provides a high voltage signal, the CKB provides a low voltage signal, the T1 is turned on, the T2 is turned off, the T3 is turned on, the T4 is turned on, the SELA outputs a high voltage signal, and the SELB outputs a low voltage signal;
in the hold frame, COE provides a high voltage signal, CKA provides a low voltage signal, CKB provides a high voltage signal, T1 is on, T2 is on, SELA outputs a low voltage signal, T3 is on, T4 is off, and SELB outputs a high voltage signal.
In at least one embodiment of the present invention, when the COE provides the high voltage signal, a voltage value of the high voltage signal provided by the COE may be set to be greater than a high voltage value of the first clock signal provided by CKA, and a voltage value of the high voltage signal provided by the COE may be set to be greater than a high voltage value of the second clock signal provided by CKB, so that the high voltage value of the first gate control signal output by the SELA and the high voltage value of the second gate control signal output by the SELB are higher, thereby enhancing the driving capability.
In at least one embodiment of the present invention, the first switch circuit includes a first switch unit circuit and a second switch unit circuit, the display device includes N data lines, N is a positive integer; the first switching unit circuit includes N first switching transistors, and the second switching unit circuit includes N second switching transistors; n is a positive integer less than or equal to N;
a control electrode of the nth first switching transistor is electrically connected with the first gating control end, a first electrode of the nth first switching transistor is electrically connected with the nth data line, and a second electrode of the nth first switching transistor is electrically connected with the source electrode driver;
the control electrode of the nth second switching transistor is electrically connected with the second gating control end, the first electrode of the nth second switching transistor is electrically connected with the nth data line, and the second electrode of the nth second switching transistor is electrically connected with the first direct current voltage end.
Optionally, the N first switch transistors and the N second switch transistors are both N-type transistors, or the N first switch transistors and the N second switch transistors are both p-type transistors.
As shown in fig. 7, on the basis of at least one embodiment of the display control module shown in fig. 1, the gate control signal generating circuit 11 includes a first generating circuit and a second generating circuit;
the first generating circuit comprises a first transistor T1, a second transistor T2 and a first capacitor C1;
a gate of the first transistor T1 is electrically connected to the first control terminal COE, a source of the first transistor T1 is electrically connected to the first clock signal terminal CKA, and a drain of the first transistor T1 is electrically connected to the first gate control terminal SELA;
a gate of the second transistor T2 is electrically connected to the second clock signal terminal CKB, a source of the second transistor T2 is electrically connected to the first gate control terminal SELA, and a drain of the second transistor T2 is electrically connected to a low voltage terminal; the low voltage end is used for providing a low voltage VGL;
a first end of the first capacitor C1 is electrically connected to the first control terminal COE, and a second end of the first capacitor C1 is electrically connected to the first gate control terminal SELA;
the second generating circuit includes a third transistor T3, a fourth transistor T4, and a second capacitor C2;
a gate of the third transistor T3 is electrically connected to the first control terminal COE, a source of the third transistor T3 is electrically connected to the second gate control terminal SELB, and a drain of the third transistor T3 is electrically connected to the second clock signal terminal CKB;
a gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKA, a source of the fourth transistor T4 is electrically connected to the low voltage terminal, and a drain of the fourth transistor T4 is electrically connected to the second gate control terminal SELB;
a first end of the second capacitor C2 is electrically connected to the first control terminal COE, and a second end of the second capacitor C2 is electrically connected to the second gate control terminal SELB;
the first switch circuit comprises a first switch unit circuit 71 and a second switch unit circuit 72, a display panel P0 in the display device comprises N data lines, and N is a positive integer;
the first switching unit circuit 71 includes N first switching transistors, and the second switching unit circuit 72 includes N second switching transistors;
in fig. 7, reference numeral T11 is a first switching transistor, reference numeral T12 is a second first switching transistor, and reference numeral T1N is an nth first switching transistor; a first second switching transistor denoted by a reference numeral T21, a second switching transistor denoted by a reference numeral T22, and an nth second switching transistor denoted by a reference numeral T2N;
the gate of T11 is electrically connected to the first gate control terminal SELA, the source of T11 is electrically connected to the first data line D1, and the drain of T11 is electrically connected to the source driver S1;
the gate of T12 is electrically connected to the first gate control terminal SELA, the source of T11 is electrically connected to the second data line D2, and the drain of T11 is electrically connected to the source driver S1;
the gate of T1N is electrically connected to the first gate control terminal SELA, the source of T1N is electrically connected to the nth data line DN, and the drain of T1N is electrically connected to the source driver S1;
the gate of T21 is electrically connected to the second gate control terminal SELB, the source of T21 is electrically connected to the first data line D1, and the drain of T21 is electrically connected to the first dc voltage terminal VZ 1;
the gate of T22 is electrically connected to the second gate control terminal SELB, the source of T21 is electrically connected to the second data line D2, and the drain of T21 is electrically connected to the first direct current voltage terminal VZ 1;
the gate of T2N is electrically connected to the second gate control terminal SELA, the source of T2N is electrically connected to the nth data line DN, and the drain of T2N is electrically connected to the first dc voltage terminal VZ 1; the first dc voltage terminal VZ1 is used to provide a first dc voltage VDC 1.
In at least one embodiment of the display control module shown in fig. 7 of the present invention, all the transistors are n-type transistors, but not limited thereto.
When the at least one embodiment of the display control module of the present invention shown in fig. 7 is in operation, as shown in fig. 8, when the at least one embodiment of the display control module is in the low speed driving mode, the display period may include a refresh frame F1, a first hold frame F21, a second hold frame F22, a third hold frame F23, and a fourth hold frame F23;
in the refresh frame F1, the COE outputs a high voltage signal, CKA outputs a high voltage signal, CKB outputs a low voltage signal, SELA outputs a high voltage signal, SELB outputs a low voltage signal, T11, T12, T1N are turned on, T21, T22, and T2N are turned off, and the source driver S1 provides corresponding data voltages for the data lines;
in the first, second, third and fourth sustain frames F21, F22, F23 and F23, COE provides a high voltage signal, CKA provides a low voltage signal, CKB provides a high voltage signal, SELA outputs a low voltage signal, SEB outputs a high voltage signal, T11, T12 and T1N are turned off, T21, T22 and T2N are turned on, a first dc voltage terminal VZ1 provides a first dc voltage VDC1 for each data line, the influence of leakage of a data writing transistor to a first node (the first node is a node with the gate of a driving transistor) is reduced, and display is improved;
in the first, second, third and fourth sustain frames F21, F22, F23 and F23, the display screen is not substantially changed, the data voltage does not need to be updated, and the light emitting state needs to be maintained.
In at least one embodiment of the present invention, the second switching circuit includes a third switching unit circuit and a fourth switching unit circuit, the display device includes P reference voltage lines, P is a positive integer; the third switching unit circuit comprises P third switching transistors, and the fourth switching unit circuit comprises P fourth switching transistors; p is a positive integer less than or equal to P;
a control electrode of a p-th third switching transistor is electrically connected with the first gating control end, a first electrode of the p-th third switching transistor is electrically connected with a p-th reference voltage line, and a second electrode of the p-th third switching transistor is electrically connected with the source driver;
and the control electrode of the p-th fourth switching transistor is electrically connected with the second gating control end, the first electrode of the p-th fourth switching transistor is electrically connected with a p-th reference voltage line, and the second electrode of the p-th fourth switching transistor is electrically connected with the second direct-current voltage end.
Optionally, the P third switching transistors and the P fourth switching transistors are both n-type transistors, or the P third switching transistors and the P fourth switching transistors are both P-type transistors.
As shown in fig. 9, on the basis of at least one embodiment of the display control module shown in fig. 2, the gate control signal generating circuit 11 includes a first generating circuit and a second generating circuit;
the first generating circuit comprises a first transistor T1, a second transistor T2 and a first capacitor C1;
a gate of the first transistor T1 is electrically connected to the first control terminal COE, a source of the first transistor T1 is electrically connected to the first clock signal terminal CKA, and a drain of the first transistor T1 is electrically connected to the first gate control terminal SELA;
a gate of the second transistor T2 is electrically connected to the second clock signal terminal CKB, a source of the second transistor T2 is electrically connected to the first gate control terminal SELA, and a drain of the second transistor T2 is electrically connected to a low voltage terminal; the low voltage end is used for providing a low voltage VGL;
a first end of the first capacitor C1 is electrically connected to the first control terminal COE, and a second end of the first capacitor C1 is electrically connected to the first gate control terminal SELA;
the second generating circuit includes a third transistor T3, a fourth transistor T4, and a second capacitor C2;
a gate of the third transistor T3 is electrically connected to the first control terminal COE, a source of the third transistor T3 is electrically connected to the second gate control terminal SELB, and a drain of the third transistor T3 is electrically connected to the second clock signal terminal CKB;
a gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKA, a source of the fourth transistor T4 is electrically connected to the low voltage terminal, and a drain of the fourth transistor T4 is electrically connected to the second gate control terminal SELB;
a first end of the second capacitor C2 is electrically connected to the first control terminal COE, and a second end of the second capacitor C2 is electrically connected to the second gate control terminal SELB;
the second switching circuit includes a third switching unit circuit 83 and a fourth switching unit circuit 84, the display device includes P reference voltage lines, P is a positive integer;
the third switching unit circuit 83 includes P third switching transistors, and the fourth switching unit circuit includes P fourth switching transistors;
in fig. 9, reference numeral T31 denotes a first third switching transistor, reference numeral T32 denotes a second third switching transistor, and reference numeral T3P denotes a pth third switching transistor; a first fourth switch transistor is marked as T41, a second fourth switch transistor is marked as T42, and a pth fourth switch transistor is marked as T4P;
the gate of the T31 is electrically connected to the first gate control terminal SELA, the source of the T31 is electrically connected to the first reference voltage line R1, and the drain of the T31 is electrically connected to the source driver S1;
the gate of the T32 is electrically connected to the first gate control terminal SELA, the source of the T32 is electrically connected to the second reference voltage line R2, and the drain of the T32 is electrically connected to the source driver S1;
the gate of T3P is electrically connected to the first gate control terminal SELA, the source of T3P is electrically connected to the pth reference voltage line RP, and the drain of T3P is electrically connected to the source driver S1;
the gate of T41 is electrically connected to the second gate control terminal SELB, the source of T41 is electrically connected to the first reference voltage line R1, and the drain of T41 is electrically connected to the second dc voltage terminal VZ 2;
the gate of T42 is electrically connected to the second gate control terminal SELB, the source of T42 is electrically connected to the second reference voltage line R2, and the drain of T42 is electrically connected to the second dc voltage terminal VZ 2;
the gate of T4P is electrically connected to the second gate control terminal SELB, the source of T4P is electrically connected to the pth reference voltage line RP, and the drain of T4P is electrically connected to the second dc voltage terminal VZ 2.
In at least one embodiment of the display control module shown in fig. 9, all the transistors are n-type thin film transistors, but not limited thereto.
In operation of at least one embodiment of the display control module of the present invention as shown in FIG. 9, as shown in FIG. 8, when the at least one embodiment of the display control module enters a low speed driving mode, the display period may include a refresh frame F1, a first hold frame F21, a second hold frame F22, a third hold frame F23 and a fourth hold frame F23;
in the refresh frame F1, the COE outputs a high voltage signal, CKA outputs a high voltage signal, CKB outputs a low voltage signal, SELA outputs a high voltage signal, SELB outputs a low voltage signal, T31, T32, T3P are turned on, T41, T42, T4P are turned off, and the source driver S1 provides a corresponding data voltage for each reference voltage line;
in the first, second, third and fourth sustain frames F21, F22, F23 and F23, COE provides a high voltage signal, CKA provides a low voltage signal, CKB provides a high voltage signal, SELA outputs a low voltage signal, SEB outputs a high voltage signal, T31, T32 and T3P are turned off, T41, T42 and T4P are turned on, a second dc voltage terminal VZ2 provides a second dc voltage Vref _ h for each reference voltage line, the leakage effect of the compensation control transistor on a first node (the first node is a node with the gate of the driving transistor) is reduced, and the display image quality is improved;
during the first, second, third and fourth sustain frames F21, F22, F23 and F23, the low-speed driving period is entered, i.e., the display screen is not substantially changed, the data voltage does not need to be updated, and the light-emitting state needs to be maintained.
The display control module according to at least one embodiment of the present invention may further include a dc module;
the direct current module is respectively electrically connected with the first direct current voltage end and the second direct current voltage end and is used for providing first direct current voltage for the first direct current voltage end and providing second direct current voltage for the second direct current voltage end.
As shown in fig. 10, on the basis of at least one embodiment of the display control module shown in fig. 7, the display control module according to at least one embodiment of the present invention further includes a dc module DCB;
the dc module DCB is electrically connected to the first dc voltage terminal VZ1, and is configured to provide a first dc voltage VDC1 to the first dc voltage terminal VZ 1.
As shown in fig. 11, on the basis of at least one embodiment of the display control module shown in fig. 9, the display control module according to at least one embodiment of the present invention further includes a dc module DCB;
the dc module DCB is electrically connected to the second dc voltage terminal VZ2, and is configured to provide a second dc voltage Vref _ h to the second dc voltage terminal VZ 2.
The display control method according to the embodiment of the present invention is applied to the display control module described above, and the display control method includes:
the source driver receives an image signal to be displayed, and judges whether the image signal to be displayed changes or not when a display period begins;
when the image signal to be displayed does not change, detecting that the display control module enters a low-speed driving mode, and setting the display period to comprise a refresh frame and at least one retention frame which are successively set;
in the refresh frame, controlling a first control signal, a first clock signal and a second clock signal to enable the gating control signal generating circuit to provide a first gating control signal and a first second gating control signal, and controlling a source driver to provide corresponding data voltages to data lines by a first switch circuit under the control of the first gating control signal and the first second gating control signal;
and in the holding frame, the first control signal, the first clock signal and the second clock signal are controlled to enable the gating control signal generating circuit to provide a second first gating control signal and a second gating control signal, and the first switch circuit controls the first direct-current voltage end to provide the first direct-current voltage for the data line under the control of the second first gating control signal and the second gating control signal.
Optionally, the display panel further includes a plurality of reference voltage lines; the display control module further comprises a second switch circuit; the display control method further includes:
the second switching circuit controls the supply of the reference voltage to the reference voltage line by the source driver under the control of the first gate control signal and the first second gate control signal in the refresh frame;
the second switching circuit controls the supply of the second dc voltage from the second dc voltage terminal to the reference voltage line under the control of the second first gate control signal and the second gate control signal in the holding frame.
In the display control method according to the embodiment of the present invention, as shown in fig. 12, when a display period starts, it is determined whether an image signal to be displayed changes, if so, a normal driving mode is entered, and if not, a low-speed driving mode is entered; after entering a low-speed driving mode, refreshing a frame firstly, and then entering a maintaining frame; judging whether the holding frame is terminated or not, if so, entering an external power supply, providing a first direct-current voltage for each data line by a first direct-current voltage end, and providing a second direct-current voltage for each reference voltage line by a second direct-current voltage end; if the holding frame is judged to be terminated, whether the low-speed driving mode is terminated is continuously judged, if not, the refresh frame is entered again, and if the low-speed driving mode is terminated, the refreshing frame is ended and then the operation is started again.
The display control method according to at least one embodiment of the present invention further includes:
when the image signal to be displayed changes, in the display period, the gate control signal generation circuit provides a first gate control signal and a first second gate control signal by controlling a first control signal, a first clock signal and a second clock signal, the first switch circuit controls the source driver to provide corresponding data voltages to the plurality of data lines respectively under the control of the first gate control signal and the first second gate control signal, and the second switch circuit controls the source driver to provide reference voltages to the plurality of reference voltage lines respectively under the control of the first gate control signal and the first second gate control signal.
In specific implementation, when the image signal to be displayed changes, the conventional driving mode is entered, the source driver provides corresponding data voltages to the data lines, and the source driver provides reference voltages to the reference voltage lines.
The embodiment of the invention also provides a display device which comprises the display control module.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A display control module is applied to a display device, the display device comprises a display panel, and the display panel comprises a plurality of data lines; the display control module comprises a gating control signal generating circuit and a first switch circuit;
the gating control signal generating circuit is respectively electrically connected with a first control end, a first clock signal end, a second clock signal end, a first voltage end, a first gating control end and a second gating control end, and is used for controlling the first gating control end to provide a first gating control signal and controlling the second gating control end to provide a second gating control signal under the control of a first control signal provided by the first control end, a first clock signal provided by the first clock signal end and a second clock signal provided by the second clock signal end;
the first switch circuit is electrically connected with the first gating control end, the second gating control end, the first direct current voltage end, the source driver and the data line respectively, and is used for controlling the source driver to provide data voltage for the data line under the control of the first gating control signal and the second gating control signal, or controlling the first direct current voltage end to provide the first direct current voltage for the data line.
2. The display control module of claim 1, wherein the display panel further comprises a plurality of reference voltage lines; the display control module further comprises a second switch circuit;
the second switch circuit is electrically connected to the first gate control terminal, the second dc voltage terminal, the source driver, and the reference voltage line, respectively, and is configured to control the source driver to provide the reference voltage line with the reference voltage under the control of the first gate control signal and the second gate control signal, or the second dc voltage terminal to provide the reference voltage line with the second dc voltage.
3. The display control module of claim 1, wherein the gate control signal generating circuit includes a first generating circuit and a second generating circuit;
the first generating circuit is respectively electrically connected with the first control end, the first clock signal end, the second clock signal end, the first gating control end and the first voltage end, and is used for controlling the communication between the first gating control end and the first clock signal end under the control of the first control signal and controlling the communication between the first gating control end and the first voltage end under the control of the second clock signal provided by the second clock signal end;
the second generating circuit is respectively electrically connected with the first control end, the first clock signal end, the second gating control end and the first voltage end, and is used for controlling the communication between the second gating control end and the second clock signal end under the control of the first control signal and controlling the communication between the second gating control end and the first voltage end under the control of the first clock signal provided by the first clock signal end.
4. The display control module of claim 3, wherein the first generation circuit comprises a first transistor, a second transistor, and a first capacitor;
a control electrode of the first transistor is electrically connected with the first control end, a first electrode of the first transistor is electrically connected with the first clock signal end, and a second electrode of the first transistor is electrically connected with the first gating control end;
a control electrode of the second transistor is electrically connected with the second clock signal end, a first electrode of the second transistor is electrically connected with the first gating control end, and a second electrode of the second transistor is electrically connected with the first voltage end;
a first end of the first capacitor is electrically connected with the first control end, and a second end of the first capacitor is electrically connected with the first gating control end;
the second generation circuit comprises a third transistor, a fourth transistor and a second capacitor;
a control electrode of the third transistor is electrically connected with the first control end, a first electrode of the third transistor is electrically connected with the second gating control end, and a second electrode of the third transistor is electrically connected with the second clock signal end;
a control electrode of the fourth transistor is electrically connected with the first clock signal end, a first electrode of the fourth transistor is electrically connected with the first voltage end, and a second electrode of the fourth transistor is electrically connected with the second gating control end;
and the first end of the second capacitor is electrically connected with the first control end, and the second end of the second capacitor is electrically connected with the second gating control end.
5. The display control module of claim 1, wherein the first switch circuit includes a first switch cell circuit and a second switch cell circuit, the display device includes N data lines, N is a positive integer; the first switching unit circuit includes N first switching transistors, and the second switching unit circuit includes N second switching transistors; n is a positive integer less than or equal to N;
a control electrode of the nth first switching transistor is electrically connected with the first gating control end, a first electrode of the nth first switching transistor is electrically connected with the nth data line, and a second electrode of the nth first switching transistor is electrically connected with the source electrode driver;
the control electrode of the nth second switching transistor is electrically connected with the second gating control end, the first electrode of the nth second switching transistor is electrically connected with the nth data line, and the second electrode of the nth second switching transistor is electrically connected with the first direct current voltage end.
6. The display control module of claim 5, wherein the N first switching transistors and the N second switching transistors are all N-type transistors or wherein the N first switching transistors and the N second switching transistors are all p-type transistors.
7. The display control module according to claim 2, wherein the second switch circuit comprises a third switch unit circuit and a fourth switch unit circuit, the display device comprises P reference voltage lines, P being a positive integer; the third switching unit circuit comprises P third switching transistors, and the fourth switching unit circuit comprises P fourth switching transistors; p is a positive integer less than or equal to P;
a control electrode of a p-th third switching transistor is electrically connected with the first gating control end, a first electrode of the p-th third switching transistor is electrically connected with a p-th reference voltage line, and a second electrode of the p-th third switching transistor is electrically connected with the source driver;
and the control electrode of the p-th fourth switching transistor is electrically connected with the second gating control end, the first electrode of the p-th fourth switching transistor is electrically connected with a p-th reference voltage line, and the second electrode of the p-th fourth switching transistor is electrically connected with the second direct-current voltage end.
8. The display control module of claim 7, wherein the P third and fourth switching transistors are both n-type transistors or the P third and fourth switching transistors are both P-type transistors.
9. The display control module of any one of claims 2 to 8, further comprising a direct current module;
the direct current module is respectively electrically connected with the first direct current voltage end and the second direct current voltage end and is used for providing first direct current voltage for the first direct current voltage end and providing second direct current voltage for the second direct current voltage end.
10. A display control method applied to the display control module according to any one of claims 1 to 9, characterized by comprising:
the source driver receives an image signal to be displayed, and judges whether the image signal to be displayed changes or not when a display period starts;
when the image signal to be displayed does not change, detecting that the display control module enters a low-speed driving mode, and setting the display period to comprise a refresh frame and at least one retention frame which are successively set;
in the refresh frame, controlling a first control signal, a first clock signal and a second clock signal to enable the gating control signal generating circuit to provide a first gating control signal and a first second gating control signal, and controlling a source driver to provide corresponding data voltages to data lines by a first switch circuit under the control of the first gating control signal and the first second gating control signal;
and in the holding frame, the first control signal, the first clock signal and the second clock signal are controlled to enable the gating control signal generating circuit to provide a second first gating control signal and a second gating control signal, and the first switch circuit controls the first direct-current voltage end to provide the first direct-current voltage for the data line under the control of the second first gating control signal and the second gating control signal.
11. The display control method of claim 10, wherein the display panel further comprises a plurality of reference voltage lines; the display control module further comprises a second switch circuit; the display control method further includes:
the second switching circuit controls the supply of the reference voltage to the reference voltage line by the source driver under the control of the first gate control signal and the first second gate control signal in the refresh frame;
the second switching circuit controls the supply of the second dc voltage from the second dc voltage terminal to the reference voltage line under the control of the second first gate control signal and the second gate control signal in the holding frame.
12. The display control method according to claim 11, further comprising:
when the image signal to be displayed changes, in the display period, the gating control signal generation circuit is enabled to provide a first gating control signal and a first second gating control signal by controlling a first control signal, a first clock signal and a second clock signal, the first switch circuit is controlled by the first gating control signal and the first second gating control signal to provide corresponding data voltages for the plurality of data lines respectively through the source driver, and the second switch circuit is controlled by the source driver to provide reference voltages for the plurality of reference voltage lines respectively through the first gating control signal and the first second gating control signal.
13. A display apparatus comprising the display control module according to any one of claims 1 to 9.
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| CN202210312809.2A CN114664219A (en) | 2022-03-28 | 2022-03-28 | Display control module, method and display device |
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| CN202210312809.2A CN114664219A (en) | 2022-03-28 | 2022-03-28 | Display control module, method and display device |
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