CN112397026B

CN112397026B - Pixel driving circuit, display panel and driving method thereof

Info

Publication number: CN112397026B
Application number: CN202011412419.XA
Authority: CN
Inventors: 张蒙蒙; 周星耀
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2022-06-28
Anticipated expiration: 2040-12-04
Also published as: CN112397026A; US20220180810A1; US11961477B2

Abstract

The invention discloses a pixel driving circuit, a display panel and a driving method thereof, relating to the technical field of display, wherein the pixel driving circuit comprises: a first power signal terminal and a second power signal terminal; a driving transistor, the grid of which is connected to the first node, the first pole of which is connected to the second node, and the second pole of which is connected to the third node; a light emitting element connected in series between the driving transistor and a second power signal terminal; the light-emitting control module is connected between the first power signal end and the light-emitting element in series, and the control end of the light-emitting control module is connected with the first output end of the light-emitting control circuit; and the bias module is electrically connected to the third node and the second output end of the light-emitting control circuit, responds to the first control signal, and is used for transmitting the first signal output by the light-emitting control circuit to the third node to adjust the bias state of the driving transistor. Therefore, the flicker phenomenon in the picture switching process is favorably improved, and the picture display effect is improved.

Description

Pixel driving circuit, display panel and driving method thereof

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel driving circuit, a display panel and a driving method thereof.

Background

The organic light emitting display device has advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, light weight, and high contrast, and is considered to be the most promising display device of the next generation. Organic light emitting display devices are increasingly used in other display devices having a display function, such as mobile phones, computers, televisions, vehicle-mounted display devices, and wearable devices.

The pixel in the organic light-emitting display device comprises a pixel driving circuit, a driving transistor in the pixel driving circuit can generate a driving current, and a light-emitting element emits light in response to the driving current, wherein the driving current generated by the driving transistor is related to the potential of a grid electrode of the driving transistor, and the grid electrode of the driving transistor is connected with a storage capacitor.

Due to the characteristics of the driving transistor, in the process of switching the display device, the driving transistor is affected by the previous frame of picture data, so that the display picture cannot be quickly switched to the preset picture, a flicker phenomenon occurs, and the display effect is affected.

Disclosure of Invention

In view of this, the present invention provides a pixel driving circuit, a display panel and a driving method thereof, which are beneficial to improving a flicker phenomenon occurring in a picture switching process and improving a picture display effect.

In a first aspect, the present application provides a pixel driving circuit, comprising:

the power supply comprises a first power supply signal end and a second power supply signal end, wherein the first power supply signal end receives a first voltage signal, and the second power supply signal end receives a second voltage signal;

a driving transistor for providing a driving current during a light emitting period; the grid electrode of the SulIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIuIu;

a light emitting element connected in series between the driving transistor and the second power signal terminal for emitting light in response to a driving current;

the light-emitting control module is connected between a first power signal end and the light-emitting element in series, and a control end of the light-emitting control module is connected with a first output end of the light-emitting control circuit;

and the bias module is electrically connected with the third node and the second output end of the light-emitting control circuit, responds to a first control signal, and is used for transmitting the first signal output by the light-emitting control circuit to the third node to adjust the bias state of the driving transistor.

In a second aspect, the present application provides a display panel including the pixel driving circuit provided by the present invention.

In a third aspect, the present application further provides a driving method of a display panel, which is suitable for the display panel provided by the present invention, where the display panel includes a driving transistor, a data writing module, a compensation module, a light emission control module, a bias module, and a light emitting element;

the driving transistor is used for providing a driving current in a light-emitting stage; the grid electrode of the driving transistor is connected to a first node, the first pole of the driving transistor is connected to a second node, and the second pole of the driving transistor is connected to a third node;

the light-emitting control module is connected between the driving transistor and the light-emitting element in series, and the control end of the light-emitting control module is connected with the first output end of the light-emitting control circuit;

the bias module is electrically connected to the third node and the second output end of the light-emitting control circuit;

the driving period of the display panel comprises a first bias voltage phase, a data writing phase and a light-emitting phase;

the driving method includes:

in the first bias stage, responding to a first control signal, transmitting a first signal output by a light-emitting control circuit to the third node, and adjusting the bias state of the driving transistor;

In the data writing phase, the data writing module is used for providing a data signal to the driving transistor; the compensation module is used for detecting and self-compensating the deviation of the threshold voltage of the driving transistor;

in the light emitting stage, the light emitting element emits light in response to the driving current.

Compared with the prior art, the pixel driving circuit, the display panel and the driving method thereof at least realize the following beneficial effects:

in the pixel driving circuit, the display panel and the driving method thereof, the bias module is introduced, the first end of the bias module is connected with the third node in the pixel driving circuit, and the second end of the bias module is connected with the second output end of the light-emitting control circuit; the bias module is used for adjusting the bias state of the driving transistor under the control of the first control signal and the first signal output by the second output end of the light-emitting control circuit, so that the bias state of the driving transistor is kept fixed before the light-emitting element emits light, and the characteristic when the driving transistor is switched between different pictures (for example, a white picture is switched to a black picture or a black picture is switched to the white picture) is kept consistent with the characteristic when the driving transistor is switched between the same pictures (for example, the white picture is switched to the white picture or the black picture is switched to the black picture). In the related art, in the process of switching the display screen, the driving transistor is affected by the data of the previous frame, and cannot generate the driving current corresponding to the preset switching screen, so that the display screen cannot be quickly switched to the preset switching screen. Before the picture is switched, the bias state of the driving transistor is adjusted to be a fixed state through the bias module, so that the driving transistor is not influenced by the data of the previous frame of picture, the driving current corresponding to the preset switching picture can be generated, and the picture is quickly switched to the preset switching picture, thereby being beneficial to improving the flicker phenomenon in the picture switching process and improving the display effect.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a frame structure of a pixel driving circuit according to an embodiment of the invention;

FIG. 2 is a characteristic curve of a driving transistor under different frames;

fig. 3 is a circuit diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 6 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 7 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 8 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

Fig. 9 is a schematic diagram illustrating another structure of a pixel driving circuit according to an embodiment of the invention;

fig. 10 is a schematic view of a display panel according to an embodiment of the present disclosure;

fig. 11 is a flowchart illustrating a driving method of a display panel according to an embodiment of the invention;

FIG. 12 is a flow chart illustrating a pixel driving method according to an embodiment of the invention;

FIG. 13 is a timing diagram of the pixel driving circuit of FIG. 3;

FIG. 14 is a timing diagram of an operation of the pixel driving circuit of FIG. 5;

FIG. 15 is a timing diagram of an operation of the pixel driving circuit of FIG. 4;

fig. 16 is a schematic diagram illustrating another structure of a pixel driving circuit according to an embodiment of the invention;

FIG. 17 is a timing diagram of an operation corresponding to the pixel driving circuit of FIG. 16;

fig. 18 is a schematic diagram illustrating another structure of a pixel driving circuit according to an embodiment of the invention;

FIG. 19 is a timing diagram of an operation of the pixel driving circuit of FIG. 18;

FIG. 20 is a timing diagram illustrating another operation of the pixel driving circuit of FIG. 3;

fig. 21 is a timing chart corresponding to the pixel driving circuit of fig. 9.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Fig. 1 is a schematic diagram of a frame structure of a pixel driving circuit according to an embodiment of the present invention, and referring to fig. 1, the embodiment of the present invention provides a pixel driving circuit 100, including:

The power supply circuit comprises a first power supply signal end PVDD and a second power supply signal end PVEE, wherein the first power supply signal end PVDD receives a first voltage signal, and the second power supply signal end PVEE receives a second voltage signal;

a driving transistor M0, the driving transistor M0 being used for providing a driving current during a light emitting period, a gate of the driving transistor M0 being connected to a first node N1, a first pole of the driving transistor M0 being connected to a second node N2, and a second pole of the driving transistor M0 being connected to a third node N3;

a light emitting element D1 connected in series between the driving transistor M0 and the second power signal terminal PVEE, for emitting light in response to a driving current;

a light emitting control module 10 connected in series between a first power signal terminal PVDD and the light emitting element D1, wherein a control terminal of the light emitting control module 10 is connected to a first output terminal Out1 of a light emitting control circuit;

a bias module 20, the bias module 20 being electrically connected to the third node N3 and the second output terminal Out2 of the light emitting control circuit, and being configured to transmit a first signal output by the light emitting control circuit to the third node N3 in response to a first control signal, so as to adjust a bias state of the driving transistor M0.

It should be noted that fig. 1 only shows one frame structure of the pixel driving circuit 100 in this application, and in some other embodiments of the application, the frame structure of the pixel driving circuit 100 may also be embodied as other structures, which is not specifically limited in this application.

Specifically, in the pixel driving circuit 100 provided by the present invention, the driving transistor M0, the light emitting element D1 and the light emitting control module 10 are provided, wherein the driving transistor M0 is used for supplying a driving current to the light emitting element D1 in a light emitting phase; the light emitting element D1 is for emitting light in response to a driving current under the control of the light emitting control module 10. Particularly, the pixel driving circuit 100 provided by the present invention further includes a bias module 20, a first end of the bias module 20 is connected to the third node N3 in the pixel driving circuit 100, a second end is connected to the second output end Out2 of the light-emitting control circuit, and a control end receives the first control signal; the bias module 20 is configured to transmit the first signal output by the light-emitting control circuit to the third node N3 under the control of the first control signal, so as to adjust the bias state of the driving transistor M0.

Fig. 2 shows a characteristic curve of the driving transistor M0 under different images, and the present invention is described by taking the first electrode of the driving transistor as the source electrode, the second electrode of the driving transistor as the drain electrode, and the control terminal of the driving transistor as the gate electrode. When the driving circuit periodically performs display, the gate potential of the driving transistor M0 may be greater than the drain potential of the driving transistor M0 in a non-bias stage such as non-light emission of the pixel circuit, and long-term arrangement may cause polarization of ions inside the driving transistor M0, which causes the threshold voltage of the driving transistor M0 to increase continuously, which causes deviation of Ids-Vgs curve, thereby affecting the driving current flowing into the light emitting element, and further affecting the display uniformity. For example, the characteristic curve of the driving transistor M0 in the black frame is L1, and the corresponding threshold voltage is Vth 1; the driving transistor M0 has a characteristic curve L2 and a corresponding threshold voltage Vth2 in a white screen. In the related art, during the switching of the image, the characteristic curve of the driving transistor M0 is affected by the previous frame of image data, and the driving current corresponding to the preset switching image cannot be generated, so that the display image cannot be switched to the preset switching image quickly, for example, a gray image between a black image and a white image appears before the black image is switched to the white image, and the image flicker phenomenon appears, which affects the display effect.

The bias module 20 is introduced to adjust the bias state of the driving transistor M0, so that the potential difference between the gate potential and the drain potential of the driving transistor M0 is improved, the internal ionization degree of the driving transistor M0 is weakened, the threshold voltage of the driving transistor M0 is reduced, and the adjustment of the threshold voltage of the driving transistor M0 is realized by biasing the driving transistor M0. Therefore, in some embodiments of the present invention, in the bias stage, the potential difference between the gate potential and the drain potential of the driving transistor M0 may be adjusted by the bias module 20 to change the internal characteristic of the driving transistor M0 to balance the influence of the gate potential of the driving transistor M0 being greater than the drain potential of the driving transistor M0 in the non-bias stage on the internal characteristic of the driving transistor, and before the picture switching, the bias state of the driving transistor M0 is adjusted to be a fixed state, so that the driving transistor is not influenced by the previous frame of picture data, and can still generate the driving current corresponding to the preset switching picture, so that the picture is quickly switched to the preset switching picture, which is beneficial to improving the flicker phenomenon occurring in the picture switching process and enhancing the display effect.

When the bias state of the driving transistor is adjusted before the picture is switched, the bias state of the driving transistor can be adjusted to be a negative bias state or a positive bias state.

The present invention will be further explained from the point of view of the voltage variation of the different nodes of the driving transistor M0, taking the driving transistor M0 adjusted to the negative bias state as an example. The driving transistor M0 is exemplified as a P-type transistor in the present invention, but it is to be understood that the driving transistor M0 may also be embodied as an N-type transistor in some other embodiments, which is not specifically limited in the present invention. Taking the driving transistor M0 as a P-type transistor as an example, in the black screen, the potential of the first node N1 is high, the potential of the second node N2 is the same as the potential of the first voltage signal terminal, and the potential of the third node N3 is 0. In a white screen, the potentials of the first node N1 and the third node N3 are both 0, and the potential of the second node N2 is the same as the potential of the first power signal terminal PVDD. After the driving transistor M0 is reset, the potentials of the second node N2 and the third node N3 are both low, when the third node N3 and the second node N2 of the driving transistor M0 are compensated by the bias module 20, the potentials of the second node N2 and the third node N3 become high, so that the voltage difference between the second node N3 and the first node N1 becomes large, when the voltage difference between the second node N3 and the first node N1 becomes large, the internal characteristic of the driving transistor M0 is changed to balance the influence on the internal characteristic of the driving transistor when the gate potential of the driving transistor M0 is greater than the drain potential of the driving transistor M0 in the non-bias stage, the bias state of the driving transistor is adjusted to be a fixed state, so that the driving transistor is not influenced by the previous frame data, and the driving current corresponding to the preset switching frame can still be generated, and the frame is rapidly switched to the preset switching frame, therefore, the flicker phenomenon in the picture switching process is improved, and the display effect is improved.

In addition, in the pixel driving circuit 100 provided by the present invention, after the bias module 20 is introduced, the second output terminal Out2 of the bias module 20, which is connected to the light-emitting control circuit, is directly multiplexed with the output terminal of the light-emitting control circuit and is used as the signal input terminal of the bias module 20, and there is no need to introduce a new signal terminal into the pixel driving circuit 100, which is favorable for simplifying the circuit complexity after the bias module 20 is introduced into the pixel driving circuit 100.

In an alternative embodiment of the present invention, with continued reference to fig. 1, the pixel driving circuit 100 further includes a compensation module 30, wherein the compensation module 30 is connected in series between the first node N1 and the third node N3, and is used for detecting and self-compensating a deviation of the threshold voltage of the driving transistor M0.

Specifically, in the present invention, the compensation module 30 is introduced between the first node N1 and the third node N3 of the driving transistor M0, and in the data writing phase of the pixel driving circuit 100, the data voltage can be written into the first node N1 from the third node N3 through the compensation module 30, so as to achieve detection and self-compensation of the deviation of the threshold voltage of the driving transistor M0, so that the threshold voltage of the driving transistor M0 is closer to the preset threshold voltage value, so that the driving current generated by driving is closer to the preset driving current, and the light-emitting element D1 is made to emit light according to the preset brightness, thereby being beneficial to improving the accuracy of the light-emitting brightness of the light-emitting element D1.

In an alternative embodiment of the invention, taking fig. 3 as an example, please refer to fig. 3, and fig. 3 is a circuit schematic diagram of the pixel driving circuit 100 according to the embodiment of the invention, in which the compensation module 30 includes a first transistor M1, a first end of the first transistor M1 is connected to the first node N1, a second end of the first transistor M1 is connected to the third node N3, and a control end of the first transistor M1 is connected to the second control signal terminal S2.

Specifically, fig. 3 shows an embodiment in which the compensation module 30 includes a first transistor M1, a first terminal and a second terminal of the first transistor M1 are respectively connected to a first node N1 and a third node N3 of the driving transistor M0, a control terminal is connected to a second control signal terminal S2, and the compensation module 30 in the present invention is formed by using the first transistor M1, so that the structure is simple, and the circuit structure of the pixel driving circuit 100 is simplified while the threshold voltage of the driving transistor M0 is detected and self-compensated.

In an alternative embodiment of the present invention, taking fig. 3 as an example, please refer to fig. 3 continuously, the bias module 20 includes a second transistor M2, a first end of the second transistor M2 is connected to the third node N3, a second end is connected to the second output end Out2 of the light-emitting control circuit, and a control end is connected to the first control signal end S1.

In particular, the embodiment shown in FIG. 3 also illustrates a refinement of the bias module 20. The bias module 20 includes a second transistor M2, a control terminal of the second transistor M2 is connected to a first control signal terminal S1, and the second transistor M2 can be controlled to be turned on or turned off by the first control signal terminal S1. In the bias stage, the second transistor M2 is controlled to be turned on, the second output terminal Out2 of the light emitting control circuit inputs a first signal to the third node N3 and the second node N2 of the driving transistor M0, when the driving transistor M0 is a P-type transistor, the first signal at this time is a high level signal, and when the voltage of the first node N1 of the driving transistor M0 is kept unchanged and the voltages of the second node N2 and the third node N3 thereof are increased, the voltage difference between the second node N2 and the first node N1 of the driving transistor M0 is increased, so as to change the internal characteristics of the driving transistor M0 to balance the influence of the gate potential of the driving transistor M0 in the non-bias stage on the driving transistor characteristics when the gate potential of the driving transistor M0 is higher than the drain potential of the driving transistor M0, so that the driving transistor M0 is kept in the picture switching stage in a fixed bias state, and is not influenced by the previous frame data, and still generates the driving current corresponding to the preset picture switching, the picture is quickly switched to the preset switching picture, so that the flicker phenomenon in the picture switching process is favorably improved, and the display effect is improved.

In an alternative embodiment of the present invention, with continued reference to fig. 3, the compensation module 30 and the bias module 20 are reused as a first node reset module for resetting the first node N1.

Specifically, during the reset phase of the pixel driving circuit 100, the compensation module 30 and the bias module 20 are turned on, and the output end E2 of the light emitting control circuit connected to the second end of the bias module 20 can output a low level signal, which is transmitted to the first node N1 of the driving transistor M0 via the bias module 20 and the compensation module 30, so as to reset the first node N1 of the driving transistor M0. In this embodiment, after the bias module 20 is introduced into the pixel driving circuit 100, the compensation module 30 and the bias module 20 are reused as the first node reset module, and there is no need to introduce a separate first node reset module into the pixel driving circuit 100, and the existing module structure is reused, so that the circuit structure of the pixel driving circuit 100 is simplified, and the manufacturing process of the pixel driving circuit 100 is simplified.

In addition, in this embodiment, since the first node N1 of the driving transistor M0 is electrically connected to the storage capacitor C0 and the first transistor M1 respectively, the first node N1 only has one drain path connected to the first transistor M1, so that the drain path of the first node N1 is effectively reduced, the potential of the first node N1 is maintained, and the driving current generated by the driving transistor M0 during the light-emitting period is more accurate.

In an alternative embodiment of the present invention, the first transistor M1 includes an oxide transistor.

Specifically, considering that the off-state leakage current of the oxide transistor is small, since the first transistor M1 in the present invention is electrically connected to the first node N1 of the driving transistor M0, when the first transistor M1 is selected as an oxide transistor in the present invention, the drain current path of the first node N1 is reduced, and at the same time, the variation range of the potential of the first node N1 can be effectively reduced, that is, the potential of the first node N1 of the driving transistor M0 is maintained, so that the driving current generated by the driving transistor M0 is more accurate. When the first transistor M1 is selected as an oxide transistor, the oxide transistor is turned on when its gate is high.

Optionally, in some other embodiments of the present invention, the first transistor M1 may also be selected as a P-type transistor, and when the first transistor M1 is selected as a P-type transistor, the P-type transistor is turned on when its gate is low, that is, when the first transistor M1 is selected as an oxide transistor or a P-type transistor, in order to achieve the turning on of the first transistor M1, the signal provided by the second control signal terminal S2 to the first transistor M1 of different type is opposite.

In an alternative embodiment of the present invention, taking fig. 3 as an example, please refer to fig. 3 continuously, the pixel driving circuit 100 further includes a power voltage writing module 80, the power voltage writing module 80 includes a third transistor M3, the third transistor M3 is connected in series between the first power signal terminal PVDD and the first node N1, and a control terminal of the third transistor M3 is electrically connected to the third output terminal Out3 of the light emitting control circuit.

Specifically, the embodiment shown in fig. 3 also shows a scheme that the pixel driving circuit 100 includes a power supply voltage writing module 80, and the power supply voltage writing module 80 is configured to write the first voltage signal output from the first power supply signal terminal PVDD to the driving transistor M0 in the light emitting phase. In this embodiment, the power voltage writing module 80 includes the third transistor M3 for example, the third transistor M3 is connected in series between the first power signal terminal PVDD and the second node N2, the third transistor M3 is turned on during the light emitting period, the first power signal terminal PVDD transmits the first voltage signal to the driving transistor M0, and the driving transistor M0 generates the driving current for driving the light emitting element D1 to emit light.

In an alternative embodiment of the present invention, the light emission control circuit includes a plurality of light emission control circuit units cascaded; the third output terminal of the light emission control circuit multiplexes the first output terminal of the light emission control circuit; or the third output end of the light-emitting control circuit and the first output end of the light-emitting control circuit correspond to the output ends of the light-emitting control circuit units of different stages respectively.

Specifically, referring to fig. 3, in this embodiment, the control terminal of the third transistor M3 is connected to the third output terminal Out3 of the light-emitting control circuit, and the third output terminal corresponds to the output terminal E1 of the nth-stage light-emitting control circuit unit in the light-emitting control circuit; the first output terminal Out1 and the second output terminal Out2 of the light-emitting control circuit correspond to the output terminal E2 of the light-emitting control circuit unit of the (n + 1) th stage in the light-emitting control circuit. In some other embodiments of the present invention, the first output terminal Out1, the second output terminal Out2, and the third output terminal Out3 of the lighting control circuit may also correspond to the output terminals of the same level of lighting control circuit unit, which will be described in detail in the following embodiments of the present invention.

In an alternative embodiment of the present invention, please continue to refer to fig. 3, the light emitting control module includes a fourth transistor M4, the fourth transistor M4 is connected in series between the light emitting element D1 and the third node N3, and a control end of the fourth transistor M4 is electrically connected to a first output end Out1 of the light emitting control circuit.

Specifically, the fourth transistor M4 is turned on or off under the control of the output signal of the first output terminal Out1 of the light emission control circuit. In the light emitting stage, the first output terminal Out1 of the light emitting control circuit is turned on under the control of the output signal, and the driving current generated by the driving transistor M0 is transmitted to the light emitting element D1, so as to control the light emitting element D1 to emit light.

Alternatively, the present invention is illustrated by taking as an example that the third transistor M3 and the fourth transistor M4 are both P-type transistors, and the P-type transistors are turned on when their gates are at a low level. Referring to fig. 3, in the bias phase, the bias module 20 is turned on, the output terminal E2 of the light emitting control circuit transmits a high level signal to the second node N2 and the third node N3 of the driving transistor M0, when the output terminal E2 of the light emitting control circuit is a high level signal, the control terminal of the fourth transistor M4 is kept in the off state under the control of the high level signal, and at this time, the output terminal E1 of the light emitting control circuit connected to the control terminal of the third transistor M3 is also a high level signal, and the third transistor M3 is controlled to be kept in the off state. In the light emitting stage, the bias module 20 is turned off, and the output terminal E2 of the light emitting control circuit electrically connected to the control terminal of the fourth transistor M4 and the output terminal E1 of the light emitting control circuit electrically connected to the control terminal of the third transistor M3 both represent low level signals, and respectively control the fourth transistor M4 and the third transistor M3 to be turned on. Thus, multiplexing of the signal terminal electrically connected to the second terminal of the bias module 20 and the control terminal of the fourth transistor M4 is achieved, which is beneficial to simplifying the structure of the pixel driving circuit 100.

In an optional embodiment of the present invention, the second output terminal Out2 of the light-emitting control circuit multiplexes the first output terminal Out1 of the light-emitting control circuit, please refer to fig. 3, the first output terminal Out1 and the second output terminal Out2 of the light-emitting control circuit both correspond to the same output terminal E2 of light-emitting control, which is equivalent to that the same signal output terminal of the multiplexed light-emitting control circuit provides an input signal for the bias module 20 and a light-emitting control signal for the light-emitting control module 10, thereby being beneficial to reducing the number of signal input terminals after introducing the bias module into the pixel driving circuit. In the following embodiments, a scheme that the second output terminal Out2 of the lighting control circuit multiplexes the first output terminal Out1 of the lighting control circuit will be described in detail.

In an optional embodiment of the present invention, the bias module 20 and the light emitting control module 10 multiplex a light emitting element resetting module for resetting the light emitting element D1.

Specifically, referring to fig. 3, after the bias module 20 is introduced, the bias module 20 and the light-emitting control module 10 may be multiplexed as a light-emitting element reset module in the embodiment of the present invention, in a reset stage of the light-emitting element D1, the bias module 20 is controlled to be turned on, the output end E2 of the light-emitting control circuit is a low-level signal, at this time, the fourth transistor M4 in the light-emitting control module 10 is turned on, the low-level signal of the output end E2 of the light-emitting control circuit is transmitted to the fourth node N4, and optionally, the fourth node N4 corresponds to an anode of the light-emitting element D1, so that the light-emitting element D1 is reset. The multiplexing bias module 20 and the fourth transistor M4 of the present invention are used as the light emitting device resetting module 50, and a separate light emitting device resetting module is not required to be introduced, which is favorable for simplifying the structure and the manufacturing process of the pixel driving circuit 100.

Fig. 4 is a schematic diagram of another structure of the pixel driving circuit 100 according to an embodiment of the present invention, wherein the bias module 20 is arranged in the same manner as the previous embodiments, except that the control terminal of the third transistor M3, the control terminal of the fourth transistor M4 and the second terminal of the bias module 20 in the embodiment shown in fig. 4 are connected to the output terminal E1 of the light emitting control circuit in the same stage, and the first node reset module 40 and the light emitting element reset module 50 are introduced into the pixel driving circuit 100, which will be described in detail below with reference to fig. 4.

In an alternative embodiment of the present invention, referring to fig. 4, the pixel driving circuit 100 further includes a first node resetting module 40 and a light emitting element resetting module 50, wherein the first node resetting module 40 includes a fifth transistor M5, and the light emitting element resetting module 50 includes a sixth transistor M6; a first terminal of the fifth transistor M5 is connected to the first node N1, a second terminal thereof is connected to a first reset signal terminal Vref1, and a control terminal thereof is connected to the third control signal terminal S3; a first terminal of the sixth transistor M6 is connected to the first terminal of the light emitting device D1, a second terminal thereof is connected to the first reset signal terminal Vref1, and a control terminal thereof is connected to the first control signal terminal S1, wherein the second terminal of the light emitting device D1 is electrically connected to the second power signal terminal PVEE.

Specifically, in the embodiment provided by the present invention, a first node reset module 40 and a light emitting element reset module 50 may be further introduced into the pixel driving circuit 100, wherein the first node reset module 40 is configured to reset the first node N1 of the driving transistor M0, and the light emitting element reset module 50 is configured to reset the light emitting element D1. Fig. 4 illustrates an example in which the first node reset module 40 includes a fifth transistor M5, and the light emitting device reset module 50 includes a sixth transistor M6, wherein a first terminal of the fifth transistor M5 is connected to the first node N1, and a second terminal thereof is connected to the first reset signal terminal Vref 1; a first end of the sixth transistor M6 is connected to the fourth node N4, a second end is connected to the first reset signal terminal Vref1, a control end of the fifth transistor M5 is connected to the third control signal terminal S3, and control ends of the sixth transistors M6 are both connected to the first control signal terminal S1. In the reset phase, under the control of the third control signal terminal S3 and the first control signal terminal S1, the fifth transistor M5 and the sixth transistor M6 are turned on, and a low-level signal of the first reset signal terminal Vref1 is transmitted to the first node N1 of the driving transistor M0 and the fourth node N4 corresponding to the light emitting element D1, so that the first node N1 and the fourth node N4 are reset, that is, the driving transistor M0 and the light emitting element D1 are reset simultaneously. In this embodiment, the first node N1 and the fourth node N4 are reset by using the signal of the first reset signal terminal Vref1, the signal output by the first reset signal terminal Vref1 is a direct current signal, and is not easily interfered by other signals, which is also beneficial to improving the signal stability of the potential of the first node N1 and the potential of the fourth node N4 after reset, and is beneficial to improving the reset effect.

Optionally, the fifth transistor M5 is an oxide transistor. Considering that the off-state leakage current of the oxide transistor is small, since the fifth transistor M5 in the present invention is electrically connected to the first node N1 of the driving transistor M0, when the fifth transistor M1 is selected as an oxide transistor in the present invention, the leakage current path of the first node N1 is reduced, and at the same time, the variation range of the potential of the first node N1 can be effectively reduced, which is beneficial to maintaining the potential of the first node N1 of the driving transistor M0, so that the driving current generated by the driving transistor M0 is more accurate. When the fifth transistor M5 is selected as an oxide transistor, the oxide transistor is turned on when its gate is high.

Optionally, with continued reference to fig. 4, the control terminal of the third transistor M3, the control terminal of the fourth transistor M4, and the second terminal of the bias module 20 are connected to the output terminal E1 of the light-emitting control circuit of the nth stage, where n is an integer greater than or equal to 1.

Specifically, the present invention connects the control terminal of the third transistor M3, the control terminal of the fourth transistor M4, and the second terminal of the bias module 20 to the output terminal E1 of the light emission control circuit of the same stage, thereby reducing the number of terminals to be connected to the pixel driving circuit 100. In this embodiment, the control terminal of the bias module 20 and the control terminal of the sixth transistor M6 are both connected to the first control signal terminal S1, the control terminal of the fifth transistor M5 corresponding to the first node reset module 40 is connected to the third control signal terminal S3, the type of the second transistor M2 corresponding to the bias module 20 and the type of the sixth transistor M6 corresponding to the light emitting device reset module 50 are the same, the second transistor M2 corresponding to the bias module 20 and the sixth transistor M6 corresponding to the light emitting device reset module 50 are simultaneously turned on or off under the control of the first control signal terminal S1, the second transistor M2, the fifth transistor M5 and the sixth transistor M6 are controlled to be simultaneously turned on in the bias stage, the output terminal E1 of the light emitting control circuit outputs a high level signal to the second node N2 and the third node N3, at this time, the third transistor M3 and the fourth transistor M4 are turned off, the fifth transistor M5 and the sixth transistor M6 are turned on, the signal of the first reset signal terminal Vref1 is transmitted to the first node N1 and the fourth node N4, the first node N1 and the fourth node N4 are reset. Because the signal that first reset signal end Vref1 exported is direct current signal, direct current signal is difficult to receive the interference of other signals, therefore when adopting the signal of first reset signal end Vref1 to reset first node N1 and fourth node N4, be favorable to promoting the signal stability of the electric potential of first node N1 and the electric potential of fourth node N4 after the reset operation, be favorable to promoting the reset effect.

Fig. 5 is a schematic diagram of another structure of the pixel driving circuit 100 according to an embodiment of the present invention, which illustrates a case where the second terminal of the bias module 20 and the control terminal of the light-emitting control module 10 are connected to output terminals of light-emitting control circuits of different stages. The following will specifically be explained.

In an alternative embodiment of the present invention, referring to fig. 5, the light-emitting control circuit includes a plurality of light-emitting control circuit units connected in cascade, and the first output terminal Out1 of the light-emitting control circuit and the second output terminal Out2 of the light-emitting control circuit correspond to the output terminals of the light-emitting control circuit units of different stages, respectively. In the embodiment shown in fig. 5, the control terminal of the third transistor M3 and the control terminal of the fourth transistor M4 are both connected to the output terminal E1 of the lighting control circuit of the nth stage; the second end of the bias module 20 is connected to the output end E2 of the light-emitting control circuit of the (n + 1) th stage, where n is an integer greater than or equal to 1.

Specifically, in this embodiment, the control terminal of the third transistor M3 and the control terminal of the fourth transistor M4 in the lighting control module 10 are connected to the output terminal E1 of the lighting control circuit in the same stage (nth stage), and the second terminal of the bias module 20 is connected to the output terminal E2 of the lighting control circuit in the (n + 1) th stage. In the bias stage, the second transistor M2 is turned on, and the high level signal of the output terminal E2 of the light emission control circuit is transmitted to the third node N3 and the second node N2 of the driving transistor M0, so as to adjust the bias state of the driving transistor M0, and adjust the driving transistor M0 to the negative bias state, and at this time, the output terminal E1 of the light emission control circuit is also at the high level, and control the third transistor M3 and the fourth transistor M4 to keep the off state. In this embodiment, the bias period, the first node N1 reset period and the light emitting device D1 reset period can be controlled to be performed simultaneously, thereby also facilitating the simplification of the driving timing of the pixel driving circuit 100. In addition, in this embodiment, the signal of the first reset signal terminal Vref1 is used to reset the first node N1 and the fourth node N4, and the signal output by the first reset signal terminal Vref1 is a direct current signal, which is not easily interfered by other signals, and is also beneficial to improving the signal stability of the potential of the first node N1 and the potential of the fourth node N4 after reset, and is beneficial to improving the reset effect.

Fig. 6, fig. 7 and fig. 8 respectively show several embodiments of the pixel driving circuit 100 including the holding module, wherein fig. 6 to fig. 8 respectively show another structural schematic diagram of the pixel driving circuit 100.

In an alternative embodiment of the present invention, referring to fig. 6 to 8, the pixel driving circuit 100 further includes a holding module 70, and the holding module 70 is connected in series between the first power signal and the bias module 20 for holding the adjusted bias voltage.

Specifically, before the light emitting element D1 emits light, the bias state of the driving transistor M0 is adjusted by the bias module 20, that is, the bias state of the driving transistor M0 is adjusted to a fixed bias state by adjusting the potentials of the second node N2 and the third node N3 of the driving transistor M0. The invention introduces the maintaining module 70 in the pixel driving circuit 100, after the bias state of the driving transistor M0 is adjusted, before the light emitting element D1 emits light, the potentials of the second node N2 and the third node N3 of the driving transistor M0 may change, the maintaining module 70 introduced by the application can maintain the potentials of the adjusted second node N2 and the third node N3 of the driving transistor M0, that is, the potential difference between the gate potential and the drain potential of the adjusted driving transistor M0, so as to weaken the internal ionization degree of the driving transistor M0, reduce the threshold voltage of the driving transistor M0, keep the driving transistor M0 in a fixed bias state before the picture switching, and can generate the driving current corresponding to the preset switching picture without being influenced by the previous frame picture data, so as to quickly switch the picture to the preset switching picture, therefore, the flicker phenomenon in the picture switching process is improved, and the display effect is improved.

The holding module 70 will be described in detail below with reference to fig. 6 to 8, respectively.

In an alternative embodiment of the present invention, referring to fig. 6, the holding module 70 includes a first capacitor C1, the first capacitor C1 is connected in series between the first power signal terminal PVDD and the third node N3, and the first capacitor C1 is configured to hold a potential of the third node N3.

Specifically, in the embodiment shown in fig. 6, in which the first capacitor C1 is introduced between the first power signal terminal PVDD and the third node N3 as the holding module 70, since the voltage signal of the first power signal terminal PVDD connected to one end of the first capacitor C1 is constant and the capacitance value of the first capacitor C1 is also constant, the voltage signal of the third node N3 connected to the other end of the first capacitor C1 is also constant, in this way, the potential of the third node N3 of the driving transistor M0 can be effectively held. After the first node N1 of the driving transistor M0 is reset, the second node N2 and the third node N3 of the driving transistor M0 are equipotential, and when the potential of the third node N3 is maintained, the potential of the second node N2 can also be maintained, so that the driving transistor M0 maintains a fixed bias state, and is prevented from being influenced by the previous frame of picture data, therefore, the introduction of the first capacitor C1 is beneficial to improving the picture flicker phenomenon caused by the unstable characteristics of the driving transistor, and is beneficial to improving the picture display effect.

In an alternative embodiment of the present invention, referring to fig. 7, the holding module 70 includes a second capacitor C2, the second capacitor C2 is connected in series between the first power signal terminal PVDD and the second node N2, and the second capacitor C2 is used for holding a potential of the second node N2.

Specifically, in the embodiment shown in fig. 7, in which the second capacitor C2 is introduced between the first power signal terminal PVDD and the second node N2 as the holding module 70, since the voltage signal of the first power signal terminal PVDD connected to one end of the second capacitor C2 is constant and the capacitance value of the second capacitor C2 is also constant, the voltage signal of the second node N2 connected to the other end of the second capacitor C2 is also constant, in this way, the potential of the second node N2 of the driving transistor M0 can be effectively held. After the first node N1 of the driving transistor M0 is reset, the third node N3 and the second node N2 of the driving transistor M0 are equipotential, and when the potential of the second node N2 is maintained, the potential of the third node N3 can also be maintained, so that the driving transistor M0 maintains a fixed bias state, and is prevented from being influenced by the previous frame of picture data, therefore, the introduction of the second capacitor C2 is beneficial to improving the picture flicker phenomenon caused by the unstable characteristics of the driving transistor, and is beneficial to improving the picture display effect.

In an alternative embodiment of the present invention, referring to fig. 8, the holding module 70 includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected in series between the first power signal terminal PVDD and the third node N3, the second capacitor C2 is connected in series between the first power signal terminal PVDD and the second node N2, the first capacitor C1 is used for holding a potential of the third node N3, and the second capacitor C2 is used for holding a potential of the second node N2.

Specifically, the embodiment shown in fig. 8 illustrates a scheme of introducing a first capacitor C1 between the first power supply signal terminal PVDD and the third node N3, and introducing a second capacitor C2 between the first power supply signal terminal PVDD and the second node N2. Since the voltage signal of the first power signal terminal PVDD connected to the first capacitor C1 and the second capacitor C2 is constant, and the first capacitor C1 and the second capacitor C2 are also constant, the potentials of the third node N3 and the second node N2 can be respectively maintained by using the first capacitor C1 and the second capacitor C2, so that the driving transistor M0 maintains a fixed bias state, and is prevented from being influenced by the previous frame of picture data, which is also beneficial to improving the picture flicker phenomenon caused by the unstable characteristics of the driving transistor, and thus is beneficial to improving the picture display effect.

In an alternative embodiment of the present invention, referring to fig. 1, fig. 3 to fig. 8, the pixel driving circuit 100 further includes a data writing module 60, and the data writing module 60 is configured to provide a data signal to the driving transistor M0. In the data writing phase of the pixel driving circuit 100, the data writing module 60 is turned on, the data signal is written into the driving transistor M0, and in the light emitting phase, the driving transistor M0 generates a driving current for driving the light emitting element D1 to emit light according to the data signal and the signal of the first power signal terminal PVDD.

In an alternative embodiment of the present invention, referring to fig. 3 to 8, the data writing module 60 includes a seventh transistor M7, wherein a first terminal and a second terminal of the seventh transistor M7 are connected in series between the data signal terminal Vdata and the second node N2, and a control terminal is connected to the fourth control signal terminal S4.

Specifically, fig. 3 to 8 show that the data writing module 60 includes a seventh transistor M7 of a seventh transistor M7, a first terminal of which is connected to the data signal terminal Vdata, a second terminal of which is connected to the second node N2 of the driving transistor M0, a control terminal of which is connected to the fourth control signal terminal S4, and a control line of a signal transmitted by the seventh transistor M7 at the fourth control signal terminal S4 is turned on or off. In the data writing phase, the seventh transistor M7 is turned on in response to the low level signal transmitted from the fourth control signal terminal S4, and the data signal of the data signal terminal Vdata is transmitted to the driving transistor M0 via the first transistor M1, thereby implementing the writing of the data signal.

Fig. 9 is a schematic diagram illustrating another structure of a pixel driving circuit 100 according to an embodiment of the present invention, which illustrates another implementation manner of the data writing module 60 in the pixel driving circuit 100.

In an alternative embodiment of the present invention, referring to fig. 9, the data writing module 60 includes an eighth transistor M8, a ninth transistor M9 and a third capacitor C3, a first end of the eighth transistor M8 is connected to a data signal terminal Vdata, a second end of the eighth transistor M8 is connected to a first pole of a third capacitor C3, a second pole of the third capacitor C3 is connected to the first node N1, and a control end of the eighth transistor M8 is connected to a fourth control signal terminal S4; the first terminal and the second terminal of the ninth transistor M9 are connected in series between the initialization signal terminal Vref and the second terminal of the eighth transistor M8, and the control terminal is connected to the output terminal E2 of the light emission control circuit.

Specifically, in the pixel driving circuit 100 provided in the embodiment shown in fig. 9, the second transistor M2 corresponding to the bias module 20 and the first transistor M1 corresponding to the compensation module 30 are multiplexed as the first node reset module 40, the second transistor M2 and the fourth transistor M4 are multiplexed as the light emitting element reset module 50, the second transistor M2 is turned on under the control of the first control signal terminal S1, the first transistor M1 is turned on under the control of the second control signal terminal S2, the output terminal E2 of the light emitting control circuit transmits a low level signal to the first node N1, and the first node N1 of the driving transistor M0 is reset; meanwhile, a low level signal output from the output terminal E2 of the light emission control circuit controls the fourth transistor M4 to be turned on, and the low level signal is transmitted to the fourth node N4 via the fourth transistor M4, so that the light emitting element D1 is reset. In the bias stage, the second transistor M2 is turned on, and the output terminal E2 of the light emission control circuit transmits a high level signal to the third node N3 and the second node N2 of the driving transistor M0, so as to adjust the bias state of the driving transistor M0 and adjust the bias state of the driving transistor M0 to a fixed bias state. In the data writing phase, the fourth control signal terminal S4 controls the eighth transistor M8 to be turned on, and the data signal is transmitted to the fifth node N5 through the eighth transistor M8 (the fifth node N5 is located between the second terminal of the eighth transistor M8 and the first pole of the third capacitor C3); meanwhile, the output end E2 of the light-emitting control circuit outputs a low-level signal to control the third transistor to be turned on; the second control signal terminal S2 outputs a high level signal to control the first transistor to be turned on; the signal of the first power signal terminal PVDD is transmitted to the driving transistor M0 through the third transistor M3, and then transmitted from the third node N3 to the first node N1 through the first transistor, so as to compensate the voltage of the first node N1. In the light emitting stage, the output terminals E1 and E2 of the light emitting driving circuit control the third transistor M3, the fourth transistor M4 and the ninth transistor M9 to be turned on, a low level signal of the initialization signal terminal Vref is transmitted to the fifth node N5, the potential of the fifth node N5 is pulled down, the low potential of the fifth node N5 is coupled to the first node N1 through the third capacitor C3, so that the driving transistor M0 is turned on; the driving transistor M0 generates a driving current according to the first power signal terminal PVDD and the voltage of the first node N1, the driving current is transmitted to the fourth node N4, and the light emitting element D1 is driven to emit light.

Based on the same inventive concept, the present application further provides a display panel, and fig. 10 is a schematic diagram of the display panel provided in the embodiment of the present application, where the display panel includes the pixel driving circuit provided in any of the embodiments of the present application. When the display panel in the application includes the pixel driving circuit provided by the above embodiment, the bias state of the driving transistor is favorably adjusted to be a fixed bias state before the picture is switched, the influence of the previous frame of picture data is avoided, the picture flicker phenomenon caused by the unstable characteristic of the driving transistor is favorably improved, and the picture display effect is favorably improved.

It should be noted that, for the embodiments of the display panel provided in the embodiments of the present application, reference may be made to the embodiments of the pixel driving circuit, and repeated descriptions are omitted. The display panel provided by the application can be applied to: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Based on the same inventive concept, the present invention further provides a driving method of a display panel, taking the display panel 200 in the above embodiment of the present invention as an example, and not taking the display panel as a limitation, fig. 11 is a flowchart of the driving method of the display panel 200 provided in the embodiment of the present invention, and with reference to fig. 1 and fig. 11, the display panel includes a driving transistor M0, a data writing module 60, a compensation module 30, a light emitting control module 10, a bias module 20, and a light emitting device D1;

The driving transistor M0 is used for providing a driving current in a light-emitting phase; the gate of the driving transistor M0 is connected to a first node N1, the first pole of the driving transistor M0 is connected to a second node N2, and the second pole of the driving transistor M0 is connected to a third node N3;

the light emitting control module 10 is connected in series between the driving transistor M0 and the light emitting element D1, and a control end of the light emitting control module 10 is connected to a first output end Out1 of the light emitting control circuit;

the bias module 20 is electrically connected between the third node N3 and the second output terminal Out2 of the light-emitting control circuit;

the driving method includes:

in the first bias phase, the bias module 20 transmits the first signal output by the light emitting control circuit to the third node in response to the first control signal, and adjusts the bias state of the driving transistor;

in the data writing phase, the data writing module 60 is configured to provide a data signal to the driving transistor; the compensation module 30 is used for detecting and self-compensating the deviation of the threshold voltage of the driving transistor M0;

In the light-emitting stage, the light-emitting element D1 emits light in response to the drive current.

Specifically, in the driving method of the pixel driving circuit provided in the embodiment of the present invention, a first bias stage is introduced, in which the bias module 20 adjusts the bias state of the driving transistor M0, adjusts the driving transistor M0 to a fixed bias state, so as to adjust the drain potential of the driving transistor M0, improve the potential difference between the gate potential and the drain potential of the driving transistor M0, reduce the degree of ionization inside the driving transistor M0, reduce the threshold voltage of the driving transistor M0, and realize the adjustment of the threshold voltage of the driving transistor M0 by biasing the driving transistor M0. Therefore, when switching to the next picture, before the threshold compensation of the driving transistor M0, the bias state of the driving transistor M0 is adjusted to be a fixed state, so that the driving transistor is not affected by the previous frame of picture data during compensation, a driving current corresponding to the preset switching picture is generated, and the picture is quickly switched to the preset switching picture, thereby being beneficial to improving the flicker phenomenon in the picture switching process and improving the display effect.

In an alternative embodiment of the present invention, fig. 12 is another flowchart of the pixel driving method provided in the embodiment of the present invention, please refer to fig. 1 and fig. 12, the driving method of the pixel driving circuit further includes a second bias stage, and the second bias stage is located after the first bias stage and is used for maintaining the bias state of the driving transistor M0.

Specifically, the second bias stage is introduced after the first bias stage, and after the state of the driving transistor M0 is adjusted to be a fixed bias state by the first bias stage, the bias state of the driving transistor M0 is maintained by the second bias stage, so that the driving transistor M0 is always kept in the fixed bias state after the first bias stage and before the light-emitting stage, that is, the introduction of the second bias stage can maintain the fixed bias state of the driving transistor M0 for a period of time, and before the picture switching, the bias state of the driving transistor M0 is kept in the fixed state, so that the driving transistor is not affected by the data of the previous frame, and the driving current corresponding to the preset switching picture can be generated, and the picture is rapidly switched to the preset switching picture, thereby being beneficial to improving the flicker phenomenon occurring in the picture switching process, and the display effect is improved.

In an alternative embodiment of the present invention, the driving method of the pixel driving circuit further includes a reset phase for resetting the first node N1.

The operation of the pixel driving circuit will be described in detail with reference to fig. 3 and 13, in which fig. 13 is a timing chart corresponding to the pixel driving circuit of fig. 3. Wherein, T1 represents the reset phase, T2 represents the first bias phase, T3 represents the second bias phase, T4 represents the data write phase, and T5 represents the light-emitting phase. Fig. 13 is a timing diagram corresponding to the pixel driving circuit shown in fig. 6 to 8.

In the reset period T1, the output terminal E1 of the light emitting driving circuit is at a high level, and the third transistor M3 is turned off; the output end E2 of the light-emitting driving circuit is at low level, and the fourth transistor M4 is turned on; the first control signal terminal S1 is at low level, and the second transistor M2 is turned on; the second control signal terminal S2 is at high level, the first transistor M1 is turned on; a low-level signal of the output terminal E2 of the light-emitting driving circuit is transmitted to the first node N1 and the fourth node N4, and the driving transistor M0 and the light-emitting element are reset;

in the first bias period T2, the output terminal E1 of the light emitting driving circuit is at a high level, and the third transistor M3 is turned off; the output end E2 of the light emitting driving circuit is at high level, and the fourth transistor M4 is turned off; the first control signal terminal S1 is at low level, and the second transistor M2 is turned on; the second control signal terminal S2 is at low level, the first transistor M1 is turned off; the high level at the output terminal E2 of the light emitting driving circuit is transmitted to the third node N3 and the second node N2 of the driving transistor M0, so that the driving transistor M0 is adjusted to a negative bias state.

In the second bias period T3, the output terminal E1 of the light-emitting driving circuit maintains a high level, the output terminal E2 of the light-emitting driving circuit maintains a high level, and the second node N2 and the third node N3 of the driving transistor M0 maintain a high level, so that the driving transistor M0 is kept in its bias state, which corresponds to a negative bias state.

In the data writing phase T4, the output terminals E1 and E2 of the light emitting driving circuit maintain a high level, the third transistor M3 and the fourth transistor M4 maintain an off state, the first control signal terminal S1 is at a high level, and the second transistor M2 is turned off; the second control signal terminal S2 is at high level, the first transistor M1 is turned on; the fourth control signal terminal S4 is at a low level, the seventh transistor M7 is turned on, and the data signal terminal Vdata writes the data signal into the second node N2 and the third node N3 of the driving transistor M0, and further transmits the data signal to the first node N1 through the third node N3;

in the light-emitting period T5, the output terminals E1 and E2 of the light-emitting driving circuit are changed to low level, the third transistor M3 and the fourth transistor M4 are turned on, the first control signal terminal S1 is at high level, the second control signal terminal S2 is at low level, the fourth control signal terminal S4 is at high level, and the first transistor M1, the second transistor M2 and the seventh transistor M7 are turned off; the signal of the first voltage signal terminal is transmitted to the driving transistor M0, and the driving transistor M0 generates a driving current to drive the light emitting element to emit light.

It should be noted that when the second bias stage is introduced into the first bias stage and the data writing stage, a certain time interval T is provided between the low level provided by the first control signal terminal S1 in the reset stage T1 and the low level signal provided by the fourth control signal terminal S4 in the data writing stage T4, where the time interval T corresponds to the time for scanning at least one row of sub-pixels in the display panel, if a row of sub-pixels is correspondingly provided in the display panel, and a front and back porch time is usually provided within one frame time (the front and back porch time does not scan the sub-pixels), if the front and back porch time is the same as the time for scanning the sub-pixels in the b row, and the display frequency is f, the one frame time is 1/f, and a + b row is scanned within one frame time, i.e. the time for scanning one row of sub-pixels is H, H ≧ 1/f)/(a + b, T ≧ 1/f)/(a + b), according to the arrangement, after the voltages of the second node and the third node of the driving transistor are adjusted in the first bias stage, the potentials of the second node and the third node can be kept by using the interval time, and it is ensured that the driving transistor always keeps a negative bias state after the first bias stage and before the light-emitting stage, that is, the introduction of the interval time t can maintain the negative bias state of the driving transistor for a period of time, and before the picture is switched, the bias state of the driving transistor M0 is kept in a fixed negative bias state, so that the driving transistor is not influenced by the picture data of the previous frame, and can still generate a driving current corresponding to the preset switching picture, and the picture is quickly switched to the preset switching picture, thereby being beneficial to improving the flicker phenomenon in the picture switching process and improving the display effect. It should be noted that the second bias stage in the present invention falls within the time range of the interval time t.

In an alternative embodiment of the present invention, please refer to fig. 3 and 13, in the same driving cycle, the reset phase is performed before the data writing phase, and the first bias phase T2 is located between the reset phase T1 and the data writing phase T4. That is, the first bias phase T2 is between the reset phase T1 and the data write phase T4. The first bias stage T1 is introduced before the data writing stage T4, the bias state of the driving transistor M0 is adjusted to adjust the drain potential of the driving transistor M0, improve the potential difference between the gate potential and the drain potential of the driving transistor M0, weaken the internal ionization degree of the driving transistor M0, reduce the threshold voltage of the driving transistor M0, and implement the adjustment of the threshold voltage of the driving transistor M0 by biasing the driving transistor M0, and adjust the driving transistor M0 to be in a fixed negative bias state, so that the driving transistor is not affected by the previous frame of picture data, and still can generate the driving current corresponding to the preset switching picture, so as to quickly switch the picture to the preset switching picture, thereby being beneficial to improving the flicker phenomenon occurring in the picture switching process and improving the display effect.

In an alternative embodiment of the present invention, please refer to fig. 3 and 13, in which the compensation module 30 and the bias module 20 are reused as the first node N1 reset module, and the bias module 20 and the fourth transistor M4 in the light emitting control module are reused as the light emitting element reset module;

in the reset phase, the fourth transistor M4 in the bias module 20, the compensation module 30 and the light emitting module is turned on, and the second terminal of the bias module 20 outputs a reset signal to the first node N1 and the fourth node N4, respectively;

in the first bias period T2, the compensation module 30 and the light emission control module 10 are turned off, the bias module 20 is turned on, and the second terminal of the bias module 20 outputs bias signals to the third node N3 and the second node N2, respectively.

Specifically, in this embodiment, the second transistor M2 in the bias module 20 and the first transistor M1 in the compensation module 30 are multiplexed as a first node reset module, and the second transistor M2 in the bias module 20 and the fourth transistor M4 in the lighting control module 10 are multiplexed as a lighting element reset module, so that the reset of the first node N1 and the reset of the lighting element are completed simultaneously in the reset phase T1, thereby facilitating to simplify the control timing of the pixel driving circuit. In addition, the first node N1 reset module and the light-emitting element reset module are multiplexed, and a separate reset module is not required to be introduced into the pixel driving circuit, thereby being beneficial to simplifying the circuit structure of the pixel driving circuit. It should be noted that, since the bias module 20 and the first transistor M1 are used as the first node N1 reset module, and the bias module 20 and the fourth transistor M4 are used as the light emitting element reset module, in the reset phase T1, the electrical signal transmitted by the output terminal E2 of the light emitting driving circuit connected to the bias module 20 is a low level signal; in the first bias stage, the signal transmitted by the output end E2 of the light emitting driving circuit connected to the bias module 20 is a high level signal.

Fig. 14 is an operation timing diagram corresponding to the pixel driving circuit of fig. 5, and fig. 5 and 14 show another scheme in which the first bias period is between the reset period and the data writing period. Wherein, T1 represents the reset phase, T2 represents the first bias phase, T3 represents the second bias phase, T4 represents the data write phase, and T5 represents the light-emitting phase. The operation of the pixel driving circuit of fig. 5 will be described in detail with reference to fig. 5 and 14.

In the reset phase T1, the output terminal E1 of the light emitting driving circuit is at a high level, the output terminal E2 of the light emitting driving circuit is at a low level, and the third transistor M3 and the fourth transistor M4 are turned off; the second control signal terminal S2 is at low level, the first transistor M1 is turned off; the first control signal terminal S1 is at low level, and the sixth transistor M6 and the second transistor M2 are turned on; the third control signal terminal S3 is at high level, and the fifth transistor M5 is turned on; a low-level signal of the first reset signal terminal is transmitted to the first node N1 and the fourth node N4, respectively, to reset the driving transistor M0 and the light emitting element D1;

in the first bias period T2, the output terminal E1 of the light emitting driving circuit is maintained at a high level, the third transistor M3 and the fourth transistor M4 are maintained at an off state, and the output terminal E2 of the light emitting driving circuit becomes a high level, which is transmitted to the second node N2 and the third node N3 of the driving transistor M0, to adjust the driving transistor M0 to a fixed bias state, for example, to a negative bias state.

In the second bias period T3, the output terminal E1 of the light emitting driving circuit maintains a high level; the output terminal E2 of the light emitting driving circuit maintains a high level, and the second node N2 and the third node N3 of the driving transistor M0 maintain a high level, so that the driving transistor M0 maintains a negative bias state.

In the data writing period T4, the output terminal E1 of the light emitting driving circuit maintains a high level, the third transistor M3 and the fourth transistor M4 maintain an off state, the first control signal terminal S1 is a high level, and the second transistor M2 is turned off; the second control signal terminal S2 is at high level, the first transistor M1 is turned on; the fourth control signal terminal S4 is at a low level, the seventh transistor M7 is turned on, and the data signal terminal Vdata writes the data signal into the second node N2 and the third node N3 of the driving transistor M0, and further transmits the data signal to the first node N1 through the third node N3;

in the light-emitting period T5, the output terminal E1 of the light-emitting driving circuit changes to low level, the third transistor M3 and the fourth transistor M4 are turned on, the first control signal terminal S1 is at high level, the second control signal terminal S2 is at low level, the fourth control signal terminal S4 is at high level, and the first transistor M1, the second transistor M2 and the seventh transistor M7 are turned off; the signal of the first power signal terminal PVDD is transmitted to the driving transistor M0, and the driving transistor M0 generates a driving current to drive the light emitting element D1 to emit light.

In an alternative embodiment of the present invention, please refer to fig. 5 and fig. 14, in the reset phase T1, the first node reset module 40 and the light emitting device reset module 50 are turned on, and the first reset signal terminal Vref1 outputs the reset signals to the first node N1 and the light emitting device, respectively; in the first bias phase, the bias module 20 is turned on, the first node reset module 40 and the light emitting device reset module 50 are turned off, and the bias module 20 outputs the first signal to the third node N3 and the second node N2, respectively.

In the embodiment corresponding to fig. 5 and 14, the reset phase T1 is executed before the first bias phase T2, the first node reset module 40 and the light emitting device reset module 50 correspond to the same first reset signal terminal Vref1, and since the signal output by the first reset signal terminal Vref1 is a dc signal, the dc signal is not easily interfered by other signals, when the first node N1 and the fourth node N4 are reset by using the signal of the first reset signal terminal Vref1, the signal stability of the potential of the first node N1 and the potential of the fourth node N4 after reset is favorably improved, and the reset effect is favorably improved.

Fig. 15 is a timing chart corresponding to the pixel driving circuit of fig. 4. The embodiments shown in fig. 4 and 15 show a scenario where the first bias phase is performed simultaneously with the reset phase. Wherein, T1 represents the reset phase and the first bias phase, T2 the second bias phase, T3 the data writing phase, and T4 the light emitting phase. The operation of the pixel driving circuit of fig. 4 will be described in detail with reference to fig. 4 and 15. In an alternative embodiment of the present invention, referring to fig. 4 and fig. 15, in the same driving period, the first bias stage and the reset stage are performed simultaneously, and the manner of performing the first bias stage and the reset stage simultaneously does not need to introduce different timings for the first bias stage and the reset stage, so as to facilitate simplifying the driving timing of the pixel driving circuit. In addition, the first bias phase and the reset phase are carried out simultaneously, which is equivalent to that the bias state of the driving transistor is adjusted when the driving transistor is reset, compared with a mode that the first bias phase is carried out after the reset phase, the time of the first bias phase is prolonged, so that the bias state of the driving transistor is maintained for a longer time, namely, the time for maintaining the potential difference between the grid potential and the drain potential of the adjusted driving transistor is longer, the internal ionization degree of the driving transistor is more favorably weakened, the threshold voltage of the driving transistor is reduced, and the screen shaking phenomenon and the poor display effect phenomenon caused by the hysteresis effect of the driving transistor in the low-frequency display mode are more favorably improved.

Referring to fig. 4 and fig. 15, in the reset phase and the first bias phase T1, the first control signal terminal S1 is at a low level, and the second transistor M2 and the sixth transistor M6 are both turned on; the third control signal terminal S3 is at high level, and the fifth transistor M5 is turned on; the output end E1 of the light emitting driving circuit is at high level, and the third transistor M3 and the fourth transistor M4 are turned off; the second control signal terminal S2 is at low level, the first transistor M1 is turned off; the low level signal of the first reset signal terminal Vref is transmitted to the first node N1 and the fourth node N4, respectively, and the high level of the output terminal E1 of the light-emitting driving circuit is transmitted to the third node N3 and the second node N2, adjusting the driving transistor M0 to a negative bias state. That is, in this embodiment, in the first bias phase, the bias module 20 and the first node reset module 40 are both turned on, the second terminal of the bias module 20 outputs the first signal, i.e., the bias signal, to the third node N3 and the second node N2, respectively, and meanwhile, the first reset signal terminal Vref1 outputs the reset signal to the first node N1 and the fourth node N4, respectively, which is favorable for simplifying the driving timing of the pixel driving circuit. Meanwhile, because the signal output by the first reset signal terminal Vref1 is a direct current signal, the direct current signal is not easily interfered by other signals, and therefore when the signal of the first reset signal terminal Vref1 is used for resetting the first node N1 and the fourth node N4, the signal stability of the potential of the first node N1 and the potential of the fourth node N4 after resetting is facilitated to be improved, and the resetting effect is facilitated to be improved.

In the second bias period T2, the output terminal E1 of the light emitting driving circuit maintains a high level, and the second node N2 and the third node N3 of the driving transistor M0 maintain a high level, so that the driving transistor M0 maintains a negative bias state.

In the data writing phase T3, the output terminal E1 of the light emitting driving circuit maintains a high level, the third transistor M3 and the fourth transistor M4 maintain an off state, the first control signal terminal S1 is at a high level, and the second transistor M2 is turned off; the second control signal terminal S2 is at high level, the first transistor M1 is turned on; the fourth control signal terminal S4 is at a low level, the seventh transistor M7 is turned on, and the data signal terminal Vdata writes the data signal into the second node N2 and the third node N3 of the driving transistor M0, and further transmits the data signal to the first node N1 through the third node N3;

in the light-emitting period T4, the output terminal E1 of the light-emitting driving circuit changes to low level, the third transistor M3 and the fourth transistor M4 are turned on, the first control signal terminal S1 is at high level, the second control signal terminal S2 is at low level, the fourth control signal terminal S4 is at high level, and the first transistor M1, the second transistor M2 and the seventh transistor M7 are turned off; the signal of the first voltage signal terminal is transmitted to the driving transistor M0, and the driving transistor M0 generates a driving current to drive the light emitting element to emit light.

Optionally, in the embodiment shown in fig. 13 to fig. 15, the first control signal terminal S1 and the fourth control signal terminal S4 may reuse the same signal terminal, so that a certain time is left between two adjacent low level signals output by the same signal terminal, and the time can leave enough time for the second bias stage, so as to keep the bias state of the driving transistor M0 for a longer time, ensure that the driving transistor M0 can be maintained in a fixed bias state before the data writing stage, and avoid being affected by the previous frame of picture data, so that the driving current generated by the driving transistor M0 in the current frame is the same as or approximately the same as the preset driving current, and avoid the phenomenon of flicker or screen shaking occurring when different pictures are switched, thereby being beneficial to improving the picture display effect.

It should be noted that fig. 13 to fig. 15 show embodiments of adjusting the bias state of the driving transistor to a negative bias state, and in some other embodiments of the present invention, the bias state of the driving transistor may also be adjusted to a positive bias state. In adjusting the bias state of the drive transistor to a forward bias state, optionally, the first bias phase is performed before the reset phase in the same drive period. A scheme of adjusting the bias state of the driving transistor to the forward bias state will be described in detail below with reference to fig. 16 and 17, and fig. 18 and 19.

Fig. 16 is another schematic diagram of the pixel driving circuit according to the embodiment of the invention, and fig. 17 is an operation timing chart corresponding to the pixel driving circuit of fig. 16, in which T1 represents a first bias phase a, T2 represents a second bias phase B, T3 represents a second bias phase, T4 represents a reset phase, T5 represents a data writing phase, and T6 represents a light emitting phase. Fig. 16 is different from the embodiment shown in fig. 3 in that a tenth transistor M10 is introduced between the light emitting element D1 and the light emitting control module 10, a control terminal of the tenth transistor is connected to an output terminal E3 of the light emitting control circuit, and output terminals E3 of the light emitting control circuit and E1/E2 of the light emitting control circuit units of different stages correspond. It should be noted that, optionally, the tenth transistor M10 may also be connected between the driving transistor M0 and the light emitting control module 10. The operation of the pixel driving circuit in fig. 16 will be described in detail with reference to fig. 17.

At stage T1, i.e., the first bias stage a, the output terminal E1 of the light emitting control circuit is at a low level, the output terminal E2 is at a high level, the first control signal terminal S1 is at a low level, the second control signal terminal S2 is at a high level, the second transistor and the first transistor are turned on, the high level of E2 is transmitted to the first node N1, and the first node N1 is at a high level.

At a stage T2, i.e., a first bias stage B, the output terminal E2 of the light emitting control circuit becomes a low level, the second control signal terminal S2 becomes a low level, the second transistor is turned on, the first transistor is turned off, the low level of E2 is transmitted to the third node N3, and the driving transistor M0 is adjusted to a forward bias state;

in the second bias period T3, the output terminal E3 of the light-emitting control circuit is kept at a high level, and the potentials of the first node and the third node are kept, so that the driving transistor M0 is kept in a forward bias state;

in a reset stage T4, an output end E2 of the light emitting control circuit is at a low level, a first control signal end S1 is at a low level, a second control signal end S2 is at a high level, a second transistor M2, a first transistor M1, and a fourth transistor M4 are turned on, the low level of E2 resets a first node N1 and the light emitting element, and a driving transistor M0 is turned on;

in the data writing phase T5, the first control signal terminal S1 is at a high level, the second control signal terminal S2 is at a high level, the fourth control signal terminal S4 is at a low level, the first transistor M1 and the seventh transistor M7 are both turned on, and the signal of the data signal terminal Vdata is written into the first node N1 through the driving transistor M0 and the first transistor M1;

in the light-emitting period T6, the output terminals E1, E2 and E3 of the light-emitting control circuit are all at low level, the signal of the first voltage signal terminal PVDD is transmitted to the driving transistor M0, and the driving transistor M0 generates a driving current to drive the light-emitting element D1 to emit light.

Fig. 18 is another schematic diagram of the pixel driving circuit according to the embodiment of the invention, and fig. 19 is an operation timing chart corresponding to the pixel driving circuit of fig. 18, in which T1 represents a first bias phase a, T2 represents a second bias phase B, T3 represents a second bias phase, T4 represents a reset phase, T5 represents a data writing phase, and T6 represents a light emitting phase. Fig. 18 is different from the embodiment shown in fig. 5 in that a tenth transistor M10 is introduced between the light emitting element D1 and the light emitting control module 10, a control terminal of the tenth transistor is connected to an output terminal E3 of the light emitting control circuit, and output terminals E3 of the light emitting control circuit and E1/E2 of the light emitting control circuit units of different stages correspond. It should be noted that, optionally, the tenth transistor M10 may also be connected between the driving transistor M0 and the light emitting control module 10. The operation of the pixel driving circuit in fig. 18 will be described in detail with reference to fig. 19.

In the stage T1, i.e., the first bias stage a, the output terminal E1 of the light emitting control circuit is at a low level, the output terminal E2 is at a high level, the first control signal terminal S1 is at a low level, the second control signal terminal S2 is at a high level, the second transistor M2 and the first transistor M1 are turned on, the high level of the output terminal E2 is transmitted to the first node N1, and the first node N1 is at a high level.

At the stage T2, i.e. the first bias stage B, the output terminal E2 of the light emitting control circuit becomes low level, the second control signal terminal S2 becomes low level, the second transistor M2 is turned on, the first transistor M1 is turned off, the low level of E2 is transmitted to the third node N3, and the driving transistor M0 is adjusted to be in positive bias state.

In the second bias period T3, the output terminal E3 of the light-emitting control circuit is kept at a high level, and the potentials of the first node N1 and the third node N3 are kept, so that the driving transistor M0 is kept in a forward bias state.

In the reset period T4, the third control signal terminal S3 is at a high level, the fifth transistor M5 is turned on, the reset signal of the first reset signal terminal Vref1 is transmitted to the first node, and the first node N1 is reset; in this embodiment, the first node N1 is reset by using the signal of the first reset signal terminal Vref1, the signal output by the first reset signal terminal Vref1 is a direct current signal, and is not easily interfered by other signals, which is also beneficial to improving the signal stability of the potential of the first node N1 and the potential of the fourth node N4 after reset, and is beneficial to improving the reset effect.

In the data writing phase T5, the fourth control signal terminal S4 is at a low level, the second control signal terminal S2 is at a high level, the first transistor M1 and the seventh transistor M7 are both turned on, and the signal of the data signal terminal Vdata is written into the first node N1 through the driving transistor M0 and the first transistor M1;

Optionally, in the embodiment shown in fig. 18 and fig. 19, the first control signal terminal S1 and the fourth control signal terminal S4 may reuse the same signal terminal, so that a certain time is left between two adjacent low level signals output by the same signal terminal, and the time can leave enough time for the second bias stage, so as to keep the bias state of the driving transistor M0 for a longer time, ensure that the driving transistor M0 can be maintained in a fixed forward bias state before the data writing stage, and avoid being affected by the data of the previous frame, so that the driving current generated by the driving transistor M0 in the current frame is the same as or approximately the same as the preset driving current, and avoid the phenomenon of flicker or screen shaking occurring during switching of different frames, thereby being beneficial to improving the image display effect.

The embodiments shown in fig. 16 to 19 show a scheme of adjusting the bias state of the driving transistor to a fixed forward bias state before the data writing phase, improving the potential difference between the gate potential and the drain potential of the driving transistor M0, weakening the internal ionization degree of the driving transistor M0, reducing the threshold voltage of the driving transistor M0, and realizing the adjustment of the threshold voltage of the driving transistor M0 by biasing the driving transistor M0. Therefore, before switching the picture, the bias state of the driving transistor M0 is adjusted to be a fixed forward bias state, so that the driving transistor is not affected by the previous frame of picture data, and still can generate the driving current corresponding to the preset switching picture, so that the picture is quickly switched to the preset switching picture, thereby being beneficial to improving the flicker phenomenon in the picture switching process and improving the display effect.

In an alternative embodiment of the present invention, there is at least one first bias phase after the light emitting phase in the same driving period. This will be explained below in conjunction with fig. 3 and 20. Fig. 20 is another operation timing diagram corresponding to the pixel driving circuit of fig. 3, showing a scheme of performing the first bias phase again after the light-emitting phase. Wherein, T1 represents the reset phase, T2 represents the first bias phase, T3 represents the second bias phase, T4 represents the data write phase, and T5 represents the light-emitting phase. The operation of the pixel driving circuit of fig. 3 will be described in detail with reference to fig. 3 and 20.

Referring to fig. 3 and 20, in the reset period T1, the output terminal E1 of the light emitting driving circuit is at a high level, and the third transistor M3 is turned off; the output end E2 of the light-emitting driving circuit is at low level, and the fourth transistor M4 is turned on; the first control signal terminal S1 is at low level, and the second transistor M2 is turned on; the second control signal terminal S2 is at high level, the first transistor M1 is turned on; a low-level signal of the output terminal E2 of the light-emitting driving circuit is transmitted to the first node N1 and the fourth node N4, and the driving transistor M0 and the light-emitting element are reset;

In the first bias period T2, the output terminal E1 of the light emitting driving circuit is at a high level, and the third transistor M3 is turned off; the output end E2 of the light-emitting driving circuit is at high level, and the fourth transistor M4 is turned off; the first control signal terminal S1 is at low level, and the second transistor M2 is turned on; the second control signal terminal S2 is at low level, the first transistor M1 is turned off; the high level of the output terminal E2 of the light emitting driving circuit is transmitted to the third node N3 and the second node N2 of the driving transistor M0. In this embodiment, during the first bias phase, the compensation module 30 and the light emission control module 10 are turned off, the bias module 20 is turned on, and the second terminal of the bias module 20 outputs bias signals to the third node N3 and the second node N2, respectively, to adjust the driving transistor M0 to a negative bias state.

In the second bias period T3, the output terminal E1 of the light emitting driving circuit maintains a high level, the output terminal E2 of the light emitting driving circuit maintains a high level, and the second node N2 and the third node N3 of the driving transistor M0 maintain a high level, so that the driving transistor M0 maintains a negative bias state.

In the data writing phase T4, the output terminals E1 and E2 of the light emitting driving circuit maintain a high level, the third transistor M3 and the fourth transistor M4 maintain an off state, the first control signal terminal S1 is at a high level, and the second transistor M2 is turned off; the second control signal terminal S2 is at high level, the first transistor M1 is turned on; the fourth control signal terminal S4 is at a low level, the seventh transistor M7 is turned on, the data signal terminal writes the data signal into the second node N2 and the third node N3 of the driving transistor M0, and then the data signal is transmitted to the first node N1 from the third node N3;

In the light-emitting period T5, the output terminals E1 and E2 of the light-emitting driving circuit are changed to low level, the third transistor M3 and the fourth transistor M4 are turned on, the first control signal terminal S1 is at high level, the second control signal terminal S2 is at low level, the fourth control signal terminal S4 is at high level, and the first transistor M1, the second transistor M2 and the seventh transistor M7 are turned off; the signal of the first voltage signal terminal is transmitted to the driving transistor M0, and the driving transistor M0 generates a driving current to drive the light emitting element D1 to emit light.

Particularly, after the light-emitting period T5, the first bias period T2 is introduced to adjust the bias state of the driving transistor M0 again, so that the driving transistor M0 remains in the negative bias state, and is not affected by the previous frame of image data, and a driving current corresponding to the preset switching image can be generated, so that the image is quickly switched to the preset switching image, thereby facilitating to improve the flicker phenomenon occurring during the image switching process and improving the display effect.

It should be noted that, in the embodiment of the present invention, the first bias stage may be disposed after the reset stage and before the data writing stage, and the first bias stage may be disposed after the light-emitting stage and before the next data writing stage, and the first bias stage may be introduced multiple times according to the magnitude of the frequency, so that the adjustment of the bias state of the driving transistor can be achieved. Optionally, the first bias stage may be introduced after the reset stage and before the data writing stage, and at least one first bias stage may be introduced after the light emitting stage and before the next data writing stage to adjust the drain potential of the driving transistor for multiple times, so as to improve the potential difference between the gate potential and the drain potential of the driving transistor, thereby being more beneficial to weakening the ionization degree inside the driving transistor, reducing the threshold voltage of the driving transistor, and realizing the adjustment of the threshold voltage of the driving transistor by biasing the driving transistor, thereby being more beneficial to improving the screen shaking phenomenon and the display effect in the low frequency display mode.

It should be noted that, in the above embodiment, the circuit shown in fig. 3 is taken as an example to illustrate that the same driving period includes two first bias stages, and optionally, in the embodiments shown in fig. 4 to fig. 9, fig. 16, and fig. 18, at least two first bias stages may also be introduced in the same driving period to adjust the bias state of the driving transistor for multiple times, so as to ensure that the bias state of the picture switching transistor is a fixed bias state, which is more favorable for improving a flicker or screen shaking phenomenon in the picture switching process, and is more favorable for improving the picture display effect.

The operation of the pixel driving circuit will be described in detail with reference to fig. 9 and 21, in which fig. 21 is a timing chart corresponding to the pixel driving circuit of fig. 9, in which T1 represents a reset phase, T2 represents a first bias phase, T3 represents a second bias phase, T4 represents a data writing phase, and T5 represents a light emitting phase.

In a reset phase T1, the first control signal terminal S1 is at a low level, the first control signal terminal S2 is at a high level, the output terminal E2 of the light-emitting driving circuit is at a low level, the second transistor M2 is turned on under the control of the first control signal terminal S1, the first transistor M1 is turned on under the control of the second control signal terminal S2, the output terminal E2 of the light-emitting driving circuit transmits a low-level signal to the first node N1, and the first node N1 of the driving transistor M0 is reset; meanwhile, a low-level signal output by the output terminal E2 of the light-emitting control circuit controls the fourth transistor M4 to be turned on, and the low-level signal is transmitted to the fourth node N4 through the fourth transistor M4, so that the light-emitting element D1 is reset;

In the first bias period T2, the first control signal terminal S1 is at a low level, the second control signal terminal S2 is at a low level, the output terminal E2 of the light-emitting driving circuit is at a high level, the second transistor M2 is turned on, the first transistor M1 is turned off, the fourth transistor M4 is turned off, the output terminal E2 of the light-emitting driving circuit transmits a high-level signal to the third node N3 and the second node N2 of the driving transistor M0, the bias state of the driving transistor M0 is adjusted, and the bias state of the driving transistor M0 is adjusted to be negative.

In the second bias period T3, the output terminal E2 of the light emitting driving circuit maintains a high level, and the second node N2 and the third node N3 of the driving transistor M0 maintain a high level, so that the driving transistor M0 maintains a negative bias state.

In the data writing phase T4, the fourth control signal terminal S4 is at a low level, the second control signal terminal S2 is at a high level, the output terminal E1 of the light emitting driving circuit is at a low level, the output terminal E2 of the light emitting driving circuit is at a high level, the eighth transistor M8, the third transistor M3 and the first transistor M1 are turned on, and the data signal is transmitted to the fifth node N5 through the eighth transistor M8 (the fifth node N5 is located between the second terminal of the eighth transistor M8 and the first electrode of the third capacitor C3); the signal of the first power signal terminal PVDD is transmitted to the driving transistor M0 through the third transistor M3, and then transmitted from the third node N3 to the first node N1 through the first transistor M1, so as to compensate the voltage of the first node N1.

In the light-emitting period T4, the output terminals E1 and E2 of the light-emitting driving circuit are both at a low level, the third transistor M3, the fourth transistor M4 and the ninth transistor M9 are turned on, a low-level signal of the initialization signal terminal Vref is transmitted to the fifth node N5, the potential of the fifth node N5 is pulled down, and the low potential of the fifth node N5 is coupled to the first node N1 through the third capacitor C3; the driving transistor M0 generates a driving current according to the voltage of the first power signal terminal PVDD and the first node N1, the driving current is transmitted to the fourth node N4, and the light emitting element D1 is driven to emit light.

In summary, the pixel driving circuit, the display panel and the driving method thereof provided by the invention at least achieve the following beneficial effects:

in the pixel driving circuit, the display panel and the driving method thereof, a bias module is introduced, wherein the first end of the bias module is connected with a third node in the pixel driving circuit, and the second end of the bias module is connected with the output end of a light-emitting control circuit; the bias module is used for adjusting the bias state of the driving transistor under the control of the first control signal and the first signal output by the second output end of the light-emitting control circuit, so that the bias state of the driving transistor is kept fixed before the light-emitting element emits light, and the characteristic of the driving transistor when the driving transistor is switched between different pictures (for example, the white picture is switched to the black picture or the black picture is switched to the white picture) is kept consistent with the characteristic of the driving transistor when the driving transistor is switched between the same pictures (for example, the white picture is switched to the white picture or the black picture is switched to the black picture). In the related art, in the process of switching the display screen, the driving transistor is affected by the data of the previous frame, and cannot generate the driving current corresponding to the preset switching screen, so that the display screen cannot be quickly switched to the preset switching screen. Before the picture is switched, the bias state of the driving transistor is adjusted to be a fixed state through the bias module, so that the driving transistor is not influenced by the data of the previous frame of picture, the driving current corresponding to the preset switching picture can be generated, and the picture is quickly switched to the preset switching picture, thereby being beneficial to improving the flicker phenomenon in the picture switching process and improving the display effect.

Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A pixel driving circuit, comprising:

a driving transistor for providing a driving current during a light emitting period; the grid electrode of the driving transistor is connected to a first node, the first pole of the driving transistor is connected to a second node, and the second pole of the driving transistor is connected to a third node;

the light-emitting control module is connected between the first power signal end and the light-emitting element in series, and the control end of the light-emitting control module is connected with the first output end of the light-emitting control circuit;

A bias module, electrically connected to the third node and the second output terminal of the light emission control circuit, for transmitting a first signal output by the light emission control circuit to the third node and the second node in a bias stage in response to a first control signal to adjust a bias state of the driving transistor;

transmitting a second signal to the first node at or before the bias phase; in the bias stage, the first signal is a high level signal and the second signal is a low level signal, or the first signal is a low level signal and the second signal is a high level signal.

2. The pixel driving circuit according to claim 1, further comprising a compensation module connected in series between the first node and the third node for detecting and self-compensating for a deviation of the threshold voltage of the driving transistor.

3. The pixel driving circuit according to claim 2, wherein the compensation module comprises a first transistor having a first terminal connected to the first node, a second terminal connected to the third node, and a control terminal connected to a second control signal terminal.

4. The pixel driving circuit of claim 1, wherein the bias module comprises a second transistor having a first terminal connected to the third node, a second terminal connected to the second output terminal of the emission control circuit, and a control terminal connected to the first control signal terminal.

5. The pixel driving circuit according to claim 2,

the compensation module and the bias module are multiplexed as a first node reset module for resetting the first node.

6. The pixel driving circuit according to claim 3, wherein the first transistor comprises an oxide transistor.

7. The pixel driving circuit according to claim 1, further comprising a power supply voltage writing module including a third transistor connected in series between the first power supply signal terminal and the first node, a control terminal of the third transistor being electrically connected to a third output terminal of the light emission control circuit.

8. The pixel driving circuit according to claim 7, wherein the emission control circuit comprises a plurality of emission control circuit units connected in cascade;

The third output terminal of the light emission control circuit multiplexes the first output terminal of the light emission control circuit; or the third output end of the light-emitting control circuit and the first output end of the light-emitting control circuit correspond to the output ends of the light-emitting control circuit units of different stages respectively.

9. The pixel driving circuit according to claim 1, wherein the light emission control module comprises a fourth transistor connected in series between the light emitting element and the third node, and a control terminal of the fourth transistor is electrically connected to the first output terminal of the light emission control circuit.

10. The pixel driving circuit according to claim 1, wherein the second output terminal of the emission control circuit is multiplexed with the first output terminal of the emission control circuit.

11. The pixel driving circuit of claim 1, wherein the bias module and the emission control module multiplex a light emitting element reset module for resetting a light emitting element.

12. The pixel driving circuit according to claim 1, further comprising a first node reset module and a light emitting element reset module, wherein the first node reset module comprises a fifth transistor, and wherein the light emitting element reset module comprises a sixth transistor; a first end of the fifth transistor is connected with the first node, a second end of the fifth transistor is connected with a first reset signal end, and a control end of the fifth transistor is connected with a third control signal end; the first end of the sixth transistor is connected with the first end of the light-emitting element, the second end of the sixth transistor is connected with the first reset signal end, the control end of the sixth transistor is connected with the first control signal end, and the second end of the light-emitting element is electrically connected with the second power supply signal end.

13. The pixel driving circuit according to claim 1, wherein the emission control circuit comprises a plurality of emission control circuit units connected in cascade, and a first output terminal of the emission control circuit and a second output terminal of the emission control circuit correspond to output terminals of different stages of the emission control circuit units, respectively.

14. The pixel driving circuit of claim 1, further comprising a hold module connected in series between the first power signal and the bias module for holding the adjusted bias voltage.

15. The pixel driving circuit according to claim 14, wherein the holding module comprises a first capacitor connected in series between the first power supply signal terminal and the third node, the first capacitor being configured to hold a potential of the third node.

16. The pixel driving circuit according to claim 14, wherein the holding module includes a second capacitor connected in series between the first power supply signal terminal and the second node, the second capacitor being configured to hold a potential of the second node.

17. The pixel driving circuit according to claim 14, wherein the holding module includes a first capacitor connected in series between the first power supply signal terminal and the third node, and a second capacitor connected in series between the first power supply signal terminal and the second node, the first capacitor being configured to hold a potential of the third node, and the second capacitor being configured to hold a potential of the second node.

18. The pixel driving circuit of claim 1, further comprising a data writing module configured to provide a data signal to the driving transistor.

19. The pixel driving circuit of claim 18, wherein the data writing module comprises a seventh transistor, a first terminal and a second terminal of the seventh transistor are connected in series between a data signal terminal and the second node, and a control terminal is connected to a fourth control signal terminal.

20. The pixel driving circuit according to claim 18, wherein the data writing module comprises an eighth transistor, a ninth transistor and a third capacitor, a first terminal of the eighth transistor is connected to the data signal terminal, a second terminal of the eighth transistor is connected to a first electrode of the third capacitor, a second electrode of the third capacitor is connected to the first node, and a control terminal of the eighth transistor is connected to a fourth control signal terminal; the first end and the second end of the ninth transistor are connected in series between an initialization signal end and the second end of the eighth transistor, and the control end is connected with the output end of the light-emitting control circuit.

21. A display panel comprising the pixel driving circuit according to any one of claims 1 to 20.

22. The driving method of a display panel is characterized in that the display panel comprises a driving transistor, a data writing module, a compensation module, a light-emitting control module, a bias module and a light-emitting element;

the bias module is electrically connected between the third node and the second output end of the light-emitting control circuit;

the driving method includes:

transmitting a second signal to the first node at or before the first bias phase;

In the first bias stage, the bias module transmits a first signal output by the light-emitting control circuit to the third node in response to a first control signal to adjust the bias state of the driving transistor; in the bias stage, the first signal is a high-level signal and the second signal is a low-level signal, or the first signal is a low-level signal and the second signal is a high-level signal;

23. The driving method as claimed in claim 22, further comprising a second bias stage, after the first bias stage, for maintaining a bias state of the driving transistor.

24. The driving method according to claim 22, further comprising a reset phase for resetting the first node.

25. The driving method as claimed in claim 24, wherein the reset phase is performed before the data write phase and the first bias phase is between the reset phase and the data write phase in the same driving cycle.

26. The driving method according to claim 25, wherein the compensation module and the bias module are reused as the first node reset module, and the bias module and the light emitting control module are reused as the light emitting element reset module;

in the reset phase, the bias module, the compensation module and the light emitting control module are turned on, and a second end of the bias module outputs a reset signal to the first node and the light emitting element respectively;

in the first bias stage, the compensation module and the light emitting control module are turned off, the bias module is turned on, and the bias module outputs the first signal to a third node and a second node, respectively.

27. The driving method according to claim 25, wherein in the reset phase, the first node reset module and the light emitting element reset module are turned on, and the first reset signal terminal outputs a reset signal to the first node and the light emitting element, respectively;

in the first bias stage, the bias module is turned on, the first node reset module and the light emitting element reset module are turned off, and the bias module outputs the first signal to the third node and the second node, respectively.

28. The driving method as claimed in claim 24, wherein the first bias phase and the reset phase are performed simultaneously in the same driving period.

29. The driving method according to claim 28, wherein in the first bias phase, a bias module and a first node reset module are both turned on, the bias module outputs the first signal to the third node and the second node, respectively, and simultaneously a first reset signal terminal outputs a reset signal to the first node and the light emitting element, respectively.

30. The driving method according to claim 24, wherein the first bias phase is performed before the reset phase in the same driving cycle.

31. The driving method as claimed in claim 25, 28 or 30, wherein at least one of the first bias periods is located after the light emitting period in the same driving period.

32. The driving method as claimed in claim 31, wherein in the first bias phase, the compensation module and the light emitting control module are turned off, the bias module is turned on, and the bias module outputs the first signal to a third node and a second node, respectively.