CN1146639A - Method for preparation of silicon quantum wire using SiGe/Si heterogeneous structure - Google Patents
Method for preparation of silicon quantum wire using SiGe/Si heterogeneous structure Download PDFInfo
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- CN1146639A CN1146639A CN 95112707 CN95112707A CN1146639A CN 1146639 A CN1146639 A CN 1146639A CN 95112707 CN95112707 CN 95112707 CN 95112707 A CN95112707 A CN 95112707A CN 1146639 A CN1146639 A CN 1146639A
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Abstract
The preparation method of silicon quantum line by using SiGe/Si heterostructure is characterized by that a Si/SiGe/Si heterofilm is grown on silico monocrystal, and a channel is formed by using photoetching and reactive ionic etching process, and a selective chemical etching process is used to remove SiGe layer and form silicon line, and then the silicon line is refined and smoothened by using low-temp. thermal oxidation process so as to obtain its required silicon quantum line with required size, and at the same time obtain the high-quality Si/SiO2 heterointerface.
Description
The present invention relates to the preparation of silicon quantum wire in the semi-conducting material.
Silicon quantum wire will become in the device to play the role of a nucleus as the basis of nano-electron in super huge size integrated circuit, silicon quantum effect device and silicon based opto-electronics subclass, be the research focus in the field, current International Technology forward position.For this reason, at first must have the hyperfine quantum wire structure at physical restriction interface, and carry out the research of physics and device with the most controlled method preparation.The major technology method is by reactive ion etching, the corrosion of anisotropy chemistry and control thermal oxidation process at present, acquires Si/SiO on silicon monocrystalline substrate or SOI substrate
2The hyperfine silicon quantum wire of heterogeneous interface.Referring to [1] Morimoto K, Hirai Y, Yuki K et al.One-dimensionalconduction of ultra fine silicon quantum wires.ExtendedAbstracts of 93 ' ICSSDM, 1993, pp.344-346.
[2] Shi Yi, Liu Jianlin, Zheng Youdou etc.Si/SiO
2The hyperfine silicon quantum wire of heterogeneous interface.Science Bulletin, 1995,40 (18): 000;
[3]Takahashi?Y，Nagase?M，Tabe?M?et?al.Fabricationtechnique?for?Si?single-electron?transitor?operatingroom?temperature.Elec?Lett，1995，31(2)：136-137
The means that above-mentioned art methods provided are single, can not prepare the silicon quantum wire with complicated lines, and many new construction silicon device developments are restricted, and the specification requirement height.On the other hand, SiGe heteroepitaxy film referring to CN901005603, has many new character and characteristics as a kind of novel semiconductor material of developed recently, and compatible mutually with silicon process technology, has obtained extensive studies and application.Simultaneously, because it at aspects such as high quality epitaxial growth, selection chemical corrosion and thermal oxidations, just is being subjected to pay attention to day by day on preparation low-dimensional quantum structure and related device.
Purpose of the present invention is utilized the good characteristic of SiGe heteroepitaxy film just, develops the meticulous silicon quantum wire structural approach of new preparation, for development new construction silicon quantum device etc. provides necessary means.
The present invention proposes a kind of SiGe/Si of employing heteroepitaxial growth, select chemical corrosion and thermal oxidation technique realization to have the method for the hyperfine silicon quantum wire structure at physical restriction interface.
Below in conjunction with description of drawings inventive method and embodiment.
The step that silicon quantum wire preparation process that Fig. 1 (a)-(d) is corresponding comprises:
The silicon quantum wire preparation process comprise four key steps (such as Fig. 1 (a)-(d) correspondence): (a) Si/SiGe/Si heterofilm epitaxial growth; (b) photoetching and reactive ion etching form groove; (c) adopt to select chemical corrosion to remove the SiGe layer and form the silicon line, (d) the silicon line is carried out refinement and smoothly reaches final desirable size, obtain high-quality Si/SiO simultaneously by the low thermal oxidation process
2Heterogeneous interface.This Si/SiO
2The heterogeneous interface structure has very high potential barrier to charge carrier (electronic type hole), plays strong restriction.
Fig. 2 is the SEM photo of sample section after the selection chemical corrosion.
Fig. 3 is the SEM photo of quantum wire cross section.Fig. 4 is the indicatrix of silicon line thermal oxidation.
Concrete steps and implementation process are as follows: (a) Si/SiGe/Si heterofilm epitaxial growth.The whole process of preparation of sample is based on the SiGe/Si heteroepitaxial growth basis, therefore at first must obtain high-quality SiGe/Si heteroepitaxy thin-film material, and it also will have good abrupt interface except low dislocation density.For this reason, the growth rate of sample must be controlled at the atom level level, and (UHV-CVD, VLP-CVD), molecular beam epitaxy (MBE) etc. can satisfy these requirements to adopt ultra high vacuum or ultralow pressure chemical vapor deposition techniques.The Ge component promptly will consider to guarantee the epitaxial film quality on selecting, and notes the chemical corrosion selection ratio that keeps certain again.What be worth proposition especially is that owing to adopt the epitaxy technology of atom level, the thickness of outer Si can be precisely controlled, thereby controlled the size of silicon quantum wire on a dimension well.(b) photoetching and reactive ion etching.On the good sample of growth, obtain groove through mask, hyperfine photoetching and reactive ion etching (RIE), so that select chemical corrosion to carry out from the side.(c) select chemical corrosion.Adopt and select chemical corrosion removal SiGe layer and form the silicon line.The selection chemical mordant of SiGe/Si heterofilm has many kinds, and is conventional as HNO
3+ CH
3COOH or H
2O)+and dilution HF, H
2O
2+ H
2O+HF etc.
Must notice in the enforcement that corrosive agent should have good corrosion surface and to the protectiveness of mask.Can accurately regulate corrosion rate and selection ratio by changing the proportioning of this selective etchant, control the size of silicon line effectively,, obtain the cross section and have nearly square silicon line so that on a controlled etching time yardstick to SiGe and Si.(d) low thermal oxidation.For the SiGe heterogeneous structure material, because the restriction of its thermal stability, the high-temperature oxydation that surpasses 850 ℃ is under an embargo fully, and the low temperature dry-oxygen oxidation needs long time to arrive desirable size by the silicon line thinning.The low temperature wet-oxygen oxidation provides a valid approach for refinement silicon line.Simultaneously, the rib that wet-oxygen oxidation produces at silicon face is by force less than dry-oxygen oxidation, and helps keeping the integrality of silicon quantum wire.Experiment finds, exists from limiting oxidative phenomena about the wet-oxygen oxidation of silicon line below 750 ℃, and this is mainly due to silicon line surface SiO
2Strong the increasing of additional rib due to.Can determine the final lateral dimension of silicon quantum wire accurately and efficiently by utilizing from limiting oxidation effect.
Therefore, adopt first low temperature wet oxygen and back two step of dry-oxygen oxidation process in the enforcement, the lateral dimension of quantum wire was controlled by silicon line original dimension, oxidizing temperature and time.
This method has good controllability, and compatible mutually with silicon process technology, is applicable to the multiple new construction silicon quantum device of preparation.This is to propose first in the world and successfully realize in the laboratory, reaches the international leading level.
The above employing SiGe/Si heteroepitaxial growth of inventing, selection chemical corrosion and thermal oxidation technique realization have the method for the hyperfine nanometer dimension silicon quantum wire structure at physical restriction interface, be to propose first in the world and successfully realize in the laboratory, reached the leading level in the world.Experiment knot shows, this method can realize hyperfine quantum wire structure with controllability, and compatible mutually with silicon process technology, can prepare the silicon quantum device of multiple new construction.To carrying out the research of silicon low-dimensional quantum structure physics and silicon quantum device from now on, the development nano-electron has crucial meaning.
Fig. 2 has provided and has selected that the SEM in sample cross section observes photo after the chemical corrosion.Can be clear that to erode the Si linear array that stays behind the SiGe layer that top flat dried calotte is the etching mask layer of not removing; Fig. 3 provides the SEM observation photo that low warm oxygen is handled quantum wire cross section, back.Middle garden shape white portion among the figure is a silicon quantum wire, and the black that makes a circle in week is SiO
2Layer, about 20 nanometers of being seen quantum wire radius.
The Si resilient coating of at first on the silicon monocrystalline substrate of (100) crystal orientation, growing successively, Si
1-xGex epitaxial loayer, structure is shown in Fig. 1 .A.Epitaxial growth is carried out in computer-controlled RRH/VLP-CVD system, and reactant gas source is SiH
4, GeH
4For guaranteeing that extension goes out high-quality single crystalline Si and SIGe strained layer on silicon monocrystalline substrate, carry out heat before the growth and clean and the hydrogen preliminary treatment.In this sandwich construction, the Si epitaxy layer thickness can accurately be regulated as required.
Growth sample well is through photoetching, and reactive ion etching gets the tongue figure, and its cross section is selected chemical corrosion at 25 ℃ then shown in Fig. 1 .B.Selective etching liquid is by HNO
3The nearly certain proportion of+HAC+HF mixes, its to the corrosion rate of GeSi greater than corrosion rate to Si.
Sample through selective etching is made wet oxygen, and dry-oxygen oxidation is with smooth and refinement silicon line.We do the oxidation of different time respectively under 850 ℃ and 750 ℃ of situations, so that research oxidization time temperature forms the influence of feature to quantum wire.Finally we make high-quality Si/SiO
2The hyperfine silicon quantum wire of heterogeneous interface structure.
Adopt the HITACHI550 scanning electron microscopy, measure, analyze the dimension of quantum wire, oxidated layer thickness.In order to improve the contrast of image, with the sample that above-mentioned steps makes, extension one deck polysilicon with the quantum wire array transversely truncation, through selective etching silicon dioxide, is made canonical profile SEM sample again.
Fig. 2 is the SEM photo of sample section after the selection chemical corrosion, and the cross section that can clearly observe by the support of neck shape germanium silicon is nearly semicircular silicon linear array (mask layer of top flat calotte for not removing).HNO
3+ HAC+HF is used widely as the SiGe selective etchant.Change the proportioning of selective etching liquid, scalable rate of corrosion and selection ratio, thereby the size of controllable silicon line, and good corrosion surface is arranged.
The mask layer of sample is removed, cleaned the back and the silicon line is carried out refinement, thereby obtain with SiO by oxidation
2Be barrier layer Si/SiO
2The silicon quantum wire of heterogeneous interface.In order not destroy the Si/SiGe heterogeneous structure material, we adopt and are lower than 850 ℃ wet-oxygen oxidation, adopt dry-oxygen oxidation to obtain high-quality Si/SiO at last
2The interface.
Obviously, oxidizing condition is a critical process to preparation high-quality quantum wire.For this reason, we have carried out Primary Study to the thermal oxidation feature of silicon line.According to the oxidation data, do Fig. 4 .A, curve shown in the 4.B.
In Fig. 4 .A, transverse axis is an oxidization time, and the longitudinal axis is the quantum wire footpath.Average Si line initial size is about 250 nanometers.Under 850 ℃ of situations, along with the carrying out of oxidation, the quantum wire rate of size decrease diminishes gradually, but when oxidization time during greater than 16 hours, and we observe the phenomenon that the silicon line of silicon quantum wire disappears because of the saturating face of oxidation.And under 750 ℃ of situations, same carrying out along with oxidation, the quantum wire rate of size decrease diminishes gradually, and after 38 hours oxidation, sub-line ruler 40 nanometers of cun still having an appointment, thereby can think in the time of 750 ℃, with regard to the quantum wire preparation condition of this paper, exist the restriction phenomenon certainly of wet-oxygen oxidation.
Oxidizing process in the quantum wire preparation is actually a kind of two dimensional oxidation (curved surface oxidation) process, and it is different on the functional relation of oxidation bed thickness and time with traditional one dimension oxidation (plane oxidation) process.In Fig. 4 .B, conclusively show out the difference of these two kinds of oxidations.Transverse axis is an oxidization time, and the longitudinal axis is the oxidation bed thickness.Here when plane oxidation bed thickness and time were line style and concern, the curved surface oxidation had shown restricted trend.For the oxygen oxidizing process, we find that the curved surface oxidation exists from restriction effect below 950 ℃.The curved surface oxidation need be considered the effect of more unexistent factors in the plane oxidation, there are many theories to explain the feature of this two dimensional oxidation, as the influence of crystal orientation to oxidation, oxygen transporting in lth layer, the viscous of curved surface oxide layer is mobile etc., and main influence may derive from the additional effect of stressing in the curved surface oxide layer.Because silicon dioxide has very high viscosity, thereby in the plane oxidation process already present the stressing, nonplanar viscous deformation of silicon dioxide will produce very big stressing.This stresses the oxidation reaction process that makes at silicon face to become difficult.And temperature is low more, and stressing of being produced is also big more, thereby causes more obvious oxidation to stop.Stress influence to the oxidation reaction process of silicon face may be reflected in the variation of diffusion coefficient D of surface oxidation reaction constant Ks and oxidation.
Claims (2)
1. a method of utilizing the SiGe/Si heterostructure to prepare silicon quantum wire is characterized in that growth Si/SiGe/Si heterofilm on silicon single crystal, and photoetching and reactive ion etching form groove; Adopt to select chemical corrosion to remove the SiGe layer and also form the silicon line, the silicon line is carried out refinement and smoothly reaches final desirable size, obtain high-quality Si/SiO simultaneously by the low thermal oxidation process
2Heterogeneous interface.
2. by the described method for preparing silicon quantum wire of claim 1, it is characterized in that under 700 ℃ of-850 ℃ of temperature, carrying out hot oxygen oxidation.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311525C (en) * | 2003-07-28 | 2007-04-18 | 英特尔公司 | Method of fabricating an ultra-narrow channel semiconductor device |
| CN103441062A (en) * | 2013-09-09 | 2013-12-11 | 厦门大学 | Method for preparing Ge component and bandwidth regulated SiGe nanobelt |
| CN103928297A (en) * | 2013-12-28 | 2014-07-16 | 华中科技大学 | Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure |
-
1995
- 1995-09-27 CN CN 95112707 patent/CN1146639A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311525C (en) * | 2003-07-28 | 2007-04-18 | 英特尔公司 | Method of fabricating an ultra-narrow channel semiconductor device |
| CN103441062A (en) * | 2013-09-09 | 2013-12-11 | 厦门大学 | Method for preparing Ge component and bandwidth regulated SiGe nanobelt |
| CN103441062B (en) * | 2013-09-09 | 2016-09-28 | 厦门大学 | A kind of Ge component and the preparation method of bandwidth regulatable SiGe nano belt |
| CN103928297A (en) * | 2013-12-28 | 2014-07-16 | 华中科技大学 | Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure |
| CN103928297B (en) * | 2013-12-28 | 2017-04-26 | 华中科技大学 | Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure |
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