CN1146638A - Semiconductor device capable of reducing power dissipation in stand-by state - Google Patents
Semiconductor device capable of reducing power dissipation in stand-by state Download PDFInfo
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- CN1146638A CN1146638A CN96108463A CN96108463A CN1146638A CN 1146638 A CN1146638 A CN 1146638A CN 96108463 A CN96108463 A CN 96108463A CN 96108463 A CN96108463 A CN 96108463A CN 1146638 A CN1146638 A CN 1146638A
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- mos transistor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000926 separation method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 3
- 241000220317 Rosa Species 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000009466 transformation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device capable of reducing power dissipation in stand-by state, has power supply line at prearrange voltage value setting at the semiconductor device inner circuit, also has ground line at ground voltage value setting at the semiconductor device inner circuit, ground line includes first MOS transistor setting between power supply line and secondary circuit block at least one part, circuit block are formed by many circuits of inner circuits in the standby state and the operation state at the same time, or formed by ground line and secondary circuit block, when secondary circuit block in the standby state, turned off first transistor by control substrate voltage, rose threshold voltage to reduce sub-threshold current.
Description
The present invention relates to reduce at stand-by state because the semiconductor device of the power dissipation that subthreshold current causes, particularly relate to and be applicable to the gigabit memory or utilize the semiconductor device of cut-off characteristics than the transistorized logical device of deep sub-micron MOS of the cut-off characteristics difference of long channel transistor, it can reduce standby current significantly, therefore, reduced the power dissipation of stand-by state.
Fig. 1 represents the basic circuit diagram of conventional memory or logical device.As shown in Figure 1, general supply line L100 and total ground wire L0 are directly linked circuit block B0 formation custom circuit.Therefore, adopt the transistorized situation of deep sub-micron MOS at circuit, even also have many subthreshold currents to flow through circuit in cut-off state.This has increased the power dissipation of stand-by state widely.When scaled MOS transistor, can reduce threshold voltage, the result, even, promptly exist in transistorized threshold zone | V
Gs＜V
T|, also can increase subthreshold current.This has just produced the problems referred to above.Therefore, in gigabit memory device that is made of the deep sub-micron MOS transistor or logical device, the power dissipation of stand-by state becomes serious problem.For addressing the above problem, proposed to realizing reducing several technology in the power dissipation purpose of stand-by state.The SWitched Sourceimpedance CMOS circuit technology that the first is delivered at " IEEE Journal of Solid State ci-rcuits Vol.28,11, NoVember 1993 " by the Hitachi, Ltd (Hitachi) of Japan.This technology can reduce the subthreshold current of stand-by state significantly.But it has increased the delay of circuit.And make by standby attitude slack-offly, thereby reduced the entire circuit performance to the transformation of operating state.
The purpose of this invention is to provide a kind of semiconductor device, be fast to the transformation of operating state wherein, and reduce the subthreshold current of stand-by state, therefore, can reduce power dissipation by stand-by state.
To achieve the object of the present invention, provide a kind of semiconductor device that can reduce in the power consumption of stand-by state.The whole interior circuit of its oriented semiconductor device provides the power line of predetermined power source voltage; With the ground wire that ground voltage is provided to internal circuit, this semiconductor device comprises: the 1st MOS transistor, it is arranged at least a portion between power line and the secondary circuit block, this secondary circuit block is made of a plurality of circuit that are in stand-by state and operating state in same timing in the internal circuit, or constitute by ground wire and secondary circuit block, when secondary circuit block is in stand-by state, the control underlayer voltage can make the 1st MOS transistor end and increase its threshold voltage, so that reduce its threshold current.
In conjunction with the drawings,, can understand the novel feature that belongs to characteristic of the present invention better to being described in detail of following special embodiment, and further feature and advantage.
Fig. 1 represents the principle assumption diagram of conventional semiconductor device;
Fig. 2 represents the principle assumption diagram according to the semiconductor device of the embodiment of the invention;
Fig. 3 represents the timing diagram of control signal as shown in Figure 2;
Fig. 4 represents the principle assumption diagram according to the semiconductor device of other embodiment of the present invention;
Fig. 5 A and Fig. 5 B represent to be used to realize the schematic diagram of semiconductor device three well structures of the object of the invention.
With reference to the accompanying drawings, the preferred embodiments of the present invention are described.
Fig. 2 represents the Physics of Semiconductor Devices structure chart according to one embodiment of the invention.As shown in Figure 2, constitute semiconductor device of the present invention as described below, general supply line L100 does not directly link to each other with circuit block with total ground wire L0, but whole circuit blocks are divided into many secondary circuit block Bi, each circuit block Bi is made of a plurality of circuit that identical stand-by state and operating state are arranged.Corresponding to the secondary power line Lai of the part of each secondary circuit block Bi and local secondary ground wire Lbi respectively with general supply line L100 and always ground wire L0 be that PMOS transistor MPi is connected with nmos pass transistor and forms hierarchy thus by switch.The trap that forms the N trap of PMOS transistor MPi and nmos pass transistor MNi and P trap respectively thereon and form other MOS transistor of memory or logical device on it is separated from each other, and Fig. 3 is the sequential chart of control signal shown in Figure 2.
As shown in Figure 3, be input to the signal psi of PMOS transistor MPi grid
Pi, when the secondary circuit block Bi that connects PMOS transistor MPi is when being in stand-by state, be logic " height " level, when in running order, φ
PiIt is logic " low " level.On the other hand, be input to the signal psi of nmos pass transistor MNi grid
Ni, when the secondary circuit block that connects nmos pass transistor MNi is when being in stand-by state, be logic " low " level, when in running order, φ
NiIt is logic " height " level.Therefore, if secondary circuit block changes to stand-by state from operating state, according to control signal φ
Pi, φ
Ni, PMOS transistor MPi and nmos pass transistor MNi turn-off.Like this, secondary power line Lai and secondary ground wire Lbi and general supply line L100 and total ground wire L0 isolate, so, be in the power consumption of stand-by state by the subthreshold current decision of flowing through PMOS transistor MPi and nmos pass transistor MNi.
As shown in Figure 3, to the voltage V of the N-trap that forms PMOS MPi thereon
NWi, the voltage V of stand-by state
NW-SBVoltage V than operating state
NW-ACHigh predetermined value.Voltage V to the P-trap that forms NMOS MNi thereon
PWi, the voltage V of stand-by state
PW-SBVoltage V than operating state
PW-ACLow predetermined value.Like this, each threshold voltage of PMOS transistor MPi and nmos pass transistor MNi increases with bulk effect.Therefore, PMOS transistor MPi and nmos pass transistor MNi significantly increase at the subthreshold current of stand-by state, and the result has reduced power consumption.
Simultaneously, if stand-by state becomes operating state, control signal φ
PiBecome logic " low " level, control signal φ from logic " height " level
NiBecome logic " height " level from logic " low " level.Simultaneously, voltage V
NWiFrom voltage V
NW-SBReduce to voltage V
NW-AC ', then, voltage V
PWiFrom voltage V
PW-SBBe increased to voltage V
PW-AC ', therefore, reduce PMOS transistor MPi and each corresponding threshold voltage of nmos pass transistor MNi.Therefore, stand-by state is converted to operating state very soon.Just, each trap voltage of PMOS transistor MPi and nmos pass transistor MNi, different when stand-by state and operating state.Like this,, increase threshold voltage, reduce threshold current at stand-by state.On the other hand, reduce threshold voltage in working order, make from stand-by state and be converted to operating state very soon, simultaneously, improve the current driving ability of PMOS transistor MPi and nmos pass transistor MNi.With reference to Fig. 2, general supply line L100 can directly link to each other with circuit block with one of total ground wire L0, and another can be used for using in the stage circuit structure of secondary power line.
Usually, the logic level of internal node is fixed on stand-by state in the memory resembling dynamic random access memory (DRAM).In this case, can more effectively reduce subthreshold current.Fig. 4 represents a kind of power line to be linked the method that logic level is fixed on the internal circuit of stand-by state.Circuit block as shown in Figure 4 comprises three inverters of coupled in series.In this circuit, if the input node n1 of inverter is logic " height " level, node n2 is logic " low " level, node n3 is logic " height " level, node n4 is logic " low " level, PMOS transistor MPa, nmos pass transistor MNb, the subthreshold current of PMOS transistor MPc causes that the voltage of secondary power line Lai reduces, and the voltage of secondary ground wire Lbi increases.As shown in Figure 4, here, if the transistor MPa of subthreshold current path, MNb, MPc is linked secondary power line Lai or secondary ground wire Lbi, and other transistor is linked general supply line L100 and total ground wire Lo, and then reverse voltage is added between the grid and source electrode of transistor MPa, MNb, MPc.Subthreshold current significantly reduces.Therewith relatively, add reverse voltage if give between the grid of MOS transistor and the source electrode, this threshold current can sharply reduce.
Because the subthreshold current effect, the voltage of secondary power line Lai is compared with the power supply of general supply line L100, reduces certain value Δ V
DDOn the other hand, because the subthreshold current effect, the voltage of secondary ground wire Lbi is compared with the voltage of total ground wire L0, increases same amount Δ V
SSTherefore, between the grid of transistor MPa and MPc and source electrode, apply and be equivalent to voltage difference delta V
DDReverse biased, between the grid and source electrode of transistor MNb, apply and be equivalent to voltage difference delta V
SSReverse biased.
Fig. 5 A and Fig. 5 B are the schematic diagrams that is expressed as semiconductor device three well structures of realizing the object of the invention.Because as the PMOS transistor MPi of the switch between general supply line and total ground wire and secondary power line and the secondary ground wire and the underlayer voltage of nmos pass transistor MNi, should be spaced from each other with other the transistorized underlayer voltage that forms internal circuit, so transistor MPi and MNi should be formed on the separated trap.That is, three well structures are the structures that are suitable on trap spaced apart from each other forming PMOS transistor MPi and nmos pass transistor MNi, so that the voltage of control trap (underlayer voltage) freely.
Fig. 5 A represents one by being separated from each other and being formed on three well structures that 1N-trap 1 on the P type substrate 10 and 2N-trap 2 constitute, 1P-trap 3 and the 1st and 2N-trap 1 and opening in 2 minutes, and 2P-trap 4 is formed in the 1N-trap 1.PMOS transistor MPi is as the general supply line and be formed on switch between the secondary power line of 2N-trap 2, and nmos pass transistor MNi is as total ground wire be formed on switch between the secondary ground wire in the 2P-trap 4.Therefore, even change trap voltage V
NWiAnd V
PWi, not influencing other transistor of forming circuit yet, Fig. 5 B represents three well structures that constitute according to another embodiment of the present invention.This triple-well by be separated from each other and be formed on 1P-trap 11 on the N-type substrate 20 and 2P-trap 12 and the 1st and 2P-trap 11 and 12 separated 1N-traps 13 and the 2N-trap 14 that is formed in the 1P-trap 11 constitute.PMOS transistor MPi is as the general supply line and be formed on switch between the secondary power line on the 2nd N-trap 14, and nmos pass transistor MNi is as total ground wire and be formed on the switch between the secondary ground wire in the 2P-trap 12.Therefore, even change trap voltage V
NWiAnd V
PWi, do not influence other transistor of forming circuit yet.
If one of general supply line L100 and total ground wire L0 directly link circuit block, another then is used for using the stage circuit structure of secondary power line, shown in Fig. 5 A, then may only constitute in the 2P-trap 4 that forms switching transistor thereon and the 2N-trap 2.In device shown in Fig. 5 B, can form trap by above-mentioned same principle.
As mentioned above,, be transformed into operating conditions very soon, reduce power consumption, thereby improved the used highly integrated memory of the portable type electronic product that requires low-power consumption or the reliability of logical device by the subthreshold current that reduces standby attitude by standby attitude according to the present invention.
And, should be understood that to the invention is not restricted to the specific embodiments as realization optimal mode of the present invention disclosed herein, and be not limited to the disclosed specific embodiment of this specification that claim of the present invention has been stipulated protection scope of the present invention.
Claims (5)
1, a kind of semiconductor device that reduces the standby power dissipation has the power line that predetermined power source voltage is provided to the totality circuit of described semiconductor device, also has the ground wire that ground voltage is provided to described internal circuit, and described semiconductor device comprises:
Be arranged on the 1st MOS transistor of at least a portion between described power line and the secondary circuit block, it is made of a plurality of circuit that are in stand-by state and operating state in same timing, perhaps constitute by described ground wire and described secondary circuit block, when described secondary circuit block is in stand-by state, make described the 1st MOS transistor turn-off and increase its threshold voltage by the control underlayer voltage, so that reduce its subthreshold current.
2, the semiconductor device that dissipates in standby power according to the minimizing of claim 1, wherein, logic level at the destined node of described secondary circuit block is fixed under the situation of stand-by state, form the 2nd MOS transistor of the subthreshold current path in a plurality of the 2nd MOS transistor of described secondary circuit block, linked on described power line or the ground wire by described the 1st MOS transistor, its another be not that the 2nd MOS transistor of subthreshold current path is directly linked on described power line or the described ground wire.
3, the semiconductor device that dissipates in standby power according to the minimizing of claim 1, wherein, the described grid of the 1st MOS transistor between described power line and described secondary circuit block, when the described secondary circuit block that connects described the 1st MOS transistor is when being in stand-by state, receive logic " height " level, when the described secondary circuit block that connects described the 1st MOS transistor when being in running order, receive logic " low " level, the 1st MOS transistor described underlayer voltage in working order that is made of the P-channel MOS transistor that underlayer voltage is arranged is than the low predetermined value of underlayer voltage of stand-by state.
4, the semiconductor device that dissipates according to the minimizing standby power of claim 1, wherein, the grid of the 1st MOS transistor between described ground wire and described secondary circuit block, when the described secondary circuit block that connects described the 1st MOS transistor is when being in stand-by state, receive logic " low " level, when the described secondary circuit block that connects described the 1st MOS transistor when being in running order, receive logic " height " level, described the 1st MOS transistor described underlayer voltage in working order that is made of the N-channel MOS transistor that underlayer voltage is arranged is than the high predetermined value of underlayer voltage of stand-by state.
5, the semiconductor device that dissipates according to the minimizing standby power of claim 4, wherein, described the 1st MOS transistor that forms on the separation trap can freely be controlled described underlayer voltage, and does not influence described the 2nd MOS transistor that forms described secondary circuit block.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012617A KR0150750B1 (en) | 1995-05-19 | 1995-05-19 | Reduced power consumption semiconductor circuit in the stand-by state |
| KR12617/95 | 1995-05-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1146638A true CN1146638A (en) | 1997-04-02 |
| CN1047262C CN1047262C (en) | 1999-12-08 |
Family
ID=19414959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96108463A Expired - Fee Related CN1047262C (en) | 1995-05-19 | 1996-05-19 | Semiconductor device capable of reducing power dissipation in stand-by state |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0983335A (en) |
| KR (1) | KR0150750B1 (en) |
| CN (1) | CN1047262C (en) |
| GB (1) | GB2300985B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1747062B (en) * | 2004-08-04 | 2010-05-12 | 松下电器产业株式会社 | Semiconductor memory device |
| CN1538521B (en) * | 2003-04-16 | 2010-05-26 | 精工爱普生株式会社 | Semiconductor integrated circuit, electronic apparatus and back grid potential control method of transistor |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19738714A1 (en) * | 1997-09-04 | 1999-03-18 | Siemens Ag | Integrated circuit with a switching transistor |
| FR2772217B1 (en) * | 1997-12-09 | 2001-11-23 | Sgs Thomson Microelectronics | BASIC INTEGRATED CIRCUIT CELL |
| KR100252844B1 (en) * | 1998-02-12 | 2000-04-15 | 김영환 | Circuit for standby current reduction |
| KR100451495B1 (en) * | 1998-12-12 | 2004-12-31 | 주식회사 하이닉스반도체 | Semiconductor Integrated Circuits with Standby Current Reduction Circuits |
| WO2000077785A1 (en) * | 1999-06-15 | 2000-12-21 | Hitachi, Ltd. | Reproduction system and integrated circuit |
| WO2002065642A1 (en) * | 2001-02-15 | 2002-08-22 | Hitachi,Ltd | Semiconductor integrated circuit, data processing system, and mobile communication terminal apparatus |
| JP2002352581A (en) * | 2001-05-25 | 2002-12-06 | Fujitsu Ltd | Semiconductor integrated circuit |
| JP4974202B2 (en) * | 2001-09-19 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
| JP3786608B2 (en) * | 2002-01-28 | 2006-06-14 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP2004171445A (en) | 2002-11-22 | 2004-06-17 | Renesas Technology Corp | Semiconductor data processor and data processing system |
| JP4261507B2 (en) | 2005-03-31 | 2009-04-30 | 富士通マイクロエレクトロニクス株式会社 | Clock network power consumption reduction circuit |
| JP2007095787A (en) * | 2005-09-27 | 2007-04-12 | Nec Electronics Corp | Semiconductor integrated circuit |
| WO2007113712A1 (en) * | 2006-03-30 | 2007-10-11 | Nxp B.V. | Low operational power control including power-gating switches |
| JP4191214B2 (en) * | 2006-08-01 | 2008-12-03 | エルピーダメモリ株式会社 | Semiconductor device |
| JP6263833B2 (en) * | 2012-10-22 | 2018-01-24 | 株式会社ソシオネクスト | Electronic circuit and semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567385A (en) * | 1983-06-22 | 1986-01-28 | Harris Corporation | Power switched logic gates |
| KR100254134B1 (en) * | 1991-11-08 | 2000-04-15 | 나시모토 류우조오 | Semiconductor integrated circuit having current reduction circuit in the standby state |
| KR100281600B1 (en) * | 1993-01-07 | 2001-03-02 | 가나이 쓰도무 | A semiconductor integrated circuit having a power reduction mechanism |
| EP0739097B1 (en) * | 1995-04-21 | 2004-04-07 | Nippon Telegraph And Telephone Corporation | MOSFET circuit and CMOS logic circuit using the same |
-
1995
- 1995-05-19 KR KR1019950012617A patent/KR0150750B1/en not_active IP Right Cessation
-
1996
- 1996-05-19 CN CN96108463A patent/CN1047262C/en not_active Expired - Fee Related
- 1996-05-20 JP JP8125085A patent/JPH0983335A/en active Pending
- 1996-05-20 GB GB9610573A patent/GB2300985B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538521B (en) * | 2003-04-16 | 2010-05-26 | 精工爱普生株式会社 | Semiconductor integrated circuit, electronic apparatus and back grid potential control method of transistor |
| CN1747062B (en) * | 2004-08-04 | 2010-05-12 | 松下电器产业株式会社 | Semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9610573D0 (en) | 1996-07-31 |
| CN1047262C (en) | 1999-12-08 |
| JPH0983335A (en) | 1997-03-28 |
| KR0150750B1 (en) | 1998-10-01 |
| KR960043149A (en) | 1996-12-23 |
| GB2300985B (en) | 2000-05-31 |
| GB2300985A (en) | 1996-11-20 |
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