WO2007113712A1

WO2007113712A1 - Low operational power control including power-gating switches

Info

Publication number: WO2007113712A1
Application number: PCT/IB2007/050952
Authority: WO
Inventors: Phillip Christie
Original assignee: Nxp B.V.; U.S. Philips Corporation
Priority date: 2006-03-30
Filing date: 2007-03-19
Publication date: 2007-10-11

Abstract

A method and device for controlling application of power to a low operational power (LOP) CMOS circuit are disclosed. The method comprising the step of incorporating a power grating circuit between a power supply and the LOP CMOS circuit, the power grating circuit controlling the electrical power flow the LOP CMOS circuit, wherein a leakage current in the LOP CMOS circuit is increased to reduce dynamic power required.

Description

LOW OPERATIONAL POWER CONTROL INCLUDING POWER-GATING SWITCHES

This invention is related to the field of Low Operational Power circuits (LOP) and, more specifically, to the incorporation of power-grating switching to LOP circuits

Many portable consumer devices, such as MP3 players, cell phones, Personal Digital Assistants (PDAs) or medical devices, such a heart pace monitors, have a need for extended battery life when in active mode.

Low power operational (LOP) circuits have been developed using CMOS technology that satisfies many of the requirements of extended battery life. However, such circuits sacrifice transistor leakage current for an overall reduction in the operational power - i.e., the sum of the leakage and dynamic power. For many applications, such as heart rate monitors with no standby mode, such an increase in leakage is acceptable. However, the range of applications of LOP CMOS circuitry could be greatly extended, to include, for example, battery operated and portable MP3 players, cell phones, Personal Digital Assistants (PDAs), etc., if the LOP CMOS circuits could be easily switched off when not in use. Hence, there is need in the industry for a method for switching off circuitry using LOP

CMOS technology when the circuitry is not in use.

A device suitable for controlling application of power to a low operational power CMOS is disclosed. The device comprising an LOP CMOS circuit operable to perform a known function and a power switch connected between the LOP CMOS circuit and a power supply, the power switch controlling an electrical flow to the LOP CMOS circuit wherein a leakage current in the LOP CMOS circuit is increased to reduce dynamic power required.

Figure 1 illustrates an exemplary low operational power circuit for extending battery life in accordance with the principles of the invention.

It is to be understood that this drawing is solely for the purpose of illustrating the concepts of the invention and is not intended as a definition of the limits of the invention. The embodiment shown in the figure and described in the accompanying detailed description is to be used as illustrative embodiment and should not be construed as the only manner of practicing the invention. For many portable consumer devices it is important to minimize the total operational power (static and dynamic power) rather than only the static power. The optimum trade-off for the sum of these two power components occurs when they are approximately equal. This may be represented as: f / ^« 4Λ [i]

Dynamic Static

where Vdd is the supply voltage; Iiea_k is the leakage current; Cioad is the total capacitive load; a is the logic activity (the average percentage of devices that switch during a clock cycle;

/is the clock frequency represented as l/L_dT_g;

L_d is the equivalent logic depth (the range number of logic cells between two clocked latches; and T_g is the intrinsic gate delay represented as Cι_oadVdd/I_on-

Rewriting equation 1 in the form of:

K K_nn __ LL_ad [2]

'^■ leak

shows that the minimum operation power is achieved when the ratio of the on- to off-state currents, I_0n, Iι_eak, respectively, is approximately equal to the ratio of the logic depth to the activity factor. Equation 2 couples optimum device technology with application dependent design in a very simple and elegant manner. From equation 2, it can be seen that the optimum on- to off- current ratio is approximately 100 for a logic depth of 30 and logic activity of 30 percent. This may be compared to a value of several hundred thousand for low standby leakage devices that are more typically used in consumer electronics and medical monitoring applications. LOP devices that maximize active battery life are therefore very leaky when compared to their drive currents and thousands of times more leaky than their low standby power counterparts. For applications where a stand-by mode is highly desirable, even LP (low power) devices may be too leaky when measured on a per unit area basis.

Power switches were created to control the excessive standby leakage of deep-submicron logic gates. However, these power switches have been designed to control very small amounts of leakage associated with Low Standby Power (LSTP) logic. LOP CMOS logic, on the other hand, is designed so that the leakage current is many times greater (in the order of thousands of times greater) than for LSTP logic. The increased leakage current allows lower operating voltages to minimize the total power. However, because of the large leakage current, LOP CMOS is not viable in standby mode.

In accordance with the principles of the invention by combining power grating switches with LOP CMOS logic, LOP CMOS circuitry may be fabricated that includes a standby mode, and, consequently extending battery life.

Figure 1 illustrates an exemplary circuit 1 OO for achieving minimum operational power in accordance with the principles of the invention. In this illustrated circuit a power-gating circuit 110 is incorporated between one or both power rails 130, 135 of LOP CMOS circuit 120. Power- gating circuit 110 comprises a high impendence FET 112 that is capable of switching voltage V^ on rail 130 to a virtual Vdd rail 135. Virtual Vdd rail 135 provides power to LOP CMOS circuit 120. The switch of voltage V^ onto virtual Vdd rail 135controls the active/standby state of LOP CMOS circuit 120. Capacitors 140 and 145 represent loads presented by other CMOS circuitry and are drawn to show that the illustrated circuit is not in isolation from other circuit components.

While there has been shown, described, and pointed out fundamental novel features of the present invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the apparatus described, in the form and details of the devices disclosed, and in their operation, may be made by those skilled in the art without departing from the spirit of the present invention. It is expressly intended that all combinations of those elements that perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated.

Claims

What is claimed is:

1. A method for controlling application of power to a low operational power (LOP) CMOS circuit, said method comprising the step of: incorporating a power grating circuit between a power supply and the LOP CMOS circuit, the power grating circuit controlling the electrical power flow to the LOP CMOS circuit, wherein a leakage current in the LOP CMOS circuit is increased to reduce dynamic power required.

2. The method as recited in claim 1, wherein the power grating circuit controls electrical power flow to at least one LOP CMOS circuit.

3. A device for implementing a standby mode in LOP CMOS circuit, said device comprising: a power grating circuit incorporated between a power supply and the LOP CMOS circuit; and the power grating circuit controlling the electrical power flow to the LOP CMOS circuit, wherein a leakage current in the LOP CMOS circuit is increased to reduce dynamic power required.

4. The device as recited in claim 3, wherein the power grating circuit controls electrical power flow to at least one LOP CMOS circuit.