GB2300985A - CMOS IC with reduced subthreshold standby leakage current - Google Patents
CMOS IC with reduced subthreshold standby leakage current Download PDFInfo
- Publication number
- GB2300985A GB2300985A GB9610573A GB9610573A GB2300985A GB 2300985 A GB2300985 A GB 2300985A GB 9610573 A GB9610573 A GB 9610573A GB 9610573 A GB9610573 A GB 9610573A GB 2300985 A GB2300985 A GB 2300985A
- Authority
- GB
- United Kingdom
- Prior art keywords
- mos transistor
- standby state
- circuit block
- lower circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 description 10
- 230000007704 transition Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The power supplies to circuit blocks in a CMOS integrated circuit, such as a very dense DRAM, are disabled during standby by series MOS switches MP1-MPm and MN1-MNm, whose substrate (back-gate) potentials VNW1-VNWm and VPW1-VPWm are changed in synchronism (figure 3) with the disabling signals applied to their gates such that standby leakage current is reduced. Some circuit blocks may have only one power switch, a direct connection being provided to the other supply.
Description
SEMICONDUCTOR DEVICE FOR REDUCING POWER
CONSUMPTION IN STANDBY STATE
The present invention relates to a semiconductor device for reducing power consumption due to a subthreshold current in a standby state.
In a particular arrangement to be described below and illustrative of the invention there will be described a semiconductor device suitable for being applied to a gigabit memory or logic device using a deep submicron MOS transistor having a cutoff characteristic poorer than that of a long channel transistor, to reduce dramatically a standby current, thereby decreasing power consumption in a standby state.
A previously proposed arrangement will now be described with reference to Fig. 1 of the accompanying drawings which show schematically the circuit configuration of a memory or logic device. As shown in
Fig. 1, the previously proposed circuit is constructed so that a global power line L100 and global ground line LO are directly connected to a circuit block BO.
Accordingly, when the circuit uses a deep submicron MOS transistor, a lot of subthreshold current flows through the circuit, even in a cutoff state. This largely increases the power consumption in the standby state. As the MOS transistor is scaled down, its threshold voltage is decreased, resulting in an increase of the sub threshold current, even in a threshold region IVGS > VTI, # of the transistor. This leads to the above problem.
Therefore, in the gigabit memory device or logic device consisting of the deep submicron MOS transistors, power consumption in the standby state becomes a serious problem. To solve this problem, several techniques for the purpose of reducing power consumption in the standby state have been proposed. One of those is switchedsource impedance CMOS circuit technology published in "IEEE Journal of solid state circuits, Vol. 28, 11,
November 1993" by Hitachi in Japan. This technique can reduce the subthreshold current in the standby state remarkably. However, it increases the delay of the circuit. Also, the standby state to an active state transition becomes slow, decreasing the overall circuit performance.
Features of a semiconductor device to be described below, as an example, are that the transition from the standby state to the active state is fast, and the subthreshold current in the standby state is decreased, thereby reducing its power consumption.
In a particular arrangement to be described below, as an example, there is a semiconductor device for reducing power consumption in a standby state, which has a power line providing internal circuits of the semiconductor device with a predetermined power voltage, and a ground line providing the internal circuits with a ground voltage, and which includes a first MOS transistor between the power line and a lower circuit block having circuits with identical timing in a standby state and in an active state respectively in the internal circuits, or between the ground line and the lower circuit block, the first MOS transistor being turned off and its threshold voltage being increased by controlling a substrate voltage when the lower circuit block is in the standby state, to reduce its subthreshold current.
Embodiments illustrative of the invention will now be described, by way of example, with reference to Figs.
2 to 5A and 5B of the accompanying drawings in which:
Fig. 2 shows schematically the configuration of one embodiment of a semiconductor device,
Fig. 3 is a timing diagram of a control signal for use with the embodiment of Fig. 2,
Fig. 4 shows schematically the configuration of another embodiment of a semiconductor device, and
Figs. 5A and 5B are schematic diagrams showing a triple-well structure of a semiconductor device illustrative of the present invention.
Referring to the accompanying drawings, Fig. 2 shows schematically the configuration of a semiconductor device. As shown in Fig. 2, the semiconductor device is constructed in such a manner that a global power line
L100 and global ground line LO are not directly connected to a circuit block, (B1, B2...Bm). The overall circuit blocks are divided into a plurality of lower circuit blocks,(B1, Bz...Bm), each of which consists of circuits having identical standby states and active states.
Local lower power lines Lal, La2...Lam, and local lower ground lines Lbl, Lb2...Lbm, corresponding to respective lower circuit blocks B1, B2...Bm are respectively connected to global power line L100 and global ground line LO through respective switches, PMOS transistor MP1, MP2...MPm and NMOS transistor MN1, MN2...MNm thereby to form a hierarchy. An N-well and P-well on which PMOS transistor MP1 and NMOS transistor MN1 are respectively formed are separated from wells on which other MOS transistors are formed, which form a memory or logic device. Fig. 3 is a timing diagram of a control signal of Fig. 2. Since the lower circuit blocks B1, B2...Bm have identical states, the operation of one of them only will be described.
As shown in Fig. 3, a signal bPi inputting to the gate of PMOS transistor MP1 has a logic level "high" when lower circuit block B1 to which PMOS transistor MP1 is connected is in the standby state, and it has a logic level "low" in the case of the active state. On the other hand, a signal XNi inputting to the gate of NMOS transistor MN1 has a logic level "low" when lower circuit block B1 to which NMOS transistor MN1 is connected is in the standby state, and it has a logic level "high" in the case of the active state.Accordingly, if the lower circuit block B1 is changed from the active state to the standby state, PMOS transistor MP1 and NMOS transistor
MN1 are turned off according to control signal OPI, XNi- As a result, lower power line Lal and lower ground line
Lbl are isolated from global power line L100 and global ground line LO, and thus power consumption in the standby state is determined by the subthreshold current which flows through PMOS transistor MP1 and NMOS transistor MN1.
As shown in Fig. 3, for the voltage VNwi of the Nwell on which PMOS MP1 is formed, voltage VNW-SB in the standby state is higher than voltage VNW-AC in the active state by a predetermined value. For the voltage Vpwi of the P-well on which NMOS MN1 is formed, voltage VpW-SB in the standby state is lower than voltage VPW~AC in the active state by a predetermined value. As a result, respective threshold voltages of PMOS transistor MP1 and
NMOS transistor MN1 are increased according to body effect. Accordingly, the subthreshold currents of PMOS transistor MP1 and NMOS transistor MP1 in the standby state are remarkably decreased, resulting in a reduction of the power consumption.
Meanwhile, if the standby state is changed to the active state, control signal bPi iS changed from a logic level "high" to a logic level "low", and control signal mNi from a logic level "low" to a logic level "high". At the same time voltage VNWi is decreased from voltage VNw, SB to voltage VNW-ACI and in turn voltage Vpwi is increased from voltage Vpw-SB to voltage VpW~Ac, thereby reducing the respective threshold voltages of PMOS transistor MP1 and NMOS transistor MN1. Accordingly, the standby state to active state transition occurs quickly.
That is, the respective well voltages of PMOS transistor
MP1 and NMOS transistor MN1 are different from each other in the standby state and the active state. As a result, the threshold voltage is increased in the standby state, reducing the threshold current. On the other hand, the threshold voltage is decreased in the active state so that the standby state to the active state transition occurs quickly, and at the same time, the current driving capabilities of PMOS transistor MP1 are NMOS transistor
MN1 are improved. Referring to Fig. 2, one of global power line L100 and global ground line LO may be directly connected to the circuit block, and the other one may be used for hierarchy using the lower power line.
Generally, in a memory device such as a dynamic random access memory (DRAM), the logic level of an internal node is fixed in the standby state. In this case, the subthreshold current can be more effectively reduced. Fig. 4 shows a method for connecting a power line to an internal circuit having a fixed logic level in the standby state. The circuit block shown in Fig. 4 consists of three serially connected inverters. In this circuit, if an input node nl of the inverter is logic "high", node n2 logic "low", node n3 logic "high", and node n4 logic "low", the subthreshold current of PMOS transistor MPa, NMOS transistor MNb, and PMOS transistor
MPc cause lower power line Lai to decrease its voltage, and lower ground line Lbi to increase its voltage.Here, as shown in Fig. 4, transistors MPa, MNb and MPc as paths of the subthreshold current, are connected to lower power line Lai or lower ground line Lbi, and other transistors are connected to global power line L100 and global ground line LO, and a reverse voltage is applied between the gates and the sources of transistors MPa, MNb and MPc.
This reduces the subthreshold current considerably.
Similarly, the subthreshold current of the MOS transistor is abruptly decreased if the reverse voltage is applied between its gate and source.
The voltage of lower power line Lai is decreased by some quantity of value AVDD in comparison with the voltage of global power line L100, due to the subthreshold current. On the other hand, the voltage of lower ground line Lbi is increased by some quantity of value AVss in comparison with the voltage of global ground line LO, due to the subthreshold current. Accordingly, the reverse bias corresponding to the voltage difference AVDD is applied between the gates and sources of transistors MPa and MPc, and the reverse bias corresponding to voltage the difference hvSs is applied between the gate and source of the transistor MNb.
Figs. 5A and 5B are schematic diagrams showing a triple-well structure for the purpose of realizing a semiconductor device illustrative of the arrangement of
Fig. 4. Since the substrate voltages of PMOS transistor
MPi and NMOS transistor MNi, which serve as switches between the global power line and global ground line, and the lower power line and lower ground line, should be isolated from the substrate voltages of the other transistors forming the internal circuits, the transistors MPi and MNi should be formed on wells separated from each other. That is, the triple-well structure is suitable for forming PMOS transistor MPi and
NMOS transistors MNi on separate wells in order to contro freely the voltage of the well (substrate voltage).
Fig. 5A shows a triple-well consisting of a first Nwell 1 and second N-well 2 which are separated from each other and formed on a P-type substrate 10, a first P-well 3 separated from first and second N-wells 1 and 2, and a second P-well 4 formed in first N-well 1. PMOS transistor MPi serving as a switch between the global power line and the lower power line is formed in second
N-well 2, and NMOS transistor MNi serving as a switch between the global ground line and the lower ground line is formed in second P-well 4. Accordingly, even if the well voltages, VNwi and Vpwi are changed, other transistors forming the circuit are not affected. Fig. 5B shows a triple-well structure according to the other embodiment of the present invention.This triple-well consists of a first P-well 11 and second P-well 12 which are separated from each other and formed on an N-type substrate 20, a first N-well 13 separated from first and second P-wells 11 and 12, and a second N-well 14 formed in the first P-well 11. PMOS transistor MPi serving as a switch between the global power line and the lower power line is formed in second N-well 14, and NMOS transistor
MNi serving as a switch between the global ground line and the lower ground line is formed in the second P-well 12. Accordingly, even if the well voltages VNWi and Vpwi are changed, other transistors forming the circuit are not affected.
In the case that one of the global power line L100 and the global ground line L0 is directly connected to the circuit block, and the other one is used for hierarchy using the lower power line, only one of second
P-well 4 and second N-well 2 may be formed on which the switching transistors are formed, as shown in Fig. 5A.
Also, in the case of the device shown in Fig. 5B, the well may be formed according to the same principle as that of the aforementioned case.
As described, in the above embodiments of the present invention, the standby state to the active state transition becomes fast, and power consumption is reduced by decreasing the subthreshold current in the standby state, thereby improving the reliability of a high integration memory or logic device used for portable electronic products requiring low power consumption.
It will be understood that, although the present invention has been illustrated, by way of example, with reference to particular embodiments, variations and modifications thereof, as well as other embodiments, may be made within the scope of the protection sought by the appended claims.
Claims (7)
1. A semiconductor device for reducing power consumption in a standby state, having a power line providing internal circuits of the semiconductor device with a predetermined power voltage, and a ground line providing the internal circuits with a ground voltage, the semiconductor device including a first MOS transistor provided between the power line and a lower circuit block which includes circuits having identical timing in a standby state and an active state in the internal circuits, or between the ground line and the lower circuit block, the first MOS transistor being turned off and its threshold voltage being increased by controlling a substrate voltage when the lower circuit block is in the standby state, to reduce its subthreshold current.
2. A semiconductor device for reducing power consumption in a standby state as claimed in claim 1, wherein in the case in which predetermined nodes of the lower circuit block have a fixed logic level in the standby state, a second MOS transistor, providing a path for subthreshold current of second MOS transistors forming the lower circuit block, is connected to the power line or the ground line through the first MOS transistor and the other second MOS transistor which is not to provide a path for the subthreshold current is directly connected to the power line or the ground line.
3. A semiconductor device for reducing power consumption in a standby state as claimed in claim 1, wherein the gate of the first MOS transistor between the power line and the lower circuit block receives a logic level "high" when the lower circuit block to which the first MOS transistor connected is in the standby state, and receives a logic level "low" when the lower circuit block to which the first MOS transistor connected is in the active state, the first MOS transistor being a Pchannel MOS transistor having a substrate voltage, and the substrate voltage in the active state being lower than that in the standby state by a predetermined value.
4. A semiconductor device for reducing power consumption in a standby state as claimed in claim 1, wherein the gate of the first MOS transistor between the ground line and the lower circuit block receives a logic level "low" when the lower circuit block to which the first MOS transistor connected is in the standby state, and receives a logic level "high" when the lower circuit block to which the first MOS transistor connected is in the active state, the first MOS transistor being a Nchannel MOS transistor having a substrate voltage, and the substrate voltage in the active state being higher than that in the standby state by a predetermined value.
5. A semiconductor device for reducing power consumption in a standby state as claimed in claim 4, wherein the first MOS transistor is on a separate well to control freely the substrate voltage without affecting the second MOS transistor of the lower circuit block.
6. A semiconductor device as claimed in claim 1 including an arrangement substantially as described herein with reference to Fig. 2, Fig. 4 or Fig. 5 of the accompanying drawings.
7. A method of operating a semiconductor device as claimed in claim 1 substantially as described herein with reference to Fig. 3 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012617A KR0150750B1 (en) | 1995-05-19 | 1995-05-19 | Reduced power consumption semiconductor circuit in the stand-by state |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9610573D0 GB9610573D0 (en) | 1996-07-31 |
| GB2300985A true GB2300985A (en) | 1996-11-20 |
| GB2300985B GB2300985B (en) | 2000-05-31 |
Family
ID=19414959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9610573A Expired - Fee Related GB2300985B (en) | 1995-05-19 | 1996-05-20 | Semiconductor device for reducing power consumption in standby state |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0983335A (en) |
| KR (1) | KR0150750B1 (en) |
| CN (1) | CN1047262C (en) |
| GB (1) | GB2300985B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012261A1 (en) * | 1997-09-04 | 1999-03-11 | Siemens Aktiengesellschaft | Integrated circuit with a switching transistor |
| FR2772217A1 (en) * | 1997-12-09 | 1999-06-11 | Sgs Thomson Microelectronics | Electronic library cell element structure |
| GB2334391A (en) * | 1998-02-12 | 1999-08-18 | Lg Semicon Co Ltd | CMOS standby current reduction |
| US7257720B2 (en) | 2002-11-22 | 2007-08-14 | Renesas Technology Corp. | Semiconductor processing device for connecting a non-volatile storage device to a general purpose bus of a host system |
| WO2007113712A1 (en) * | 2006-03-30 | 2007-10-11 | Nxp B.V. | Low operational power control including power-gating switches |
| US7463076B2 (en) | 2005-03-31 | 2008-12-09 | Fujitsu Limited | Power consumption reduction circuit for clock network |
| US8378741B2 (en) | 2001-09-19 | 2013-02-19 | Renesas Electronics Corporation | Multiple circuit blocks with interblock control and power conservation |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451495B1 (en) * | 1998-12-12 | 2004-12-31 | 주식회사 하이닉스반도체 | Semiconductor Integrated Circuits with Standby Current Reduction Circuits |
| WO2000077785A1 (en) * | 1999-06-15 | 2000-12-21 | Hitachi, Ltd. | Reproduction system and integrated circuit |
| WO2002065642A1 (en) * | 2001-02-15 | 2002-08-22 | Hitachi,Ltd | Semiconductor integrated circuit, data processing system, and mobile communication terminal apparatus |
| JP2002352581A (en) * | 2001-05-25 | 2002-12-06 | Fujitsu Ltd | Semiconductor integrated circuit |
| JP3786608B2 (en) * | 2002-01-28 | 2006-06-14 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP2004336010A (en) * | 2003-04-16 | 2004-11-25 | Seiko Epson Corp | Semiconductor integrated circuit, electronic equipment, and method of controlling back-gate potential of transistor |
| JP4330516B2 (en) * | 2004-08-04 | 2009-09-16 | パナソニック株式会社 | Semiconductor memory device |
| JP2007095787A (en) * | 2005-09-27 | 2007-04-12 | Nec Electronics Corp | Semiconductor integrated circuit |
| JP4191214B2 (en) * | 2006-08-01 | 2008-12-03 | エルピーダメモリ株式会社 | Semiconductor device |
| JP6263833B2 (en) * | 2012-10-22 | 2018-01-24 | 株式会社ソシオネクスト | Electronic circuit and semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567385A (en) * | 1983-06-22 | 1986-01-28 | Harris Corporation | Power switched logic gates |
| US5274601A (en) * | 1991-11-08 | 1993-12-28 | Hitachi, Ltd. | Semiconductor integrated circuit having a stand-by current reducing circuit |
| US5408144A (en) * | 1993-01-07 | 1995-04-18 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69632098T2 (en) * | 1995-04-21 | 2005-03-24 | Nippon Telegraph And Telephone Corp. | MOSFET circuit and its application in a CMOS logic circuit |
-
1995
- 1995-05-19 KR KR1019950012617A patent/KR0150750B1/en not_active IP Right Cessation
-
1996
- 1996-05-19 CN CN96108463A patent/CN1047262C/en not_active Expired - Fee Related
- 1996-05-20 JP JP8125085A patent/JPH0983335A/en active Pending
- 1996-05-20 GB GB9610573A patent/GB2300985B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4567385A (en) * | 1983-06-22 | 1986-01-28 | Harris Corporation | Power switched logic gates |
| US5274601A (en) * | 1991-11-08 | 1993-12-28 | Hitachi, Ltd. | Semiconductor integrated circuit having a stand-by current reducing circuit |
| US5408144A (en) * | 1993-01-07 | 1995-04-18 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012261A1 (en) * | 1997-09-04 | 1999-03-11 | Siemens Aktiengesellschaft | Integrated circuit with a switching transistor |
| FR2772217A1 (en) * | 1997-12-09 | 1999-06-11 | Sgs Thomson Microelectronics | Electronic library cell element structure |
| GB2334391A (en) * | 1998-02-12 | 1999-08-18 | Lg Semicon Co Ltd | CMOS standby current reduction |
| GB2334391B (en) * | 1998-02-12 | 2000-03-29 | Lg Semicon Co Ltd | Circuit for standby current reduction |
| US8378741B2 (en) | 2001-09-19 | 2013-02-19 | Renesas Electronics Corporation | Multiple circuit blocks with interblock control and power conservation |
| US7257720B2 (en) | 2002-11-22 | 2007-08-14 | Renesas Technology Corp. | Semiconductor processing device for connecting a non-volatile storage device to a general purpose bus of a host system |
| US7447932B2 (en) | 2002-11-22 | 2008-11-04 | Renesas Technology Corp. | Semiconductor data processing device and data processing system |
| US7463076B2 (en) | 2005-03-31 | 2008-12-09 | Fujitsu Limited | Power consumption reduction circuit for clock network |
| WO2007113712A1 (en) * | 2006-03-30 | 2007-10-11 | Nxp B.V. | Low operational power control including power-gating switches |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1047262C (en) | 1999-12-08 |
| KR0150750B1 (en) | 1998-10-01 |
| JPH0983335A (en) | 1997-03-28 |
| GB9610573D0 (en) | 1996-07-31 |
| KR960043149A (en) | 1996-12-23 |
| GB2300985B (en) | 2000-05-31 |
| CN1146638A (en) | 1997-04-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100520 |