CN114647541B - Circuit self-repairing method based on improved evolution hardware - Google Patents
Circuit self-repairing method based on improved evolution hardware Download PDFInfo
- Publication number
- CN114647541B CN114647541B CN202210269757.5A CN202210269757A CN114647541B CN 114647541 B CN114647541 B CN 114647541B CN 202210269757 A CN202210269757 A CN 202210269757A CN 114647541 B CN114647541 B CN 114647541B
- Authority
- CN
- China
- Prior art keywords
- evolution
- circuit
- output
- node
- hardware
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 230000008439 repair process Effects 0.000 claims abstract description 11
- 108090000623 proteins and genes Proteins 0.000 claims description 41
- 210000000349 chromosome Anatomy 0.000 claims description 38
- 230000002068 genetic effect Effects 0.000 claims description 28
- 238000004364 calculation method Methods 0.000 claims description 18
- 230000003068 static effect Effects 0.000 claims description 17
- 230000003044 adaptive effect Effects 0.000 claims description 12
- 230000007246 mechanism Effects 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 6
- 230000006978 adaptation Effects 0.000 claims description 4
- 230000001960 triggered effect Effects 0.000 claims description 4
- 230000009191 jumping Effects 0.000 claims description 2
- 230000035772 mutation Effects 0.000 claims description 2
- 230000002441 reversible effect Effects 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 35
- 238000010586 diagram Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/181—Eliminating the failing redundant component
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1456—Hardware arrangements for backup
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/187—Voting techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/12—Computing arrangements based on biological models using genetic models
- G06N3/126—Evolutionary algorithms, e.g. genetic algorithms or genetic programming
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biophysics (AREA)
- Bioinformatics & Cheminformatics (AREA)
- Bioinformatics & Computational Biology (AREA)
- Evolutionary Biology (AREA)
- Physiology (AREA)
- Genetics & Genomics (AREA)
- Artificial Intelligence (AREA)
- Biomedical Technology (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Hardware Redundancy (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a circuit self-repairing method based on improved evolution hardware, which adopts the evolution hardware to realize a self-repairing circuit; and adding a compensation circuit to the circuit system, repairing the error output, and performing exclusive-or operation on the target output and the error output to obtain a truth table of the compensation system by utilizing the characteristic of reversible computation of exclusive-or operation, wherein the compensation system realizes the function of repairing the error output by utilizing exclusive-or operation. The invention uses the self-repairing circuit of the evolution hardware to repair the error part only, reduces the circuit resource and improves the reliability.
Description
Technical Field
The invention belongs to the technical field of design of a reliable embedded system, and particularly relates to a circuit self-repairing method based on improved evolution hardware.
Background
For aviation, aerospace, navigation, weapons and other application scenes, the operation of the circuit is difficult to be manually interfered. The ability of the circuit to self-repair once it fails is desirable. The traditional repairing method adopts triple-modular redundancy backup, and is directly switched to a brand new circuit when faults occur; this approach, while effective, may utilize excessive circuit resources because a small error initiates the entire backup system.
Because of the characteristics of application scenes such as aviation, aerospace, navigation, weapons and the like, all information which is possibly in error cannot be input manually in advance. The self-evolution characteristic of the evolution hardware perfectly fits the application scene, only a truth table of the evolution hardware is needed to be given, the evolution hardware utilizes a genetic algorithm to carry out optimization to find the configuration information of the target evolution circuit, and the evolution of the circuit is completed. The evolution hardware characteristics can well realize the compensation system, and different compensation systems are evolved according to different errors to repair.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a circuit self-repairing method based on improved evolution hardware, which realizes a self-repairing circuit by using the improved evolution hardware and improves the evolution speed of the evolution hardware.
The invention adopts the following technical scheme:
The circuit self-repairing method based on the improved evolution hardware is characterized by comprising the following steps of:
S1, when a circuit fails, performing bit exclusive OR operation on an error output column of the failed circuit and an output column in a truth table of the correct circuit, and when a return value is 1, determining a repair section for the failed circuit; injecting the input columns of the truth table of the correct circuit into the fault circuit to obtain an error output column;
s2, the compensation system performs exclusive OR calculation on the real output column in the true circuit truth table and the error output column of the fault circuit according to the step S1 to obtain a target output column of the evolution hardware;
S3, performing bit exclusive OR calculation on the target output columns of the evolution hardware in the step S2 and the evolution hardware target output columns stored in the static configuration library respectively after the target output columns are inverted, adding each bit of the calculation result to obtain a sum value, and taking the sum value as an evolution hardware similarity value between the target evolution hardware and the evolution hardware stored in the static configuration library; taking the chromosome corresponding to the maximum value in the sum values in the static configuration library as the chromosome of the high-similarity individual;
s4, dividing the non-evolved evolution hardware into a plurality of blocks by using a block evolution mechanism, and dividing a target output column and a target input column of the evolution hardware according to the same block number according to the divided block number;
S5, the evolution hardware target input column divided in the step S4 and the high-similarity individual chromosome obtained in the step S3 are respectively transmitted into the non-evolution hardware of which the corresponding blocks are divided, an adaptive genetic algorithm of the adaptive evolution hardware is realized in an ARM computing core of the evolution hardware, and the evolution of the non-evolution hardware is completed;
S6, performing exclusive OR operation on the evolved evolution hardware evolved in the step S5 and the error bit corresponding to the fault circuit to finish repair.
Specifically, in step S5, the evolution hardware includes an FPGA logic array and an ARM computing core, and a VRC virtual reconfigurable circuit is built in the FPGA logic array; utilizing a chromosome to configure a VRC virtual reconfigurable circuit, inputting the configured VRC virtual reconfigurable circuit into an evolution hardware target input column to generate an output column, carrying out Hamming distance comparison on the output column and the evolution hardware target output column, and summing the comparison values to be used as fitness values of corresponding chromosomes; and realizing a genetic method by programming in an ARM computing core.
Further, the VRC virtual reconfigurable circuit comprises input nodes, PE nodes and output nodes, wherein the PE nodes are arranged in a matrix form, the linking degree L is set, and the middle PE nodes in the same column are connected with the front L-1 column;
The PE node comprises two input circuits and one output circuit and has a unique number; the two input circuits are respectively connected with an output circuit for selecting PE nodes by using a multiplexer, and the serial numbers of the selected PE nodes are used as the gene bits of the PE nodes;
selecting a logic operation for two input values selected by two input circuits by using a multiplexer in each PE node, and taking the selected logic operation number as the gene bit of the PE node; taking the PE node numbers and the logic calculation numbers of the two input values selected by the two input circuits as the genome of the PE node;
The output node of the VRC virtual reconfigurable circuit uses a multiplexer to select the output of a PE node as input, and the serial number of the selected PE node is used as the genome of the output node;
the genomes of all PE nodes and the output node together constitute the chromosome of the VRC virtual reconfigurable circuit.
Furthermore, a plurality of input signals exist in the PE node, the input signals enter the first multiplexer to select a first input signal, and the first input signal is the gene bit 1 corresponding to the PE node number; the plurality of input signals enter a second multiplexer to select a second input signal, wherein the second input signal is gene bit 2 corresponding to the PE node number; the PE node stores a function table which contains a plurality of one-bit logic operations and has corresponding numbers; selecting a function as an operation function of the PE node, and selecting a signal as a gene position 3 of the corresponding PE node; the selected two input signals are operated by the selected logic operation to obtain PE node output.
Further, the hamming distance is more specifically:
Inputting the configured VRC virtual reconfigurable circuit into a target input column to obtain an output column, performing exclusive OR calculation on the output column and the corresponding evolution hardware target output column respectively after inverting, and summing each bit to obtain a Hamming distance; and summing all the hamming distances to obtain the fitness value of the chromosome.
Further, the genetic method implemented in the ARM computing core specifically comprises the following steps:
S501, taking the chromosomes of the individuals with high similarity matched in the static configuration library as an initial individual, and randomly generating m-1 individuals; creating a roulette selection function fun_ roulette (m, n) according to a roulette method, wherein the function is the fitness of inputting m individuals, selecting n individuals according to the roulette method, creating a random generation function random (k), and generating k random numbers Ri;
S502, an ARM computing core is utilized to realize an fitness computing module, fitness values of m individuals are computed and stored, a genetic algorithm is jumped out after the output condition of a fitness function is triggered, and evolution is finished to obtain a target circuit; simultaneously calculating a population diversity parameter delta;
S503, judging whether the maximum fitness of m individuals is equal to or greater than a maximum fitness value; if the adaptation value is equal to or greater than the maximum adaptation value, the evolution is exited, the evolution is completed, and otherwise, the step S504 is entered;
S504, setting self-adaptive exchange probability Pc, when population diversity parameter delta is larger than diversity comparison value a, pc is 1.3, increasing, selecting n1 individuals from m individuals in step S502 as crossed chromosomes by using roulette selection function fun_ roulette (m, n 1), generating k random numbers by using random generation function random (k) according to total chromosome gene number k, pairing every two n1 individuals, and exchanging the ith gene position when the ith random number is larger than self-adaptive exchange probability Pc;
S505, setting self-adaptive variation probability Pm, when a diversity parameter delta is larger than a diversity comparison value a and Pm is increased by 1.1, selecting n2 individuals from m individuals in the step S502 as chromosomes by using a roulette selection function fun_ roulette (m, n 2), calculating the number w of gene bits needing to be mutated according to the total number k of the gene bits by Pm, generating w random numbers by using a random generation function random (w), multiplying the w random numbers by the number k of the gene bits to obtain the number of the gene bits needing to be mutated, and randomly changing the gene bits needing to be mutated into a gene value in a specified range;
S506, obtaining n1 exchange offspring from the step S504 by using an epoch-crossing elite algorithm, obtaining n2 variation offspring from the step S505, respectively calculating fitness values, obtaining m parent fitness values from the step S502, and selecting m individuals from m+n1+n2 individuals by using a function fun_ roulette (m+n1+n2, m);
s507, obtaining m individuals from the step S506, entering the step S502, jumping out of the genetic algorithm after the fitness function output condition is triggered, and ending evolution to obtain a target circuit.
Further, in step S502, the diversity parameter δ is specifically:
wherein favg is the m individual fitness average, fmax is the m individual fitness maximum, fmin is the m individual fitness minimum.
Further, in step S504, the adaptive switching probability Pc is specifically:
wherein a is a diversity comparison value, and delta is a diversity parameter.
Further, in step S504, the gene exchange is specifically:
wherein Ri is a random number.
Further, in step S505, the automatic variation probability Pm is changed as follows:
Wherein a is a diversity comparison value, and delta is a diversity parameter;
the j-th gene bit is randomly transformed into a value in a specified range, and the j value is specifically:
wherein Ri is a random number.
Compared with the prior art, the invention has at least the following beneficial effects:
The circuit self-repairing method based on the improved evolution hardware is different from the traditional self-repairing circuit design method. The self-repairing function of the circuit is realized by adopting an evolution hardware method, and various logic errors can be self-repaired under the condition of using less circuit resources. The traditional circuit uses a triple-modular redundancy backup repair circuit, and the whole backup circuit can be started when a tiny logic error occurs in the circuit. The self-repairing circuit using the evolution hardware only repairs the error part, thereby greatly reducing circuit resources and improving reliability.
Furthermore, for the realization of evolution hardware, a VRC virtual reconfigurable circuit is established at the bottom layer by utilizing an FPGA, and different circuit errors are correspondingly repaired by means of the programmable characteristic of the FPGA. And a genetic algorithm is realized in an ARM core of evolution hardware, so that the evolution speed is improved, and the evolution function of a circuit is completed better.
Furthermore, the construction mode of the VRC virtual reconfigurable circuit is used in the reconfigurable part of the FPGA, and the reconfigurable characteristic of the circuit is finished under the condition that the underlying logic of the FPGA is not required to be known. The logic abstraction is carried out by using a logic programming language, the bottom layer configuration bit stream is not particularly manipulated any more, and the reconstruction characteristic can be better realized.
Further, in the VRC virtual reconfigurable circuit, the matrix is implemented by a plurality of PE nodes, and the PE nodes are two-input and one-output logic circuits. The PE node selects two input signals for a plurality of input signals using two multiplexers and selects a two input logic function using one multiplexer. So that the logic circuit information of each PE node can be expressed only by the selection signals of three multiplexers. The genome number of the circuit chromosome information representing the whole VRC is greatly reduced, and the evolution speed of the genetic algorithm is improved.
Furthermore, an important parameter for evaluating whether the chromosome information reaches the evolution requirement in the genetic algorithm is an fitness value, and the fitness value is realized by a fitness function. And the output result of the target circuit is 0/1 to form a serial code by being embodied as a logic circuit. Therefore, the design of the fitness function adopts the Hamming distance between the output of the evolution hardware and the target output, and the similarity degree of the two 0/1 strings of codes represents the fitness value of the evolution hardware after evolution.
Furthermore, a genetic algorithm is realized in ARM as a target circuit optimizing algorithm. Because the circuit is a 0/1 logic function, gradient optimization cannot be performed, and the genetic algorithm performs similarity optimization by using the fitness value under the condition of not using the gradient, so that the method has good agreement on the characteristics of evolving hardware.
Further, there is a characteristic for genetic algorithms that they tend to be early maturing and easily enter a locally optimal solution, because populations in genetic algorithms converge rapidly after several rounds of evolution, with poor diversity. Therefore, the diversity parameter delta is introduced to evaluate the similarity degree of the population, the parameter is enlarged to indicate that the similarity degree of the population is higher, the diversity is worse, and the population can be adjusted in the subsequent evolution.
Further, an important parameter affecting population diversity is the crossover probability Pc; when the population diversity is reduced, the crossover probability Pc can be increased, resulting in an increase in population diversity. However, the too large exchange probability Pc causes too large population diversity and too slow searching speed of the optimal solution; and completing the self-adaptive exchange probability Pc by using the population diversity parameter delta construction interval, and dynamically adjusting.
Further, a random genome exchange method is employed for a specific genome exchange. For k genome exchanges, realizing that k values are located at 0-1 random numbers, and carrying out gene bit exchange when the random numbers are larger than Pc, otherwise, keeping unchanged.
Further, an important parameter affecting population diversity is variation probability Pm. When the population diversity is reduced, the exchange variation Pm can be improved, so that the population diversity is increased. However, too large variation probability Pm may cause too large population diversity and too slow searching speed of the optimal solution. And completing the self-adaptive variation probability Pm by using the population diversity parameter delta construction interval, and dynamically adjusting.
In summary, the present invention utilizes improved evolving hardware to implement self-repair circuits. The traditional evolution hardware is improved, so that the evolution speed of the evolution hardware is improved.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a diagram illustrating the overall architecture of the present invention;
FIG. 2 is a flow chart of the present invention;
FIG. 3 is a comparison diagram of a static configuration library of the present invention;
FIG. 4 is a block evolution hardware diagram of the present invention;
FIG. 5 is a diagram of an evolutionary circuit configuration of the present invention;
FIG. 6 is a diagram of an implementation of a PE module in accordance with the invention;
FIG. 7 is a schematic diagram of a VRC virtual reconfigurable circuit implementation of the present invention;
FIG. 8 is a flowchart of the genetic algorithm of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Various structural schematic diagrams according to the disclosed embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and their relative sizes, positional relationships shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
The invention provides a circuit self-repairing method based on improved evolution hardware, which adopts the evolution hardware to realize a self-repairing circuit; the compensation mechanism is a self-repairing circuit implementation principle, and a compensation circuit is additionally arranged on a circuit system, so that error output is repaired. The principle of the compensation system is to use the reversible computation characteristic of the exclusive-or operation, and the target output and the error output are subjected to the exclusive-or operation to obtain a truth table of the compensation system. After the compensation system is realized, the exclusive OR operation is utilized to complete the error output repairing function.
Referring to fig. 1 and 2, the circuit self-repairing method based on improved evolution hardware of the present invention includes the following steps:
S1, when a circuit fails, performing bit exclusive OR operation on an error output column of the failed circuit and an output column in a truth table of the correct circuit, and when a return value is 1, determining a repair section for the failed circuit; injecting the input column of the truth table of the correct circuit into the fault circuit to obtain an error output column, and transmitting the truth table of the correct circuit and the error output column of the fault circuit to a compensation system;
S2, utilizing a principle mechanism of a compensation system, and respectively performing exclusive OR calculation on a real output column and a fault circuit error output column in a true circuit truth table according to the step S1 by the compensation system to obtain a target output column of the evolution hardware;
s3, matching the target output column of the evolution hardware with the once-stored output column of the evolution hardware in the static configuration library, wherein a Hamming distance is used as a comparison basis between the target output column of the evolution hardware and the once-stored output column of the evolution hardware;
referring to fig. 3, after the target output columns of the evolution hardware in step S2 are inverted, the target output columns are respectively processed by bit exclusive or calculation with a plurality of evolution hardware target output columns stored in a static configuration library (the static configuration library stores chromosome information of a plurality of evolution hardware which has been evolved and corresponding evolution hardware output thereof), and then each bit of the calculation result is added; the sum value is a similarity value of the target evolution hardware and one type of evolution hardware stored in the static configuration library; the corresponding chromosome of the maximum value in the plurality of sum values in the static configuration library is used as the chromosome of the high-similarity individual;
s4, dividing the non-evolved evolution hardware into a plurality of blocks by using a block evolution mechanism, and dividing a target output column and a target input column of the evolution hardware according to the same block number according to the divided block number;
S5, the evolution hardware target input column divided in the step S4 and the high-similarity individual chromosome obtained in the step S3 are respectively transmitted into the non-evolution hardware which is also divided into corresponding blocks, an adaptive genetic algorithm of the adaptive evolution hardware is realized in an ARM core of the evolution hardware, and the non-evolution hardware is evolved;
Referring to fig. 4 and 5, the evolution hardware consists of an FPGA logic array and an ARM computing core; and constructing a VRC virtual reconfigurable circuit in the FPGA logic array by using a Verilog language, and simultaneously realizing an adaptability calculation module in the FPGA logic array. And transmitting the target input column and the target output column of the evolving hardware into the FPGA. And (3) realizing a genetic algorithm in the ARM core, and transmitting the genetic algorithm into a high-similarity chromosome individual.
Referring to fig. 6, a plurality of input signals enter a first multiplexer to select the first input signal, wherein the selected signal is the gene bit 1 of the PE. The multiple input signals enter the second multiplexer to select the second input signal, which is the gene bit 2 of the PE. A function table in the PE node comprises a plurality of one-bit logic operations, for example { AND, OR, NOR, XOR, NAND } are altogether 5, a function is selected as the operation function of the PE node, and a signal is selected as the gene bit 3 of the PE; and performing logic operation on the two selected input signals to finally obtain output.
A VRC virtual reconfigurable circuit is composed of input nodes of a first column, PE nodes arranged in a matrix form in the middle and output nodes of a last column. Referring to fig. 7, 6 PE nodes 2*3 are arranged in matrix, 3 input nodes and 3 output nodes, a total of 12 nodes are numbered 0-11, and the function set is exemplified by { AND, OR, NOR, XOR, NAND } for 5, numbered 0-4.
And setting the link degree L, wherein nodes in the same column cannot be connected according to the constraint of the matrix CGP, and can only be connected with the front L-1 column. Each PE node selects the number of the connection node as the locus of that node. The loci of the three multiplexers { input node 1, input node 2, operational function } of the PE node make up the genome of this node. Output nodes have only { output nodes } as individual genes. The genomes of all PE nodes and output nodes together form the chromosome of this VRC virtual reconfigurable circuit. Different chromosomes represent different circuits represented by VRCs.
And the second part is to utilize FPGA to realize a fitness calculation module, and utilize a VRC virtual reconfigurable circuit configured by a chromosome to input an evolution hardware target input and to compare an output value with an evolution hardware output value in a Hamming distance.
And performing exclusive OR calculation on the output train negation and the corresponding evolution hardware target output train, and summing each bit to obtain the Hamming distance. And summing the hamming distances between the output of the VRC virtual reconfigurable circuit which is well configured and the output value of the evolution hardware target and is input to an ARM computing core to evolve by using a genetic algorithm, wherein the hamming distances are the fitness values of the chromosome.
In the third part, please refer to fig. 8, a genetic algorithm is implemented in the ARM computing core.
S501, the matched high-similarity individual chromosome in the static configuration library is used as an initial individual, and m-1 individuals are randomly generated. Creating a function fun_ roulette (m, n) according to a roulette algorithm, wherein the function is to input the fitness of m individuals, and n individuals are selected according to the roulette algorithm; creating a random generation function random (k), wherein the function is to generate k random numbers, and the value range is 0-1.
Setting parameters: a maximum fitness value MAX; adaptive crossover probability Pc, adaptive mutation probability Pm, diversity comparison value a.
S502, m individuals enter a fitness calculation module to calculate fitness values, the fitness calculation module is utilized to calculate fitness values of the m individuals, and the fitness values are stored in a fitness storage module. Meanwhile, calculating a representative diversity parameter delta, which is specifically:
wherein favg is the m individual fitness average, fmax is the m individual fitness maximum, fmin is the m individual fitness minimum. A larger delta value represents a lower population diversity, whereas a smaller population diversity.
S503, judging whether the maximum fitness of m individuals is equal to or greater than MAX; if yes, the evolution is exited, the evolution is completed, and otherwise, the next step is entered;
S504, n1 individuals (n 1 is an even number) are selected from m individuals using a function fun_ roulette (m, n 1). Automatically changing the crossover probability Pc according to the following formula;
When the diversity parameter delta is larger than a, the diversity is poor, and the Pc value is increased; when the diversity parameter delta is smaller than a, the diversity is better, and the Pc value is kept unchanged.
Generating k random numbers by using a random generation function random (k) according to the total chromosome gene number k (k=3+1+1 output node number), wherein the value range is 0-1, n1 individuals are pairwise paired, and when the ith random number is larger than the Pc value, the ith gene position is unchanged; when the ith random number is smaller than the Pc value, the ith gene bit is exchanged.
S505, selecting n2 individual tickets from m individuals by using a function fun_ roulette (m, n 2), automatically changing variation probability Pm, and increasing Pm value when a diversity parameter delta is larger than a and the diversity is poor; when the diversity parameter delta is smaller than a, the diversity is good, the Pm value is kept unchanged, the gene bit number w needing to be mutated is calculated according to the total gene bit number k of the chromosome multiplied by Pm, and a random generation function random (w) is used for generating w random numbers, and the value range is 0-1;
The j-th gene bit randomly changes another value, and the formula of j is as follows:
S506, calculating n1 exchange offspring, n2 variation offspring fitness values, m father, n1 exchange offspring and n2 variation offspring by using an epoch-crossing elite algorithm, and selecting m individuals from m+n1+n2 individuals by using a function fun_ roulette (m+n1+n2, m) as the next generation to enter S502.
Using a block evolution mechanism to complete evolution hardware, wherein each block of evolution total target outputs a part, and each block of target inputs are the same;
s6, performing exclusive OR operation on the evolved evolution hardware and error bits corresponding to the fault circuit to finish repair.
The improvement of the invention is as follows:
1. realizing static configuration library
When an error occurs and evolution repair is carried out, chromosome information of error output and corresponding evolution hardware is stored; when the next error occurs, a matching item is first found in the static configuration library. The same error exists, and the chromosome information is directly output. When the errors are not identical, searching an individual with the highest similarity as an individual of the genetic algorithm in the evolution hardware, so that the evolution speed is improved.
2. For large-scale circuit evolution, a packet evolution method is adopted
The target outputs are grouped, thereby improving parallelism.
3. Use of adaptive genetic algorithms in evolving hardware
The genetic algorithm often has the phenomenon of precocity, and population individuals are highly similar after several iterations and enter a local optimal solution. The diversity of the population decreases rapidly. In order to solve the problem, an adaptive genetic algorithm is adopted, and the diversity of each generation of population is estimated by introducing a parameter delta. When the diversity is low, the exchange parameter Pm and the variation parameter Pc are increased so as to increase the population diversity. The exchange parameter Pm and the variation parameter Pc automatically change according to population characteristics.
In the application environment of aerospace navigation, high requirements are placed on the reliability of a circuit. The evolution hardware is used as a circuit self-repairing system, so that the repairing function of the circuit can be automatically completed under the condition of no manual intervention. Meanwhile, for the traditional triple-modular redundancy backup method, under the condition that a circuit is in error, only the error part of the circuit is corrected, the whole backup is not started any more, and the circuit resource is greatly reduced. Meanwhile, a block evolution mechanism and a self-adaptive Pm and Pc parameter method are provided, and the evolution speed is improved.
In conclusion, the circuit self-repairing method based on the improved evolution hardware has good application scenes in the environments such as aerospace navigation and the like, and the self-adapting characteristic can be used for repairing various logic circuits more flexibly.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. The circuit self-repairing method based on the improved evolution hardware is characterized by comprising the following steps of:
S1, when a circuit fails, performing bit exclusive OR operation on an error output column of the failed circuit and an output column in a truth table of the correct circuit, and when a return value is 1, determining a repair section as the failed circuit; injecting the input columns of the truth table of the correct circuit into the fault circuit to obtain an error output column;
s2, performing exclusive OR calculation on a real output column in the true circuit truth table and an error output column of the fault circuit according to the determination of the step S1 to obtain a target output column of the evolution hardware;
S3, performing bit exclusive OR calculation on the target output columns of the evolution hardware in the step S2 and the evolution hardware target output columns stored in the static configuration library respectively after the target output columns are inverted, adding each bit of the calculation result to obtain a sum value, and taking the sum value as an evolution hardware similarity value between the target evolution hardware and the evolution hardware stored in the static configuration library; taking the chromosome corresponding to the maximum value in the sum values in the static configuration library as the chromosome of the high-similarity individual;
s4, dividing the non-evolved evolution hardware into a plurality of blocks by using a block evolution mechanism, and dividing a target output column and a target input column of the evolution hardware according to the same block number according to the divided block number;
S5, the evolution hardware target input column divided in the step S4 and the high-similarity individual chromosome obtained in the step S3 are respectively transmitted into the non-evolution hardware of which the corresponding blocks are divided, an adaptive genetic algorithm of the adaptive evolution hardware is realized in an ARM computing core of the evolution hardware, and the evolution of the non-evolution hardware is completed;
S6, performing exclusive OR operation on the evolved evolution hardware evolved in the step S5 and the error bit corresponding to the fault circuit to finish repair.
2. The method according to claim 1, wherein in step S5, the evolution hardware comprises an FPGA logic array and an ARM computation core, and a VRC virtual reconfigurable circuit is built in the FPGA logic array; utilizing a chromosome to configure a VRC virtual reconfigurable circuit, inputting the configured VRC virtual reconfigurable circuit into an evolution hardware target input column to generate an output column, carrying out Hamming distance comparison on the output column and the evolution hardware target output column, and summing the comparison values to be used as fitness values of corresponding chromosomes; and realizing a genetic method by programming in an ARM computing core.
3. The method of claim 2, wherein the VRC virtual reconfigurable circuit includes input nodes, PE nodes and output nodes, the PE nodes being arranged in a matrix, the degree of linking L being set, an intermediate PE node of the same column being connected to the previous L-1 column;
The PE node comprises two input circuits and one output circuit and has a unique number; the two input circuits are respectively connected with an output circuit for selecting PE nodes by using a multiplexer, and the serial numbers of the selected PE nodes are used as the gene bits of the PE nodes;
selecting a logic operation for two input values selected by two input circuits by using a multiplexer in each PE node, and taking the selected logic operation number as the gene bit of the PE node; taking the PE node numbers and the logic calculation numbers of the two input values selected by the two input circuits as the genome of the PE node;
The output node of the VRC virtual reconfigurable circuit uses a multiplexer to select the output of a PE node as input, and the serial number of the selected PE node is used as the genome of the output node;
the genomes of all PE nodes and the output node together constitute the chromosome of the VRC virtual reconfigurable circuit.
4. A method according to claim 3, wherein a plurality of input signals are present in the PE node, the plurality of input signals entering the first multiplexer to select a first input signal, the first input signal being gene bit 1 corresponding to the PE node number; the plurality of input signals enter a second multiplexer to select a second input signal, wherein the second input signal is gene bit 2 corresponding to the PE node number; the PE node stores a function table which contains a plurality of one-bit logic operations and has corresponding numbers; selecting a function as an operation function of the PE node, and selecting a signal as a gene position 3 of the corresponding PE node; the selected two input signals are operated by the selected logic operation to obtain PE node output.
5. The method according to claim 2, wherein the hamming distance comparison is specifically:
Inputting the configured VRC virtual reconfigurable circuit into a target input column to obtain an output column, performing exclusive OR calculation on the output column and the corresponding evolution hardware target output column respectively after inverting, and summing each bit to obtain a Hamming distance; and summing all the hamming distances to obtain the fitness value of the chromosome.
6. The method according to claim 2, characterized in that the implementation of the genetic method in the ARM computing core is in particular:
S501, taking the chromosomes of the individuals with high similarity matched in the static configuration library as an initial individual, and randomly generating m-1 individuals; creating a roulette selection function fun_ roulette (m, n) according to a roulette method, wherein the function is the fitness of inputting m individuals, selecting n individuals according to the roulette method, creating a random generation function random (k), and generating k random numbers Ri;
S502, an ARM computing core is utilized to realize an fitness computing module, fitness values of m individuals are computed and stored, a genetic algorithm is jumped out after the output condition of a fitness function is triggered, and evolution is finished to obtain a target circuit; simultaneously calculating a population diversity parameter delta;
S503, judging whether the maximum fitness of m individuals is equal to or greater than a maximum fitness value; if the adaptation value is equal to or greater than the maximum adaptation value, the evolution is exited, the evolution is completed, and otherwise, the step S504 is entered;
S504, setting self-adaptive exchange probability Pc, when population diversity parameter delta is larger than diversity comparison value a, pc is 1.3, increasing, selecting n1 individuals from m individuals in step S502 as crossed chromosomes by using roulette selection function fun_ roulette (m, n 1), generating k random numbers by using random generation function random (k) according to total chromosome gene number k, pairing every two n1 individuals, and exchanging the ith gene position when the ith random number is larger than self-adaptive exchange probability Pc;
S505, setting self-adaptive variation probability Pm, when a diversity parameter delta is larger than a diversity comparison value a and Pm is increased by 1.1, selecting n2 individuals from m individuals in the step S502 as chromosomes by using a roulette selection function fun_ roulette (m, n 2), calculating the number w of gene bits needing to be mutated according to the total number k of the gene bits by Pm, generating w random numbers by using a random generation function random (w), multiplying the w random numbers by the number k of the gene bits to obtain the number of the gene bits needing to be mutated, and randomly changing the gene bits needing to be mutated into a gene value in a specified range;
S506, obtaining n1 exchange offspring from the step S504 by using an epoch-crossing elite algorithm, obtaining n2 variation offspring from the step S505, respectively calculating fitness values, obtaining m parent fitness values from the step S502, and selecting m individuals from m+n1+n2 individuals by using a function fun_ roulette (m+n1+n2, m);
s507, obtaining m individuals from the step S506, entering the step S502, jumping out of the genetic algorithm after the fitness function output condition is triggered, and ending evolution to obtain a target circuit.
7. The method according to claim 6, wherein in step S502, the diversity parameter δ is specifically:
wherein favg is the m individual fitness average, fmax is the m individual fitness maximum, fmin is the m individual fitness minimum.
8. The method according to claim 6, wherein in step S504, the adaptive switching probability Pc is specifically:
wherein a is a diversity comparison value, and delta is a diversity parameter.
9. The method according to claim 6, wherein in step S504, the gene exchange is specifically:
wherein Ri is a random number.
10. The method according to claim 6, wherein in step S505, the mutation probability Pm is automatically changed as follows:
Wherein a is a diversity comparison value, and delta is a diversity parameter;
the j-th gene bit is randomly transformed into a value in a specified range, and the j value is specifically:
wherein Ri is a random number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210269757.5A CN114647541B (en) | 2022-03-18 | 2022-03-18 | Circuit self-repairing method based on improved evolution hardware |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210269757.5A CN114647541B (en) | 2022-03-18 | 2022-03-18 | Circuit self-repairing method based on improved evolution hardware |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114647541A CN114647541A (en) | 2022-06-21 |
| CN114647541B true CN114647541B (en) | 2024-04-26 |
Family
ID=81994799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210269757.5A Active CN114647541B (en) | 2022-03-18 | 2022-03-18 | Circuit self-repairing method based on improved evolution hardware |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114647541B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135928A (en) * | 2011-03-30 | 2011-07-27 | 武汉大学 | Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware |
| CN102254225A (en) * | 2011-06-03 | 2011-11-23 | 中国科学院西安光学精密机械研究所 | Evolution hardware implementation method based on trend type compact genetic algorithm |
| CN106055426A (en) * | 2016-05-21 | 2016-10-26 | 大连理工大学 | Real-time fault tolerant system design method based on evolvable hardware |
| LU102400A1 (en) * | 2019-08-06 | 2021-02-09 | Nanjing Seawolf Ocean Tech Co Ltd | Path planning method and system for unmanned surface vehicle based on improved genetic algorithm |
-
2022
- 2022-03-18 CN CN202210269757.5A patent/CN114647541B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135928A (en) * | 2011-03-30 | 2011-07-27 | 武汉大学 | Isomerous triple modular redundancy fault-tolerant method based on LUT (Look-up Table) evolvable hardware |
| CN102254225A (en) * | 2011-06-03 | 2011-11-23 | 中国科学院西安光学精密机械研究所 | Evolution hardware implementation method based on trend type compact genetic algorithm |
| CN106055426A (en) * | 2016-05-21 | 2016-10-26 | 大连理工大学 | Real-time fault tolerant system design method based on evolvable hardware |
| LU102400A1 (en) * | 2019-08-06 | 2021-02-09 | Nanjing Seawolf Ocean Tech Co Ltd | Path planning method and system for unmanned surface vehicle based on improved genetic algorithm |
Non-Patent Citations (3)
| Title |
|---|
| 在线演化系统容错机制的研究;桑博;李智;牛军浩;;桂林电子科技大学学报;20170825(04);57-62 * |
| 数字电路硬件演化研究;耿建平;王天蒙;李智;牛军浩;;桂林航天工业学院学报;20150315(01);7-11 * |
| 演化电路的故障自修复设计与实现;娄建安;李川涛;杰;李阳;;计算机工程;20130915(09);314-316+322 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114647541A (en) | 2022-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112085204B (en) | Line transformation method for quantum compiling | |
| US8521673B2 (en) | Parallel processing device and parallel processing method | |
| CN111612252A (en) | Automatic site selection method and device for large-scale emergency facilities and readable storage medium | |
| CN112559374A (en) | Test case sequencing method and electronic equipment | |
| CN104618134B (en) | A kind of multistage light splitting passive optical network optimization method of power distribution communication net | |
| Sharifi et al. | Using NSGA II algorithm for a three objectives redundancy allocation problem with k-out-of-n sub-systems | |
| CN110459258B (en) | Multi-memory built-in self-test method based on multi-target clustering genetic algorithm | |
| CN112035059A (en) | Single-point failure recovery method for distributed storage system, electronic equipment and storage medium | |
| CN111709526A (en) | Multi-mode and multi-target evolution algorithm based on multi-factor transfer learning | |
| CN116258357A (en) | Heterogeneous unmanned aerial vehicle cooperative target distribution method based on polygene genetic algorithm | |
| Schnier et al. | Using negative correlation to evolve fault-tolerant circuits | |
| CN114647541B (en) | Circuit self-repairing method based on improved evolution hardware | |
| Marchal et al. | Embryonics: The birth of synthetic life | |
| Ripon et al. | Dynamic facility layout problem under uncertainty: a Pareto-optimality based multi-objective evolutionary approach | |
| CN117764025A (en) | Integrated circuit design method through population optimization algorithm | |
| CN111412795A (en) | Test point setting scheme generation method and device | |
| Ping et al. | A mixed isomorphism approach for kinematic structure enumeration graphs based on intelligent design and manufacturing | |
| CN117093131A (en) | Distributed data storage optimization method and device | |
| Mangal et al. | Analysis of multidimensional xor classification problem with evolutionary feedforward neural networks | |
| CN112488314B (en) | System elasticity recovery method and system based on improved genetic algorithm | |
| JP2003168101A (en) | Learning device and method using genetic algorithm | |
| KR102211604B1 (en) | GPU-based AI system using channel-level architecture search for deep neural networks | |
| Kaufmann et al. | Toward self-adaptive embedded systems: multi-objective hardware evolution | |
| KR20100031218A (en) | System and method for manufacturing mask using genetic algorithm and dna computing | |
| CN113111446A (en) | Matching method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |